WO2023143587A1 - 相变材料、相变存储芯片、存储设备及电子设备 - Google Patents

相变材料、相变存储芯片、存储设备及电子设备 Download PDF

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WO2023143587A1
WO2023143587A1 PCT/CN2023/073739 CN2023073739W WO2023143587A1 WO 2023143587 A1 WO2023143587 A1 WO 2023143587A1 CN 2023073739 W CN2023073739 W CN 2023073739W WO 2023143587 A1 WO2023143587 A1 WO 2023143587A1
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phase
phase change
change
layer
change memory
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PCT/CN2023/073739
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English (en)
French (fr)
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马平
李响
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华为技术有限公司
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Priority claimed from CN202210266567.8A external-priority patent/CN116615092A/zh
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Publication of WO2023143587A1 publication Critical patent/WO2023143587A1/zh

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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801Constructional details of multistable switching devices
    • H10N70/881Switching materials
    • H10N70/882Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8825Selenides, e.g. GeSe
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B63/00Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/20Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20Multistable switching devices, e.g. memristors
    • H10N70/231Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801Constructional details of multistable switching devices
    • H10N70/841Electrodes
    • H10N70/8413Electrodes adapted for resistive heating
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801Constructional details of multistable switching devices
    • H10N70/881Switching materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801Constructional details of multistable switching devices
    • H10N70/881Switching materials
    • H10N70/882Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8828Tellurides, e.g. GeSbTe

Definitions

  • the present disclosure relates to the technical field of semiconductor storage, in particular to phase change materials, phase change memory chips, storage devices and electronic devices.
  • Phase change materials exhibit low resistivity in the crystalline state and high resistivity in the amorphous state.
  • Phase change memory Phase change memory (Phase change memory, PCM) is based on the resistance difference between the crystalline state and the amorphous state of the phase change material. To achieve data storage and erasure. Among them, the phase change material has an important influence on the reading and writing speed and cycle life of the phase change memory chip.
  • phase change memories prepared based on Sb 2 Te 3 materials still need to be improved in terms of read and write speed and cycle life.
  • the present disclosure provides a phase change material, a phase change memory chip, a storage device and an electronic device, which can solve the above technical problems.
  • phase change material in one aspect, includes a Sb n X m material, where n:m ⁇ 1:1;
  • the Sb n X m material with an atomic percentage content n:m ⁇ 1:1 is used as a phase change material, so that the atomic percentage content of the Sb element is greater than or equal to the atomic percentage content of the doping element X.
  • the Sb element with high SET speed and high fatigue characteristics is used as the main material, and the doping element X is used as the supplementary material. Since the difference between the atomic radius of the doping element X and the atomic radius of Sb satisfies the first threshold condition, the element X and Sb form a weakly polar bond.
  • phase change material provided by the embodiments of the present disclosure is used in a phase change memory chip, it is beneficial to improve the SET speed and cycle life of the phase change memory chip, so that the phase change memory chip can achieve the read/write speed and cycle life required for memory-level data storage. life possible.
  • the first threshold condition includes that the difference is less than or equal to The atomic radii of element X and element Sb are made as close as possible so that a weakly polar bond is formed between them.
  • the second threshold condition includes that the resistance time of the element X at 400° C. is greater than or equal to 30 minutes, which ensures that the element X has excellent thermal stability.
  • the element X includes at least one of Te, Sn, Se, Ni, Nb, Zr, and Y.
  • X can be one, any two, any three, or more of Te, Sn, Se, Ni, Nb, Zr, and Y.
  • phase change memory unit has good thermal stability.
  • the Sb n X m material is in the form of an Sb-X alloy, a Sb-X binary compound, or a mixture of Sb and X.
  • phase change memory chip in another aspect, includes: a plurality of phase change memory cells, each of the phase change memory cells has a phase change film, and the phase change film includes: alternately stacked phase change material layer and template layer;
  • phase-change material layer is formed of any one of the above-mentioned phase-change materials
  • the template layer is formed of a template material, and the lattice mismatch between the template material and the Sb n X m material satisfies a third threshold condition, so that the template layer can be used as a crystallization template of the phase change material layer.
  • the phase-change thin film is alternately laminated with phase-change material layers and template layers, wherein the phase-change material layers are formed of Sb n X m materials.
  • the phase change material layer has a higher performance.
  • SET speed and cycle life By using the template layer 102 to provide a crystallization template, it is beneficial to further improve the SET speed and cycle life of the phase change memory unit.
  • phase change material layer 101 based on the Sb n X m material and the template layer 102 is conducive to significantly improving the SET speed and cycle life of the phase change memory chip in the embodiment of the present disclosure, so that the phase change memory chip can achieve memory-level data
  • the read and write speed and cycle life required by the storage are possible.
  • the thickness of the phase change material layer is 1 nm to 100 nm;
  • the thickness of the template layer is 1nm-10nm.
  • the number of cycles in which the phase-change material layer and the template layer are alternately stacked is 1-100, for example, 2-100, 2-90, 2-80, 2-70, 2-60 , 2 ⁇ 50, 2 ⁇ 40, etc.
  • the third threshold condition includes that the lattice mismatch is less than or equal to 10%, for example, the lattice mismatch between the template material and the Sb n X m material is less than or equal to 8 %, further, less than or equal to 5%, less than or equal to 4%, less than or equal to 3%, less than or equal to 2%, less than or equal to 1%, less than or equal to 0.5%, etc., so that the phase change material can be obtained faster the crystallization speed.
  • the template material includes at least one of TiTe 2 and Ti-Sb-Te ternary compounds.
  • TiTe 2 and Ti-Sb-Te ternary compounds as template materials has at least the following advantages:
  • TiTe 2 and Ti-Sb-Te and Sb n X m materials have the advantage of high lattice matching, that is, the lattice mismatch is low, and this smaller lattice constant between the two The difference can provide driving force for the crystallization of the phase-change material layer 101, and improve the crystallization speed of the phase-change material layer 101 and the stability of the crystalline structure formed during crystallization.
  • TiTe 2 and Ti-Sb-Te have high thermal stability, and the template layer 102 based on them remains stable during the working process of the phase-change material layer 101, which is beneficial to enhance the cycle life of the phase-change memory unit.
  • the template layer 102 based on Ti-Sb-Te can spontaneously suppress the diffusion caused by the Sb concentration difference, so that the phase-change material layer 101 can More stable, showing higher high temperature resistance, which is also extremely beneficial for enhancing the cycle life of the phase change memory unit.
  • the phase change memory unit further includes: a substrate, a bottom electrode, a top electrode, and an insulating and heat insulating layer;
  • the bottom electrode is located on the surface of the substrate
  • the phase change film is connected between the bottom electrode and the top electrode;
  • the insulation and heat insulation layer is covered on the side of the phase change film.
  • the structure of the phase-change memory cell includes, but is not limited to: a restricted structure, a T-shaped structure, and the like.
  • an embodiment of the present disclosure provides a storage device, the storage device includes a controller and any phase-change memory chip described above, and the controller is used to store data in the phase-change memory chip.
  • the phase-change memory chip provided by the embodiments of the present disclosure has at least the following advantages: fast reading and writing speed, high stability, strong temperature resistance, high cycle life, and high-density multi-valued storage.
  • an embodiment of the present disclosure provides an electronic device, where the electronic device includes a processor and the above-mentioned storage device, and the processor is configured to store data generated by the electronic device in the storage device.
  • the electronic devices include, but are not limited to: computers, cell phones, music playback devices, digital broadcasting devices, messaging devices, game control devices, medical devices, fitness devices, personal digital assistants, and the like.
  • FIG. 1 is a schematic structural diagram of an exemplary phase change film provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of a phase-change memory cell with an exemplary confinement structure provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of another exemplary phase-change memory cell with a restricted structure provided by an embodiment of the present disclosure
  • FIG. 4 is a schematic structural diagram of an exemplary phase-change memory cell with a T-shaped structure provided by an embodiment of the present disclosure
  • FIG. 5 is a schematic structural diagram of an exemplary phase-change memory chip 1R provided by an embodiment of the present disclosure
  • FIG. 6 is a schematic structural diagram of an exemplary phase-change memory chip 1T1R provided by an embodiment of the present disclosure
  • FIG. 7 is a schematic structural diagram of an exemplary phase-change memory chip 1D1R provided by an embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of an application scenario of an exemplary phase-change memory chip in an electronic device provided by an embodiment of the present disclosure
  • FIG. 9 is a cycle life distribution diagram of a phase change memory array based on a phase change film provided by an embodiment of the present disclosure.
  • Phase change memory also known as phase change memory chip
  • Phase change memory chip is a solid-state semiconductor non-volatile memory, which uses phase change materials as storage media, and phase change materials can change between crystalline and amorphous states. Reversible transformation is carried out between them, and the difference between the high resistivity and low resistivity corresponding to the phase change material in the amorphous state and the crystalline state is used, and the phase change memory realizes the storage of data "0" and "1".
  • the working process of the phase change memory includes: an erase operation (SET) process and a write operation (RESET) process.
  • the SET process refers to: apply a wide and weak electric pulse to heat the phase change material, so that the temperature of the phase change material rises to between the crystallization temperature and the melting temperature, and the phase change material crystallizes into an ordered state, forming a The crystalline state of resistivity to realize the storage of data "0".
  • the RESET process refers to applying a narrow and strong electric pulse to heat the phase change material, so that the temperature of the phase change material rises above the melting temperature, melts into a disordered state, and then undergoes a rapid cooling quenching process (> 10 9 K/s), the phase change material directly enters the amorphous state with higher resistivity from the molten state, so as to realize the storage of data "1".
  • Phase-change materials have an important impact on the read-write speed and cycle life of phase-change memory.
  • Related technology phase-change materials however, Sb 2 Te 3 materials have problems such as insufficient crystallization speed, poor temperature stability, and low fatigue performance, which make The phase change memory prepared by the phase change material based on Sb 2 Te 3 still needs to be improved in terms of reading and writing speed and cycle life.
  • the cycle life involved here refers to the number of cycles that the phase change memory can perform before failure by setting the phase change memory to 0 or 1 to perform repeated cycle operations.
  • Sb simple substance can also be used as a phase change material.
  • Sb simple substance exhibits faster SET operation and higher cycle life, it is prone to problems such as set-stuck.
  • set-stuck refers to the phase change material The resistance value of is always kept in a low resistance state, and cannot be changed to a high resistance state by any RESET operation.
  • phase change material includes a Sb n X m material, wherein, n:m ⁇ 1:1, and the difference between the atomic radius of the element X and the atomic radius of the element Sb satisfies the first
  • the threshold condition enables the element X to form a weakly polar bond with the element Sb, and the thermal stability parameter of the element X satisfies a second threshold condition such that the element X remains stable at the phase transition temperature of the element Sb.
  • the Sb n X m material with an atomic percentage content n:m ⁇ 1:1 is used as a phase change material, so that the atomic percentage content of the Sb element is greater than or equal to the atomic percentage content of the doping element X.
  • the Sb element with high SET speed and high fatigue characteristics is used as the main material, and the doping element X is used as the supplementary material. Since the difference between the atomic radius of the doping element X and the atomic radius of Sb satisfies the first threshold condition, the element X and Sb form a weakly polar bond.
  • phase change material provided by the embodiments of the present disclosure is used in a phase change memory chip, it is beneficial to improve the SET speed and cycle life of the phase change memory chip, so that the phase change memory chip can achieve the read/write speed and cycle life required for memory-level data storage. life possible.
  • the memory-level data storage involved here refers to the storage of data by phase change memory, that is, the speed of reading, writing and erasing data is comparable to that of dynamic random access memory (Dynamic Random Access Memory, DRAM). of.
  • DRAM Dynamic Random Access Memory
  • Sb can avoid the formation of large grain set-stuck, because, for Sb single material, there is a non-polar bond between Sb-Sb, which makes it easier to aggregate between Sb-Sb , which in turn leads to large grain set-stuck.
  • the X material is doped in the Sb material, so that a weak polar bond is formed between Sb-X, and the weak polar bond can avoid aggregation between Sb-Sb, Thus avoiding the main material Sb from forming a large grain set-stuck.
  • the desired first threshold condition includes a difference less than or equal to That is, the difference between the atomic radius of element X and the atomic radius of element Sb satisfies less than or equal to Furthermore, less than or equal to less than or equal to less than or equal to wait. In this way, the atomic radii of element X and element Sb are made as close as possible so that a weakly polar bond is formed between them.
  • the second threshold condition includes element X withstanding time at 400°C greater than or equal to 30 minutes, for example, element X withstanding time at 400°C equal to 30 minutes, 40 minutes, 50 minutes, 60 minutes , 120 minutes or The above etc., in this way, element X is ensured to have excellent thermal stability.
  • some X that meet the above conditions include at least one of Te (tellurium), Sn (tin), Se (selenium), Ni (nickel), Nb (niobium), Zr (zirconium), and Y (yttrium). species, that is, X can be one, any two, any three, or more of Te, Sn, Se, Ni, Nb, Zr, and Y.
  • the sum of the atomic percentages of two or more elements X is taken as m, so that their atoms
  • the sum of the percentages and the atomic percentage of the element Sb may be less than or equal to 1, and the ratio between the two or more different elements X may be any atomic percentage, such as 1:1-10.
  • Te, Sn, Se, Ni, Nb, Zr, and Y are elements whose atomic radius is close to that of Sb atoms, and which are easy to form weakly polar bonds with Sb elements.
  • the above types of doping elements can be avoided
  • the Sb material forms a large grain set-stuck, and prevents the Sb material from losing the ability of phase transition due to too strong bonding with the Sb element.
  • n:m ⁇ 1:1 means that the atomic ratio of the element Sb to the doping element X is ⁇ 1:1, and the amount of Sb is greater than or equal to the amount of the doping element X to ensure the phase transition Memory cells have high SET speed and cycle life.
  • the doping amount of element X is less to ensure that the Sb n X m material can maintain the advantages of Sb itself, which is manifested as a higher SET speed and cycle life.
  • the doping amount of element X it is also possible to appropriately increase the doping amount of element X in the above-mentioned atomic ratio range according to the ambient temperature. This is because increasing the doping amount of X to a certain extent can improve the thermal stability of the Sb n X m material, making the phase transition Storage units are more adaptable to high temperature environments.
  • phase change memory cell When the atomic ratio of Sb to X is within the above range, not only can the phase change memory cell have a high SET speed and cycle life, but also make the phase change memory cell have good thermal stability.
  • the Sb n X m material may be in the form of an Sb-X alloy, or in the form of a Sb-X binary compound, or in the form of a mixture of Sb element and X element.
  • the Sb n X m material is in the form of a Sb-X alloy.
  • a currently commercially available Sb-X alloy plate that meets the atomic ratio requirements can be used to prepare the phase change material layer.
  • the Sb n X m material is a mixture of Sb simple substance and X simple substance.
  • the Sb simple substance and X simple substance are uniformly mixed, and the Preparation of phase change material layer.
  • the embodiment of the present disclosure also provides a phase-change memory chip, which includes: a plurality of phase-change memory units, each phase-change memory unit has a phase-change film 1, as shown in Figure 1 , the phase change thin film 1 includes: alternately stacked phase change material layers 101 and template layers 102 .
  • the phase-change material layer is formed by any of the above-mentioned phase-change materials;
  • the template layer 102 is formed by a template material, and the lattice mismatch between the template material and the Sb n X m material satisfies the third threshold condition, so that the template layer 102 can be used as A crystallization template for the phase change material layer 101 .
  • Phase-change material layers 101 and template layers 102 are stacked alternately, wherein template layers 102 are used to provide crystallization templates for phase-change material layers 101, that is, to provide crystallization growth interfaces for phase-change material layers 101 to accelerate the phase-change memory cell Erase and write speed. Moreover, the phase-change material layer 101 is constrained by the template layer 102. In the limited confined space, it is difficult for Sb in the Sb n X m material in the phase-change material layer 101 to gather to form large grains, thereby avoiding the formation of The failure of large grains improves the cycle life of the phase change memory unit.
  • phase-change material layers 101 and template layers 102 are alternately laminated in the embodiments of the present disclosure refers to that there is a template layer 102 between any two phase-change material layers 101, or that any two template layers There is a phase change material layer 101 between 102 . That is to say, the phase change film 1 is a periodic cycle structure formed by alternately stacking phase change material layers 101 and template layers 102 , and the phase change material layers 101 and template layers 102 form a superlattice phase change material.
  • the phase-change film 1 is alternately laminated with phase-change material layers 101 and template layers 102 , wherein the phase-change material layers 101 are formed of Sb n X m materials.
  • the phase change material layer 101 has a relatively high performance. High SET speed and cycle life.
  • the template layer 102 By using the template layer 102 to provide a crystallization template, it is beneficial to further improve the SET speed and cycle life of the phase change memory unit.
  • phase change material layer 101 based on the Sb n X m material and the template layer 102 is conducive to significantly improving the SET speed and cycle life of the phase change memory chip in the embodiment of the present disclosure, so that the phase change memory chip can achieve memory-level data
  • the read and write speed and cycle life required by the storage are possible.
  • template layer 102 it is formed by template material, and template layer 102 has stronger thermal stability, and, the lattice mismatch degree of template material and Sb n X m material satisfies the third threshold value condition, like this, template material and Sb
  • the structures of the contact crystal planes of the n ⁇ m material are the same or similar, so that the two can obtain a higher degree of lattice matching, and ensure that the template layer 102 can be used as a crystallization template of the phase change material layer 101 .
  • the third threshold condition includes that the lattice mismatch degree is less than or equal to 10%, that is, the lattice mismatch degree between the template material and the Sb n X m material is less than or equal to 10%, for example, the template
  • the lattice mismatch between the material and the Sb n X m material is less than or equal to 8%, further, less than or equal to 5%, less than or equal to 4%, less than or equal to 3%, less than or equal to 2%, less than or equal to 1 %, less than or equal to 0.5%, etc., so that the phase change material can obtain a faster crystallization rate.
  • the template material includes at least one of TiTe 2 and Ti-Sb-Te ternary compound, wherein the Ti-Sb-Te ternary compound is also called Ti-Sb-Te alloy, and its chemical formula is Sb x Te y Ti 100-xy , where 0 ⁇ x ⁇ 80, 0 ⁇ y ⁇ 100-x.
  • TiTe 2 and Ti-Sb-Te ternary compounds as template materials has at least the following advantages:
  • TiTe 2 and Ti-Sb-Te and Sb n X m materials have the advantage of high lattice matching, that is, the lattice mismatch is low, and this smaller lattice constant between the two The difference can provide driving force for the crystallization of the phase-change material layer 101, and improve the crystallization speed of the phase-change material layer 101 and the stability of the crystalline structure formed during crystallization.
  • TiTe 2 and Ti-Sb-Te have high thermal stability, and the template layer 102 based on them remains stable during the working process of the phase-change material layer 101, which is beneficial to enhance the cycle life of the phase-change memory unit.
  • the template layer 102 based on Ti-Sb-Te can spontaneously suppress the diffusion caused by the Sb concentration difference, so that the phase-change material layer 101 can More stable, showing higher high temperature resistance, which is also extremely beneficial for enhancing the cycle life of the phase change memory unit.
  • the thickness range of the phase change material layer 101 involved in the phase change film 1 is 1nm to 100nm, for example, 1nm, 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm, 10nm, 20nm , 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, etc.
  • the thickness of the multi-layer phase-change material layers 101 can be all the same, or the thickness of some phase-change material layers 101 can be made the same, or The thicknesses of all the phase change material layers 101 may be made different from each other.
  • the thickness of the phase change material layer 101 of any layer can be determined according to the corresponding operating voltage or operating current when the phase change occurs.
  • the thickness range of the template layer 102 involved in the phase change film 1 is 1nm-10nm, such as 1nm, 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm, 10nm, etc.
  • the thickness of the multilayer template layers 102 can be all the same, or the thickness of some template layers 102 can be made the same, or all the template layers can be made The thicknesses of 102 are different from each other.
  • the phase-change material layer 101 and the template layer 102 are stacked alternately, and a phase-change material layer 101 and a template layer 102 stacked thereon are used as a cycle number (also referred to as a cycle number).
  • the number of cycles in which the phase-change material layer 101 and the template layer 102 are alternately stacked is 1-100, for example, 2-100, 2-90, 2-80, 2-70, 2-60, 2-50, 2-40 Etc., for example, the cycle number of alternate stacking of the phase change material layer 101 and the template layer 102 may be 5, 10, 15, 20, 25, 30, 35, 40, 45, 50, 55 and so on.
  • the phase change material layer 101 is made of two or more layers, so that the phase change film 1 can undergo layered phase change to obtain multi-level storage capability, which is beneficial to improve the data storage density of the phase change memory chip.
  • the phase-change film 1 may include sequentially stacked first phase-change material layers 101/first template layers 102/th Two phase change material layers 101/second template layer 102/third phase change material layer 101/third template layer 102/fourth phase change material layer 101/fourth template layer 102/fifth phase change material layer 101, and Further optionally, the fifth template layer 102 is laminated on the fifth phase change material layer 101 .
  • the types of Sbn X m materials used in each layer of the multilayer phase change material layer 101 may be all the same, or may be partially or completely different.
  • the types of template materials used in each layer of the multi-layer template layer 102 may be all the same, or partly or completely different. Wherein, the type of the template layer 102 must be selected according to the type of the phase-change material layer 101 adjacent to it, so as to ensure that the lattice mismatch between the template layer 102 and the phase-change material layer 101 having a stacked relationship is less than or equal to 10 %.
  • phase change thin film 1 which includes: alternately stacked phase change material layers 101 and template layers 102, and the cycle number of alternate stacking of phase change material layers 101 and template layers 102 is 2-100.
  • the thickness of the phase change material layer 101 is 1 nm ⁇ 50 nm; the thickness of the template layer 102 is 1 nm ⁇ 10 nm.
  • phase change material layer 101 it is formed by Sb n X m material, and Sb n X m material is Sb 2 Te, SbTe, SbSn, Sb 2 Sn, Sb 3 Sn, SbSe, Sb 2 Se, Sb 3 Se, SbNi, Sb 2 Ni, Sb 3 Ni, SbNb, Sb 2 Nb, Sb 3 Nb, SbZr, Sb 2 Zr, Sb 3 Zr, SbY, Sb 2 Y, Sb 3 Y, etc.
  • the template layer 102 it is formed of TiTe 2 or Ti—Sb—Te ternary compound.
  • phase change film 1 involved in the embodiment of the present disclosure can be prepared by the following preparation method:
  • phase change material layer 101 and template layer 102 Provide Sb n X m material and template material; according to the stacking sequence of phase change material layer 101 and template layer 102 in phase change film 1, use Sb n X m material and template material to alternately form phase change material layer 101 through thin film deposition process and template layer 102 .
  • the film deposition processes involved include, but are not limited to, the following: atomic layer deposition (atomic layer deposition, ALD), physical vapor deposition (Physical Vapor Deposition, PVD), chemical vapor deposition (Chemical Vapor Deposition, CVD), etc.
  • Magnetron sputtering is a common physical vapor deposition process.
  • the phase change film 1 can be prepared by using the magnetron sputtering process.
  • some applicable magnetron sputtering parameters are as follows:
  • the background vacuum is 10 -3 Pa ⁇ 10 -5 Pa, for example, 1 ⁇ 10 -4 Pa ⁇ 5 ⁇ 10 -4 Pa; the sputtering pressure is 0.3Pa ⁇ 0.8Pa, etc.; the substrate temperature, that is, the temperature of the sample stage Room temperature to 400°C, where the room temperature can be 20°C to 30°C, for example, the temperature of the sample stage is 200°C, 250°C, 300°C, 350°C, 400°C, etc.; the sputtering power is 7W to 50W, etc.; the sputtering gas Including but not limited to: at least one of argon, krypton, xenon, neon, and nitrogen, for example, argon Ar is selected as the sputtering gas.
  • the magnetron sputtering method can be DC magnetron sputtering or radio frequency magnetron sputtering.
  • phase-change memory chip also provided by the embodiments of the present disclosure is based on the use of any of the above-mentioned phase-change films, so that the phase-change memory chip has at least the following advantages:
  • the phase change material layer 101 adopts Sb n X m material, wherein, n:m ⁇ 1:1, X includes at least one of Te, Sn, Se, Ni, Nb, Zr, Y, so that the phase change material Layer 101 can maintain the advantages of Sb material, which is manifested as higher SET speed and higher cycle life.
  • the existence of X element can also overcome the cluster aggregation failure, interface void and poor interface adhesion caused by Sb itself.
  • the problem is to prevent Sb from forming a large grain set-stuck, improve the thermal stability of Sb, and then increase the service life of the phase change memory unit.
  • the doping amount of element X (Te, Sn, Se, Ni, Nb, Y, etc.) Excellent time delay and anti-fatigue performance make the phase change memory unit more adaptable to high temperature environment.
  • the lattice mismatch between the template material and the Sbn ⁇ m material is less than or equal to 10%, so that the template layer 102 provides a crystallization template, so that the phase change material layer 101 can grow from the interface of the template layer 102 by epitaxial growth.
  • Performing crystallization and using the template layer 102 as a crystal growth template is beneficial to significantly reduce the crystallization time, increase the phase change speed of the phase change material layer 101, and further increase the read and write speed of the phase change memory chip.
  • the template layer 102 will maintain a stable crystal structure, which effectively prevents the element migration of the phase change material in the direction of the electric field, which is beneficial to improve the cycle life of the phase change material, and thus improve the phase change storage capacity. unit cycle life.
  • the phase-change material layer 101 can be designed as two layers or more than two layers, so that the phase-change film 1 can be layered and phase-transformed to obtain the ability of multi-level storage, so that the storage unit can realize multi-value storage, which is conducive to improving phase-change storage.
  • the data storage density of the chip can be designed as two layers or more than two layers, so that the phase-change film 1 can be layered and phase-transformed to obtain the ability of multi-level storage, so that the storage unit can realize multi-value storage, which is conducive to improving phase-change storage.
  • the phase-change memory cell involved in the embodiment of the present disclosure, as shown in accompanying drawings 2-4, the phase-change memory cell includes a substrate 2, a top electrode 32, and a bottom electrode 31 in addition to the above-mentioned phase-change film 1 , insulating heat insulating layer 4; Wherein, bottom electrode 31 is positioned at the surface of substrate 2; Phase-change film 1 is connected between bottom electrode 31 and top electrode 32; .
  • a direction close to the substrate 2 is defined as a bottom direction, and a direction away from the substrate 2 is defined as a top direction.
  • the structure of the phase-change memory cell includes, but is not limited to: a restricted structure, a T-type structure, etc.
  • FIG. 2 illustrates a phase change memory cell of a confinement type structure, as shown in accompanying drawing 2, the direction from top to bottom, top electrode 32, phase change thin film 1, bottom electrode 31, substrate 2 contact sequentially, Moreover, the insulation and heat insulation layer 4 covers the side of the phase change film 1 and is located between the bottom electrode 31 and the top electrode 32 .
  • the bottom layer of the phase change film 1 can be the phase change material layer 101 or the template layer 102, and the type of the bottom layer of the phase change film 1 can be adaptively selected according to the specific type of the bottom electrode 31
  • FIG. 2 shows that the lowest layer of the phase change thin film 1 is a phase change material layer 101 .
  • the topmost layer of the phase change film 1 can be a phase change material layer 101, or a template layer 102. According to the specific type of the top electrode 32, the type of the bottom layer of the phase change film 1 can be adaptively selected, for example, as shown in FIG. 2 The topmost layer beyond the phase change film 1 is the template layer 102 .
  • phase-change memory cell with a confinement structure
  • the number of phase-change material layers 101 that undergo phase change can be changed, for example, along the direction from the bottom to the top, only the bottom phase-change material layer can be 101 undergoes a phase change, or two layers of phase change material layers 101 can also undergo a phase change, or three layers of phase change material layers 101 can also undergo a phase change, etc., so that the phase change memory cell can achieve a layered phase change Effect, with the ability of multi-level storage.
  • phase-change memory cell of this restricted structure it can be prepared by the following method:
  • a cleaned substrate 2 is provided, and a bottom electrode 31 is formed on the surface of the substrate 2 .
  • An insulating spacer is formed on the surface of the bottom electrode 31
  • the thermal layer 4 is such that the insulating and heat insulating layer 4 completely covers the bottom electrode 31 .
  • the phase change film 1 is formed in the heat insulation hole of the heat insulation layer 4 .
  • a top electrode 32 is formed on the top surfaces of the phase-change film 1 and the insulating and heat-insulating layer 4 to obtain the phase-change memory unit of the confinement structure.
  • phase-change memory unit of this confinement structure comprises: phase-change film 1, substrate 2, top electrode 32, bottom electrode 31. Insulation and heat insulation layer 4, heating electrode 5; in the direction from top to bottom, the top electrode 32, phase change film 1, heating electrode 5, bottom electrode 31, and substrate 2 are in sequential contact, and the insulation and heat insulation layer 4 Covered on the sides of the phase change film 1 and the heating electrode 5 , and located between the bottom electrode 31 and the top electrode 32 .
  • the heater electrode 5 is used instead of the bottom electrode 31 to contact the bottom surface of the phase change film 1 .
  • Using the heating electrode 5 can enable the phase change material layer 101 to obtain higher heating efficiency, reduce heat dissipation, and further improve the phase change speed.
  • phase-change memory cell with a confined structure of the heating electrode 5 it can be prepared by the following method:
  • a cleaned substrate 2 is provided, and a bottom electrode 31 is formed on the surface of the substrate 2 .
  • the insulating and heat insulating layer 4 is formed on the surface of the bottom electrode 31 so that the insulating and heat insulating layer 4 completely covers the bottom electrode 31 .
  • the heater electrode 5 is formed in the heat insulating hole. According to the preparation method of the phase change film 1 , continue to form the phase change film 1 on the heating electrode 5 .
  • a top electrode 32 is formed on the top surfaces of the phase-change film 1 and the insulating and heat-insulating layer 4 to obtain the phase-change memory unit of the confinement structure.
  • phase-change memory unit of T-type structure comprises: Phase-change film 1, substrate 2, top electrode 32, bottom electrode 31 1. Insulation and heat insulation layer 4; wherein, the substrate 2 has a through hole, and the bottom electrode 31 is located in the through hole on the substrate 2; the top electrode 32, the phase change film 1, and the substrate 2 are in contact with each other in turn, and the phase change film 1 is also connected to the bottom electrode 31; the insulating and heat insulating layer 4 is wrapped around the peripheral side of the phase change film 1.
  • the bottom layer of the phase change film 1 can be the phase change material layer 101, or the template layer 102.
  • FIG. 4 shows that the bottom layer of the phase change film 1 is the phase change material layer 101;
  • the topmost layer of the phase change film 1 may be the phase change material layer 101 or the template layer 102 , for example, FIG. 4 shows that the topmost layer of the phase change film 1 is the template layer 102 .
  • phase change material layers 101 undergoing phase change can be changed. For example, along the direction from the bottom to the top, only the bottommost phase change material layer 101 can be phase changed, or two layers of phase change material layers 101 can be phase changed, or three layers of phase change material layers 101 can be phase changed. Layer 101 undergoes a phase change, etc., so that the phase change memory cell achieves the effect of layered phase change, and has the capability of multi-level storage.
  • phase-change memory unit of this T-shaped structure it can be prepared by the following method:
  • a through hole is formed on the substrate 2, and then a bottom electrode 31 is formed in the through hole, and the top surfaces of the substrate 2 and the bottom electrode 31 are made to be flat.
  • the phase change film 1 is formed on the top surfaces of the substrate 2 and the bottom electrode 31 .
  • the top electrode 32 is formed on the top surface of the phase change film 1 .
  • the insulating and heat insulating layer 4 is formed in the etching space until the insulating and heat insulating layer 4 completely covers the top electrode 32 and the phase change film 1 .
  • Etching is performed on the top of the insulating and heat insulating layer 4 to expose the top electrode 32 to obtain the T-shaped phase-change memory cell.
  • the substrate 2 its material includes but not limited to: silicon dioxide, silicon carbide, silicon wafer, sapphire, diamond and so on.
  • the surface of the substrate 2 can be cleaned with an organic solvent, such as ethanol and/or acetone, to remove impurities on the surface. After cleaning, the substrate 2 can be dried in an oven at 50°C-100°C.
  • top electrode 32 and the bottom electrode 31 its materials include but not limited to: titanium tungsten (TiW), tungsten (W), aluminum (Al), Titanium nitride (TiN), titanium (Ti), tantalum (Ta), silver (Ag), platinum (Pt), carbon (C), copper (Cu), ruthenium (Ru), gold (Au), cobalt (Co ), chromium (Cr), nickel (Ni), iridium (Ir), palladium (Pd), rhodium (Rh), etc.
  • the insulating heat insulating layer 4 its function includes the following: first, the phase change film 1 is restricted in the heat insulating hole on it, to reduce the heat required for the phase change, which is beneficial to reduce the power consumption of the phase change memory chip; Second, the short circuit between the top electrode 32 and the bottom electrode 31 can be avoided.
  • the insulating and heat insulating material used for the insulating and heat insulating layer 4 includes but not limited to: silicon nitride (Si 3 N 4 ), silicon dioxide (SiO 2 ) and the like.
  • the heating electrode 5 its material includes but not limited to: titanium nitride (TiN), tungsten (W), trititanium heptatungsten (Ti 3 W 7 ) and the like.
  • an embodiment of the present disclosure also provides a method for preparing a phase-change memory chip, wherein the phase-change memory chip is as described above, and the method for preparing the phase-change memory chip includes: preparing a phase-change memory unit, which It also includes forming a phase change thin film 1 .
  • the forming phase change film 1 includes: providing Sb n X m material and template material; according to the stacking sequence of phase change material layer 101 and template layer 102 in phase change film 1, using Sb n X m material and template material, by film deposition The process alternately forms the phase change material layer 101 and the template layer 102 .
  • the thin film deposition processes used include, but are not limited to, the following: atomic layer deposition, physical vapor deposition, chemical vapor deposition, and the like.
  • Magnetron sputtering is a physical vapor deposition process.
  • the phase change film 1 is prepared by using the magnetron sputtering process.
  • some applicable magnetron sputtering parameters are as follows:
  • the background vacuum is 10 -3 Pa ⁇ 10 -5 Pa, for example, 1 ⁇ 10 -4 Pa ⁇ 5 ⁇ 10 -4 Pa; the sputtering pressure is 0.3Pa ⁇ 0.8Pa, etc.; the substrate temperature, that is, the temperature of the sample stage Room temperature to 400°C, where the room temperature can be 20°C to 30°C, for example, the temperature of the sample stage is 200°C, 250°C, 300°C, 350°C, 400°C, etc.; the sputtering power is 7W to 50W, etc.; the sputtering gas Including but not limited to: at least one of argon, krypton, xenon, neon, and nitrogen, for example, argon Ar is selected as the sputtering gas.
  • the magnetron sputtering method can be DC magnetron sputtering or radio frequency magnetron sputtering.
  • the phase-change memory cell provided by the embodiment of the present disclosure includes, in addition to the above-mentioned phase-change film 1, a substrate 2, a top electrode 32, a bottom electrode 31, an insulating and heat-insulating layer 4, and an optional heating element. Electrode 5.
  • phase change memory cell may be a restricted structure or a T-shaped structure
  • preparation method of the phase-change memory cell with the restricted structure or T-shaped structure may refer to the preparation methods shown above, and will not be repeated here.
  • the phase change film 1 may also be polished so as to grow the top electrode 32 on the phase change film 1 .
  • phase-change memory chip provided by the embodiments of the present disclosure can be used as an independent memory, or can be used together with a dynamic random access memory as a hybrid memory.
  • the phase-change memory chip provided by the embodiments of the present disclosure has at least the following advantages: fast reading and writing speed, high stability, strong temperature resistance, high cycle life, and high-density multi-valued storage.
  • a phase-change memory chip generally includes a plurality of phase-change memory cells 100 and read/write circuits (including word lines 201 and bit lines 202) to form a phase-change memory array, further, as shown in Figure 6 or As shown in FIG. 7 , the phase-change memory chip may further include transistors 300 , diodes 400 , etc., to cooperate with the phase-change memory unit 100 to form phase-change memory chips with different structures.
  • the structure of the phase-change memory chip involved in the embodiments of the present disclosure includes, but is not limited to: 1R structure, 1T1R structure, or 1D1R structure, etc., which are illustrated as follows:
  • Accompanying drawing 5 shows a kind of 1R (One Resistor) structure, as shown in accompanying drawing 5, independent phase-change memory unit 100 cooperates with read-write circuit, wherein, two electrodes of phase-change memory unit 100 are respectively connected to read and write The word line 201 and the bit line 202 of the write circuit.
  • 1R One Resistor
  • each phase-change memory cell 100 all connects a transistor 300 in series, and on this basis again with the word line 201 of read-write circuit It is connected to the bit line 202.
  • the transistor 300 plays the role of gate and isolation. When operating on the target phase-change memory unit 100, its corresponding transistor 300 is turned on, while the transistors 300 corresponding to other phase-change memory units 100 are turned off, which can avoid affecting the surrounding phase-change memory.
  • the unit 100 generates crosstalk and misoperation, and plays an isolation role.
  • each phase-change memory unit 100 all connects a rectifying diode 400 in series, on this basis again with the word of read-write circuit Line 201 and bit line 202 are connected.
  • the 1D1R structure uses a diode 400 to select the phase-change memory unit 100 to be operated. Due to the rectification effect of the diode 400, the current can only flow through the corresponding phase-change memory unit 100 from one direction, thereby suppressing the crosstalk in the phase-change memory array. Phenomenon.
  • an embodiment of the present disclosure further provides a storage device, the storage device includes a controller and any phase-change memory chip described above, and the controller is used to store data in the phase-change memory chip. As shown in Figure 8, the controller reads and writes the data stored in the storage device, and communicates interactively with the external interface.
  • the storage device (also referred to as memory) may be configured to store various types of data, such as contact data, phonebook data, messages, pictures, videos, etc., and may also be instructional data.
  • the storage devices involved in the embodiments of the present disclosure may be configured in various types, for example, including but not limited to: memory, hard disk, magnetic disk, optical disk, and so on.
  • an embodiment of the present disclosure further provides an electronic device, where the electronic device includes a processor and the above-mentioned storage device, and the processor is configured to store data generated by the electronic device in the storage device.
  • the electronic devices include, but are not limited to: computers, cell phones, music playback devices, digital broadcasting devices, messaging devices, game control devices, medical devices, fitness devices, personal digital assistants, and the like.
  • This embodiment provides a phase-change memory cell with a confinement structure.
  • the structure of the phase-change memory cell is shown in FIG.
  • the substrates 2 are sequentially contacted, and the insulating and heat insulating layer 4 covers the side of the phase change film 1 and is located between the bottom electrode 31 and the top electrode 32 .
  • the phase-change thin film 1 includes: alternately stacked phase-change material layers 101 and template layers 102 , and the cycle number of alternately stacking the phase-change material layers 101 and the template layers 102 is 10.
  • the phase change material layer 101 is formed of Sb 2 Te material
  • the template layer 102 is formed of TiTe 2 material.
  • the phase change film 1 is prepared by radio frequency magnetron sputtering process, and the involved magnetron sputtering parameters are as follows: background vacuum degree is 2 ⁇ 10 -4 Pa ⁇ 3 ⁇ 10 -4 Pa; sputtering pressure is 0.5Pa; sample stage temperature is 250°C; sputtering power is 30W; The sputtering gas was argon.
  • phase-change memory array is prepared based on the phase-change memory unit, and the cycle life test of the phase-change memory array is performed, as follows:
  • the phase-change memory array was annealed at 370°C, and then read and written at a speed of 10 ns to obtain its cycle life.
  • the cycle life distribution diagram obtained from the test is shown in FIG. 9 . It can be seen from Figure 9 that the maximum cycle life of the phase change memory array is greater than 1E9 (ie 10 9 ) times, and the median cycle life of the phase change memory array is greater than 1E8 (ie 10 8 ) times, it can be seen that based on the embodiment of the present disclosure
  • the provided phase change memory array of the phase change thin film 1 exhibits excellent cycle life.
  • phase change material layer 101 is replaced by Sb 2 Te material with Sb 2 Sn, Sb 2 Se, Sb 2 Ni, Sb 3 Nb, Sb 3 Zr, Sb 2 Y, the obtained phase change memory
  • the arrays also exhibited excellent cycle life.

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Abstract

本申请公开了相变材料、相变存储芯片、存储设备及电子设备,属于半导体存储技术领域。该相变材料包括SbnXm材料,其中,n:m≥1:1;元素X的原子半径与元素Sb的原子半径的差值满足第一阈值条件,使得元素X能够与元素Sb形成弱极性键;以及,元素X的热稳定性参数满足第二阈值条件,使得元素X在元素Sb的相变温度下保持稳定。该相变材料用于相变存储芯片时,利于提高相变存储芯片的SET速度和循环寿命,使得相变存储芯片达到内存级数据存储所要求的读写速度和循环寿命成为可能。

Description

相变材料、相变存储芯片、存储设备及电子设备
本申请要求于2022年1月30日提交中国专利局、申请号为202210114235.8、发明名称为“一种相变存储器”的中国专利申请的优先权,以及于2022年03月17日提交的申请号为202210266567.8、发明名称为“相变材料、相变存储芯片、存储设备及电子设备”的中国专利申请的优先权,前述两件专利申请的全部内容通过引用结合在本申请中。
技术领域
本公开涉及半导体存储技术领域,特别涉及相变材料、相变存储芯片、存储设备及电子设备。
背景技术
相变材料在晶态下表现为低电阻率,在非晶态下表现为高电阻率,相变存储器(Phase change memory,PCM)基于相变材料在晶态和非晶态之间的电阻差异来实现数据的存储和擦写。其中,相变材料对于相变存储芯片的读写速度和循环寿命具有重要的影响。
相关技术多采用Sb2Te3材料作为相变材料,然而,基于Sb2Te3材料制备得到的相变存储器,在读写速度和循环寿命方面还有待提高。
发明内容
鉴于此,本公开提供了相变材料、相变存储芯片、存储设备及电子设备,能够解决上述技术问题。
具体而言,包括以下的技术方案:
一方面,提供了一种相变材料,所述相变材料包括SbnXm材料,其中,n:m≥1:1;
元素X的原子半径与元素Sb的原子半径的差值满足第一阈值条件,使得所述元素X能够与所述元素Sb形成弱极性键;以及,所述元素X的热稳定性参数满足第二阈值条件,使得所述元素X在所述元素Sb的相变温度下保持稳定。
本公开实施例将原子百分含量n:m≥1:1的SbnXm材料作为相变材料,使Sb元素的原子百分含量大于或等于掺杂元素X的原子百分含量,这样,具有较高的SET速度及高疲劳特性的Sb元素作为主材料,掺杂元素X作为补充材料。由于掺杂元素X的原子半径与Sb的原子半径的差值满足第一阈值条件,使得元素X与Sb形成弱极性键,由于弱极性键的存在,一方面抑制了Sb-Sb之间聚集并形成大晶粒,进而避免Sb形成大晶粒set-stuck,另一方面还防止成键过强使得Sb失去相变的能力,使得SbnXm材料能保持Sb元素的优点,同时避免其缺点,表现为较高的SET速度和循环寿命。并且,元素X在元素Sb的相变温度下保持稳定,进而改善该SbnXm材料的热稳定性,这也利于提高SbnXm材料的循环寿命。可见,本公开实施例提供的相变材料用于相变存储芯片时,利于提高相变存储芯片的SET速度和循环寿命,使得相变存储芯片达到内存级数据存储所要求的读写速度和循环寿命成为可能。
在一些可能的实现方式中,所述第一阈值条件包括所述差值小于或等于使元素X与元素Sb的原子半径尽可能地接近,使得两者之间形成弱极性键。
所述第二阈值条件包括所述元素X在400℃下的耐受时间大于或等于30分钟,确保元素X具有优异的热稳定性。
在一些可能的实现方式中,所述元素X包括Te、Sn、Se、Ni、Nb、Zr、Y中的至少一种。其中,X可以为Te、Sn、Se、Ni、Nb、Zr、Y中的一种、任意两种、任意三种、或者更多种。
在一些可能的实现方式中,1:0.2≥n:m≥1:1,Sb与X的原子比在上述范围内,不仅能确保相变存储单元具有较高的SET速度和循环寿命,还使得该相变存储单元具有良好的热稳定性。
在一些可能的实现方式中,所述SbnXm材料为Sb-X合金形式、Sb-X二元化合物形式、或者Sb单质与X单质的混合物形式。
另一方面,提供了一种相变存储芯片,所述相变存储芯片包括:多个相变存储单元,每个所述相变存储单元具有相变薄膜,所述相变薄膜包括:交替层叠的相变材料层和模板层;
所述相变材料层由上述任一种相变材料形成;
所述模板层由模板材料形成,所述模板材料与所述SbnXm材料的晶格失配度满足第三阈值条件,使得所述模板层能够作为所述相变材料层的结晶模板。
本公开实施例提供的相变存储芯片,其相变薄膜使相变材料层与模板层交替层叠,其中,相变材料层由SbnXm材料形成。通过选用SET速度更快及高疲劳特性(即循环寿命更高)的Sb作为主相变材料,并在Sb中掺杂热稳定性高的掺杂元素X,使得相变材料层表现为较高的SET速度和循环寿命。通过使用模板层102来提供结晶模板,利于进一步提高相变存储单元的SET速度和循环寿命。综上可知,基于SbnXm材料的相变材料层101和模板层102的配合,利于显著提高本公开实施例相变存储芯片的SET速度和循环寿命,使得相变存储芯片达到内存级数据存储所要求的读写速度和循环寿命成为可能。
在一些可能的实现方式中,所述相变材料层的厚度为1nm~100nm;
所述模板层的厚度为1nm~10nm。
在一些可能的实现方式中,所述相变材料层与所述模板层交替层叠的循环数目为1~100,例如为2~100、2~90、2~80、2~70、2~60、2~50、2~40等。
在一些可能的实现方式中,所述第三阈值条件包括所述晶格失配度小于或等于10%,举例来说,模板材料与SbnXm材料的晶格失配度小于或等于8%,进一步地,小于或等于5%、小于或等于4%、小于或等于3%、小于或等于2%、小于或等于1%、小于或等于0.5%等,以使相变材料获得更快的结晶速度。
在一些可能的实现方式中,所述模板材料包括TiTe2、Ti-Sb-Te三元化合物中的至少一种。
选用TiTe2、Ti-Sb-Te三元化合物作为模板材料,至少具有以下优点:
其一,TiTe2和Ti-Sb-Te与SbnXm材料具有晶格匹配度高的优点,即,晶格失配度较低,两者之间存在的这种更小的晶格常数差异,能够为相变材料层101的结晶提供动力,提高相变材料层101结晶速度和结晶时形成的晶态结构的稳定性。
其二,TiTe2和Ti-Sb-Te具有较高的热稳定性,基于它们的模板层102在相变材料层101的工作过程中保持稳定不变,利于增强相变存储单元的循环寿命。
其三,当相变材料层101中的Sb在高温环境发生扩散时,基于Ti-Sb-Te的模板层102能够自发抑制Sb浓度差带来的扩散,使得相变材料层101在高温环境下更稳定,表现为更高的抗高温能力,这也对于增强相变存储单元的循环寿命是极为有利的。
在一些可能的实现方式中,所述相变存储单元还包括:衬底、底电极、顶电极、绝缘隔热层;
所述底电极位于所述衬底的表面;
所述相变薄膜连接于所述底电极和所述顶电极之间;
所述绝缘隔热层包覆于所述相变薄膜的侧部。
其中,相变存储单元的结构包括但不限于:限制型结构、T型结构等。
再一方面,本公开实施例提供了一种存储设备,所述存储设备包括控制器及上述任一种相变存储芯片,所述控制器用于存储数据至所述相变存储芯片。
基于使用了上述相变存储芯片,本公开实施例提供的相变存储芯片至少具有以下优点:读写速度快、稳定性高、耐温性强、循环寿命高、能够实现高密度多值存储等。
再一方面,本公开实施例提供了一种电子设备,所述电子设备包括处理器及上述的存储设备,所述处理器用于存储所述电子设备产生的数据至所述存储设备。
在一些示例中,该电子设备包括但不限于:计算机、手机、音乐播放设备、数字广播设备、消息收发设备、游戏控制设备、医疗设备、健身设备、个人数字助理等。
附图说明
图1为本公开实施例提供的一示例性相变薄膜的结构示意图;
图2为本公开实施例提供的一示例性限制型结构的相变存储单元的结构示意图;
图3为本公开实施例提供的另一示例性限制型结构的相变存储单元的结构示意图;
图4为本公开实施例提供的一示例性T型结构的相变存储单元的结构示意图;
图5为本公开实施例提供的一示例性相变存储芯片1R结构示意图;
图6为本公开实施例提供的一示例性相变存储芯片1T1R结构示意图;
图7为本公开实施例提供的一示例性相变存储芯片1D1R结构示意图;
图8为本公开实施例提供的一示例性相变存储芯片在电子设备中的应用场景示意图;
图9为本公开实施例提供的基于相变薄膜的相变存储阵列的循环寿命分布图。
附图标记分别表示:
100-相变存储单元,
1-相变薄膜,101-相变材料层,102-模板层,
2-衬底,31-底电极,32-顶电极,
4-绝缘隔热层,5-加热电极,
201-字线,202-位线,300-晶体管,400-二极管。
具体实施方式
为使本公开的技术方案和优点更加清楚,下面将结合附图对本公开实施方式作进一步地详细描述。
相变存储器(Phase change memory,PCM),又称为相变存储芯片,是一种固态半导体非易失性存储器,其以相变材料作为存储介质,相变材料能够在晶态和非晶态之间进行可逆转变,利用相变材料在非晶态和晶态时对应的高电阻率和低电阻率的差异,相变存储器进而实现数据“0”和“1”的存储。
相变存储器工作过程包括:擦操作(SET)过程和写操作(RESET)过程。SET过程指的是:施加一个宽而弱的电脉冲对相变材料进行加热,使相变材料的温度升高至结晶温度和熔化温度之间,相变材料结晶为有序状态,形成具有低电阻率的晶态,以实现数据“0”的存储。RESET过程指的是,施加一个窄而强的电脉冲对相变材料进行加热,使相变材料的温度升高到熔化温度以上,融化为无序状态,随后经过一个快速冷却的淬火过程(>109K/s),相变材料由熔融态直接进入具有较高电阻率的非晶态,以实现数据“1”的存储。
相变材料对于相变存储器的读写速度和循环寿命具有重要的影响,相关技术相变材料,然而,Sb2Te3材料存在晶化速度不够快,温度稳定性差,疲劳性能低等问题,使得基于Sb2Te3的相变材料制备得到的相变存储器,在读写速度和循环寿命方面还有待提高。其中,此处涉及的循环寿命指的是,将相变存储器置0或置1来进行反复循环操作,相变存储器在失效前所能进行的循环次数。
Sb单质也可以作为相变材料,然而,Sb单质虽然表现为更快的SET操作和更高的循环寿命,但是却容易发生set-stuck等问题,其中,set-stuck指的是,相变材料的电阻值始终保持在低阻态,而无法通过任何RESET操作转变为高阻态。
本公开实施例提供了一种相变材料,该相变材料包括SbnXm材料,其中,n:m≥1:1,元素X的原子半径与元素Sb的原子半径的差值满足第一阈值条件,使得元素X能够与元素Sb形成弱极性键,以及,元素X的热稳定性参数满足第二阈值条件,使得元素X在元素Sb的相变温度下保持稳定。
本公开实施例将原子百分含量n:m≥1:1的SbnXm材料作为相变材料,使Sb元素的原子百分含量大于或等于掺杂元素X的原子百分含量,这样,具有较高的SET速度及高疲劳特性的Sb元素作为主材料,掺杂元素X作为补充材料。由于掺杂元素X的原子半径与Sb的原子半径的差值满足第一阈值条件,使得元素X与Sb形成弱极性键,由于弱极性键的存在,一方面抑制了Sb-Sb之间聚集并形成大晶粒,进而避免Sb形成大晶粒set-stuck,另一方面还防止成键过强使得Sb失去相变的能力,使得SbnXm材料能保持Sb元素的优点,同时避免其缺点,表现为较高的SET速度和循环寿命。并且,元素X在元素Sb的相变温度下保持稳定,进而改善该SbnXm材料的热稳定性,这也利于提高SbnXm材料的循环寿命。可见,本公开实施例提供的相变材料用于相变存储芯片时,利于提高相变存储芯片的SET速度和循环寿命,使得相变存储芯片达到内存级数据存储所要求的读写速度和循环寿命成为可能。
其中,此处涉及的内存级数据存储指的是,相变存储器对数据的存储,即,对数据的读、写和擦操作速度与动态随机存取存储器(Dynamic Random Access Memory,DRAM)是相当的。
关于掺杂元素X能够避免Sb形成大晶粒set-stuck,这是因为,对于Sb单质材料,Sb-Sb之间为非极性键,该非极性键使得Sb-Sb之间更容易聚集,进而导致大晶粒set-stuck。而本公开实施例提供的SbnXm材料,在Sb材料中掺杂了X材料,使得Sb-X之间形成弱极性键,该弱极性键能够避免Sb-Sb之间的聚集,进而避免主材料Sb形成大晶粒set-stuck。
在一些示例中,期望第一阈值条件包括差值小于或等于即,元素X的原子半径与元素Sb的原子半径的差值满足小于或等于进一步地,小于或等于小于或等于小于或等于等。这样,使元素X与元素Sb的原子半径尽可能地接近,使得两者之间形成弱极性键。
在一些示例中,第二阈值条件包括元素X在400℃下的耐受时间大于或等于30分钟,例如,元素X在400℃下的耐受时间等于30分钟、40分钟、50分钟、60分钟、120分钟或者 以上等,这样,确保元素X具有优异的热稳定性。
在一些示例中,满足上述条件的一些X包括Te(碲)、Sn(锡)、Se(硒)、Ni(镍)、Nb(铌)、Zr(锆)、Y(钇)中的至少一种,即,X可以为Te、Sn、Se、Ni、Nb、Zr、Y中的一种、任意两种、任意三种、或者更多种。
当X为Te、Sn、Se、Ni、Nb、Zr、Y中的两种或两种以上时,将两种或两种以上的元素X的原子百分含量之和作为m,使它们的原子百分含量之和与元素Sb的原子百分含量小于或等于1即可,并且,该两种或两种以上的不同元素X之间可以是任意原子百分比,例如为1:1~10等。
Te、Sn、Se、Ni、Nb、Zr、Y为一类原子半径与Sb原子的原子半径接近的元素,且容易与Sb元素形成弱极性键的元素,以上各类掺杂元素均能够避免Sb材料形成大晶粒set-stuck,且防止与Sb元素成键过强使得Sb材料失去相变的能力。
SbnXm材料中,n:m≥1:1,指的是元素Sb与掺杂元素X的原子比≥1:1,Sb的量大于或等于掺杂元素X的量,以确保相变存储单元具有较高的SET速度和循环寿命。
在一些实现方式中,1:0.2≥n:m≥1:1,举例来说,n:m的数值包括但不限于以下:1:0.2、1:0.25、1:0.28、1:0.3、1:0.32、1:0.35、1:0.37、1:0.4、1:0.43、1:0.45、1:0.48、1:0.5、1:0.51、1:0.52、1:0.53、1:0.54、1:0.55、1:0.56、1:0.58、1:0.6、1:0.65、1:0.7、1:0.75、1:0.8、1:0.85、1:0.87、1:0.9等。
本公开实施例中,期望元素X的掺杂量较少,以确保SbnXm材料能保持Sb自身的优点,表现为较高的SET速度和循环寿命,当然,在一些实际应用场景中,还可以根据环境温度在上述原子比范围为适当上调元素X的掺杂量,这是因为,在一定程度上增加X的掺杂量,可以提高SbnXm材料的热稳定性,使得相变存储单元对高温环境具有更强的适应性。
Sb与X的原子比在上述范围内,不仅能确保相变存储单元具有较高的SET速度和循环寿命,还使得该相变存储单元具有良好的热稳定性。
在一些实现方式中,SbnXm材料可以为Sb-X合金形式,也可以为Sb-X二元化合物形式,还可以为Sb单质与X单质的混合物形式。
在一些示例中,SbnXm材料为Sb-X合金形式,该种情形下,可以采用目前市售的,满足原子比要求的Sb-X合金板进行相变材料层的制备。
在一些示例中,SbnXm材料为Sb单质与X单质的混合物形式,该种情形下,根据SbnXm材料中Sb与X的原子比,将Sb单质与X单质混合均匀,并进行相变材料层的制备。
另一方面,本公开实施例还提供了一种相变存储芯片,该相变存储芯片包括:多个相变存储单元,每个相变存储单元具有相变薄膜1,如附图1所示,该相变薄膜1包括:交替层叠的相变材料层101和模板层102。
其中,相变材料层由上述任一种相变材料形成;模板层102由模板材料形成,模板材料与SbnXm材料的晶格失配度满足第三阈值条件,使得模板层102能够作为相变材料层101的结晶模板。
相变材料层101与模板层102交替层叠,其中,模板层102用于为相变材料层101提供结晶模板,即,为相变材料层101提供晶化生长界面,以加速相变存储单元的擦写速度。并且,相变材料层101被模板层102所约束,在有限的约束空间内,相变材料层101中的SbnXm材料中的Sb很难发生聚集而形成大晶粒,进而能够避免形成大晶粒失效,提高相变存储单元的循环寿命。
本公开实施例中所涉及的“相变材料层101与模板层102交替层叠”,指的是,任意两层相变材料层101之间具有一层模板层102,或者,任意两层模板层102之间具有一层相变材料层101。也就是说,该相变薄膜1为相变材料层101和模板层102交替堆叠形成的一种周期性循环结构,相变材料层101与模板层102形成超晶格相变材料。
本公开实施例提供的相变存储芯片,其相变薄膜1使相变材料层101与模板层102交替层叠,其中,相变材料层101由SbnXm材料形成。通过选用SET速度更快及高疲劳特性(即循环寿命更高)的Sb作为主相变材料,并在Sb中掺杂热稳定性高的掺杂元素X,使得相变材料层101表现为较高的SET速度和循环寿命。通过使用模板层102来提供结晶模板,利于进一步提高相变存储单元的SET速度和循环寿命。综上可知,基于SbnXm材料的相变材料层101和模板层102的配合,利于显著提高本公开实施例相变存储芯片的SET速度和循环寿命,使得相变存储芯片达到内存级数据存储所要求的读写速度和循环寿命成为可能。
对于模板层102,其由模板材料形成,模板层102具有更强的热稳定性,并且,模板材料与SbnXm材料的晶格失配度满足第三阈值条件,这样,模板材料与SbnXm材料的接触晶面的结构相同或者类似,以使两者获得更高的晶格匹配度,确保模板层102能够作为相变材料层101的结晶模板。
本公开实施例中,使第三阈值条件包括晶格失配度小于或等于10%,即,模板材料与SbnXm材料的晶格失配度小于或等于10%,举例来说,模板材料与SbnXm材料的晶格失配度小于或等于8%,进一步地,小于或等于5%、小于或等于4%、小于或等于3%、小于或等于2%、小于或等于1%、小于或等于0.5%等,以使相变材料获得更快的结晶速度。
在一些实现方式中,模板材料包括TiTe2、Ti-Sb-Te三元化合物中的至少一种,其中,Ti-Sb-Te三元化合物又称为Ti-Sb-Te系合金,化学式为SbxTeyTi100-x-y,其中,其中0<x<80,0<y<100-x。
选用TiTe2、Ti-Sb-Te三元化合物作为模板材料,至少具有以下优点:
其一,TiTe2和Ti-Sb-Te与SbnXm材料具有晶格匹配度高的优点,即,晶格失配度较低,两者之间存在的这种更小的晶格常数差异,能够为相变材料层101的结晶提供动力,提高相变材料层101结晶速度和结晶时形成的晶态结构的稳定性。
其二,TiTe2和Ti-Sb-Te具有较高的热稳定性,基于它们的模板层102在相变材料层101的工作过程中保持稳定不变,利于增强相变存储单元的循环寿命。
其三,当相变材料层101中的Sb在高温环境发生扩散时,基于Ti-Sb-Te的模板层102能够自发抑制Sb浓度差带来的扩散,使得相变材料层101在高温环境下更稳定,表现为更高的抗高温能力,这也对于增强相变存储单元的循环寿命是极为有利的。
在一些实现方式中,相变薄膜1中涉及的相变材料层101的厚度范围均为1nm~100nm,例如为1nm、2nm、3nm、4nm、5nm、6nm、7nm、8nm、9nm、10nm、20nm、30nm、40nm、50nm、60nm、70nm、80nm、90nm、100nm等。
当相变材料层101的数目为多层(即,两层或者两层以上)时,多层相变材料层101的厚度可以全部相同,也可以使部分相变材料层101的厚度相同,还可以使全部的相变材料层101的厚度彼此不同。
对于任意层的相变材料层101的厚度,可以根据其发生相变时对应的操作电压或者操作电流的大小来确定。
在一些可能的实现方式中,相变薄膜1中涉及的模板层102的厚度范围均为1nm~10nm,例如为1nm、2nm、3nm、4nm、5nm、6nm、7nm、8nm、9nm、10nm等。
当模板层102的数目为多层(即,两层或者两层以上)时,多层模板层102的厚度可以全部相同,也可以使部分模板层102的厚度相同,还可以使全部的模板层102的厚度彼此不同。
使相变材料层101的厚度和模板层102的厚度在上述范围内,利于使得相变存储单元获得较宽的调节范围。
本公开实施例中,相变材料层101与模板层102交替层叠,以一层相变材料层101和与其层叠的一层模板层102作为一个循环数目(又称为循环数目)。可以使相变材料层101与模板层102交替层叠的循环数目为1~100,例如为2~100、2~90、2~80、2~70、2~60、2~50、2~40等,举例来说,相变材料层101与模板层102交替层叠的循环数目可以为5、10、15、20、25、30、35、40、45、50、55等。
在一些示例中,使相变材料层101为两层或两层以上,使得相变薄膜1能够分层相变,以获得多级存储的能力,利于提高相变存储芯片的数据存储密度。
举例来说,以相变材料层101与模板层102交替层叠的循环数目为5举例来说,该相变薄膜1可以包括依次层叠的第一相变材料层101/第一模板层102/第二相变材料层101/第二模板层102/第三相变材料层101/第三模板层102/第四相变材料层101/第四模板层102/第五相变材料层101,以及进一步可选地,层叠于第五相变材料层101上的第五模板层102。
相变薄膜1中,多层相变材料层101各层所使用的SbnXm材料的种类可以全部相同,也可以部分不同,还可以全部不同。
多层模板层102各层所使用的模板材料的种类可以全部相同,也可以部分不同,还可以全部不同。其中,模板层102的种类须根据与其相邻的相变材料层101的种类进行选择,以确保具有层叠关系的模板层102与相变材料层101之间的晶格失配度小于或等于10%。
在一些示例中,本公开实施例公开了这样一种相变薄膜1,其包括:交替层叠的相变材料层101和模板层102,相变材料层101与模板层102交替层叠的循环数目为2-100。
其中,相变材料层101的厚度为1nm~50nm;模板层102的厚度为1nm~10nm。
对于相变材料层101,其由SbnXm材料形成,SbnXm材料为Sb2Te、SbTe、SbSn、Sb2Sn、Sb3Sn、SbSe、Sb2Se、Sb3Se、SbNi、Sb2Ni、Sb3Ni、SbNb、Sb2Nb、Sb3Nb、SbZr、Sb2Zr、Sb3Zr、SbY、Sb2Y、Sb3Y等。对于模板层102,其由TiTe2或者Ti-Sb-Te三元化合物形成。
本公开实施例涉及的相变薄膜1,可以采用以下制备方法制备得到:
提供SbnXm材料和模板材料;根据相变薄膜1中相变材料层101与模板层102的层叠顺序,利用SbnXm材料和模板材料,通过薄膜沉积工艺交替形成相变材料层101和模板层102。
所涉及的薄膜沉积工艺包括但不限于以下:原子层沉积(atomic layer deposition,ALD)、物理气相沉积(Physical Vapour Deposition,PVD)、化学气相沉积(Chemical Vapor Deposition,CVD)等。
磁控溅射是一种常见的物理气相沉积工艺,本公开实施例中,可以使用磁控溅射工艺来制备相变薄膜1。
在一些示例中,在制备相变薄膜1时,一些适用的磁控溅射参数如下所示:
本底真空度为10-3Pa~10-5Pa,例如为1×10-4Pa~5×10-4Pa;溅射气压为0.3Pa~0.8Pa等;基板温度,也就是样品台温度为室温~400℃,其中,室温可以为20℃~30℃,例如样品台温度为200℃、250℃、300℃、350℃、400℃等;溅射功率为7W~50W等;溅射气体包括但不限于:氩气、氪气、氙气、氖气、氮气中的至少一种,例如,选用氩气Ar作为溅射气体。磁控溅射方式可以为直流磁控溅射,也可以为射频磁控溅射。
本公开实施例还提供的相变存储芯片基于使用了上述涉及的任一种相变薄膜,使得相变存储芯片至少具有以下优点:
(1)相变材料层101采用SbnXm材料,其中,n:m≥1:1,X包括Te、Sn、Se、Ni、Nb、Zr、Y中的至少一种,使得相变材料层101即能够保持Sb材料的优点,表现为更高的SET速度和更高的循环寿命,同时X元素的存在还能够克服Sb本身易引起的团簇聚集失效和界面空洞和界面粘附性差等问题,避免Sb形成大晶粒set-stuck,改善Sb的热稳定性,进而提高相变存储单元的使用寿命。
(2)在特定的原子比范围内,元素X(Te、Sn、Se、Ni、Nb、Y等)向元素Sb中的掺杂量的提高,使得相变存储单元对高温应用场景达到更高的时延和抗疲劳性能,使得相变存储单元对高温环境具有更强的适应性。
(3)模板材料与SbnXm材料的晶格失配度小于或等于10%,使模板层102提供结晶模板,这样,相变材料层101可以通过外延生长的方式从模板层102的界面进行结晶,以模板层102作为结晶生长模板,利于显著降低结晶时间,提高相变材料层101的相变速度,进而提高相变存储芯片的读写速度。另外,相变材料层101发生相变时,模板层102会保持稳定的晶体结构,有效阻止了相变材料在电场方向上的元素迁移,利于提高相变材料的循环寿命,进而提高相变存储单元的循环寿命。
(4)相变材料层101可以设计为两层或两层以上,使得该相变薄膜1能够分层相变,获得多级存储的能力,使得存储单元实现多值存储,利于提高相变存储芯片的数据存储密度。
本公开实施例涉及的相变存储单元,如附图2-附图4所示,该相变存储单元除了包括上述相变薄膜1之外,还包括衬底2、顶电极32、底电极31、绝缘隔热层4;其中,底电极31位于衬底2的表面;相变薄膜1连接于底电极31和顶电极32之间;绝缘隔热层4包覆于相变薄膜1的侧部。
本公开实施例将靠近衬底2的方向定义为底部方向,将远离衬底2的方向定义为顶部方向。
相变存储单元的结构包括但不限于:限制型结构、T型结构等,以下分别对这两类结构的相变存储单元的构成进行示例性描述:
附图2示例了一种限制型结构的相变存储单元,如附图2所示,自顶部到底部的方向,顶电极32、相变薄膜1、底电极31、衬底2顺次接触,并且,绝缘隔热层4包覆于相变薄膜1的侧部,以及位于底电极31和顶电极32之间。
在该实现方式中,相变薄膜1的最底层可以是相变材料层101,也可以是模板层102,根据底电极31的具体类型,来适应性地选择相变薄膜1的最底层的类型,例如,图2示出了相变薄膜1的最底层为相变材料层101。
相变薄膜1的最顶层可以是相变材料层101,也可以是模板层102,根据顶电极32的具体类型,来适应性地选择相变薄膜1的最底层的类型,例如,图2示出了相变薄膜1的最顶层为模板层102。
对于限制型结构的相变存储单元,通过改变操作电压或者操作电流,可以改变发生相变的相变材料层101的数量,例如,沿底部自顶部的方向,可以仅使最底层相变材料层101发生相变,或者,还可以使两层相变材料层101发生相变,或者,还可以使三层相变材料层101发生相变等,使得该相变存储单元达到分层相变的效果,具有多级存储的能力。
对于该限制型结构的相变存储单元,其可以通过以下方法制备得到:
提供清洗干净的衬底2,在衬底2的表面形成底电极31。在底电极31的表面形成绝缘隔 热层4,使绝缘隔热层4全部覆盖底电极31。对绝缘隔热层4进行刻蚀,特别地,将绝缘隔热层4上对应于隔热孔的部分刻蚀掉,并暴露出底电极31,这样能够在绝缘隔热层4中形成隔热孔。在隔热层4的隔热孔内形成相变薄膜1。在相变薄膜1、绝缘隔热层4的顶部表面形成顶电极32,得到该限制型结构的相变存储单元。
附图3示例了另一种限制型结构的相变存储单元,如附图3所示,该限制型结构的相变存储单元包括:相变薄膜1、衬底2、顶电极32、底电极31、绝缘隔热层4、加热电极5;自顶部到底部的方向,顶电极32、相变薄膜1、加热电极5、底电极31、衬底2顺次接触,并且,绝缘隔热层4包覆于相变薄膜1和加热电极5的侧部,且位于底电极31和顶电极32之间。
在该限制型结构的相变存储单元中,使用加热电极5,而并非使用底电极31来与相变薄膜1的底部表面接触。使用加热电极5能够使相变材料层101获得更高的发热效率,减少热散,利于进一步提高相变速度。
对于该类具有加热电极5的限制型结构的相变存储单元,其可以通过以下方法制备得到:
提供清洗干净的衬底2,在衬底2的表面形成底电极31。在底电极31的表面形成绝缘隔热层4,使绝缘隔热层4全部覆盖底电极31。对绝缘隔热层4进行刻蚀,特别地,将绝缘隔热层4上对应于隔热孔的部分刻蚀掉,并暴露出底电极31,这样能够在绝缘隔热层4中形成隔热孔。在隔热孔内形成加热电极5。按照相变薄膜1的制备方法,继续在加热电极5上形成相变薄膜1。在相变薄膜1、绝缘隔热层4的顶部表面形成顶电极32,得到该限制型结构的相变存储单元。
附图4示例了一种T型结构的相变存储单元,如附图4所示,该T型结构的相变存储单元包括:相变薄膜1、衬底2、顶电极32、底电极31、绝缘隔热层4;其中,衬底2上具有通孔,底电极31位于衬底2上的通孔内;顶电极32、相变薄膜1、衬底2依次接触,并且,相变薄膜1还与底电极31连接;绝缘隔热层4包覆于相变薄膜1的周侧。
在该实现方式中,相变薄膜1的最底层可以是相变材料层101,也可以是模板层102,例如,图4示出了相变薄膜1的最底层为相变材料层101;相变薄膜1的最顶层可以是相变材料层101,也可以是模板层102,例如,图4示出了相变薄膜1的最顶层为模板层102。
对于该类结构,通过改变操作电压或者操作电流,可以改变发生相变的相变材料层101的数量。例如,沿底部自顶部的方向,可以仅使最底层的相变材料层101发生相变,或者,还可以使两层相变材料层101发生相变,或者,还可以使三层相变材料层101发生相变等,使得该相变存储单元达到分层相变的效果,具有多级存储的能力。
对于该T型结构的相变存储单元,可以通过以下方法制备得到:
在衬底2上形成通孔,然后在通孔内形成底电极31,并使衬底2和底电极31的顶部表面持平。按照相变薄膜1的制备方法,在衬底2和底电极31的顶部表面形成相变薄膜1。继续在相变薄膜1的顶部表面形成顶电极32。对顶电极32和相变薄膜1的侧部进行刻蚀,直至暴露衬底2,形成刻蚀空间。在刻蚀空间内形成绝缘隔热层4,直至绝缘隔热层4将顶电极32和相变薄膜1完全包覆。对绝缘隔热层4的顶部进行刻蚀,以暴露顶电极32,得到该T型结构的相变存储单元。
对于衬底2,其材质包括但不限于:二氧化硅、碳化硅、硅片、蓝宝石、金刚石等。在用于制备相变存储单元时,可以采用有机溶剂,例如乙醇和/或丙酮等将衬底2的表面清洗干净,以除去表面的杂质。清洗完毕,将衬底2置于烘箱中于50℃-100℃下干燥即可。
对于顶电极32和底电极31,其材质包括但不限于:钨化钛(TiW)、钨(W)、铝(Al)、 氮化钛(TiN)、钛(Ti)、钽(Ta)、银(Ag)、铂(Pt)、碳(C)、铜(Cu)、钌(Ru)、金(Au)、钴(Co)、铬(Cr)、镍(Ni)、铱(Ir)、钯(Pd)、铑(Rh)等。
对于绝缘隔热层4,其作用包括以下:其一,使得相变薄膜1被限制在其上的隔热孔内,以降低相变所需的热量,利于降低相变存储芯片的功耗;其二,能够避免顶电极32和底电极31发生短路。
示例性地,绝缘隔热层4所采用的绝缘隔热材料包括但不限于:氮化硅(Si3N4)、二氧化硅(SiO2)等。
对于加热电极5,其材质包括但不限于:氮化钛(TiN)、钨(W)、七钨化三钛(Ti3W7)等。
另一方面,本公开实施例还提供了一种相变存储芯片的制备方法,其中,该相变存储芯片如上述所示,该相变存储芯片的制备方法包括:制备相变存储单元,这又包括形成相变薄膜1。
该形成相变薄膜1包括:提供SbnXm材料和模板材料;根据相变薄膜1中相变材料层101与模板层102的层叠顺序,利用SbnXm材料和模板材料,通过薄膜沉积工艺交替形成相变材料层101和模板层102。
所使用的薄膜沉积工艺包括但不限于以下:原子层沉积、物理气相沉积、化学气相沉积等。磁控溅射是一种物理气相沉积工艺,本公开实施例中,使用磁控溅射工艺来制备相变薄膜1。
在一些示例中,在制备相变薄膜1时,一些适用的磁控溅射参数如下所示:
本底真空度为10-3Pa~10-5Pa,例如为1×10-4Pa~5×10-4Pa;溅射气压为0.3Pa~0.8Pa等;基板温度,也就是样品台温度为室温~400℃,其中,室温可以为20℃~30℃,例如样品台温度为200℃、250℃、300℃、350℃、400℃等;溅射功率为7W~50W等;溅射气体包括但不限于:氩气、氪气、氙气、氖气、氮气中的至少一种,例如,选用氩气Ar作为溅射气体。磁控溅射方式可以为直流磁控溅射,也可以为射频磁控溅射。
基于上述可知,本公开实施例提供的相变存储单元,除了包括上述相变薄膜1之外,还包括衬底2、顶电极32、底电极31、绝缘隔热层4、以及可选的加热电极5。
上述相变存储单元可以是限制型结构或者T型结构,该限制型结构或者T型结构的相变存储单元的制备方法可参见上述所示的各制备方式,在此不再赘述。
在一些示例中,在形成相变薄膜1后,还可以对相变薄膜1进行抛光,以便于在相变薄膜1上生长顶电极32。
本公开实施例提供的相变存储芯片可以作为单独的内存进行使用,也可以与动态随机存取存储器共同作为混合内存进行使用。
基于使用了上述相变存储单元,本公开实施例提供的相变存储芯片至少具有以下优点:读写速度快、稳定性高、耐温性强、循环寿命高、能够实现高密度多值存储等。
如附图5所示,相变存储芯片通常包括多个相变存储单元100和读写电路(包括字线201和位线202),以形成相变存储阵列,进一步地,如附图6或者附图7所示,相变存储芯片还可以包括晶体管300、二极管400等,以与相变存储单元100配合作用,形成不同结构的相变存储芯片。
举例来说,本公开实施例涉及的相变存储芯片的结构包括但不限于:1R结构、1T1R结构或者1D1R结构等,以下分别进行示例性说明:
附图5示出了一种1R(One Resistor)结构,如附图5所示,单独的相变存储单元100与读写电路相配合,其中,相变存储单元100的两个电极分别连接读写电路的字线201和位线202。
附图6示出了一种1T1R(One Transistor One Resistor)结构,如附图6所示,每一个相变存储单元100均串联一个晶体管300,在此基础上再与读写电路的字线201和位线202相连接。
晶体管300起到选通和隔的作用,当对目标相变存储单元100操作时,其对应的晶体管300导通,而其他相变存储单元100对应的晶体管300关闭,能够避免对周围相变存储单元100产生串扰和误操作,起到隔离作用。
附图7示出了一种1D1R(One Diode One Resistor)结构,如附图7所示,每一个相变存储单元100均串联一个整流用二极管400,在此基础上再与读写电路的字线201和位线202相连接。1D1R结构采用二极管400来选择所需操作的相变存储单元100,由于二极管400的整流作用,电流只能从一个方向流过对应的相变存储单元100,来抑制了相变存储阵列中的串扰现象。
再一方面,本公开实施例还提供了一种存储设备,该存储设备包括控制器和上述的任一种相变存储芯片,控制器用于存储数据至相变存储芯片。如附图8所示,控制器对存储设备中保存的数据进行读写,并和外部接口进行交互通讯。
该存储设备(又可以称为存储器),可以被配置为存储各种类型的数据,这些数据可以为联系人数据,电话簿数据,消息,图片,视频等,也可以为指令性数据。
本公开实施例涉及的存储设备可以设置成各种类型,例如,这包括但不限于:内存、硬盘、磁盘、光盘等。
再一方面,本公开实施例还提供了一种电子设备,该电子设备包括处理器和上述的存储设备,处理器用于存储电子设备产生的数据至存储设备。
在一些示例中,该电子设备包括但不限于:计算机、手机、音乐播放设备、数字广播设备、消息收发设备、游戏控制设备、医疗设备、健身设备、个人数字助理等。
下面将通过更具体的实施例进一步地描述本公开,虽然下面描述了一些具体的实施方式,然而应该理解,可以以各种形式实现本公开而不应被这里阐述的实施例所限制。实施例中未注明具体技术或条件者,按照本领域内的文献所描述的技术或条件或者按照产品说明书进行,所用试剂或仪器未注明生产厂商者,均可以为可以通过市购获得的常规产品。
实施例
本实施例提供了一种限制型结构的相变存储单元,该相变存储单元的结构如附图2所示,自顶部到底部的方向,顶电极32、相变薄膜1、底电极31、衬底2顺次接触,并且,绝缘隔热层4包覆于相变薄膜1的侧部,以及位于底电极31和顶电极32之间。
其中,相变薄膜1包括:交替层叠的相变材料层101和模板层102,相变材料层101与模板层102交替层叠的循环数目为10。其中,相变材料层101由Sb2Te材料形成,模板层102由TiTe2材料形成。
该相变薄膜1采用射频磁控溅射工艺制备得到,所涉及的磁控溅射参数如下所示:本底真空度为2×10-4Pa~3×10-4Pa;溅射气压为0.5Pa;样品台温度为250℃;溅射功率为30W; 溅射气体为氩气。
基于该相变存储单元制备相变存储阵列,对相变存储阵列进行循环寿命测试,如下所示:
对该相变存储阵列在370℃下进行退火处理,然后以10ns的速度进行读写作业,以获取其循环寿命,测试得到的循环寿命分布图如图9所示。如图9可知,该相变存储阵列的最大循环寿命大于1E9(即109)次,该相变存储阵列的循环寿命中位数大于1E8(即108)次,可见,基于本公开实施例提供的相变薄膜1的相变存储阵列表现为优异的循环寿命。
基于上述同样的操作,当相变材料层101由Sb2Te材料替换成Sb2Sn、Sb2Se、Sb2Ni、Sb3Nb、Sb3Zr、Sb2Y时,所得到的相变存储阵列同样表现为优异的循环寿命。
以上所述仅是为了便于本领域的技术人员理解本公开的技术方案,并不用以限制本公开。凡在本公开的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本公开的保护范围之内。

Claims (13)

  1. 一种相变材料,其特征在于,所述相变材料包括SbnXm材料,其中,n:m≥1:1;
    元素X的原子半径与元素Sb的原子半径的差值满足第一阈值条件,使得所述元素X能够与所述元素Sb形成弱极性键;以及,所述元素X的热稳定性参数满足第二阈值条件,使得所述元素X在所述元素Sb的相变温度下保持稳定。
  2. 根据权利要求1所述的相变材料,其特征在于,所述第一阈值条件包括所述差值小于或等于
    所述第二阈值条件包括所述元素X在400℃下的耐受时间大于或等于30分钟。
  3. 根据权利要求2所述的相变材料,其特征在于,所述元素X包括Te、Sn、Se、Ni、Nb、Zr、Y中的至少一种。
  4. 根据权利要求1所述的相变材料,其特征在于,1:0.2≥n:m≥1:1。
  5. 根据权利要求1-4任一项所述的相变材料,其特征在于,所述SbnXm材料为Sb-X合金形式、Sb-X二元化合物形式、或者Sb单质与X单质的混合物形式。
  6. 一种相变存储芯片,其特征在于,所述相变存储芯片包括:多个相变存储单元,每个相变存储单元具有相变薄膜(1),所述相变薄膜(1)包括:交替层叠的相变材料层(101)和模板层(102);
    所述相变材料层(101)由权利要求1-5任一项所述的相变材料形成;
    所述模板层(102)由模板材料形成,所述模板材料与所述SbnXm材料的晶格失配度满足第三阈值条件,使得所述模板层(102)能够作为所述相变材料层(101)的结晶模板。
  7. 根据权利要求6所述的相变存储芯片,其特征在于,所述相变材料层(101)的厚度为1nm~100nm;
    所述模板层(102)的厚度为1nm~10nm。
  8. 根据权利要求6所述的相变存储芯片,其特征在于,所述相变材料层(101)与所述模板层(102)交替层叠的循环数目为1~100。
  9. 根据权利要求6-8任一项所述的相变存储芯片,其特征在于,所述第三阈值条件包括所述晶格失配度小于或等于10%。
  10. 根据权利要求9所述的相变存储芯片,其特征在于,所述模板材料包括TiTe2、Ti-Sb-Te三元化合物中的至少一种。
  11. 根据权利要求6-10任一项所述的相变存储芯片,其特征在于,所述相变存储单元还包括:衬底(2)、底电极(31)、顶电极(32)、绝缘隔热层(4);
    所述底电极(31)位于所述衬底(2)的表面;
    所述相变薄膜(1)连接于所述底电极(31)和所述顶电极(32)之间;
    所述绝缘隔热层(4)包覆于所述相变薄膜(1)的侧部。
  12. 一种存储设备,其特征在于,所述存储设备包括控制器及至少一个如权利要求6-11任一项所述的相变存储芯片,所述控制器用于存储数据至所述相变存储芯片。
  13. 一种电子设备,其特征在于,所述电子设备包括处理器及权利要求12所述的存储设备,所述处理器用于存储所述电子设备产生的数据至所述存储设备。
PCT/CN2023/073739 2022-01-30 2023-01-29 相变材料、相变存储芯片、存储设备及电子设备 WO2023143587A1 (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007250876A (ja) * 2006-03-16 2007-09-27 Ricoh Co Ltd 相変化型不揮発性メモリ素子及び半導体メモリ及びデータプロセシングシステム
US20080237564A1 (en) * 2005-09-07 2008-10-02 Electronics And Telecommunications Research Institute Phase-Change Memory Device Using Sb-Se Metal Alloy and Method of Fabricating the Same
CN103794723A (zh) * 2014-03-04 2014-05-14 中国科学院上海微系统与信息技术研究所 一种相变存储器单元及其制备方法
CN110061131A (zh) * 2019-04-23 2019-07-26 中国科学院上海微系统与信息技术研究所 一种相变材料、相变存储单元及其制备方法
CN113161480A (zh) * 2021-03-24 2021-07-23 华为技术有限公司 一种相变存储材料及其制备方法和相变存储器

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080237564A1 (en) * 2005-09-07 2008-10-02 Electronics And Telecommunications Research Institute Phase-Change Memory Device Using Sb-Se Metal Alloy and Method of Fabricating the Same
JP2007250876A (ja) * 2006-03-16 2007-09-27 Ricoh Co Ltd 相変化型不揮発性メモリ素子及び半導体メモリ及びデータプロセシングシステム
CN103794723A (zh) * 2014-03-04 2014-05-14 中国科学院上海微系统与信息技术研究所 一种相变存储器单元及其制备方法
CN110061131A (zh) * 2019-04-23 2019-07-26 中国科学院上海微系统与信息技术研究所 一种相变材料、相变存储单元及其制备方法
CN113161480A (zh) * 2021-03-24 2021-07-23 华为技术有限公司 一种相变存储材料及其制备方法和相变存储器

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