WO2024041611A1 - 选通管材料、相变存储芯片、存储设备及电子设备 - Google Patents

选通管材料、相变存储芯片、存储设备及电子设备 Download PDF

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Publication number
WO2024041611A1
WO2024041611A1 PCT/CN2023/114724 CN2023114724W WO2024041611A1 WO 2024041611 A1 WO2024041611 A1 WO 2024041611A1 CN 2023114724 W CN2023114724 W CN 2023114724W WO 2024041611 A1 WO2024041611 A1 WO 2024041611A1
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gate
phase change
layer
change memory
unit
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PCT/CN2023/114724
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English (en)
French (fr)
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郭晨阳
杨哲
郭艳蓉
童浩
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华为技术有限公司
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Publication of WO2024041611A1 publication Critical patent/WO2024041611A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/10—Phase change RAM [PCRAM, PRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors

Definitions

  • the present disclosure relates to the field of semiconductor storage technology, and in particular to gate tube materials, phase change memory chips, storage devices and electronic devices.
  • Phase Change Memory has great potential in terms of high storage density and fast operating speed.
  • Phase change memory includes multiple phase change memory cells.
  • the leakage current affects adjacent phase change memory cells, and a gate tube unit that acts as a switch is configured for each phase change memory cell.
  • the gate tube unit includes a gate layer prepared from a gate tube material.
  • a gate layer prepared from a gate tube material.
  • Te-based materials such as CTe material, BTe material, SiTe material, etc. can be used to prepare the gate layer.
  • the thermal stability of the gate material provided by the related technology is poor. Especially in a high-temperature environment, the thermal stability of the gate material will decrease significantly.
  • the present disclosure provides gate tube materials, phase change memory chips, storage devices and electronic devices, which can solve the above technical problems.
  • a gate material is provided.
  • the gate material includes Te element and doping element.
  • the atomic percentage of the Te element is greater than or equal to 50% and less than or equal to 90%, and the balance is The doping elements;
  • the doping elements include: a first doping element and a second doping element.
  • the first doping element is one of B, C, N, Si, S, and Se.
  • the second doping element It is one of Al, Zn, Ge, Cd, Mg, Ga, and In.
  • the gate material provided by the embodiment of the present disclosure makes the atomic percentage of the Te element with bidirectional threshold switching characteristics greater than or equal to 50% and less than or equal to 90%, so as to effectively suppress problems such as element separation and segregation, which is beneficial to improving Cycle life of gate material.
  • the gate material also includes doping elements with an atomic percentage greater than or equal to 10% and less than or equal to 45%, which includes one of B, C, N, Si, S, and Se as the first doping element element, and one of Al, Zn, Ge, Cd, Mg, Ga, and In as the second doping element, by causing a specific type of first doping element and a specific type of second doping element to cooperate, This will not affect the bidirectional threshold switching characteristics of the gate material.
  • the doping element remains stable at the phase transition temperature of the Te element, which can significantly improve the thermal stability and temperature resistance of the gate material, making the gate material It can still maintain excellent thermal stability in high temperature environments.
  • the gate tube material provided by the embodiment of the present disclosure is used to prepare the gate tube unit, the gate tube unit has the advantages of strong thermal stability, long cycle life, high driving capability, and low time delay.
  • the general chemical formula of the gate material is Ax By By Te 1-(x+y) ;
  • A is the first doping element, and the A element is one of B, C, N, Si, S, and Se.
  • B is the second doping element, and the B element is Al, Zn, Ge, One of Cd, Mg, Ga and In;
  • x and y are each atomic percentage, 0.1 ⁇ x+y ⁇ 0.45.
  • the doping elements further include a third doping element that is different from the first doping element and the second doping element.
  • the doping element is one of B, C, N, Ge, Si, Al, Zn, Ga, S, and Se, which makes the gate material have long cycle life, high driving ability, low delay, and fatigue resistance. High, thermal stability and other advantages.
  • the general chemical formula of the gate material is Ax By By C z Te 1-(x+y+z) ;
  • A is the first doping element, and the A element is one of B, C, N, Si, S, and Se.
  • B is the second doping element, and the B element is Al, Zn, Ge, One of Cd, Mg, Ga, and In,
  • C is the third doping element, and the C element is one of B, C, N, Ge, Si, Al, Zn, Ga, S, and Se;
  • x, y and z are each atomic percentage, 0.1 ⁇ x+y+z ⁇ 0.45.
  • phase change memory chip includes: a plurality of memory sub-units, each of the memory sub-units including a strobe tube unit and a phase change memory unit connected in series;
  • Each of the gate tube units includes a gate layer, and the gate layer is made of the above-mentioned gate tube material.
  • phase change memory chip provided by the embodiments of the present disclosure is based on the use of gate tube materials rich in Te elements, so that the phase change memory chip has the advantages of long cycle life, high driving capability, low delay, and high fatigue.
  • the gate tube unit further includes a buffer layer stacked on one surface or two opposite surfaces of the gate layer, and the buffer layer is used to inhibit the selection process. Element segregation occurs in the pass layer, further achieving the purpose of improving the thermal stability of the gate tube unit.
  • the buffer material corresponding to the buffer layer is selected from at least one of amorphous carbon compounds, MoTe 2 , MoS 2 , MnTe, HfO 2 /TaO, WTe 2 , and WS 2 .
  • the thickness of the gate layer is 10 nm to 50 nm.
  • the gate unit is integrated with the phase change memory unit.
  • the gate tube unit includes a gate layer and a buffer layer
  • the phase change memory unit includes a phase change layer
  • the buffer layer is located between the gate layer and the phase change layer.
  • the gate tube unit includes a gate layer and a buffer layer
  • the phase change memory unit includes a phase change layer
  • One of the buffer layers is located between the gate layer and the phase change layer, and the other buffer layer is located between the gate layer and the corresponding electrode.
  • the memory subunit includes a gate layer, a buffer layer, a phase change layer, a first top electrode, a first bottom electrode, a first insulating medium and a first substrate;
  • the gate layer, the buffer layer, and the phase change layer are stacked in sequence, and the three are integrally connected between the first top electrode and the first bottom electrode;
  • the first bottom electrode is located on the first substrate, and the first insulating medium is configured to provide insulating isolation for the memory subunit.
  • the memory subunit includes a gate layer, a buffer layer, a phase change layer, a first top electrode, a first bottom electrode, a first insulating medium and a first substrate;
  • One of the buffer layers, the gate layer, the other buffer layer, and the phase change layer are stacked in sequence, and the four are integrally connected between the first top electrode and the first bottom electrode;
  • the first bottom electrode is located on the first substrate, and the first insulating medium is configured to provide insulating isolation for the memory subunit.
  • the gate unit and the phase change memory unit are independent of each other.
  • the gate tube unit includes a gate layer, a second top electrode, a second bottom electrode, a second insulating medium and a second substrate;
  • the second top electrode, the gate layer, the second bottom electrode, and the second substrate are stacked in sequence from top to bottom;
  • the second insulating medium is configured to provide insulating isolation to the gate unit.
  • the gate tube unit includes a gate layer, a buffer layer, a second top electrode, a second bottom electrode, a second insulating medium and a second substrate;
  • the second top electrode, the buffer layer, the gate layer, the second bottom electrode, and the second substrate are stacked in sequence from top to bottom;
  • the second insulating medium is configured to provide insulating isolation to the gate unit.
  • a storage device in another aspect, includes a controller and at least one phase change memory chip.
  • the phase change memory chip is as shown in any one of the above.
  • the controller is used to store data to the phase change memory chip. Change the memory chip.
  • the controller reads and writes data stored in the storage device and communicates interactively with the external interface.
  • the storage devices involved in the embodiments of the present disclosure can be provided in various types.
  • this includes but is not limited to: memory, hard disk, magnetic disk, optical disk, etc.
  • an electronic device in yet another aspect, includes a processor and the above-mentioned storage device.
  • the processor is configured to store data generated by the electronic device into the storage device.
  • the electronic equipment includes but is not limited to: computers, mobile phones, music playing equipment, digital broadcasting equipment, messaging equipment, game control equipment, medical equipment, fitness equipment, personal digital assistants, etc.
  • Figure 1 is a schematic structural diagram of an exemplary 1S1R structure memory subunit provided by an embodiment of the present disclosure
  • Figure 2 is a schematic structural diagram of an exemplary 1SnR structure memory subunit provided by an embodiment of the present disclosure
  • Figure 3 is a schematic structural diagram of an exemplary gate tube unit provided by an embodiment of the present disclosure.
  • Figure 4 is a schematic structural diagram of another exemplary gate tube unit provided by an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of a memory subunit integrated with an exemplary gate layer and a restricted structure phase change memory unit provided by an embodiment of the present disclosure
  • FIG. 6 is a schematic structural diagram of a memory subunit in an integrated arrangement of a phase change memory unit with a gate layer and a confinement structure provided by an embodiment of the present disclosure
  • FIG. 7 is a schematic structural diagram of a memory subunit in an integrated arrangement of a phase change memory unit with a gate layer and a restricted structure provided by an embodiment of the present disclosure
  • FIG. 8 is a schematic structural diagram of a memory subunit in an integrated arrangement of a phase change memory unit with a gate layer and a confinement structure provided by an embodiment of the present disclosure
  • Figure 9 is an open-state current test chart of the OTS strobe unit based on Embodiment 1;
  • Figure 10 is a test chart of the opening time of the OTS strobe unit based on Embodiment 1;
  • Figure 11 is a cycle life test chart of the OTS type strobe unit based on Embodiment 1.
  • the reference symbols respectively indicate: 001. Gate tube unit; 101. Gating layer; 102. Buffer layer; 103. Second top electrode; 104. Second bottom electrode; 105. Second insulating medium; 106. Second substrate; 002.
  • Phase Change Memory is a solid-state semiconductor non-volatile memory, also known as phase change memory chip. It uses phase change materials as storage media. Phase change materials can change between crystalline and amorphous states. By reversibly transforming the phase change material between the amorphous and crystalline states, the phase change memory can store data "0" and "1" by taking advantage of the difference between the high resistivity and low resistivity of the phase change material in the amorphous and crystalline states.
  • Phase change memory includes multiple phase change memory cells. Phase change memory cells include read, erase, and write operations. Phase change memory cells have leakage current during read, erase, and write operations. In order to prevent this leakage current from affecting adjacent phase change memory cells, The unit will be affected, causing problems such as misreading and misoperation. Each phase change memory unit is configured with a strobe unit that plays a switching role.
  • OTS Organic Threshold Switching
  • the working principle of the OTS type gate unit is as follows: when the applied voltage or applied current is less than the threshold voltage or threshold current, the gate unit maintains high resistance and the gate unit is in a closed state, which can effectively suppress leakage current. When the applied voltage or current is greater than the threshold voltage or threshold current, the strobe unit quickly changes to a low resistance, and the strobe unit is in an open state. In this way, the corresponding phase change memory unit performs read, write, and erase operations.
  • the strobe unit when reading, writing, and erasing the phase change memory unit, the strobe unit needs to be opened and closed. Therefore, the number of cycles of the strobe unit needs to be higher than the number of cycles of the phase change memory unit. At least three orders of magnitude, the cycle life of the gate unit directly affects the cycle life of the phase change memory. Among them, the cycle life involved here refers to repeatedly setting the phase change memory to 0 or 1. Cycling operation, the number of cycles each component can undergo before failure.
  • the gate tube unit includes a gate layer prepared from a gate tube material.
  • a gate layer prepared from a gate tube material.
  • Te-based materials such as CTe material, BTe material, SiTe material, etc. can be used to prepare the gate layer.
  • the thermal stability of currently known Te-based materials is poor. Especially in high-temperature environments, the thermal stability of the gate material will decrease significantly.
  • Embodiments of the present disclosure provide a gate material.
  • the gate material includes Te (tellurium) element and doping elements.
  • the atomic percentage of the Te element is greater than or equal to 50% and less than or equal to 90%, and the balance is is a doping element.
  • the “remainder is the doping element” mentioned here means that the sum of the atomic percentage content of the doping element and the atomic percentage content of the Te element constitutes 100%.
  • the atomic percentage of Te element in the gate material is 55% to 90%, 65% to 90%, 75% to 90%, 80% to 90%, etc.
  • Te Atomic percentages of elements include, but are not limited to, the following: 50%, 51%, 52%, 53%, 54%, 55%, 56%, 57%, 58%, 59%, 60%, 61%, 62% , 63%, 64%, 65%, 66%, 67%, 68%, 69%, 70%, 71%, 72%, 73%, 74%, 75%, 76%, 77%, 78%, 79 %, 80%, 81%, 82%, 83%, 84%, 85%, 86%, 87%, 88%, 89%, 90%, etc.
  • the doping elements include: a first doping element and a second doping element.
  • the first doping element is one of B, C, N, Si, S, and Se.
  • the second doping element is Al, Zn, or Ge. , Cd, Mg, Ga, In.
  • the sum of the atomic percentages of the first doping element and the second doping element is greater than or equal to 10% and less than or equal to 50%. In some examples, it may also be less than or equal to 45%, where the first doping element
  • the atomic percentage content of may be greater than, less than, or equal to the atomic percentage content of the second doping element.
  • the ratio of the atomic percentage content of the first doping atom to the atomic percentage content of the second doping element is, for example, 1:0.01 ⁇ 50, further 1:0.1 ⁇ 10, for example 1:0.1, 1:0.2, 1:0.3, 1:0.4, 1:0.5, 1:0.6, 1:0.7, 1:0.8, 1 :0.9, 1:1, 1:2, 1:3, 1:4, 1:5, 1:6, 1:7, 1:8, 1:9, 1:10, etc.
  • the first doping element and the second doping element are each selected from the above types, which not only enables the gate material to maintain the bidirectional threshold switching characteristics (ie, OTS characteristics) of the Te element, but also allows these doping elements to operate at the phase transition temperature of the Te element. Able to remain stable and have excellent thermal stability.
  • the embodiments of the present disclosure work synergistically with the Te element to not only significantly improve the thermal stability of the gate material, but also to The gate material has both high on-state current and low off-state leakage current.
  • the gate tube material and the gate layer based on the gate tube material will not cause element drift and segregation caused by high temperature even if they are kept at 400°C for 30 minutes. problem to ensure that the gating performance is always stable.
  • the above-mentioned doping elements are non-toxic (environmentally friendly) and will not cause safety hazards, making the gate tube unit easy to prepare and helping to reduce process costs.
  • the gate material provided by the embodiment of the present disclosure makes the atomic percentage of the Te element with bidirectional threshold switching characteristics greater than or equal to 50% and less than or equal to 90%, so as to effectively suppress problems such as element separation and segregation, which is beneficial to improving Cycle life of gate material.
  • the atomic percentage content of the Te element in the gate material is greater than or equal to 55% and less than or equal to 90%, and the gate material further includes an atomic percentage content greater than or equal to 10% and less than or equal to 10%.
  • 45% doping elements including one of B, C, N, Si, S, Se as the first doping element, and one of Al, Zn, Ge, Cd, Mg, Ga, In as the second doping element.
  • the gate tube unit has the advantages of strong thermal stability, long cycle life, high driving capability, and low time delay.
  • the gate material provided by the embodiments of the present disclosure is a ternary compound, and the chemical formula of the gate material is Ax By Te 1-(x+y) , where A is the first Doping element, A element is selected from one of B, C, N, Si, S, Se, B is the second doping element, and B element is selected from Al, Zn, Ge, Cd, Mg, Ga, In A kind of, x and y are both atomic percentages, 0.1 ⁇ x+y ⁇ 0.45, for example, 0.15 ⁇ x+y ⁇ 0.3, etc.
  • x:y can be 1:0.01 ⁇ 50, such as 1:0.05 ⁇ 20, 1:0.1 ⁇ 10, 1:0.5 ⁇ 5, etc., for example, x:y includes but is not limited to: 1:0.1 , 1:0.2, 1:0.3, 1:0.4, 1:0.5, 1:0.6, 1:0.7, 1:0.8, 1:0.9, 1:1, 1:2, 1:3, 1:4, 1 :5, 1:6, 1:7, 1:8, 1:9, 1:10, etc.
  • gate tube materials in the form of ternary compounds for example, the values of 0.14, 0.15, 0.17, 0.17, 0.18, 0.2, 0.21, 0.23, 0.24, 0.25, 0.27, 0.28, 0.29, 0.32, 0.33, 0.35, 0.37, 0.38, 0.38, 0.37, 0.38 0.39, 0.4, etc.
  • the values of y include but are not limited to: 0.01, 0.02, 0.03, 0.04, 0.05, 0.06, 0.07, 0.08, 0.09, 0.1, 0.11, 0.12, 0.13, 0.14, 0.15, 0.17, 0.17, 0.18, 0.2, 0.21, 0.22, 0.24, 0.25, 0.27, 0.28, 0.29, 0.32, 0.33, 0.35, 0.37, 0.38, 0.37, 0.38 0.39, 0.4, etc.
  • the gate material can be a ternary compound with the following chemical formula. They all have excellent thermal stability, can withstand higher operating current or operating temperature, and can still maintain heat even at high temperatures. Stability is excellent enough: B x Ge y Te 1-(x+y) , C x Ge y Te 1-(x+y) , N x Ge y Te 1-(x+y) , Si x Ge y Te 1 -(x+y) , S x Ge y Te 1-(x+y) , Se x Ge y Te 1-(x+y) , B x Cd y Te 1-(x+y) , C x Cd y Te 1-(x+y) , N x Cd y Te 1-(x+y) , Si x Cd y Te 1-(x+y) , S x Cd y Te 1-(x+y) , Se x Cd y Te 1-(x+y) , B x Ga y Te 1-(x+y)
  • the above-mentioned B, C, N, Si, S, Se are used as the first doping elements, and Al, Zn, Ge, Cd, Mg, Ga, In are used as the second doping elements.
  • the two doping elements are combined with the Te element. Ensure that the gate material maintains good gating performance, and these doping elements can improve the energy band structure of the gate material and help improve its thermal stability.
  • the values of x and y can be found in the above-mentioned examples of their value ranges.
  • its doping elements also include a third doping element, and the third doping element is different from the first doping element and the second doping element.
  • the third doping element is one of B, C, N, Ge, Si, Al, Zn, Ga, S, and Se.
  • the gate material provided by the embodiments of the present disclosure is a quaternary compound, and the chemical formula of the gate material is A x By C z Te 1-(x+y+z) , where, A It is the first doping element.
  • the A element is one of B, C (carbon element), N, Si, S, and Se.
  • the B element is the second doping element.
  • the B element is Al, Zn, Ge, Cd, Mg. , one of Ga and In
  • the C element is the third doping element
  • the C element is one of B, C, N, Ge, Si, Al, Zn, Ga, S, and Se.
  • x, y and z are all atomic percentages, 0.1 ⁇ x+y+z ⁇ 0.45, for example, 0.15 ⁇ x+y+z ⁇ 0.3.
  • x:y:z can be 1:0.01 ⁇ 50:0.01 ⁇ 50, for example, 1:0.05 ⁇ 20:0.05 ⁇ 20, 1:0.1 ⁇ 10:0.1 ⁇ 10, 1:0.5 ⁇ 5:0.5 ⁇ 5, etc.
  • x:y:z includes but is not limited to: 1:0.1:0.1 ⁇ 5, 1:0.2:0.1 ⁇ 5, 1:0.3:0.1 ⁇ 5, 1:0.4:0.1 ⁇ 5, 1:0.5 :0.1 ⁇ 5, 1:0.6:0.1 ⁇ 5, 1:0.7:0.1 ⁇ 5, 1:0.8:0.1 ⁇ 5, 1:0.9:0.1 ⁇ 5, 1:1:0.1 ⁇ 5, 1:2:0.1 ⁇ 5, 1:3:0.1 ⁇ 5, 1:4:0.1 ⁇ 5, 1:5:0.1 ⁇ 5, 1:6:0.1 ⁇ 5, 1:7:0.1 ⁇ 5, 1:8:0.1 ⁇ 5 , 1:9:0.1 ⁇ 5, 1:10:0.1 ⁇ 5, etc.
  • the range of z in the examples involved in x:y:z is 0.1 to 5, including but not limited to 0.1, 0.5, 1, 1.5, 2, 2.5, 3, 3.5, 4,
  • the gate material includes but is not limited to quaternary compounds with the following chemical formula: C x Ge y N z Te 1-(x+y+z) , N x In y Ge z Te 1- (x+y+z) , Si x Ge y C z Te 1-(x+y+z) , Si x Ge y N z Te 1-(x+y+z) , N x In y C z Te 1 -(x+y+z) .
  • the gate material in the form of the quaternary compound for example, the values of , 0.14, 0.15, 0.16, 0.17, 0.18, 0.19, 0.2, 0.22, 0.23, 0.24, 0.26, 0.27, 0.29, 0.31, 0.33, 0.35, 0.37, 0.37, 0.37 , 0.39, 0.4, etc.
  • the values of y include but are not limited to: 0.01, 0.02, 0.03, 0.04, 0.05, 0.06, 0.07, 0.08, 0.09, 0.1, 0.11, 0.12, 0.13, 0.14, 0.15, 0.16, 0.17, 0.18, 0.19, 0.2, 0.21 , 0.22, 0.23, 0.24, 0.25, 0.26, 0.27, 0.28, 0.29, 0.3, 0.31, 0.32, 0.33, 0.34, 0.35, 0.36, 0.37, 0.38, 0.39, 0.4, etc.
  • the values of z include but are not limited to: 0.01, 0.02, 0.03, 0.04, 0.05, 0.06, 0.07, 0.08, 0.09, 0.1, 0.11, 0.12, 0.13, 0.14, 0.15, 0.16, 0.17, 0.18, 0.19, 0.2, 0.21 , 0.22, 0.23, 0.24, 0.25, 0.26, 0.27, 0.28, 0.29, 0.3, 0.31, 0.32, 0.33, 0.34, 0.35, 0.36, 0.37, 0.38, 0.39, 0.4, etc.
  • the above-mentioned quaternary compound has the advantages of strong thermal stability, strong temperature resistance, long cycle life, high driving ability, low time delay, and high fatigue resistance.
  • the form of the gate material can exist in the following forms: alloy form, compound form such as ternary compound or quaternary compound, mixture form of element and element, mixture form of element and compound. , or a combination of the above forms.
  • the gate material is a mixture of Te element and each doping element.
  • the atomic percentage of each element is determined according to the chemical formula of the gate material, and the Te element and Each doping element element is mixed evenly, and then the gate layer is prepared. For example, this can be done by single target sputtering to prepare the gate layer.
  • the gate material is a compound or alloy containing Te element and at least one doping element mixed with the remaining doping elements.
  • the composition of each raw material is determined according to the chemical formula of the gate material. ratio to prepare the gate layer. For example, this can Co-sputtering can be performed using one or any combination of alloy targets, compound targets, and elemental targets to obtain a gate layer with a desired composition.
  • the gate tube material provided by the embodiment of the present disclosure is an OTS type, which has strong thermal stability (still has tolerance under the 400°C annealing operation) and long cycle life (the number of cycles under the 400°C annealing operation Still up to 10 10 times), high drive capability (on-state current greater than 1mA), low delay (turn-on time T on as low as 2ns), low off-state leakage current (can be as low as 2mA) and other advantages.
  • the gate material is suitable for compatibility with complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) back-end processes, making its application potential higher.
  • CMOS complementary Metal Oxide Semiconductor
  • the gate material provided by the embodiment of the present disclosure can be used to prepare an OTS gate unit.
  • the OTS gate unit has all the advantages of the gate material, making it not only compatible with CMOS back-end processes, but also capable of matching storage.
  • Storage Class Memory (SCM) SCM
  • phase change memory chip includes a plurality of memory subunits, and each memory subunit includes a series-connected memory subunit.
  • the phase change memory chip can also be called a phase change memory.
  • a gate tube unit 101 is configured for each phase change memory unit 102.
  • the gate unit 101 is used as a switching device of the phase change memory unit 102, which can effectively suppress phase change memory. Leakage current generated during chip operation.
  • the phase change memory chip provided by the embodiment of the present disclosure is based on the use of the gate tube material mentioned above, so that the phase change memory chip has strong thermal stability, long cycle life, high driving capability, low delay, and low leakage current. Etc.
  • phase change memory chips involved in the embodiments of the present disclosure include but are not limited to 1S1R (One Selector One Resistor) structure, 1SnR (One Selector n Resistor) structure, etc.
  • Figure 1 illustrates a memory subunit in a phase change memory chip with a 1S1R structure, in which a strobe unit 001 correspondingly controls a phase change memory unit 002;
  • Figure 2 illustrates a phase change memory chip with a 1SNR structure. storage subunit, wherein one strobe unit 001 corresponds to controlling N phase change storage units 002 at the same time.
  • the gate tube unit 001 also includes a buffer layer 102 , and the buffer layer 102 is laminated on one surface of the gate layer 101 or on the opposite side. On both surfaces, the buffer layer 102 is used to suppress element segregation in the gate layer 101 to further achieve the purpose of improving the thermal stability of the gate tube unit 001.
  • the buffer layer 102 may be laminated on at least one of the top surface and the bottom surface of the gate layer 101 (the orientations shown as “top” and “bottom” referred to here can refer to the orientation shown in FIG. 4 ), for example, the buffer layer 102 Isolating the gate layer 101 from the phase change layer, or isolating the gate layer 101 from the corresponding electrode, can further suppress element drift and segregation in the gate layer 101 and the optional phase change layer.
  • the buffer material corresponding to the buffer layer 102 is selected from at least one of amorphous carbon compounds, MoTe 2 , MoS 2 , MnTe, HfO 2 /TaO, WTe 2 , and WS 2 .
  • the amorphous carbon compound may include amorphous carbon and doping elements, such as Si, Te, S, etc., for example, a compound composed of amorphous carbon and Si elements may be defined as a C-Si compound, A compound composed of amorphous carbon and elements Te and S can be defined as a C-(Te, S) compound.
  • the buffer layer 102 prepared by using the above buffer material can effectively prevent the element migration or segregation of the gate material in the direction of the electric field, reduce the diffusion between the gate material and the electrode or the phase change layer, and further improve the gate. Layer 101 for thermal stability and cycle life purposes.
  • the thickness of the gate layer 101 may be determined according to the corresponding operating voltage or operating current of the gate unit 001.
  • the thickness of the gate layer 101 may be 10 nm to 50 nm, for example, 10 nm to 40 nm. 10nm ⁇ 30nm, 10nm ⁇ 20nm, etc., including but not limited to: 10nm, 11nm, 12nm, 13nm, 14nm, 15nm, 16nm, 17nm, 18nm, 19nm, 20nm, 21nm, 22nm, 23nm, 24nm, 25nm, 26nm, 27nm , 28nm, 29nm, 30nm, 31nm, 32nm, 33nm, 34nm, 35nm, 36nm, 37nm, 38nm, 39nm, 40nm, 41nm, 42nm, 43nm, 44nm, 45nm, 46nm, 47nm, 48nm, 49nm, 50nm, etc.
  • the thickness of the buffer layer 102 can be adjusted through factors such as resistance, leakage current, threshold voltage, etc.
  • the thickness of the buffer layer 102 can be 1 nm to 20 nm, such as 1 nm to 15 nm, 2 nm to 10 nm, etc., including but Not limited to: 1nm, 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm, 10nm, etc.
  • the gate tube unit 001 in its storage sub-unit, on the one hand, can be integrated with the phase change memory unit 002; on the other hand, the gate tube unit 001 can also be independent of the phase change memory unit.
  • the arrangement of the storage unit 002 is variable, and the following are exemplary descriptions of the two implementation methods:
  • the gate tube unit 001 and the phase change memory unit 002 are integrated, that is, the gate layer 101 of the gate tube unit 001 and the phase change layer 201 of the phase change memory unit 002 are arranged in the same layer structure unit. and share the top and bottom electrodes.
  • the strobe unit 001 can further include a buffer layer 102, and the buffer layer 102 is used to isolate the strobe layer 101 and the phase change layer 201, effectively preventing the strobe layer 101 from being Element segregation and drift occur between the phase change layer 201 and the phase change layer 201 .
  • the number of the buffer layer 102 in each gate tube unit 001 is one, and the buffer layer 102 is only stacked and arranged on the surface of the gate layer 101 facing the phase change layer 201 .
  • the gate tube unit 001 includes a gate layer 101 and a buffer layer 102
  • the phase change memory unit 002 includes a phase change layer 201
  • the buffer layer 102 is located between the gate layer 101 and the phase change layer 201 .
  • Figures 5 and 6 illustrate the structure of a memory subunit in which the gate layer 101 and the phase change memory unit 002 of the restricted structure are integrated.
  • the memory subunit includes the gate layer 101, the buffer layer 102, and the phase change layer 201. , the first top electrode 202, the first bottom electrode 203, the first insulating medium 204 and the first substrate 205, wherein the number of the buffer layer 102 is one.
  • the gate layer 101, the buffer layer 102, and the phase change layer 201 are stacked in sequence, and the three are integrally connected between the first top electrode 202 and the first bottom electrode 203; the first bottom electrode 203 is located on the first substrate 205,
  • the first insulating medium 204 is configured to provide insulating isolation to the memory subunit.
  • the first insulating medium 204 covers the side portions of the gate layer 101 , the buffer layer 102 , the phase change layer 201 , the first top electrode 202 , and the first bottom electrode 203 .
  • the buffer layer 102 and the phase change layer 201 includes but is not limited to the following:
  • the first top electrode 202 along the top-down direction, the first top electrode 202 , the phase change layer 201 , the buffer layer 102 , the gate layer 101 , the first bottom electrode 203 and the first substrate
  • the bottoms 205 are arranged in layers.
  • the first top electrode 202 , the gate layer 101 , the buffer layer 102 , the phase change layer 201 , the first bottom electrode 203 and the first The substrates 205 are stacked in sequence.
  • phase change memory unit 002 is not limited to the restricted structure.
  • the phase change memory unit 002 of a structure such as a T-shaped structure, a U-shaped trench structure, an L-shaped structure, etc. can also be combined with the gate layer 1 Integrated layout.
  • the number of buffer layers 102 in each gate tube unit 001 is two, and the two buffer layers 102 are respectively stacked and arranged on the surface of the gate layer 101 facing the phase change layer 201 and the surface of the gate layer 101 facing the phase change layer 201 . the surface of the electrode.
  • the gate tube unit 001 includes a gate layer 101 and a buffer layer 102
  • the phase change memory unit 002 includes a phase change layer 201; one of the buffer layers 102 is located between the gate layer 101 and the phase change layer 201 between them, and another buffer layer 102 is located between the gate layer 101 and the corresponding electrode.
  • the memory subunit includes the gate layer 101, the buffer layer 102, the phase change layer 201, the first The top electrode 202, the first bottom electrode 203, the first insulating medium 204 and the first substrate 205, where the number of buffer layers 102 is two.
  • One buffer layer 102, the gate layer 101, another buffer layer 102, and the phase change layer 201 are stacked in sequence, and the four are integrally connected between the first top electrode 202 and the first bottom electrode 203; the first bottom electrode 203 is located On the first substrate 205, the first insulating medium 204 is configured to provide insulation isolation for the memory subunit.
  • the first insulating medium 204 covers the two gate layers 101, the buffer layer 102, the phase change layer 201, Side portions of the first top electrode 202 and the first bottom electrode 203 .
  • the buffer layer 102 and the phase change layer 201 includes but is not limited to the following:
  • the first top electrode 202 , the phase change layer 201 , the buffer layer 102 , the gate layer 101 , the buffer layer 102 , and the first bottom electrode 203 and the first substrate 205 are stacked in sequence.
  • the first top electrode 202 , the buffer layer 102 , the gate layer 101 , the buffer layer 102 , the phase change layer 201 , and the first bottom electrode 203 and the first substrate 205 are stacked in sequence.
  • the gate unit 001 and the phase change memory unit 002 are each independent, that is, an electrode layer of the gate unit 001 and an electrode layer of the corresponding phase change memory unit 002 can be interconnected through wires such as copper. Connect in series via wires, etc.
  • the gate tube unit 001 includes a gate layer 101 , a second top electrode 103 , a second bottom electrode 104 , a second insulating medium 105 and a second substrate 106 .
  • the second top electrode 103, the gate layer 101, the second bottom electrode 104, and the second substrate 106 are stacked in sequence from top to bottom; the second insulating medium 105 is configured to provide insulation isolation for the gate tube unit 001. , for example, the second insulating medium 105 covers the gate layer 101, Side portions of the second top electrode 103 and the second bottom electrode 104 .
  • the gate tube unit 001 further includes a buffer layer 102 , which is used to isolate the gate layer 101 and the electrode, thereby effectively preventing element segregation and drift in the gate layer 101 .
  • the number of the buffer layer 102 may be one, and the buffer layer 102 is arranged on the top surface of the gate layer 101 facing the second top electrode 103 or the buffer layer 102 is arranged on the bottom surface of the gate layer 101 facing the second bottom electrode 104 .
  • the number of buffer layers 102 may be two, and the two buffer layers 102 are respectively arranged on the top surface of the gate layer 101 facing the second top electrode 103 and the bottom surface of the gate layer 101 facing the second bottom electrode 104 .
  • Figure 4 illustrates a gate tube unit 001 provided with a buffer layer 102.
  • the gate tube unit 001 includes a gate layer 101, a buffer layer 102, a second top electrode 103, and a second bottom electrode 104. , the second insulating medium 105 and the second substrate 106.
  • the second top electrode 103, the buffer layer 102, the gate layer 101, the second bottom electrode 104, and the second substrate 106 are stacked in sequence from top to bottom; the second insulating medium 105 is configured to provide insulation to the gate tube unit 001
  • the second insulating medium 105 covers the sides of the gate layer 101, the buffer layer 102, the second top electrode 103, and the second bottom electrode 104.
  • phase change memory unit 002 that is independent of the gate unit 001, its structure includes but is not limited to: restricted structure, T-shaped structure, U-shaped trench structure, L-shaped structure, etc.
  • the upper electrode, phase change layer, lower electrode, and substrate layer are stacked in sequence in the top-down direction, and the insulating medium simultaneously covers the upper electrode and phase change layer. , lower electrode, and the side of the substrate layer.
  • the phase change layer 201 involved in the phase change memory unit 002 may include alternately stacked phase change material layers and template layers.
  • the number of cycles of alternate stacking of phase change material layers and template layers is 2 to 100.
  • the phase change material layer is made into two or more layers, so that the phase change film 201 can undergo layered phase change to obtain multi-level storage capabilities, which is beneficial to improving the data storage density of the phase change memory chip.
  • phase change materials used in the phase change material layer are, for example, Ge-Te binary compounds, Sb-Te binary compounds (for example, Sb 2 Te 3 ), Bi-Te binary compounds, Ge-Sb-Te ternary compounds, Ga -Sb binary compounds, Sb, etc.
  • the template material used in the template layer is, for example, TiTe 2 , Ti-Sb-Te ternary compound, etc.
  • both can be semiconductor substrates, which include but are not limited to: silicon dioxide, silicon carbide, silicon wafer, sapphire, diamond, etc.
  • an organic solvent such as ethanol and/or acetone
  • ethanol and/or acetone can be used to clean the surface of the first substrate 205 or the second substrate 106 to remove the substrate.
  • the first substrate 205 or the second substrate 106 is placed in an oven and dried at 50°C to 100°C.
  • this includes the first top electrode 202, the first bottom electrode 203, the second top electrode 103, and the second bottom electrode 104, both of which are inert metals.
  • this can effectively prevent Te-rich elements from being absorbed.
  • the elements in the gate material diffuse to the electrodes, improving the cycle life of the gate unit; on the other hand, this can effectively prevent the electrodes from being oxidized or corroded, thereby preventing the gate unit from failing and further ensuring the durability of the gate unit. cycle life.
  • this includes but is not limited to the following: titanium tungsten (TiW), tungsten (W), aluminum (Al), titanium nitride (TiN), titanium (Ti), tantalum (Ta), silver (Ag), platinum (Pt), carbon (C), copper (Cu), ruthenium (Ru), gold (Au), cobalt (Co), chromium (Cr), nickel (Ni), iridium (Ir), palladium (Pd), rhodium (Rh), etc.
  • this includes but is not limited to the following: Pt (platinum), Ti (titanium), W (tungsten), Au (gold), Ru (ruthenium), Al (aluminum), TiW (titanium tungsten), TiN (titanium nitride), TaN (tantalum nitride), IrO 2 (iridium dioxide), ITO (indium tin oxide), IZO (indium zinc oxide) At least one.
  • the electrode materials used by the first top electrode 202 and the first bottom electrode 203 and the second top electrode 103 and the second bottom electrode 104 may be the same or different.
  • the insulating medium this includes the first insulating medium 204 and the second insulating medium 105.
  • the insulating medium has insulating properties and can avoid short circuits in the corresponding top electrode and bottom electrode; second, it can make the functional layer (for example, select The pass layer and/or phase change material layer) is limited in the accommodation hole thereon, which helps the functional layer maintain precise dimensions and can be effectively protected.
  • the insulating materials used in the first insulating medium 204 and the second insulating medium 105 include, but are not limited to: silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ), etc.
  • phase change memory chip provided by embodiments of the present disclosure is a memory-level phase change memory chip.
  • phase change memory chip provided by the embodiment of the present disclosure can be used as a separate memory, or can be used together with a dynamic random access memory as a hybrid memory.
  • embodiments of the present disclosure also provide a method for preparing a phase change memory chip, wherein the phase change memory chip is as shown above.
  • Other layers in the phase change memory chip besides the substrate, such as the gate layer, the buffer layer, the phase change layer, the top electrode and the bottom electrode, etc., can all be formed through a thin film deposition process.
  • PVD Physical Vapor Deposition
  • ALD Atomic Layer Deposition
  • MOCVD Metal Organic Chemical Vapor Deposition
  • MBE Molecular Beam epitaxy
  • Magnetron sputtering is a common physical vapor deposition process.
  • the magnetron sputtering process can be used to prepare each layer in the phase change memory chip.
  • the magnetron sputtering method can be DC magnetron sputtering or radio frequency magnetron sputtering.
  • the gate material used can be in the form of an alloy, or in the form of a multi-component compound or form, or in the form of a mixture of a single substance and a single substance, or a mixture of a simple substance and a compound, or it can be A combination of the above forms.
  • the gate material is a mixture of Te elemental substance and each doping element element.
  • the Te elemental substance is determined according to the respective atomic percentages of Te and each doping element in the gate tube material.
  • one way is to uniformly mix a specific mass of Te elemental substance and the elemental powder of each doping element and prepare a gate layer.
  • Another way is to uniformly mix and smelt a specific mass of Te elemental substance and elemental powder of each doping element to prepare the gate layer.
  • Another way is to directly use an elemental target corresponding to a specific mass of Te elemental substance and the elemental substance of each doping element to prepare the gate layer. For example, for the above elemental materials, single target sputtering can be used to obtain a gate layer with a desired composition.
  • the gate material is a combination of different Te-containing compounds or a combination of a Te-containing compound and a doping element element.
  • one or any of alloy targets, compound targets, elemental targets can be used. Co-sputtering is performed in combination to obtain the gate layer with the desired composition.
  • the gate material is C x Ge y Te 1-(x+y) or C x Ge y N z Te 1-(x+y+z) .
  • the specific GeTe compound can be It is obtained by doping C elemental substance, or C elemental substance and N elemental substance, that is, using compound target and elemental target for combined co-sputtering.
  • the above preparation method can be used to directly deposit the gate layer on the corresponding layer (for example, the bottom electrode or the buffer layer).
  • inventions of the present disclosure also provide a storage device.
  • the storage device includes a controller and any one of the above-mentioned phase change memory chips.
  • the controller is used to store data to the phase change memory chip, wherein the controller is configured to store data.
  • the data saved in the device is read and written, and interactively communicates with the external interface.
  • the storage device (also called a memory) can be configured to store various types of data, which can be contact data, phonebook data, messages, pictures, videos, etc., or can also be instructional data.
  • the storage devices involved in the embodiments of the present disclosure can be provided in various types.
  • this includes but is not limited to: memory, hard disk, magnetic disk, optical disk, etc.
  • an embodiment of the present disclosure also provides an electronic device, which includes a processor and the above-mentioned storage device.
  • the processor is configured to store data generated by the electronic device in the storage device.
  • the electronic device includes, but is not limited to: a computer, a mobile phone, a music playing device, a digital broadcasting device, a messaging device, a game control device, a medical device, a fitness device, a personal digital assistant, etc.
  • Embodiment 1 provides an OTS type gate unit.
  • the structure of the gate unit is shown in Figure 4.
  • the gate unit 001 includes a gate layer 101, a buffer layer 102, and a second top electrode 103. , the second bottom electrode 104, the second insulating medium 105 and the second substrate 106, the second top electrode 103, the buffer layer 102, the gate layer 101, the second bottom electrode 104, and the second substrate 106 in order from top to bottom. Stacked arrangement; the second insulating medium 105 covers the sides of the gate layer 101, the buffer layer 102, the second top electrode 103, and the second bottom electrode 104.
  • the gate tube material used in the gate layer 101 is C 0.17 Ge 0.13 Te 0.7 , which can also be defined as C 17 Ge 13 Te 70 . That is to say, if the sum of the percentages of each atom is 1, the C element The atomic percentage is 0.17, the atomic percentage of Ge element is 0.13, and the atomic percentage of Te element is 0.7.
  • the thickness of the gate layer 101 is 30 nm; the buffer material used in the buffer layer 102 is an amorphous carbon layer, and the thickness of the buffer layer 102 is 5 nm.
  • the material of the second top electrode 103 and the second bottom electrode 104 is metal W, and the thickness of both is 100 nm; the material of the second insulating medium 105 is silicon dioxide.
  • the preparation method of the OTS type strobe unit is as follows:
  • a silicon wafer with a silicon dioxide layer on the surface and a crystal phase of ⁇ 100> is used as the second substrate 106.
  • the second substrate 106 is placed in acetone and alcohol in sequence for ultrasonic cleaning.
  • the cleaning time is 15 minutes. After the cleaning is completed, use a nitrogen gun to blow off the remaining liquid on the surface of the second substrate 106 and dry it for use.
  • a layer of second bottom electrode 104 is deposited on the second substrate 106 through a magnetron sputtering process.
  • An insulating medium made of silicon dioxide is formed on the second bottom electrode 104 through a plasma-enhanced chemical vapor deposition process.
  • the plasma is inductively coupled.
  • the bulk etching system etches the insulating medium and forms accommodating holes thereon to obtain the second insulating medium 105 .
  • the gate tube material is C 0.17 Ge 0.13 Te 0.7 material
  • GeTe compound target and C elemental target are used to deposit the gate layer 101 into the accommodation hole based on the co-sputtering process, and then, the gate layer 101 is deposited in the accommodation hole through the magnetron sputtering process.
  • a second top electrode 103 is deposited on the gate layer 101 .
  • the gate layer 101 is prepared using a radio frequency magnetron sputtering process.
  • the magnetron sputtering parameters involved are as follows: the background vacuum degree is 10 -4 Pa; the sputtering pressure is 0.8 Pa; the sample stage temperature is room temperature. ; The sputtering power is 35W (RF); the sputtering gas is argon.
  • the OTS gate unit prepared in Example 1 was annealed at 400°C for 30 minutes, and then the gate performance of the annealed OTS gate unit was tested.
  • the specific test items are as follows:
  • the OTS type strobe unit provided in Embodiment 1 was excited through a triangular wave pulse, and its open-state current was measured. Test, the test results are shown in Figure 9. As shown in Figure 9, the on-state current I on of the strobe unit provided in Embodiment 1 is 1.2mA, which shows that the on-state current of the OTS type strobe unit provided in Embodiment 1 It can support the read, write and erase operations of phase change memory, giving it high drive capability.
  • the WGFMU fast acquisition module i.e., waveform generator/fast measurement unit
  • the opening time (which represents the opening speed) of the OTS type strobe unit provided in Embodiment 1 was tested.
  • the test results are shown in Figure 10.
  • the turn-on time T on of the strobe unit is about 2ns, which shows a fast turn-on speed (ie, low delay), making the strobe unit match the storage level memory is possible.
  • the WGFMU pulse module (i.e., pulse generator unit) of the semiconductor device analysis and tester B1500A was used to test the cycle life of the OTS type strobe unit provided in Embodiment 1.
  • the test results are shown in Figure 11, as shown in Figure 11
  • the gate unit has undergone the annealing operation, the number of stable openings of the gate unit is still as high as 1.2 ⁇ 10 10 times. It can be seen that the gate unit has excellent cycle life and high fatigue characteristics, making This strobe unit makes it possible to match storage-class memory.
  • the dotted line at the top is On Current, which is the current distribution in the on state
  • the dotted line at the bottom is Off Current, which is the current distribution in the off state.
  • This Embodiment 3 provides other OTS-type gate tube units.
  • the structures and preparation methods of these OTS-type gate tube units are the same as those in Embodiment 1.
  • the difference lies in that the gate layers in these gate tube units use The pass tube material is different from Example 1.
  • the chemical formula of the gate tube material is determined based on the atomic percentage of each element, and then the gate tube materials are determined accordingly as follows: N 0.05 Ge 0.25 Te 0.7 material, B 0.15 Ge 0.13 Te 0.72 material, C 0.1 Ga 0.15 Te 0.75 material, C 0.15 N 0.07 Ge 0.15 Te 0.63 material, Si 0.22 N 0.05 Ge 0.13 Te 0.6 material, B 0.15 N 0.05 Ge 0.12 Te 0.68 material, Si 0.15 C 0.1 Ge 0.15 Te 0.6 material, N 0.05 In 0.05 Ge 0.1 Te 0.8 material.
  • OTS-type gate units were prepared using the above-mentioned gate materials.
  • the gate performance of these OTS-type gate units was tested in the same manner as in Example 2.
  • the test results showed that these OTS-type gate units
  • the off-state leakage current, on-state current, turn-on time, and cycle life of the gate unit are basically the same as those of the OTS gate unit provided in Embodiment 1. It also has strong thermal stability, long cycle life, high driving capability, The advantages of low delay are reflected in excellent gating performance.

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Abstract

本公开公开了选通管材料、相变存储芯片、存储设备及电子设备，属于半导体存储技术领域。该选通管材料包括Te元素和掺杂元素，Te元素的原子百分含量大于或等于50％且小于或等于90％，余量为掺杂元素；掺杂元素包括：第一掺杂元素和第二掺杂元素，所述第一掺杂元素为B、C、N、Si、S、Se中的一种，所述第二掺杂元素为Al、Zn、Ge、Cd、Mg、Ga、In中的一种。将本公开实施例提供的上述富Te元素的选通管材料用于选通管单元时，选通管单元兼具热稳定性强、循环寿命长、关态漏电流低、开态电流高、开启速度快、无安全隐患等优点。

Description

选通管材料、相变存储芯片、存储设备及电子设备
本公开要求于2022年08月25日提交的申请号为202211028549.2、发明名称为“选通管材料、相变存储芯片、存储设备及电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及半导体存储技术领域，特别涉及选通管材料、相变存储芯片、存储设备及电子设备。
背景技术
相变存储器(Phase Change Memory，PCM)在高存储密度和快运行速度方面具有较大的潜力，相变存储器包括多个相变存储单元，为了防止目标相变存储单元的读、擦、写操作的漏电流对邻近的相变存储单元造成影响，针对每一个相变存储单元配置一个起到开关作用的选通管单元。
选通管单元包括由选通管材料制备得到的选通层，例如，CTe材料、BTe材料、SiTe材料等Te基材料均能够用于制备选通层。
然而，相关技术提供的选通管材料，其热稳定性较差，特别是在高温环境下，选通管材料的热稳定性会显著下降。
公开内容
鉴于此，本公开提供了选通管材料、相变存储芯片、存储设备及电子设备，能够解决上述技术问题。
具体而言，包括以下的技术方案：
一方面，提供了一种选通管材料，所述选通管材料包括Te元素和掺杂元素，所述Te元素的原子百分含量大于或等于50％且小于或等于90％，余量为所述掺杂元素；
所述掺杂元素包括：第一掺杂元素和第二掺杂元素，所述第一掺杂元素为B、C、N、Si、S、Se中的一种，所述第二掺杂元素为Al、Zn、Ge、Cd、Mg、Ga、In中的一种。
本公开实施例提供的选通管材料，使具有双向阈值开关特性的Te元素的原子百分含量大于或等于50％且小于或等于90％，以有效抑制元素分离、偏析等问题，这利于提高选通管材料的循环寿命。该选通管材料中还包括原子百分含量大于或等于10％且小于或等于45％的掺杂元素，其包括B、C、N、Si、S、Se中的一种作为第一掺杂元素，以及，Al、Zn、Ge、Cd、Mg、Ga、In中的一种作为第二掺杂元素，通过使特定种类的第一掺杂元素和特定种类的第二掺杂元素协同作用，这不会影响选通管材料的双向阈值开关特性，掺杂元素在Te元素的相变温度下保持稳定，这能够显著改善选通管材料的热稳定性和耐温性，使得选通管材料在高温环境下仍然能够保持优异的热稳定性。利用本公开实施例提供的选通管材料制备选通管单元时，选通管单元兼具热稳定性强、循环寿命长、驱动能力高、时延性低等优点。
在一些可能的实现方式中，所述选通管材料的化学通式为AxByTe1-(x+y)；
其中，A为所述第一掺杂元素，A元素为B、C、N、Si、S、Se中的一种，B为所述第二掺杂元素，B元素为Al、Zn、Ge、Cd、Mg、Ga、In中的一种；
x和y各自为原子百分含量，0.1≤x+y≤0.45。
在一些可能的实现方式中，所述掺杂元素还包括第三掺杂元素，所述第三掺杂元素不同于所述第一掺杂元素和所述第二掺杂元素，所述第三掺杂元素为B、C、N、Ge、Si、Al、Zn、Ga、S、Se中的一种，使得该选通管材料具有循环寿命长、驱动能力高、时延性低、抗疲劳性高、热稳定性强等优点。
在一些可能的实现方式中，所述选通管材料的化学通式为AxByCzTe1-(x+y+z)；
其中，A为所述第一掺杂元素，A元素为B、C、N、Si、S、Se中的一种，B为所述第二掺杂元素，B元素为Al、Zn、Ge、Cd、Mg、Ga、In中的一种，C为所述第三掺杂元素，C元素为B、C、N、Ge、Si、Al、Zn、Ga、S、Se中的一种；
x、y和z各自为原子百分含量，0.1≤x+y+z≤0.45。
另一方面，提供了一种相变存储芯片，所述相变存储芯片包括：多个存储子单元，每一所述存储子单元包括相串联的选通管单元和相变存储单元；
每个所述选通管单元包括选通层，所述选通层采用上述的选通管材料制备得到。
本公开实施例提供的相变存储芯片，基于使用了富含Te元素的选通管材料，使得该相变存储芯片兼具循环寿命长、高驱动能力、低时延、高疲劳等优点。
在一些可能的实现方式中，所述选通管单元还包括缓冲层，所述缓冲层层叠于所述选通层的一个表面或者相对的两个表面，所述缓冲层用于抑制所述选通层发生元素偏析，进一步达到提高选通管单元热稳定性的目的。
在一些可能的实现方式中，所述缓冲层对应的缓冲材料选自非晶碳类化合物、MoTe2、MoS2、MnTe、HfO2/TaO、WTe2、WS2中的至少一种。
在一些可能的实现方式中，所述选通层的厚度为10nm～50nm。
在一些可能的实现方式中，所述选通管单元与所述相变存储单元集成设置。
在一些可能的实现方式中，所述选通管单元包括选通层和缓冲层，以及，所述相变存储单元包括相变层；
所述缓冲层位于所述选通层和所述相变层之间。
在一些可能的实现方式中，所述选通管单元包括选通层和缓冲层，以及，所述相变存储单元包括相变层；
其中一个所述缓冲层位于所述选通层和所述相变层之间，以及，另一个所述缓冲层位于所述选通层和相应的电极之间。
在一些可能的实现方式中，所述存储子单元包括选通层、缓冲层、相变层、第一顶电极、第一底电极、第一绝缘介质和第一衬底；
所述选通层、所述缓冲层、所述相变层依次层叠布置，且三者整体连接于所述第一顶电极和所述第一底电极之间；
所述第一底电极位于所述第一衬底上，所述第一绝缘介质被配置为对所述存储子单元提供绝缘隔离作用。
在一些可能的实现方式中，所述存储子单元包括选通层、缓冲层、相变层、第一顶电极、第一底电极、第一绝缘介质和第一衬底；
一个所述缓冲层、所述选通层、另一个所述缓冲层、所述相变层依次层叠布置，且四者整体连接于所述第一顶电极和所述第一底电极之间；
所述第一底电极位于所述第一衬底上，所述第一绝缘介质被配置为对所述存储子单元提供绝缘隔离作用。
在一些可能的实现方式中，所述选通管单元与所述相变存储单元各自独立。
在一些可能的实现方式中，所述选通管单元包括选通层、第二顶电极、第二底电极、第二绝缘介质和第二衬底；
所述第二顶电极、所述选通层、所述第二底电极、所述第二衬底由上至下依次层叠布置；
所述第二绝缘介质被配置为对选通管单元提供绝缘隔离作用。
在一些可能的实现方式中，所述选通管单元包括选通层、缓冲层、第二顶电极、第二底电极、第二绝缘介质和第二衬底；
所述第二顶电极、所述缓冲层、所述选通层、所述第二底电极、所述第二衬底由上至下依次层叠布置；
所述第二绝缘介质被配置为对选通管单元提供绝缘隔离作用。
再一方面，提供了一种存储设备，所述存储设备包括控制器、至少一个相变存储芯片，所述相变存储芯片如上述任一所示，所述控制器用于存储数据至所述相变存储芯片。控制器对存储设备中保存的数据进行读写，并和外部接口进行交互通讯。
本公开实施例涉及的存储设备可以设置成各种类型，例如，这包括但不限于：内存、硬盘、磁盘、光盘等。
再一方面，提供了一种电子设备，所述电子设备包括处理器及上述的存储设备，所述处理器用于存储所述电子设备产生的数据至所述存储设备。
该电子设备包括但不限于：计算机、手机、音乐播放设备、数字广播设备、消息收发设备、游戏控制设备、医疗设备、健身设备、个人数字助理等。
附图说明
图1为本公开实施例提供的一示例性1S1R结构的存储子单元的结构示意图；
图2为本公开实施例提供的一示例性1SnR结构的存储子单元的结构示意图；
图3为本公开实施例提供的一示例性选通管单元的结构示意图；
图4为本公开实施例提供的另一示例性选通管单元的结构示意图；
图5为本公开实施例提供的一示例性选通层和限制型结构的相变存储单元集成布置的存储子单元的结构示意图；
图6为本公开实施例提供的另一示例性选通层和限制型结构的相变存储单元集成布置的存储子单元的结构示意图；
图7为本公开实施例提供的又一示例性选通层和限制型结构的相变存储单元集成布置的存储子单元的结构示意图；
图8为本公开实施例提供的再一示例性选通层和限制型结构的相变存储单元集成布置的存储子单元的结构示意图；
图9为基于实施例1的OTS型选通管单元的开态电流测试图；
图10为基于实施例1的OTS型选通管单元的开启时间测试图；
图11为基于实施例1的OTS型选通管单元的循环寿命测试图。
附图标记分别表示：
001、选通管单元；
101、选通层；102、缓冲层；103、第二顶电极；
104、第二底电极；105、第二绝缘介质；106、第二衬底；
002、相变存储单元；
201、相变薄膜；202、第一顶电极；203、第一底电极；
204、第一绝缘介质；205、第一衬底。
具体实施方式
为使本公开的技术方案和优点更加清楚，下面将结合附图对本公开实施方式作进一步地详细描述。
相变存储器(Phase Change Memory，PCM)是一种固态半导体非易失性存储器，又称为相变存储芯片，其以相变材料作为存储介质，相变材料能够在晶态和非晶态之间进行可逆转变，利用相变材料在非晶态和晶态时对应的高电阻率和低电阻率的差异，相变存储器能够实现数据“0”和“1”的存储。
相变存储器包括多个相变存储单元，相变存储单元包括读、擦、写操作，相变存储单元在读、擦、写操作时存在着漏电流，为了防止该漏电流对邻近的相变存储单元产生影响，造成误读、误操作等问题，针对每一个相变存储单元配置一个起到开关作用的选通管单元。
双向阈值开关(Ovonic Threshold Switching，OTS)型选通管单元具有高开态电流、低漏电流等优点，从而被广泛用于相变存储器。
OTS型选通管单元的工作原理如下所示：当外加电压或者外加电流小于阈值电压或者阈值电流时，选通管单元保持高阻，选通管单元处于关闭状态，能够有效抑制漏电流。当外加电压或者外加电流大于阈值电压或者阈值电流时，选通管单元迅速转变为低阻，选通管单元处于开启状态，这样，与之对应的相变存储单元进行读、写、擦操作。
可见，在对相变存储单元进行读、写、擦操作时，需要使选通管单元进行开启和关闭操作，所以，需要使选通管单元的循环次数比相变存储单元的循环次数高出至少3个数量级，选通管单元的循环寿命直接影响了相变存储器的循环寿命。其中，此处涉及的循环寿命指的是，将相变存储器置0或置1来进行反复 循环操作，各部件在失效之前所能进行的循环次数。
选通管单元包括由选通管材料制备得到的选通层，例如，CTe材料、BTe材料、SiTe材料等Te基材料均能够用于制备选通层。然而，目前已知的Te基材料，其热稳定性较差，特别是在高温环境下，选通管材料的热稳定性会显著下降。
本公开实施例提供了一种选通管材料，该选通管材料包括Te(碲)元素和掺杂元素，Te元素的原子百分含量大于或等于50％且小于或等于90％，余量为掺杂元素。此处涉及的“余量为掺杂元素”指的是，掺杂元素的原子百分含量与Te元素的原子百分含量之和构成100％。
在一些示例中，Te元素在该选通管材料中的原子百分含量为55％～90％、65％～90％、75％～90％、80％～90％等，举例来说，Te元素的原子百分含量包括但不限于以下：50％、51％、52％、53％、54％、55％、56％、57％、58％、59％、60％、61％、62％、63％、64％、65％、66％、67％、68％、69％、70％、71％、72％、73％、74％、75％、76％、77％、78％、79％、80％、81％、82％、83％、84％、85％、86％、87％、88％、89％、90％等。
掺杂元素包括：第一掺杂元素和第二掺杂元素，第一掺杂元素为B、C、N、Si、S、Se中的一种，第二掺杂元素为Al、Zn、Ge、Cd、Mg、Ga、In中的一种。
第一掺杂元素和第二掺杂元素的原子百分含量之和大于或等于10％且小于或等于50％，在一些示例中，还可以小于或等于45％，其中，第一掺杂元素的原子百分含量可以大于、小于或者等于第二掺杂元素的原子百分含量，举例来说，第一掺杂原子的原子百分含量与第二掺杂元素的原子百分含量之比例如为1:0.01～50，进一步为1:0.1～10，例如为1:0.1、1:0.2、1:0.3、1:0.4、1:0.5、1:0.6、1:0.7、1:0.8、1:0.9、1:1、1:2、1:3、1:4、1:5、1:6、1:7、1:8、1:9、1:10等。
第一掺杂元素和第二掺杂元素各自选用上述种类，不仅能够使选通管材料保持Te元素的双向阈值开关特性(即OTS特性)，且这些掺杂元素在Te元素的相变温度下能够保持稳定，具有优异的热稳定性。本公开实施例通过使特定种类的第一掺杂元素和特定种类的第二掺杂元素相配合，两者与Te元素协同作用，不仅能显著提高选通管材料的热稳定性，还能够使选通管材料兼具较高的开态电流以及较低的关态漏电流。
经测试，掺杂元素如上布置时，选通管材料和基于该选通管材料得到的选通层，即使在400℃环境下保持30分钟，也不会产生因高温而引发元素漂移和偏析等问题，确保选通性能始终稳定。
另外，上述掺杂元素均是无毒的(对环境友好)，不会产生安全隐患，使得选通管单元易于制备，利于降低工艺成本。
本公开实施例提供的选通管材料，使具有双向阈值开关特性的Te元素的原子百分含量大于或等于50％且小于或等于90％，以有效抑制元素分离、偏析等问题，这利于提高选通管材料的循环寿命。
在一些示例中，该选通管材料中Te元素的原子百分含量大于或等于55％且小于或等于90％，该选通管材料还包括原子百分含量大于或等于10％且小于或等于45％的掺杂元素，其包括B、C、N、Si、S、Se中的一种作为第一掺杂元素，以及，Al、Zn、Ge、Cd、Mg、Ga、In中的一种作为第二掺杂元素。
通过使特定种类的第一掺杂元素和特定种类的第二掺杂元素协同作用，这不会影响选通管材料的双向阈值开关特性，掺杂元素在Te元素的相变温度下保持稳定，这能够显著改善选通管材料的热稳定性和耐温性，使得选通管材料在高温环境下仍然能够保持优异的热稳定性。利用本公开实施例提供的选通管材料制备选通管单元时，选通管单元兼具热稳定性强、循环寿命长、驱动能力高、时延性低等优点。
在一些实现方式中，本公开实施例提供的选通管材料为一种三元化合物，该选通管材料的化学式为AxByTe1-(x+y)，其中，A为第一掺杂元素，A元素选自B、C、N、Si、S、Se中的一种，B为第二掺杂元素，B元素选自Al、Zn、Ge、Cd、Mg、Ga、In中的一种，x和y均为原子百分含量，0.1≤x+y≤0.45，例如，0.15≤x+y≤0.3等。
在一些示例中，x:y可以为1:0.01～50，例如为1:0.05～20、1:0.1～10、1:0.5～5等，例如，x:y包括但不限于：1:0.1、1:0.2、1:0.3、1:0.4、1:0.5、1:0.6、1:0.7、1:0.8、1:0.9、1:1、1:2、1:3、1:4、1:5、1:6、1:7、1:8、1:9、1:10等。
对于三元化合物形式的选通管材料，举例来说，x的取值包括但不限于：0.01、0.02、0.03、0.04、0.05、0.06、0.07、0.08、0.09、0.1、0.11、0.12、0.13、0.14、0.15、0.16、0.17、0.18、0.19、0.2、0.21、0.22、0.23、0.24、0.25、0.26、0.27、0.28、0.29、0.3、0.31、0.32、0.33、0.34、0.35、0.36、0.37、0.38、0.39、0.4等。
y的取值包括但不限于：0.01、0.02、0.03、0.04、0.05、0.06、0.07、0.08、0.09、0.1、0.11、0.12、0.13、 0.14、0.15、0.16、0.17、0.18、0.19、0.2、0.21、0.22、0.23、0.24、0.25、0.26、0.27、0.28、0.29、0.3、0.31、0.32、0.33、0.34、0.35、0.36、0.37、0.38、0.39、0.4等。
在一些实例中，该选通管材料可以为具有以下化学通式的三元化合物，它们均具有优异的热稳定性，能够承受较高的工作电流或工作温度，即使在高温下仍然能够保持热稳定性足够优异：BxGeyTe1-(x+y)、CxGeyTe1-(x+y)、NxGeyTe1-(x+y)、SixGeyTe1-(x+y)、SxGeyTe1-(x+y)、SexGeyTe1-(x+y)、BxCdyTe1-(x+y)、CxCdyTe1-(x+y)、NxCdyTe1-(x+y)、SixCdyTe1-(x+y)、SxCdyTe1-(x+y)、SexCdyTe1-(x+y)、BxGayTe1-(x+y)、CxGayTe1-(x+y)、NxGayTe1-(x+y)、SixGayTe1-(x+y)、SxGayTe1-(x+y)、SexGayTe1-(x+y)、BxAlyTe1-(x+y)、CxAlyTe1-(x+y)、NxAlyTe1-(x+y)、SixAlyTe1-(x+y)、SxAlyTe1-(x+y)、SexAlyTe1-(x+y)、BxZnyTe1-(x+y)、CxZnyTe1-(x+y)、NxZnyTe1-(x+y)、SixZnyTe1-(x+y)、SxZnyTe1-(x+y)、SexZnyTe1-(x+y)、BxMgyTe1-(x+y)、CxMgyTe1-(x+y)、NxMgyTe1-(x+y)、SixMgyTe1-(x+y)、SxMgyTe1-(x+y)、SexMgyTe1-(x+y)、BxInyTe1-(x+y)、CxInyTe1-(x+y)、NxInyTe1-(x+y)、SixInyTe1-(x+y)、SxInyTe1-(x+y)、SexInyTe1-(x+y)。
上述B、C、N、Si、S、Se作为第一掺杂元素，以及Al、Zn、Ge、Cd、Mg、Ga、In作为第二掺杂元素，两种掺杂元素与Te元素配合，确保选通管材料保持良好的选通性能，且这些掺杂元素均能够提高选通管材料的能带结构，利于提高其热稳定性。其中，上述各三元化合物的实例中，x和y的取值均可以参见上述就它们的取值范围的一些示例。
在一些实现方式中，对于本公开实施例提供的选通管材料，其掺杂元素还包括第三掺杂元素，第三掺杂元素不同于第一掺杂元素和第二掺杂元素，该第三掺杂元素为B、C、N、Ge、Si、Al、Zn、Ga、S、Se中的一种。
在一些示例中，本公开实施例提供的选通管材料为一种四元化合物，该选通管材料的化学式为AxByCzTe1-(x+y+z)，其中，A为第一掺杂元素，A元素为B、C(碳元素)、N、Si、S、Se中的一种，B为第二掺杂元素，B元素为Al、Zn、Ge、Cd、Mg、Ga、In中的一种，C元素为第三掺杂元素，C元素为B、C、N、Ge、Si、Al、Zn、Ga、S、Se中的一种。x、y和z均为原子百分含量，0.1≤x+y+z≤0.45，例如0.15≤x+y+z≤0.3。
进一步地，x:y:z可以为1:0.01～50:0.01～50，例如为1:0.05～20:0.05～20、1:0.1～10:0.1～10、1:0.5～5:0.5～5等，例如，x:y:z包括但不限于：1:0.1:0.1～5、1:0.2:0.1～5、1:0.3:0.1～5、1:0.4:0.1～5、1:0.5:0.1～5、1:0.6:0.1～5、1:0.7:0.1～5、1:0.8:0.1～5、1:0.9:0.1～5、1:1:0.1～5、1:2:0.1～5、1:3:0.1～5、1:4:0.1～5、1:5:0.1～5、1:6:0.1～5、1:7:0.1～5、1:8:0.1～5、1:9:0.1～5、1:10:0.1～5等。其中，此处x:y:z所涉及的示例中z的范围为0.1～5，这包括但不限于0.1、0.5、1、1.5、2、2.5、3、3.5、4、4.5、5等。
举例来说，该选通管材料包括但不限于具有以下化学通式的四元化合物等：CxGeyNzTe1-(x+y+z)、NxInyGezTe1-(x+y+z)、SixGeyCzTe1-(x+y+z)、SixGeyNzTe1-(x+y+z)、NxInyCzTe1-(x+y+z)。
对于该四元化合物形式的选通管材料，举例来说，x的取值包括但不限于：0.01、0.02、0.03、0.04、0.05、0.06、0.07、0.08、0.09、0.1、0.11、0.12、0.13、0.14、0.15、0.16、0.17、0.18、0.19、0.2、0.21、0.22、0.23、0.24、0.25、0.26、0.27、0.28、0.29、0.3、0.31、0.32、0.33、0.34、0.35、0.36、0.37、0.38、0.39、0.4等。y的取值包括但不限于：0.01、0.02、0.03、0.04、0.05、0.06、0.07、0.08、0.09、0.1、0.11、0.12、0.13、0.14、0.15、0.16、0.17、0.18、0.19、0.2、0.21、0.22、0.23、0.24、0.25、0.26、0.27、0.28、0.29、0.3、0.31、0.32、0.33、0.34、0.35、0.36、0.37、0.38、0.39、0.4等。z的取值包括但不限于：0.01、0.02、0.03、0.04、0.05、0.06、0.07、0.08、0.09、0.1、0.11、0.12、0.13、0.14、0.15、0.16、0.17、0.18、0.19、0.2、0.21、0.22、0.23、0.24、0.25、0.26、0.27、0.28、0.29、0.3、0.31、0.32、0.33、0.34、0.35、0.36、0.37、0.38、0.39、0.4等。
上述四元化合物作为选通管材料，兼具热稳定性强、耐温性强、循环寿命长、驱动能力高、时延性低、抗疲劳性高等优点。
在一些实现方式中，选通管材料的形态可以以下述形态存在：合金形式、诸如三元化合物或者四元化合物等化合物形式、单质与单质相混合的混合物形式、单质与化合物相混合的混合物形式、或者为上述各形式的组合。
在一些示例中，选通管材料为Te单质与各掺杂元素单质相混合的混合物形式，该种情形下，根据选通管材料的化学式确定其中各元素的原子百分含量，将Te单质与各掺杂元素单质混合均匀，然后进行选通层的制备。例如，这可以通过单靶溅射来进行选通层的制备。
在一些示例中，选通管材料为含Te元素和至少一种掺杂元素组成的化合物或者合金与剩余掺杂元素的单质相混合的形式，根据选通管材料的化学式确定其中各原料的配比，进行选通层的制备。例如，这可 以利用合金靶、化合物靶、单质靶的一种或者任意组合进行共溅射，来获得期望组成的选通层。
综上可知，本公开实施例提供的选通管材料为OTS型，其具有热稳定性强(在400℃退火操作下仍然具有耐受性)、循环寿命长(在400℃退火操作下循环次数仍然高达1010次)、驱动能力高(开态电流大于1mA)、时延性低(开启时间Ton低至2ns)、关态漏电流低(可低至2mA)等优点。基于该选通管材料的上述优点，使得该选通管材料适于兼容互补金属氧化物半导体(Complementary Metal Oxide Semiconductor，CMOS)后道工艺，使其应用潜力更高。
利用本公开实施例提供的选通管材料能够制备得到OTS型选通管单元，该OTS型选通管单元具有选通管材料的所有优点，使其不仅兼容CMOS后道工艺，还能够匹配存储级内存(Storage Class Memory，SCM)。
另一方面，本公开实施例还提供了一种相变存储芯片，如附图1-附图2所示，该相变存储芯片包括多个存储子单元，每一存储子单元包括相串联的选通管单元001和相变存储单元002。进一步结合图3可知，每个选通管单元001包括选通层101，选通层101由上述涉及的任一种选通管材料制备得到。
相变存储芯片还可称为相变存储器，针对每一个相变存储单元102配置一个选通管单元101，利用选通管单元101作为相变存储单元102的开关器件，能够有效抑制相变存储芯片工作过程中产生的漏电流。本公开实施例提供的相变存储芯片，基于使用了上述涉及的选通管材料，使得该相变存储芯片兼具热稳定性强、循环寿命长、驱动能力高、低时延、漏电流低等优点。
本公开实施例涉及的相变存储芯片的结构包括但不限于1S1R(One Selector One Resistor)结构、1SnR(One Selector n Resistor)结构等。
图1示例了一种1S1R结构的相变存储芯片中的存储子单元，其中，一个选通管单元001对应控制一个相变存储单元002；图2示例了一种1SNR结构的相变存储芯片中的存储子单元，其中，一个选通管单元001对应同时控制N个相变存储单元002。
在一些示例中，本公开实施例提供的相变存储芯片中，如附图4所示，选通管单元001还包括缓冲层102，缓冲层102层叠于选通层101的一个表面或者相对的两个表面，缓冲层102用于抑制选通层101发生元素偏析，进一步达到提高选通管单元001热稳定性的目的。
缓冲层102可以层叠于选通层101的顶部表面和底部表面中的至少一个(此处涉及的“顶部”和“底部”所示方位均可参见图4所示方位)，例如，缓冲层102使选通层101和相变层进行隔离，或者使选通层101和相应的电极进行隔离，从而能够进一步抑制选通层101和可选的相变层发生元素漂移和偏析。
在一些示例中，缓冲层102对应的缓冲材料选自非晶碳类化合物、MoTe2、MoS2、MnTe、HfO2/TaO、WTe2、WS2中的至少一种。
其中，非晶碳类化合物可以包括非晶碳和掺杂元素，该掺杂元素例如为Si、Te、S等，例如，可以将非晶碳和Si元素组成的化合物定义为C-Si化合物，可以将非晶碳和Te、S元素组成的化合物定义为C-(Te、S)化合物。
利用上述缓冲材料制备得到缓冲层102，能够有效阻止选通管材料在电场方向上的元素迁移或者偏析，减小选通管材料与电极或者与相变层之间的扩散，进一步达到提高选通层101热稳定性和循环寿命的目的。
可以根据选通管单元001对应的操作电压或者操作电流的大小，来确定其中选通层101的厚度，在一些示例中，选通层101的厚度可以为10nm～50nm，例如为10nm～40nm、10nm～30nm、10nm～20nm等，这包括但不限于：10nm、11nm、12nm、13nm、14nm、15nm、16nm、17nm、18nm、19nm、20nm、21nm、22nm、23nm、24nm、25nm、26nm、27nm、28nm、29nm、30nm、31nm、32nm、33nm、34nm、35nm、36nm、37nm、38nm、39nm、40nm、41nm、42nm、43nm、44nm、45nm、46nm、47nm、48nm、49nm、50nm等。
可以通过电阻大小、漏电流、阈值电压等因素来调节缓冲层102的厚度，在一些示例中，缓冲层102的厚度可以为1nm～20nm，例如为1nm～15nm、2nm～10nm等，这包括但不限于：1nm、2nm、3nm、4nm、5nm、6nm、7nm、8nm、9nm、10nm等。
对于本公开实施例提供的相变存储芯片，其存储子单元中，一方面，选通管单元001可以与相变存储单元002集成设置，另一方面，选通管单元001也可以独立于相变存储单元002布置，以下就这两种实现方式分别进行示例性描述：
在一些实现方式中，选通管单元001与相变存储单元002集成设置，即，选通管单元001的选通层101和相变存储单元002的相变层201布置在同一个层结构单元中且共用顶电极和底电极。
当选通管单元001与相变存储单元002集成布置时，还可以使选通管单元001进一步包括缓冲层102，利用缓冲层102隔离选通层101和相变层201，有效防止选通层101和相变层201之间发生元素偏析和漂移。
在一些示例中，每一选通管单元001中缓冲层102的数量为一个，缓冲层102仅层叠布置于选通层101的面向相变层201的表面。
参见图5和图6，选通管单元001包括选通层101和缓冲层102，以及，相变存储单元002包括相变层201；缓冲层102位于选通层101和相变层201之间。
附图5和附图6示例了选通层101和限制型结构的相变存储单元002集成布置的存储子单元的结构，该存储子单元包括选通层101、缓冲层102、相变层201、第一顶电极202、第一底电极203、第一绝缘介质204和第一衬底205，其中，缓冲层102的数目为一个。
选通层101、缓冲层102、相变层201依次层叠布置，且三者整体连接于第一顶电极202和第一底电极203之间；第一底电极203位于第一衬底205上，第一绝缘介质204被配置为对存储子单元提供绝缘隔离作用。例如，第一绝缘介质204包覆于选通层101、缓冲层102、相变层201、第一顶电极202、第一底电极203的侧部。
关于选通层101、缓冲层102和相变层201的布置顺序，包括但不限于以下：
作为一种示例，如附图5所示，沿着自上而下的方向，第一顶电极202、相变层201、缓冲层102、选通层101、第一底电极203和第一衬底205依次层叠布置。
作为另一种示例，如附图6所示，沿着自上而下的方向，第一顶电极202、选通层101、缓冲层102、相变层201、第一底电极203和第一衬底205依次层叠布置。
当然，本公开实施例中，相变存储单元002不仅限于限制型结构，诸如T型结构、U型沟槽结构、L字型结构等结构的相变存储单元002也可以与选通层1进行集成布置。
在一些示例中，每一选通管单元001中缓冲层102的数量为两个，两个缓冲层102分别层叠布置于选通层101的面向相变层201的表面和选通层101的面向电极的表面。
参见图7和图8，选通管单元001包括选通层101和缓冲层102，以及，相变存储单元002包括相变层201；其中一个缓冲层102位于选通层101和相变层201之间，以及，另一个缓冲层102位于选通层101和相应的电极之间。
图7和图8示例了选通层101和限制型结构的相变存储单元002集成布置的存储子单元的结构，存储子单元包括选通层101、缓冲层102、相变层201、第一顶电极202、第一底电极203、第一绝缘介质204和第一衬底205，其中，缓冲层102的数目为两个。
一个缓冲层102、选通层101、另一个缓冲层102、相变层201依次层叠布置，且四者整体连接于第一顶电极202和第一底电极203之间；第一底电极203位于第一衬底205上，第一绝缘介质204被配置为对存储子单元提供绝缘隔离作用，例如，第一绝缘介质204包覆于两个选通层101、缓冲层102、相变层201、第一顶电极202和第一底电极203的侧部。
关于选通层101、缓冲层102和相变层201的布置顺序，包括但不限于以下：
作为一种示例，如附图7所示，沿着自上而下的方向，第一顶电极202、相变层201、缓冲层102、选通层101、缓冲层102、第一底电极203和第一衬底205依次层叠布置。
作为另一种示例，如附图8所示，沿着自上而下的方向，第一顶电极202、缓冲层102、选通层101、缓冲层102、相变层201、第一底电极203和第一衬底205依次层叠布置。
在一些实现方式中，选通管单元001与相变存储单元002各自独立，即，选通管单元001的一个电极层和对应的相变存储单元002的一个电极层可以通过诸如导线例如铜互连线等方式进行串联连接。
以下就选通管单元001的结构进行示例性描述：
在一些示例中，参见图3，选通管单元001包括选通层101、第二顶电极103、第二底电极104、第二绝缘介质105和第二衬底106。
其中，第二顶电极103、选通层101、第二底电极104、第二衬底106由上至下依次层叠布置；第二绝缘介质105被配置为对选通管单元001提供绝缘隔离作用，例如，第二绝缘介质105包覆于选通层101、 第二顶电极103、第二底电极104的侧部。
进一步地，参见图4，选通管单元001进一步包括缓冲层102，利用缓冲层102隔离选通层101和电极，有效防止选通层101发生元素偏析和漂移。
缓冲层102的数目可以为一个，缓冲层102布置于选通层101面向第二顶电极103的顶部表面或者缓冲层102布置于选通层101面向第二底电极104的底部表面。
缓冲层102的数目可以为两个，两个缓冲层102分别布置于选通层101面向第二顶电极103的顶部表面和选通层101面向第二底电极104的底部表面。
附图4示例了设置一个缓冲层102的选通管单元001，如附图4所示，选通管单元001包括选通层101、缓冲层102、第二顶电极103、第二底电极104、第二绝缘介质105和第二衬底106。第二顶电极103、缓冲层102、选通层101、第二底电极104、第二衬底106由上至下依次层叠布置；第二绝缘介质105被配置为对选通管单元001提供绝缘隔离作用，例如，第二绝缘介质105包覆于选通层101、缓冲层102、第二顶电极103、第二底电极104的侧部。
对于上述独立于选通管单元001的相变存储单元002，其结构包括但不限于：限制型结构、T型结构、U型沟槽结构、L字型结构等。
以限制型结构的相变存储单元002举例来说，沿自上而下的方向，上电极、相变层、下电极、衬底层依次层叠布置，绝缘介质同时包覆于上电极、相变层、下电极、衬底层的侧部。
相变存储单元002中涉及的相变层201可以包括交替层叠的相变材料层和模板层，例如，相变材料层与模板层的交替层叠的循环数目为2～100。在一些示例中，使相变材料层为两层或两层以上，使得相变薄膜201能够分层相变，以获得多级存储的能力，利于提高相变存储芯片的数据存储密度。
相变材料层使用的相变材料例如为Ge-Te二元化合物、Sb-Te二元化合物(例如为Sb2Te3)、Bi-Te二元化合物、Ge-Sb-Te三元化合物、Ga-Sb二元化合物、Sb等。模板层使用的模板材料例如为TiTe2、Ti-Sb-Te三元化合物等。
对于上述涉及的第一衬底205和第二衬底106，两者均可以为半导体衬底，例如这包括但不限于：二氧化硅、碳化硅、硅片、蓝宝石、金刚石等。
在用于制备相变存储单元002或者选通管单元001时，可以采用有机溶剂，例如乙醇和/或丙酮等将第一衬底205或者第二衬底106的表面清洗干净，以除去衬底表面的杂质，清洗完毕，将第一衬底205或者第二衬底106置于烘箱中于50℃～100℃下干燥即可。
对于上述涉及的电极，这包括第一顶电极202、第一底电极203、第二顶电极103、第二底电极104，两者均为惰性金属，一方面，这能够有效阻止富Te元素的选通管材料中的元素扩散至电极，提高选通管单元的循环寿命；另一方面，这能够有效避免电极被氧化或者被侵蚀，以防止选通管单元失效，进一步保证选通管单元的循环寿命。
对于第一顶电极202和第一底电极203所使用的电极材料，这包括但不限于以下：钨化钛(TiW)、钨(W)、铝(Al)、氮化钛(TiN)、钛(Ti)、钽(Ta)、银(Ag)、铂(Pt)、碳(C)、铜(Cu)、钌(Ru)、金(Au)、钴(Co)、铬(Cr)、镍(Ni)、铱(Ir)、钯(Pd)、铑(Rh)等。
对于第二顶电极103、第二底电极104所使用的电极材料，这包括但不限于以下：Pt(铂)、Ti(钛)、W(钨)、Au(金)、Ru(钌)、Al(铝)、TiW(钨化钛)、TiN(氮化钛)、TaN(氮化钽)、IrO2(二氧化铱)、ITO(氧化铟锡)、IZO(铟锌氧化物)中的至少一种。
第一顶电极202和第一底电极203，以及，第二顶电极103和第二底电极104所使用的电极材料可以相同，也可以不同。
对于绝缘介质，这包括第一绝缘介质204和第二绝缘介质105，其一，绝缘介质具有绝缘性，能够避免相应的顶电极和底电极发生短路；其二，能够使得功能层(例如，选通层和/或相变材料层)被限制在其上的容置孔内，利于使功能层保持精确的尺寸，且能够得到有效的防护。
在一些示例中，第一绝缘介质204和第二绝缘介质105所采用的绝缘材料包括但不限于：二氧化硅(SiO2)、氮化硅(Si3N4)等。
在一些示例中，本公开实施例提供的相变存储芯片为内存级相变存储芯片。
本公开实施例提供的相变存储芯片可以作为单独的内存进行使用，也可以与动态随机存取存储器共同作为混合内存进行使用。
再一方面，本公开实施例还提供了一种相变存储芯片的制备方法，其中，该相变存储芯片如上述所示。对于相变存储芯片中除了衬底之外的其他层，例如，选通层、缓冲层、相变层、顶电极和底电极等，均可以通过薄膜沉积工艺来形成。
上述涉及的薄膜沉积工艺包括但不限于以下：物理气相沉积(Physical Vapour Deposition，PVD)、原子层沉积(Atomic Layer Deposition，ALD)、金属有机物化学气相沉积(Metal Organic Chemical Vapor Deposition，MOCVD)、分子束外延(Molecular Beam Epitaxy，MBE)等。
磁控溅射是一种常见的物理气相沉积工艺，本公开实施例中，可以使用磁控溅射工艺来制备相变存储芯片中的各层。
根据具体的层来确定每一层对应的磁控溅射参数，以制备选通层举例来说，一些适用的磁控溅射参数如下所示：本底真空度为10-3Pa～10-5Pa；溅射气压为0.3Pa～0.8Pa等；基板温度，也就是样品台温度为20℃～400℃；溅射功率为7W～50W等；溅射气体包括但不限于：氩气、氪气、氙气、氖气、氮气中的至少一种，例如，选用氩气Ar作为溅射气体。磁控溅射方式可以为直流磁控溅射，也可以为射频磁控溅射。
以制备选通层举例来说，所使用的选通管材料可以为合金形式，也可以为多元化合物或形式，还可以为单质与单质相混合或者单质与化合物相混合的混合物形式，还可以为上述各形式的组合。
在一些示例中，选通管材料为Te单质与各掺杂元素的单质的混合物形式，该种情形下，根据选通管材料中Te与各掺杂元素各自的原子百分含量，确定Te单质与各掺杂元素的单质的质量，一种方式是将特定质量的Te单质与各掺杂元素的单质粉末混合均匀，并进行选通层的制备。另一种方式是，将特定质量的Te单质与各掺杂元素的单质粉末混合均匀并熔炼，进行选通层的制备。再一种方式是，直接利用特定质量的Te单质与各掺杂元素的单质对应的单质靶，进行选通层的制备。举例来说，对于以上单质材料，可以利用单靶溅射获得期望组成的选通层。
在一些示例中，选通管材料为不同的含Te化合物的组合或者为含Te化合物和掺杂元素单质的组合，该种情形下，可以利用合金靶、化合物靶、单质靶的一种或者任意组合进行共溅射，来获得期望组成的选通层。
举例来说，选通管材料为CxGeyTe1-(x+y)或者CxGeyNzTe1-(x+y+z)，在该情形下，可以在特定的GeTe化合物的基础上进行C单质、或者C单质和N单质的掺杂来获得，即利用化合物靶和单质靶进行组合共溅射。
当选通管单元的选通层集成于相变存储单元时，利用上述制备方法在相应的层(例如，底电极或者缓冲层)上直接沉积形成选通层即可。
再一方面，本公开实施例还提供了一种存储设备，该存储设备包括控制器和上述的任一种相变存储芯片，控制器用于存储数据至相变存储芯片，其中，控制器对存储设备中保存的数据进行读写，并和外部接口进行交互通讯。
该存储设备(又可以称为存储器)，可以被配置为存储各种类型的数据，这些数据可以为联系人数据，电话簿数据，消息，图片，视频等，也可以为指令性数据。
本公开实施例涉及的存储设备可以设置成各种类型，例如，这包括但不限于：内存、硬盘、磁盘、光盘等。
再一方面，本公开实施例还提供了一种电子设备，该电子设备包括处理器和上述的存储设备，处理器用于存储电子设备产生的数据至存储设备。
在一些示例中，该电子设备包括但不限于：计算机、手机、音乐播放设备、数字广播设备、消息收发设备、游戏控制设备、医疗设备、健身设备、个人数字助理等。
下面将通过更具体的实施例进一步地描述本公开，虽然下面描述了一些具体的实施方式，然而应该理解，可以以各种形式实现本公开而不应被这里阐述的实施例所限制。实施例中未注明具体技术或条件者，按照本领域内的文献所描述的技术或条件或者按照产品说明书进行，所用试剂或仪器未注明生产厂商者，均可以为可以通过市购获得的常规产品。
实施例1
本实施例1提供了一种OTS型选通管单元，该选通管单元的结构如附图4所示，该选通管单元001包括选通层101、缓冲层102、第二顶电极103、第二底电极104、第二绝缘介质105和第二衬底106，第二顶电极103、缓冲层102、选通层101、第二底电极104、第二衬底106由上至下依次层叠布置；第二绝缘介质105包覆于选通层101、缓冲层102、第二顶电极103、第二底电极104的侧部。
其中，选通层101所使用的选通管材料为C0.17Ge0.13Te0.7，又可定义为C17Ge13Te70，也就是说，以各原子百分含量总和为1计算，C元素的原子百分含量为0.17，Ge元素的原子百分含量为0.13，Te元素的原子百分含量为0.7。选通层101的厚度为30nm；缓冲层102所使用的缓冲材料为非晶碳层，缓冲层102的厚度为5nm。第二顶电极103、第二底电极104的材质均为金属W，两者的厚度均为100nm；第二绝缘介质105的材质为二氧化硅。
该OTS型选通管单元的制备方法如下所示：
将表面涂覆有一层二氧化硅层且晶相为<100>的硅片作为第二衬底106，将第二衬底106依次放置于丙酮、酒精中进行超声洗涤，洗涤时间为15分钟。洗涤完毕后，使用氮气枪将第二衬底106表面残留的液体吹净烘干，待用。
通过磁控溅射工艺在第二衬底106上沉积一层第二底电极104，通过等离子体增强化学气相沉积工艺在第二底电极104上形成二氧化硅材质的绝缘介质，通过电感耦合等离子体刻蚀系统对绝缘介质进行蚀刻，在上形成容置孔，得到第二绝缘介质105。基于选通管材料为C0.17Ge0.13Te0.7材料，利用GeTe化合物靶材和C单质靶材，基于共溅射工艺向容置孔内沉积选通层101，然后，通过磁控溅射工艺在选通层101上沉积一层第二顶电极103。
其中，选通层101采用射频磁控溅射工艺制备得到，所涉及的磁控溅射参数如下所示：本底真空度为10-4Pa；溅射气压为0.8Pa；样品台温度为室温；溅射功率为35W(RF)；溅射气体为氩气。
实施例2
对实施例1中制备的OTS型选通管单元在400℃下退火处理30min，然后，对经退火处理后的OTS型选通管单元的选通性能进行测试，具体测试项目如下所示：
(1)采用半导体器件分析测试仪B1500A的WGFMU快采模块(即，波形发生器/快速测量单元)，通过三角波脉冲激发实施例1提供的OTS型选通管单元，对其开态电流进行了测试，测试结果参见图9，如图9所示，实施例1提供的选通管单元的开态电流Ion为1.2mA，这说明实施例1提供的OTS型选通管单元的开态电流能够支撑相变存储器的读写擦操作，使其具有高驱动能力。
(2)采用半导体器件分析测试仪B1500A的SMU模块(即，电源测量单元)，以DC(Direct Current，直流电)测量法对实施例1提供的OTS型选通管单元的I-V特性进行测试，测试结果表明，实施例1提供的OTS型选通管单元的漏电流Ioff为2nA，可见，实施例1提供的OTS型选通管单元表现为较低的关态漏电流，使其能够保持良好的选通性能。
(3)采用半导体器件分析测试仪B1500A的WGFMU快采模块输出信号，利用示波器采集信号的方式，对实施例1提供的OTS型选通管单元的开启时间(其代表了开启速度)进行了测试，测试结果参见图10，如图10所示，该选通管单元的开启时间Ton约为2ns，表现为较快的开启速度(即，低时延)，使得该选通管单元匹配存储级内存成为可能。
(4)采用半导体器件分析测试仪B1500A的WGFMU脉冲模块(即，脉冲发生器单元)，对实施例1提供的OTS型选通管单元的循环寿命进行了测试，测试结果参见图11，如图11所示，该选通管单元在经历退火操作后，该选通管单元的稳定开启次数仍然高达1.2×1010次，可见，该选通管单元具有优异的循环寿命和高疲劳特性，使得该选通管单元匹配存储级内存成为可能。
其中，图11中，位于上方的点线为On Current，即开态的电流分布情况，位于下方的点线为Off Current，即关态的电流分布情况。
实施例3
本实施例3提供了另一些OTS型选通管单元，这些OTS型选通管单元的结构和制备方法与实施例1一致，区别在于，这些选通管单元中的选通层所使用的选通管材料不同于实施例1，以各元素的原子百分含量来确定选通管材料的化学通式，进而相应地确定这些选通管材料分别如下所示：N0.05Ge0.25Te0.7材料、 B0.15Ge0.13Te0.72材料、C0.1Ga0.15Te0.75材料、C0.15N0.07Ge0.15Te0.63材料、Si0.22N0.05Ge0.13Te0.6材料、B0.15N0.05Ge0.12Te0.68材料、Si0.15C0.1Ge0.15Te0.6材料、N0.05In0.05Ge0.1Te0.8材料。
利用上述各选通管材料分别制备得到OTS型选通管单元，采用与实施例2中相同的方式，分别对这些OTS型选通管单元的选通性能进行测试，测试结果表明，这些OTS型选通管单元的关态漏电流、开态电流、开启时间、循环寿命与实施例1提供的OTS型选通管单元基本相当，同样兼具热稳定性强、循环寿命长、驱动能力高、时延性低等优点，表现为优异的选通性能。
以上所述仅是为了便于本领域的技术人员理解本公开的技术方案，并不用以限制本公开。凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (18)

  1. 一种选通管材料，其中，所述选通管材料包括Te元素和掺杂元素，所述Te元素的原子百分含量大于或等于50％且小于或等于90％，余量为所述掺杂元素；
    所述掺杂元素包括：第一掺杂元素和第二掺杂元素，所述第一掺杂元素为B、C、N、Si、S、Se中的一种，所述第二掺杂元素为Al、Zn、Ge、Cd、Mg、Ga、In中的一种。
  2. 根据权利要求1所述的选通管材料，其中，所述选通管材料的化学通式为AxByTe1-(x+y)；
    其中，A为所述第一掺杂元素，A元素为B、C、N、Si、S、Se中的一种，B为所述第二掺杂元素，B元素为Al、Zn、Ge、Cd、Mg、Ga、In中的一种；
    x和y各自为原子百分含量，0.1≤x+y≤0.45。
  3. 根据权利要求1所述的选通管材料，其中，所述掺杂元素还包括第三掺杂元素，所述第三掺杂元素不同于所述第一掺杂元素和所述第二掺杂元素，所述第三掺杂元素为B、C、N、Ge、Si、Al、Zn、Ga、S、Se中的一种。
  4. 根据权利要求3所述的选通管材料，其中，所述选通管材料的化学通式为AxByCzTe1-(x+y+z)；
    其中，A为所述第一掺杂元素，A元素为B、C、N、Si、S、Se中的一种，B为所述第二掺杂元素，B元素为Al、Zn、Ge、Cd、Mg、Ga、In中的一种，C为所述第三掺杂元素，C元素为B、C、N、Ge、Si、Al、Zn、Ga、S、Se中的一种；
    x、y和z各自为原子百分含量，0.1≤x+y+z≤0.45。
  5. 一种相变存储芯片，其中，所述相变存储芯片包括：多个存储子单元，每一所述存储子单元包括相串联的选通管单元(001)和相变存储单元(002)；
    每个所述选通管单元(001)包括选通层(101)，所述选通层(101)采用权利要求1-4任一项所述的选通管材料制备得到。
  6. 根据权利要求5所述的相变存储芯片，其中，所述选通管单元(001)还包括缓冲层(102)，所述缓冲层(102)层叠于所述选通层(101)的一个表面或者相对的两个表面，所述缓冲层(102)用于抑制所述选通层(101)发生元素偏析。
  7. 根据权利要求6所述的相变存储芯片，其中，所述缓冲层(102)对应的缓冲材料选自非晶碳类化合物、MoTe2、MoS2、MnTe、HfO2/TaO、WTe2、WS2中的至少一种。
  8. 根据权利要求7所述的相变存储芯片，其中，所述选通层(101)的厚度为10nm～50nm。
  9. 根据权利要求5-8任一项所述的相变存储芯片，其中，所述选通管单元(001)与所述相变存储单元(002)集成设置。
  10. 根据权利要求9所述的相变存储芯片，其中，所述选通管单元(001)包括选通层(101)和缓冲层(102)，以及，所述相变存储单元(002)包括相变层(201)；
    所述缓冲层(102)位于所述选通层(101)和所述相变层(201)之间。
  11. 根据权利要求9所述的相变存储芯片，其中，所述选通管单元(001)包括选通层(101)和缓冲层(102)，以及，所述相变存储单元(002)包括相变层(201)；
    其中一个所述缓冲层(102)位于所述选通层(101)和所述相变层(201)之间，以及，另一个所述缓 冲层(102)位于所述选通层(101)和相应的电极之间。
  12. 根据权利要求10所述的相变存储芯片，其中，所述存储子单元包括选通层(101)、缓冲层(102)、相变层(201)、第一顶电极(202)、第一底电极(203)、第一绝缘介质(204)和第一衬底(205)；
    所述选通层(101)、所述缓冲层(102)、所述相变层(201)依次层叠布置，且三者整体连接于所述第一顶电极(202)和所述第一底电极(203)之间；
    所述第一底电极(203)位于所述第一衬底(205)上，所述第一绝缘介质(204)被配置为对所述存储子单元提供绝缘隔离作用。
  13. 根据权利要求11所述的相变存储芯片，其中，所述存储子单元包括选通层(101)、缓冲层(102)、相变层(201)、第一顶电极(202)、第一底电极(203)、第一绝缘介质(204)和第一衬底(205)；
    一个所述缓冲层(102)、所述选通层(101)、另一个所述缓冲层(102)、所述相变层(201)依次层叠布置，且四者整体连接于所述第一顶电极(202)和所述第一底电极(203)之间；
    所述第一底电极(203)位于所述第一衬底(205)上，所述第一绝缘介质(204)被配置为对所述存储子单元提供绝缘隔离作用。
  14. 根据权利要求5-8任一项所述的相变存储芯片，其中，所述选通管单元(001)与所述相变存储单元(002)各自独立。
  15. 根据权利要求14所述的相变存储芯片，其中，所述选通管单元(001)包括选通层(101)、第二顶电极(103)、第二底电极(104)、第二绝缘介质(105)和第二衬底(106)；
    所述第二顶电极(103)、所述选通层(101)、所述第二底电极(104)、所述第二衬底(106)由上至下依次层叠布置；
    所述第二绝缘介质(105)被配置为对选通管单元(001)提供绝缘隔离作用。
  16. 根据权利要求14所述的相变存储芯片，其中，所述选通管单元(001)包括选通层(101)、缓冲层(102)、第二顶电极(103)、第二底电极(104)、第二绝缘介质(105)和第二衬底(106)；
    所述第二顶电极(103)、所述缓冲层(102)、所述选通层(101)、所述第二底电极(104)、所述第二衬底(106)由上至下依次层叠布置；
    所述第二绝缘介质(105)被配置为对选通管单元(001)提供绝缘隔离作用。
  17. 一种存储设备，其中，所述存储设备包括控制器、至少一个相变存储芯片，所述相变存储芯片如权利要求5-16任一项所示，所述控制器用于存储数据至所述相变存储芯片。
  18. 一种电子设备，其中，所述电子设备包括处理器及权利要求17所述的存储设备，所述处理器用于存储所述电子设备产生的数据至所述存储设备。
PCT/CN2023/114724 2022-08-25 2023-08-24 选通管材料、相变存储芯片、存储设备及电子设备 WO2024041611A1 (zh)

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