TW200832679A - Multilevel-cell memory structures employing multi-memory layers with tungsten oxides and manufacturing method - Google Patents

Abstract

The present invention provides multilevel-cell memory structures with multiple memory layer structures where each memory layer structure includes a tungsten oxide region that defines different read current levels for a plurality of logic states. Each memory layer structure can provide two bits of information, which constitutes four 1ogic states, by the use of the tungsten oxide region that provides multilevel-cell function in which the four logic states equate to four different read current levels. A memory structure with two memory layer structures would provide four bits of storage sites and 16 logic states. In one embodiment, each of the first and second memory layer structures includes a tungsten oxide region extending into a principle surface of a tungsten plug member where the outer surface of the tungsten plug is surrounded by a barrier member.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-density memory device based on a programmable resistive memory material, comprising a metal oxide type material and other materials: and manufacturing the device Methods. [Prior Art] Xin, phase-change memory materials are widely used for reading and writing optical discs. These materials have at least two solid phases including, for example, a generally amorphous solid phase and a generally crystalline solid phase. Laser pulses are used on the read and write optical discs to switch between phases and to read material optical properties after phase changes. Phase change memory materials, such as chalcogenide type materials and the like, can also be made by changing the amount of current applied to the integrated circuit by application. This general amorphous morphology is characterized by a higher resistivity than the general crystalline morphology and which has been detectable to reveal data. These features have resulted in the benefit of programmable resistive materials to form non-volatile memory circuits that are randomly readable and writable. Helium, changing from amorphous to crystalline is usually a low current operation. Change from junction $ to amorphous i here refers to resetting, usually - higher current, including - short 13⁄4 current density pulse, melting or breaking crystalline junction small, then phase changing material rapidly cooling 'quenching phase change The process allows the phase change structure to be stabilized in the amorphous form. The crystalline form is required. (5) The phase change of the morphology changes the strength of the reset current to minimize. The required reset current strength can be reduced by reducing the phase change in the cell

200832679 "The size of the w3〇6iPA ^ material element is reduced with the contact area between the electrode and the phase change material, so that a higher current density can be obtained by changing the small absolute current value of the material element. The development direction is already in the product. A small hole is formed in the body circuit structure, and the small hole is filled with a small amount of programmable resistance material. The patents for the development of the small hole include: U.S. Patent No. 5,687,112 issued to U.S. Element Having Tapered Contact”; US Patent No. 5,789,277 awarded to Zahorik et al. on August 4, 1998, "Method of Making Chalogenide [sic]

Memory Device”; US Patent No. 6,150,253 issued to Doan et al. on November 21, 2000. "Controllable Ovonic Phase-Change

Semiconductor Memory Device and Methods of Fabricating the Same" has caused problems in manufacturing such a device having a very small size and meeting the strict specifications required for a large memory device. If a large memory capacity is sought, It has been highly demanded to store more than 10 bits of phase change memory per memory layer. [Invention] The present invention provides a multi-cell unit (mlC) memory structure having a multi-memory layer structure, wherein each memory layer structure comprises tungsten monoxide. A region that defines a different amount of read current for a plurality of logic states. Each memory layer structure provides two-bit information by providing a multi-level cell function using a tungsten-tungsten region, which constitutes a four-logic state in which four logic states are equal to four Different reading currents

200832679. PA: A memory structure with two memory layer structures provides a four-bit storage address and a sixteen logic state. In the first embodiment, a multi-layer cell memory structure includes a first memory, a bulk layer structure, and a second memory layer structure. Each memory layer structure is a one-dimensional line connecting the shell to the top. The first or lower memory layer structure is connected to the quadruple body, wherein the Ν·ρ diode is connected to the first 70 line. The second or upper memory layer is connected to the diode at the bottom 'where the Ρ-Ν diode is connected to the second bit line. The second bit line is used in common between the first memory layer structure and the second memory layer structure. The second 1-yuan line is then connected to the __memory layer structure. The first and second memory layer structures each comprise a tungsten oxide region extending into the major surface of the tungsten plug component. The outer surface of the tungsten plug is surrounded by a barrier element. The critical dimension of the tungsten oxide region is less than the size of the tungsten plug component. The critical size of the oxidized crane area is also smaller than the size of the Ρ-Ν diode. The key dimensions of the oxidized crane area, the critical dimensions of the crane inspection component, and the relationship between the 产-Ν diode's thick production can be expressed by the lower vocational school: (4) Μ - 2 * tj> where the parameter “represents the key size of the crane bolt, parameters Dw represents the critical dimension of the structural component 'and the parameter b represents the critical dimension of the PN: polar body. The critical dimension of the diode is larger than the critical dimension of the oxidized crane region, mathematically expressed as dA>dw. In the second embodiment A multi-level cell memory structure includes a first memory layer structure and a second memory layer structure. The first and first layer structures each comprise - (iv) oxygen on the main surface of the piece.

fW3061PA 200832679 Area, the outer surface of the tungsten plug element is surrounded by a barrier element. Each tungsten plug structure has a size that is small enough to omit the dielectric step in the fabrication process. The critical dimension of each tungsten plug structure is approximately the same as the critical dimension of the activation zone (oxidized crane zone). In a third embodiment, a multi-level cell memory structure includes a first memory layer structure and a second memory layer structure. The first memory layer structure comprises a tungsten oxide region, a tungsten plug structure having a first plug portion and a second plug portion, and the outer wall of the second plug is surrounded by a barrier element. The critical dimension of the first plug portion is similar to the critical dimension of the activation zone, i.e., the oxidized crane region. The tungsten oxide portion extends from the major surface or top surface of the first plug portion. The first plug portion has a smaller dimension than the second plug portion. The first plug portion and the second plug portion can be fabricated using a self-aligned process or a non-self-aligned process in each memory layer structure. A method of fabricating a memory device is also disclosed that includes a plug structure that surrounds the plug material with a barrier material and is placed between the dielectric elements. The top portion of the plug material and the barrier material are etched using a first chemical dry etch followed by a second chemical wet etch. A dielectric spacer is formed on the major surface of the etch plug material. Dry oxygen plasma is used to remove the formation of the tungsten oxide region into the major surface of the etch plug material. A single line is formed to the dielectric spacer and over the tungsten oxide region. Broadly speaking, a memory structure having a plurality of memory layers includes a first memory layer structure having a first electrode having a major surface and a tungsten oxide region extending from a major surface of the first electrode and The first electrode and the second electrode are electrically connected, and the first electrode has a substantial phase

; W3061PA 200832679 is similar to the size of the tungsten oxide region; and a second memory layer structure coupled to the first memory layer structure, having a first electrode having a main surface and a tungsten oxide region, and the tungsten oxide region is formed by the first electrode The main surface extends to the second memory layer structure and is electrically connected to the first electrode of the second memory layer structure and the second electrode of the second memory layer structure, and the first electrode of the second memory layer structure is substantially similar to the second The size of the tungsten oxide region size of the memory layer structure. The structure and method of the present invention will be described in detail below. This description of the invention is not intended to define the invention. The invention is defined by the scope of the patent application. These and other embodiments, features, aspects, and advantages of the present invention will be apparent from the description and appended claims appended claims. The invention will be described in detail with reference to the specific embodiments and drawings. [Embodiment] Descriptions of structural embodiments and methods of the present invention will be described with reference to Figs. It is to be understood that the invention is not limited to the embodiments of the invention, and the invention may be practiced otherwise. Similar elements in different embodiments are generally illustrated by like reference numerals. Different embodiments are related to the fabrication of ternary memory structures and memory, such as non-volatile embedded memory to implement programmable resistive RAM. Examples of the resistive device RAM are a resistive memory (RRAM), a polymer memory, and a phase change memory (PCRAM). Figure 1 is a diagram illustrating a bistable resistive random access memory array 100 that can be implemented as shown herein. In the description of the circuit diagram in Figure 1, a total of

rW3061PA 200832679 _ The source line 128, the word line 123, and the word line 124 are arranged substantially in the gamma direction. The bit 70 lines 141 and 142 are arranged substantially in parallel in the x direction. Thus, the gamma decoder and word line driver at block Μ5 are coupled to word lines 123,124. The block X and the set of sense amplifiers in block 146 are lightly coupled to bit lines 141 and 142. A common source line 128 is coupled to the source terminals of the access transistors L, 151, 152, and 153. The gate of the access transistor 15 is coupled to the word το line 123. The gate of the transistor 151 is coupled to the word line 124. The gate of the transistor 152 is coupled to the word line 123. The gate of access transistor 153 is coupled to word line 124. The drain of the access transistor 150 is coupled to the bottom electrode element 132 of the sidewall memory cell unit 135 having a top electrode component 134 and a bottom electrode component 132. Top electrode element 134 is coupled to bit line 141. It can be seen that the common source line 128 is shared by the two columns of memory cells, and is arranged in a column in the γ direction in the circuit diagram of the description. In another embodiment, the access transistor can be replaced by a diode or other structure to control current to a particular device in the array to read or write data. Figure 2 is a simplified block diagram of an integrated circuit 200 of a rram architecture in accordance with an embodiment of the present invention. The integrated circuit 275 includes a memory array implemented on a semiconductor substrate using a bistable resistive random access memory cell with sidewall activation terminals. A column of decoders 261 is coupled to a plurality of word lines 262 and arranged in columns in memory array 260. A terminal decoder 263 is coupled to a plurality of bit lines 264 disposed along the terminals in the memory array 260 to be read and programmed by the side wall terminal memory cells in the memory array 260. An address is supplied to the terminal decoder 263 and a column of decoder 261 on the bus 265. The sense amplifier and data write structure at block 266 is via data sink 200832679

-_ ^V3061PA / melon t^267 is lightly coupled to the terminal decoder 263. The data is written or written by the write line 271 from the product 5/275 round or round out or the integrated circuit 2 is internal or external = the source of the feed is provided to the data writer structure in block 266. In the illustrated example, other circuits are included on the integrated circuit, such as a general processing = or a special purpose application circuit, or a module combination, which can be provided by a thin film bistable resistive random access memory cell _ Supported system single crystal ^ 1 can. The data is provided from the sense amplifiers of block 266 via data output line 272 to the input/output ports of integrated circuit 275 or to points within or outside of integrated circuit 275 # or other data points. In this embodiment, a biasing device 269 is used to control the application of the supply voltage 268 by a controller, such as reading, programming, erasing, verifying, and verifying the voltage. This controller can be implemented using special purpose logic circuits known in the art. In an alternate embodiment, the controller includes a general purpose processor that can be implemented in the same integrated circuit that executes a computer program to control the operation of the device. In another embodiment, a special function logic circuit and a combination of general purpose logic circuits can be utilized to implement the controller. Figure 3 is a simplified process diagram 30〇 illustrating the fabrication of a bistable resistive random access memory device with a standard tungsten plug (W-plug) or via window in a single memory cell. Refer to the steps. A via or contact dielectric elements 310, 312 and a barrier material 320 are formed. A tungsten material 33 is filled in the via window disposed between the barrier materials 320. A grinding technique such as chemical mechanical polishing (CMP) or etch back is performed on the surface 34 after the tungsten material 330 is deposited. In one embodiment, the critical dimension (cd) of the tungsten plug (W-plug) 330 12

200832679_61PA The following design: 〇·13μιη technology node, W-plug CD mesoporous window or hole between Ο.ίμιη to 0·25μιη range. Figure 4 is a process diagram 400 showing the next step in fabricating a bistable resistive random access memory for recessed silver ingots of tungsten plug component 430. The groove engraving process of the crane bolt member 430 can be carried out by SF6 dry engraving, or other chemicals including Ar and/or A and/or 〇2. The groove etch has an aspect ratio of about 1, for example, a 200 nm critical dimension having a depth of about 200 nm. After the engraving of the crane groove, a barrier-like isotropic process engraved by the barrier material 320

A portion of Ti or TiN is removed to form a barrier element 420. An appropriate etching technique for the isotropic barrier material is dry etching with chemical chlorine (CL) and/or triple gasification (BCI3) and/or others such as argon (Ar). A solvent such as EKC265 or other wet cleaning can be used to remove polymer residue during etching of the barrier material. The diagram is a process diagram 500 illustrating that tungsten oxide (w〇x) is formed by a spacer etch, a dry oxygen plasma etch, and a wet removal. In the dielectric spacers, the process involves deposition-dielectric films and dielectric gaps 510, 512. The dielectric film is deposited on the crane 430 by chemical vapor deposition (CVD) techniques. Suitable materials for the present dielectric film include yttrium oxide, ^ = nitrogen cut surface. The dielectric material has fine properties ranging from _nm to about (10) nm. The dielectric element is fine, and the money (4) is used to form the dielectric gap wall (4), the ι Γ material CF4 and 7 or his dry surface is engraved as suitable for the dielectric gap wall singularly, where the remainder stops at the crane bolt element 43 crane groove To ensure sufficient excess of the upper surface sub-amount has some 13 200832679 _ After the dielectric spacer etch, the WOx element 520 is formed by dry removal of oxygen (〇2) plasma. Examples of oxygen plasma dry removal include 〇2 gas plasma chemistry, or a mixed chemistry of 〇2 plasma, such as 〇2/N2*〇2/N2/h2. 〇2 Suitable for plasma Mixing chemistry includes 〇2/n2, o2m2/H2, or pure 〇2 gas and a plasma such as direct plasma, magnetic field enhanced reactive ion plasma, or downstream plasma. The parameters of the downstream plasma are exemplified by a pressure of about 1500 mTorr, a power of about 1000 W, a 02/N2 flow of about 3000 sccm/200 sccm, a temperature of about 150 o C, and a duration of about 400 seconds. A wet removal step is performed to remove the polymer produced during the dielectric spacer etching process. A suitable wet removal compound is an aqueous organic mixture such as EKC265 solvent or other similar or similar mixture type. A number of 〇2 plasmas have been sufficiently removed, and this wet removal step is selective. Figure 6 is a process diagram 600 showing the next step in fabricating a bistable resistive random access memory having bit line formation. An optional step is to deposit a barrier layer 61 over the dielectric elements 31A, 312 and the dielectric spacers 510, 512 using chemical vapor deposition. For example, titanium nitride (TiN) or nitride (TaN) may be selected as a suitable material for achieving the barrier layer 61. If the bit line layer _ 620 has sufficient adhesion when deposited, the barrier layer 61 is an optional step. A bit line layer 620 is deposited on the barrier layer 610 by depositing a right barrier layer. If the deposition of the barrier layer 61 is skipped, the bit line layer is deposited directly on the dielectric elements 310, 312 and the dielectric spacers 51, 512. Materials suitable for implementing the bit line layer 620 include polycrystalline, w, Cu, or A1Cu. If the polysilicon is used to realize the bit line layer 62, a large amount of impurities is required to reduce the amount of resistance.

200832679 write 1PA - process diagram 600 represents a simplified memory cell having a memory layer structure 850 and a top bit line 710 comprising a combination of only a bit line layer 62 or a bit line layer 620 and a barrier layer 610 And dielectric spacers $1 〇, $12, and dielectric elements 310, 312. Figure 7 is a process diagram of Figure 7 showing the next step in the fabrication of a bistable snubber-type random access memory connected to an optional device. The memory layer structure 850 is coupled to a P-N diode 72A, which is then coupled to the bottom bit line 730. Suitable materials for achieving the bottom bit line layer 73 include polycrystalline Si, w, Cu, or AlCu. 10 Fig. 8 is a process diagram illustrating a first embodiment of a memory structure 8 having a multi-S memory layer and a tungsten oxide region for use in a multi-layer cell function. In this embodiment, the memory structure δ 〇〇 includes two memory layers, a first memory layer 810 and a second memory layer 85 〇. The first memory layer 810 is coupled to a Ν_Ρ diode 820, which is then coupled to the bottom bit line 83A. The first memory layer structure 81A includes a tungsten oxide region 816, a tungsten plug component 812, and a barrier element 814. The tungsten oxide region 816 extends into the major surface of the tungsten plug component 812 or a first electrode 812 10 . Barrier element 814 surrounds tungsten plug element 812. The tungsten germanium region 816 in the first memory layer structure 810 is electrically contacted to a second bit line 860 or a first electrode that is coupled to the first memory layer structure 81. The two bit line 860 includes a bit line 730 only, or a combination of the bit line 730 and the early layer 862. The second bit line in this embodiment provides a dual purpose, that is, the top bit line ' combined with the first memory layer structure and the second bit line combined with the second memory layer structure 85 〇 . 15 200832679 A • The second bit line 860 is electrically coupled to the top of the P-Ν diode 720, which is then electrically coupled to the second memory layer structure 85A. The second memory layer structure 850 includes a tungsten oxide region 52, a tungsten plug element 430, and a barrier element 42. The tungsten oxide region 520 extends into the main surface of the tungsten plug element or first electrode 43A. The barrier element 420 surrounds the tungsten plug element 430. The tungsten oxide region 520 in the second memory layer structure 850 is electrically connected to the top bit line or a third bit line 7 1 Q, or a second electrode combined with the second first memory layer structure 710. The third bit line 71A includes only _ bit line 620, or a combination of bit line 620 and barrier layer 610. The critical dimension of the active region (i.e., the tungsten oxide region 52A) is determined by the size of the tungsten plug member 430 and the thickness of the dielectric spacers 51, 512. In this embodiment, the critical dimension of the tungsten oxide region 520 is less than the size of the tungsten plug element 43. The critical dimension of the oxidized crane & field is also smaller than the size of the diode 720. The relationship between the critical dimensions of the tungsten oxide region 520, the critical dimensions of the tungsten plug component, and the thickness of the P-N diode 720 can be expressed by the following mathematical formula:

dA^dw - 2 * tD 馨 where parameter 4 represents the critical dimension of the tungsten plug 520, and parameter dw represents the critical dimension of the 430 of the plug structure component, and parameters. Represents the key dimensions of the diode 720. The critical dimension of the P-N diode 720 is larger than the critical dimension of the tungsten oxide region 52, mathematically expressed as dA > dw. In one embodiment, for example, the critical dimension of the p·Ν diode 720 is approximately (7) times the critical dimension of the tungsten oxide region 52〇, expressed as a mathematical expression of dD > 10*dA. Other exemplary critical dimensions of the aforementioned parameters are but not limited to, the critical dimensions of the P-N diode are = 〇.3 μπι, the critical dimension of the tungsten plug component is dw = 〇.3 μπι, the thickness of the dielectric spacer

rW3061PA 200832679 Key ruler 135 ugly, and the key size of the oxidation _ domain dA, nm. Fig. 9 is a process diagram, a rehearsal, and a second embodiment of a memory structure having a multi-memory layer and a tungsten oxide region for multi-layer cell functions. The memory structure _ contains - the first memory layer structure 91 〇 and - the Γ memory layer structure. The first-memory layer structure then includes an oxygen-domain 816 extending from the main dice of the tungsten plug structure surrounded by the barrier element 2. The second memory layer structure 95Q includes an oxidation (four) domain,

Covering the major surface of the face structure 960 surrounded by the barrier element 962. The tungsten plug structures 920, 960 each have a size that is small enough that the dielectric step described in Figure 5 is skipped in the fabrication of the memory structure 9_. The critical dimensions of the tungsten plug structure 92 〇, 960 size are about the same as the critical dimensions of the respective activation regions, i.e., the tungsten oxide region 816 and the tungsten oxide region 52 〇. The second bit line 98, which is located above the tungsten oxide region 816 and below the P-N diode 43A, has a barrier element 982 that is similar in size to the bit line component 720. Figure 10 is a process diagram illustrating a third example of a memory structure having a multi-memory layer and a tungsten oxide region for multi-layer cell functions. The memory structure 1 includes a first memory layer structure 1〇1〇 and a second memory structure 1050. The first memory layer structure 1〇1〇 includes a tungsten oxide region 816, a tungsten plug structure having a first plug portion 1〇2〇 and a second plug portion 1〇22, and the outer wall portion of the second plug is The barrier element 1〇24 is surrounded. The critical dimension of the first plug portion 1062 is similar to the critical dimension of the active region, i.e., the tungsten oxide region 520. The tungsten oxide portion 816 extends from the major surface of the top surface of the first plug portion 1020. The first plug portion 1〇2〇 has a smaller size than the second plug portion 1022. 17

W3061PA 200832679, ' The first plug portion 1020 and the second plug portion can be fabricated using a self-aligning garment or a non-self-aligning process. For non-self-aligned potentials, a second lithography process is used to define a two-pronged plug structure having different dimensions, the first key portion of the first key portion and the second key portion and the second plug portion The second key size of 〇22. The self-alignment process involves the step of reducing the cross-section of a portion of the interlayer contacts. The reduction process is performed in some embodiments by forming a dielectric structure covering at least a portion of the interlayer contacts and reducing the material by removing material from portions of the interlayer contacts that are not covered by the electrician Share (four) ^ point ^ cut surface. The reduction of the cross section - the implementation is performed as follows. The private layer is exposed by the interlayer contact, and at least the other dielectric layer is removed by the interlayer contact. A new dielectric layer is formed to at least partially cover the interlayer contacts. Only a portion of the new dielectric layer covering the interlayer contacts is removed, leaving at least a portion of the dielectric structure covering the interlayer contacts. An example of the removal of the new material is to wet the portion of the new dielectric layer for a period of time which controls the size of the layer of the interlayer contact obtained by reducing the cross-section. A chemical mechanical polishing (CMP) system planarizes the surface and opening of the contact formed by the dielectric structure. The 〇2 electropolyoxidation is used to form a tungsten oxide region 520 and a tungsten oxide region 816. For more information on the self-alignment process and the chemical mechanical polishing process, see U.S. Patent Application Serial No. 11/426,213, filed on Jun. 23, 1989, entitled, "Programmable Resistive RAM and Manufacturing Method" 'The patent application is incorporated by reference in its entirety. The first diagram is a diagram 1100 illustrating a multi-layer single for the read current of the memory structure 800 used in the first embodiment with the tungsten oxide region 520 as the active region.

200832679rW3〇6iPA f-element control instantiation. Figure 1110 depicts the amount of current on the x-axis u12 and the number of readings 1114 on the Y-axis. The activated region, i.e., the yttrium oxide region 520, can be operated in four states (2 bits/cell) for each memory layer, as defined by the amount of read current. The four different states in the control of the multi-level cell are determined by the read current. A first data line Π20 represents a first state ("〇" state), a second data line 1122 represents a second state ("1" state), and a third data line 1124 represents a third state (&quot ;-Γ state), and the fourth data line 1126 represents a fourth state ("-2" state). The highest read current state requires a high current for the read operation. The reduction of the activation region, for example to 1/10 size, reduces the current density of the diode to less than about 103 A/cm2. In one embodiment, the four states of the read current are each: 4 nA, 40 η Α, 0·4 μΑ, and 2 μΑ. The present invention can be extended to further divide the read current window for a memory cell having multiple bits, such as a 4-bit representation of 16 bits in a memory cell. The following is a brief overview of a four-type resistive memory material suitable for use in implementing the memory structure of the present invention. The first type of memory material suitable for use in embodiments of the present invention is a super giant magnetoresistance ("CMR") material, such as PrxCay Mn03, wherein _ x:y = 0.5 : 0.5, or other having X : 〇 丨 丨; y : The composition of W. The CMR material containing manganese oxide may also be selected. The exemplary method for forming the CMR material is to use ρν〇 sputtering or magnetron sputtering, with Αγ, Ν2, 〇2, and/or The gas is at a pressure of from 1 mTorr to 1003⁄4 Torr. The temperature of the deposition can be from room temperature to 6 〇〇. (:, depending on the processing condition of the post-product effect. It can be used with a length to width ratio of 5 Measure & to improve the filling performance. In order to improve the filling performance, it is also possible to use a bias voltage of tens of voltages to hundreds of voltages. On the other hand, the dc bias test is 19 200832679

rW3061PA * Tube can be used at the same time. A magnetic field of tens of Gauss to as high as one Tesla (10,000 Gauss) can be applied to improve the magnetic crystalline phase. A deposition annealing treatment may be optionally performed after vacuum or N2 atmosphere or 〇2/any mixed atmosphere to improve the crystalline state of the CMR material. The annealing temperature is substantially between 400 ° C and 600 ° C and an annealing time of less than 2 hours.

The thickness of the CMR material depends on the design of the unit structure. CMR thickness from 1 〇 nm to 200 nm can be used as the core material. A buffer layer of YBC 〇 (YBaCu 〇 3 ', which is a one-side superconducting material type) is usually used to promote the crystalline state of the 10 CMR material. YBCO is deposited prior to deposition of the CMR material. The thickness of YBCO ranges from 30 um to 200 um. The second type of memory material is a two-element compound, such as Nix〇y;

AlxOy ' WxOy, ZnxOy, ZrxOy, CuxOy, etc. where X : y = 〇 5 : 〇 · 5 ' or other composition having χ : 0 〜 1 ; y : 〇 〜1. An exemplary formation method is to use a PVD sputtering or a magnetron sputtering method, using Ar, N2, 〇2, and/or He as a reaction gas and under a force of 1 mTorr-loo. _ Zrx〇y ; CuxOy et al. The deposition is usually carried out at room temperature. A gauge tube with an aspect ratio of 1-5 can be used to improve fill performance. In order to improve the filling energy, a DC partial housing of several tens of voltages to several hundreds of voltages can also be used. The DC bias and the calibrator can be used simultaneously if required. Alternatively, a deposition annealing treatment may be performed after the vacuum or helium atmosphere or the 爪 2 claw 2 mixed atmosphere to improve the oxygen distribution of the metal oxide. The annealing temperature is in the range of 400 ° C to 600 ° C and an annealing time of less than 2 hours. An alternative method of formation is to use PVD sputtering or magnetron sputtering. The method is Αγ/02, Ar/N2/〇2, pure 02, He/02, He/N2/02, etc. It is a reaction gas and is lightly measured by a metal oxide such as Ni, Ti, Al, W, Zn, Zr, Cu, etc. under a pressure of 1 mTorr to 100 mTorr. The deposition is usually carried out at room temperature. A measuring tube having an aspect ratio of 1.5 can be used to improve the filling performance. To improve the filling performance, a DC bias of several tens of voltages to several hundreds of voltages can also be used. The DC bias and the measuring tube can be used simultaneously if required. Alternatively, a deposition annealing treatment may be performed after vacuum or N2 atmosphere or 〇2^2 mixed atmosphere to improve the oxygen distribution of the metal oxide. The annealing temperature is in Xin 4(9). Between c and 6 〇 0 ° C and an annealing time of less than 2 hours. Another method of formation uses the oxidation of a high temperature oxidation system, such as a high temperature furnace or a rapid heat pulse ("RTP" system. The temperature ranges from 200 to 700 C with a pure enthalpy: or Ο 2/% mixed gas. From millitorr to 1 atm. The time can range from a few minutes to several hours. Another oxidation method is plasma oxidation. Use pure 〇2*Αγ/〇2 mixed gas or Αγ/Ν2/〇 2 mixed gas at 丨 millitorn to 1 Torr millitorn pressure: RF or DC source plasma to deuterate metal surface, such as thief, Ti, Ai, w, Ζη, _Zr, or Cu, etc. Oxidation time It can be in the range of seconds to minutes. The oxidation temperature can be between room temperature and 3, C_, depending on the plasma oxidation temperature. The second type of memory material is a polymer material, such as doping with c(9), Ag, etc. TCNQ or PCBM_TCNQ mixed polymer. One method of formation is by steaming by hot steaming, electron beam evaporation, or molecular beam streak ("mbe"). - Solid state TCNQ and dopant particles are co-steamed in a single reaction chamber. Solid state TCNQ and dopant particles are placed in the boat or 21

200832679TW3061pA ‘A boat or a ceramic boat. A high current or an electron beam melting source is applied to mix and vaporize the material onto the wafer. There is no reactive chemistry or gas. The deposition was carried out under HT4 to 8' torr pressure. The wafer temperature ranges from room temperature to 200 °C. A deposition annealing treatment may be optionally performed after vacuum or % atmosphere to improve the composition distribution of the polymeric material. The annealing temperature ranges from room temperature to 3 〇〇〇c with an annealing time of less than 1 hour. Another technique for forming polymeric memory materials is to use a spin coating with a Φ-doped-TCNQ solution at a rotational speed of less than 1000 rPm. After the spin coating, the wafer is supported (substantially at room temperature or at a temperature of less than 2 〇〇〇c) for a period of time sufficient for the solid to form. This support time ranges from a few minutes to a few days, depending on the time and condition. The fourth type is a chalcogen compound material such as GexSbyTez, wherein χ: 丫: z = 2 : 2 : 5, or other combination having x ··〇· 5 ; y ·· 〇~5 ; z : 〇~1〇 Things. It is optional to use GeSbTe with doping such as N-, Si-, Ti-, or elemental doping. An exemplary method for forming a chalcogenide material is to use a pvD sputtering or magnetron sputtering method using a source gas of Ar, N2, and/or II at a pressure of from Torr to 100 mTorr. The deposition is usually carried out at room temperature. A measuring tube with an aspect ratio of 1-5 can be used to improve filling performance. A DC bias of tens of voltages to several hundred voltages can also be used to improve the filling behavior. On the other hand, the DC bias and the measuring tube can be used simultaneously. A deposition annealing treatment may be optionally performed after the vacuum or the team atmosphere to improve the crystalline state of the chalcogenide material. Annealing temperature is 22

The 200832679 face 1PA fe has an annealing time of less than 30 minutes. The thickness of the chalcogenide material depends on the design of the unit structure. Generally, a chalcogenide material having a thickness of more than 8 nm has a phase change characteristic, so that the material exhibits at least a second stability type. An embodiment of the memory cell of the bistable RRAM 300 may include a phase change memory material as the first resistive random access memory layer 310 and a second resistive random access memory layer 320, including a chalcogenide type material. And other materials. The chalcogen element includes any one of four elements of oxygen (0), sulfur (3), selenium (86), and ruthenium (^) constituting part VI of the periodic table. A chalcogenide compound contains a compound of a chalcogen element and another positively charged element or substituent. The chalcogenide alloy contains a combination of a chalcogenide compound and other materials, such as a transition metal. The monochalcogenide alloy usually contains at least one element of the sixth row of the periodic table, such as germanium (Ge) and tin (Sn). Generally, the chalcogenide alloy includes a combination containing at least one of strontium (Sb), gallium (Ga), indium (In), and silver (Ag). Many phase change memory materials have been described in the technical literature, including alloys: Ga/Sb, In/Sb, In/Se, Sb/Te, Ge/Te, Ge/Sb/Te, _In/Sb/Te, Ga/Se/Te, Sn/Sb/Te, In/Sb/Ge, Ag/InISb/Te,

Ge/Sn/Sb/Te, Ge/Sb/Se/Te, and Te/Ge/Sb/S. In the Ge/Sb/Te alloy family, a wide range of alloy compositions are available. The composition is characterized by TeaGebSbn^aw. One researcher has described that the most effective alloy is that the average concentration of Te in the deposited material is less than 70%, representatively less than about 6 〇 0 / 〇 and ranging from as low as about 23% up to about 58%. Te, and most preferably about 48% to 58% Te. The Ge concentration in the material is above about 5% and in the range of an average of from about 8% to about 30%, the remainder is typically 5%. Ge 23

:W3061PA 200832679 The concentration is preferably in the range of from about 8% to about 40%. The remainder of the main constituent elements in the composition is Sb. These percentages are the atomic percentages of all 100% constituent element atoms. (Ovshinsky, U.S. Patent No. 5,687,112, pp. 10-11.) Special alloys evaluated by another researcher include Ge2Sb2Te5, GeSb2Te4, and GeSb4Te7, (Noboru Yarnada, "Potential of Ge-Sb-Te Phase-Change Optical" Disks for High-Data-Rate Recording", SPIE v. 3109, pp. 28-37 (1997).) More specifically, transition metals such as chromium (Cr), iron (Fe), nickel (Ni), cesium ( A mixture or alloy of Nb), Pd (Pd), platinum (pt), and the like can be combined with Ge/Sb/Te to form a phase change alloy having programmable resistance properties. A specific example of a memory material that can be used is provided in U.S. Patent No. 5,687,112, the entire disclosure of which is incorporated herein by reference. The phase change alloy can be transformed between a first structural state and a second structural state, the material of the first structural state being a substantially amorphous solid phase, and the second junction

The material of the configuration is a substantially crystalline solid phase unit in its active channel region with its local regularity. These alloys are at least two states. The term amorphous is used to describe a relatively small, more complex structure of a single-crystal, which has detectable characteristics such as a higher electrical conductivity than a crystalline form. The term "crystalline" is used to describe the relatively regular and relatively uniform structure of the f-type amorphous structure; the T-generation is less resistive than the amorphous one. Phase change Erqiu does not have a completely amorphous and completely crystalline morphology between the local _ different detectable state electrical conversion. _ 曰 及 and the material properties of the crystal phase change affect the original; :: electron density and activation energy. The material can be converted between a non-state phase or a mixture of at least two solid phases 24 200832679 to provide a gray-scale band in a completely amorphous and fully crystalline form. The electrical properties in the material change accordingly. The phase change alloy can be converted from one state to another by using an electric pulse. It has been observed that shorter, higher amplitude pulses tend to change the phase change material to a substantially amorphous form. A longer, lower amplitude pulse tends to change the phase change material to .^ JL «Λ Q rt/ Ab , 丹 roughly, ,, 〇日日恶恶. The amount in a shorter, higher amplitude pulse balance is high enough to break the bond of the crystalline structure and is short enough to prevent the atoms from rearranging into a crystalline form. A suitable and pulsed data sheet can be determined without undue experimentation, especially for specific phase change alloys. In the disclosure below, the phase change material refers to GST and it will be appreciated that other materials can be used to change the phase. The material described herein that can be used to implement the pCRAM is Gc2Sb2Tc^. Other programmable resistances that can be used in other embodiments of the present invention include bulk doped GST, GexSby, or others that can be changed using different crystalline phases to determine resistance. Type of material; PrxCayMn03, PrSrMn03, • ΖΐΌ:, WQx, TiOx, ALOx, or other material that can change electrical resistance using electrical impulses; 7,7,8,8-tetracyanoquinonedioxane (TCNQ) Methane fullerene M-phenyl C61-methyl butyrate (PCBM), TCNQ-PCBM, Cu-TCNQ, Ag_TCNQ, C6 "TCNq, TCNQ doped with other metals, or other pairs with electrical pulse control A polymeric material of a state or a polymorphic resistance type. Additional information on the manufacture, component materials, use and operation of phase-change random access memory devices can be found in June 2005. US Patent Application No. 11/155,067, entitled "Ding" Hin 25

The present invention has been described in connection with the preferred embodiments. Various changes and modifications can be made without departing from the spirit and scope of the invention. The specification and the drawings are intended to be illustrative of the present invention and are not intended to be limiting, and the scope of the invention is defined by the scope of the appended claims.

26

-W3061PA 200832679 [Simple diagram of the diagram] The brother 1 is the circuit diagram of the sturdy pen-resistant random access memory array of the invention. 2 is a simplified block diagram of a accumulation circuit of a bistable resistive random access memory architecture in accordance with an embodiment of the present invention. Figure 3 is a simplified process diagram of the present invention to illustrate the steps of fabricating a bistable resistive random access memory device having a standard tungsten plug (W-plug) or via window in a single memory cell. Fig. 4 is a process diagram of the present invention showing the next step of fabricating a bistable resistive random access memory having a tungsten plug structure. 5 is a process diagram of the present invention, which illustrates that a tungsten oxide (wOx) region is formed by a dielectric spacer etching, a dry oxygen plasma etching, and a wet removal. FIG. 6 is a process diagram of the present invention, which shows The next step of fabricating a dual 13⁄4 resistive random access § memory with bit line formation. Figure 7 is a process diagram of the present invention showing the next step in fabricating a bistable resistive random access memory coupled to a selected device. Figure 8 is a process diagram of a process of the present invention illustrating a first embodiment of a memory structure having a multi-memory layer and a tungsten oxide region for use in a multi-layer cell function. Figure 9 is a process diagram of the present invention illustrating a second embodiment of a memory structure having a multi-memory layer and a tungsten oxide region for use in a multi-layer cell function. Figure 10 is a process diagram of the present invention, which is illustrated for use in a multi-layer unit.

A third embodiment of the memory structure of a multi-memory layer and a tungsten oxide region of 200832679W3〇61PA w. The πth diagram is an illustration illustrating the control of the multilayer unit for reading current in the memory structure in which the tungsten oxide region is the active region in the first embodiment of the present invention. [Main component symbol description] 100 bistable resistive random access memory array 123, 124 word line 128 source line 132 bottom electrode element 134 top electrode element 135 memory unit 141, 142 bit line 146 block 150 , 151 , 152 , 153 access transistor 200 integrated circuit 260 memory array 261 column decoder 262 word line 263 terminal decoder 264 bit line 265 bus 266 block 267 data bus 268 bias supply voltage 269 biasing device 271 write line 272 data output line 275 integrated circuit 300 process diagram 310 ^ 312 dielectric component 320 barrier material 330 crane material 340 tungsten material surface 400 process diagram 420 barrier element 28 200832679_pa

430 Tungsten Bolt Element 500 Process Diagram 510,: 512 Dielectric Gap Wall 520 Tungsten Oxide Element 600 Process Diagram 610 Barrier Layer 620 Bit Line Layer 700 Process Diagram, 710 Top Bit Line 720 PN Diode 730 Bottom Bit Line 800 process diagram 810 first memory layer 812 tungsten plug element or first electrode 814 barrier element 816 tungsten oxide region 830 bottom bit line 820 NP diode 850 second memory layer structure 860 second bit line 862 barrier layer 900 Process diagram 910 First memory layer structure 920 Tungsten plug structure 922 Barrier element 950 Second memory layer structure 960 Tungsten plug structure 980 Second bit line 982 Barrier element 1000 Process diagram 1010 First memory layer structure 1020 First pin Portion 1022 Second plug portion 1024 Barrier element 1050 Second memory structure 1062 First plug portion 1100 Figure 1110 X-axis current amount 1112 Y-axis read times 1120 First data line 1122 Second data line 1124 Third Data line 1126 fourth tributary line 29

Claims (1)

200832679 Missing - Ten, the scope of application for patents · · - a memory structure with multiple memory layers, including: - brother - memory layer structure, which has a - surface with a major electrode - oxygen In the region I, the tungsten oxide region extends from the main surface of the first electrode and is electrically connected between the first electrode and a second electrode. The first electrode has a size substantially similar to the size of the oxidized town region; And a first-electrode layer structure, _to the first-memory layer structure, 10 the first memory layer structure has a first electrode having a main surface and an oxidized dummy region, the tungsten oxide region being composed of the first electrode The main surface is applied to the first § memory layer structure and electrically connected to the second electrode of the second memory layer structure and the second memory layer structure, the second memory layer structure The first electrode has a size that is substantially similar to the size of the tungsten oxide region of the second memory layer structure. The memory structure of claim 1, wherein the tungsten oxide region provides a multi-layered function for operation in the first memory layer. The memory structure of claim 1, wherein the first electrode comprises a plug structure filled with tungsten. 4. The memory structure of claim 3, further comprising a barrier material surrounding the outer surface of the tungsten in the plug structure. 5. The memory structure of claim 1, further comprising an N-P diode electrically coupled to the first electrode of the first memory layer structure. 30 200832679rW3〇61PA 6. The memory structure according to claim 5, wherein the first bit line is electrically coupled to the N-P diode. 7. The memory structure according to claim 5, wherein the semiconductor structure is electrically connected to the second memory layer structure, as in claim 7 of the patent application scope. The memory structure is described as follows: the 1st-inclusive-second-bit line is electrically coupled to the "Hg tungsten oxide region of the first-memory layer structure and the Ρ-Ν diode. 9. If the claim is for the _ _ 8th ship to find the dragon structure, the further one of the third bit line is electrically coupled to the second memory layer to form the tungsten oxide region. 10. A memory structure having a plurality of memory layers, comprising: a first memory layer structure having a first surface and a tungsten oxide region, the tungsten oxide region extending into the first The main surface of the electrode is connected to the first electrode and the second electrode; and the "% r" is a first memory layer structure coupled to the first memory layer structure, the second memory layer structure has a a first electrode having a major surface and an oxidized crane region, the tungsten oxide region extending into the main surface of the first electrode to the second memory layer structure and the first electrode of the second memory layer structure and the The second electrode of the second memory layer structure is connected. The memory structure of the invention of claim 2, wherein the tungsten oxide region provides a multi-layer function of operation in the first memory layer. 31: W3061PA 200832679, 119. The memory structure of claim 10, wherein the first electrode comprises a plug structure filled with tungsten. /, as described in the application of the memory structure described in the coffee, a step of the barrier material surrounding the outer surface of the tungsten in the plug structure. 14. The memory structure as described in the patent application No. Ditao, the advance: 3: Ν · Ρ diode electrical - combined to one of the first memory layer structure 15 · · f material range 14th The memory structure has a first bit line electrically coupled to the ^^^ diode. The memory structure according to claim 10, wherein the diode wire is coupled to the second memory layer structure, and the memory structure is as described in claim 16 of the patent application. The second strand of the second strand of the lion is combined with the rolling pigeon region of the first memory layer structure and the factory ^^ diode. Further, a cow = 8 persons, such as the memory structure described in claim 17, wherein the third bit line is electrically coupled to the second memory layer structure. The oxidized crane area. A memory structure having a plurality of memory layers, comprising: a + first memory layer structure having a first electrode having a major surface and a tungsten oxide region, the tungsten oxide region being composed of the first electrode Extending the surface and electrically connecting the first electrode and the second electrode to the first electrode to have a plug structure, the plug structure having a first plug portion of a size and a second plug having a size Part, 豸第-栓 part 32 200832679 彻. The size of the brewing ^ has a smaller value than the size of the second plug portion, the tungsten oxide region has a size substantially similar to the size of the first electrode; and a second memory layer structure having a first electrode having a major surface and a tungsten oxide region extending from the major surface of the first electrode to the second memory layer structure and the first electrode and the second memory layer structure The second electrode of the second memory layer structure is electrically connected, and the first electrode of the second memory layer structure has a size substantially similar to the size of the size of the tungsten oxide region of the second memory layer structure. The first electrode of the second memory layer structure has a plug structure having a first plug portion having a size and a second plug portion having a size, in the second memory layer structure The size of the first plug portion in the plug structure has a smaller value than the size of the second plug portion in the plug structure of the second memory layer structure, the second memory layer junction Of the first electrode having a first size based on a first substantially similar to the size of the region of the tungsten oxide layer structure of the second memory. • The memory structure of claim 19, wherein the first plug portion is self-aligned to the second plug portion. 21. The memory structure of claim 20, wherein the first plug portion is non-self-aligned to the second plug portion. 22. A method of fabricating a memory device, comprising: forming a plug structure that surrounds a plug material with a barrier material and disposed between dielectric elements; etching a top portion of the plug material and the barrier material , using a 33rd; W3061PA 200832679 ▼ a chemical dry etch followed by a second chemical wet etch; forming a dielectric spacer on a major surface of the etch plug material; using dry oxygen plasma removal to form a The tungsten oxide region enters the major surface of the etch test material and forms a one-dimensional line to the dielectric spacer and over the tungsten oxide region. 23. The method of claim 22, wherein the first chemical dry name includes an SF6 stem. 24. The method of claim 22, wherein the second chemical groove etch comprises an isotropic etch using a barrier of chlorine, boron trichloride or argon. 25. The method of claim 22, wherein the dry oxygen plasma removal comprises a 02/N2 or 02 claw 2/112 mixed chemistry. 26. The method of claim 22, wherein the dry oxygen plasma comprises a pure oxygen gas and a plasma comprising a direct plasma, a magnetic field enhanced reactive ion plasma, or a downstream plasma. ® 27. The method of claim 22, wherein the bit line comprises a bit line on the barrier layer. 34