TWI329356B - Multilevel-cell memory structures employing multi-memory layers with tungsten oxides and manufacturing method - Google Patents

Description

132' « 1329356

达达编号号: TW3061PA * IX. Description of the Invention: [Technical Field] The present invention relates to a high-density memory device based on a programmable resistive memory material, which comprises a metal oxide type material and other materials, and a manufacturing process The method of this device. [Prior Art] Phase change memory materials are widely used for reading and writing optical discs. Such materials have at least two solid phases including, for example, a generally amorphous solid phase and a generally crystalline solid phase. Laser pulses are used on the read and write optical discs to switch between phases and to read material optical properties after phase changes. Phase change memory materials, such as chalcogenide type materials and the like, can also cause a phase change by applying an amount of current suitable for implementation on the integrated circuit. This generally amorphous morphology is characterized by a higher electrical resistance than the general crystalline morphology, which has been detectable to reveal data. These features have been used to create a non-volatile memory circuit that can be programmed to form a non-volatile memory circuit that can be accessed by random access. The change from amorphous to crystalline is usually a low current operation. Changing from crystalline to amorphous, here referred to as resetting, usually a higher current operation, including a short high current density pulse to melt or break the crystalline structure, followed by phase change material rapid cooling, quenching phase Changing the process allows at least a portion of the phase change structure to settle in an amorphous form. The strength of the reset current that requires phase change material conversion from crystalline to amorphous is minimized. The strength of the reset current required for resetting can be achieved by reducing the phase change in the cell 6 1329356

" Sanda number: TW306IPA * The size of the material element is reduced by the contact area between the electrode and the phase change material, so that a relatively high current density can be obtained by changing the small absolute current value of the material element. One direction of development has been to create small holes in the integrated circuit structure and to fill the holes with a small amount of programmable resistance material. The patents for the development of the small hole include: US Patent No. 5,687,112 issued to Ovshinsky on November 11, 1997, ''Multibit Single Cell Memory Element Having Tapered Contact'; granted to Zahorik et al. on August 4, 1998. US Patent No. 5,789,277, "Method of Making Chalogenide [sic] Memory Device"; US Patent No. 6,150,253 issued to Doan et al. on November 21, 2000, "Controllable Ovonic Phase-Change Semiconductor Memory Device and Methods of Fabricating the Same" ° A problem has arisen in the manufacture of such a device having a very small size and a process that meets the strict specifications required for a large memory device. If a large memory capacity is sought, there is a high demand per The memory layer stores a plurality of _ bit phase change memory. [Invention] The present invention provides a multilayer cell (MLC) memory structure having a multi-memory layer structure, each memory layer structure including a tungsten oxide region, Defining different read current quantities for multiple logic states. Each memory layer structure uses tungsten oxide The area provides multi-level cell functions to provide two-bit information to form four logic states, where four logic states are equal to four different read currents. One 7 1329356

* Sanda number: TW3061PA A memory structure with two memory layers provides a four-bit storage address and sixteen logic states. In the first embodiment, a multi-layer cell memory structure includes a first memory layer structure and a second memory layer structure. Each memory layer structure is a one-dimensional line that is substantially and electrically connected to the top. The first or lower memory layer structure is connected to an N-P diode, wherein the Ν·Ρ diode is connected to the first bit line. The second or upper memory layer is connected to the p·Ν diode at the bottom, wherein the Ρ_Ν diode is connected to the second bit line. The second bit line is commonly used between the first memory layer structure and the second memory layer structure. The second 70-line is then connected to the first memory layer structure. The first and second memory layer structures each include a tungsten oxide region extending into a major surface of the tungsten plug component, the outer surface of the tungsten plug being surrounded by a barrier element. The critical dimension of the tungsten oxide region is less than the size of the tungsten plug component. The critical size of the oxidized crane area is also smaller than the size of the Ρ·Ν diode. The critical dimensions of the oxidized crane area and the relationship between the key dimensions of the H-bolt element and the body of the body can be expressed by the following mathematical formula:

dA-dw - 2 * tD The parameter dA represents the money of the money, the parameter "represents the § key size of the plug structure element" and the parameter 卜 represents the key dimension of the polar body. The ride of the ρ·Ν diode The size is larger than that of the yttrium oxide field: dA>dw. Qiuyu is not in the first-common case of a multi-layer cell memory memory layer structure and a first- & first sound structure. First and second memory 曰Ls—tungsten oxide 8 1329356 extending from the main surface of the tungsten plug element

: TW3061PA area, the outer surface of the tungsten plug element is surrounded by a barrier element. Each tungsten germanium structure has a size small enough to omit dielectric in the fabrication process: The critical dimension of each tungsten plug structure is approximately the same as the critical dimension of the active region tungsten region. (Emulsification In the third embodiment, a multi-layer cell memory structure includes a first memory layer structure and a second memory layer structure. The first memory layer structure includes a tungsten oxide region, a first plug portion, and a first a second plug portion of the tungsten plug structure, and the outer wall of the second plug is surrounded by a barrier element. The first plug portion: the critical dimension is similar to the critical dimension of the active region, that is, the oxidation = region. The main surface or the top surface of the first plug portion extends. The first plug portion has a smaller dimension than the second plug portion. In each of the body structure tissues, the first inspection portion and the second plug portion enable ^ Self-aligned or non-self-aligned process manufacturing. Also disclosed is a method of fabricating a memory device that includes a plug structure that blocks the plug material and is placed between the dielectric members. The tantalum material is etched using a first chemical dry etch followed by a dielectric spacer in the main surface of the Nissan material and the n-tungsten region enters the etched crane area. The electric wall is hidden and the oxidation is ', and the 5' has a more careful Memory layer structure, which has a ^The main structure comprises a oxidized crane region, and the oxidized crane region is electrically connected to each of the first electrode and the first electrode and the second electrode. The surface extends and has a substantial phase at the electrode.

The three Weiwei: TW3061PA is similar to the size of the oxidized crane area; the first to the first memory layer structure, with a ~2 memory layer structure, coupled with - tungsten oxide region, tungsten oxide region by:: the main surface of the - The electrode to the second memory layer structure and extending on the main surface of the second electrode is substantially similar to the first electrode of the first electrode structure/second electrode structure of the second memory layer structure The size of the bulk layered tungsten region. Oxygen of the alpha-hidden layer structure The structure and method of the present invention are not intended to define the present invention in the following. Other embodiments, features, aspects, and advantages of the invention will be apparent from the description and appended claims. The invention will be described in detail with reference to the specific embodiments and drawings. [Embodiment] Descriptions of structural embodiments and methods of the present invention will be described with reference to Figs. 1 to 11. It is to be understood that the invention is not limited to the embodiments of the invention, and the invention may be practiced otherwise. Similar elements in different embodiments are generally illustrated by like reference numerals. Different embodiments are related to the fabrication of ternary memory structures and memory, such as non-volatile embedded memory to implement programmable resistive RAM. Examples of the resistive device ram are a resistive memory (RRAM), a polymer memory, and a phase change memory (PCRAM). Figure 1 is a diagram illustrating a bistable resistive random access memory array 100 that can be implemented as shown herein. In the description of the circuit diagram in Figure 1, a total of 1329356

" Three-sided: TW3061PA ‘The source line word line 124 is arranged substantially parallel in the γ direction. The bit 70 lines 141 and W are arranged substantially in parallel in the X direction. Therefore, the γ decoder and the word line driving device in the block (4) are engaged to the word lines .123 and 124. The -X decoder and the set of sense amplifiers in block 146 are coupled to bit lines 141 and 142. A common source line 128 is coupled to the source terminals of the access transistors 150, 151, 152, and 153. The closed-pole coupling word line 123 of the transistor 15() is accessed. The gate of the transistor 151 is coupled to the word line 124. The gate of the transistor 152 is coupled to the word line 123. The gate of access transistor 153 is coupled to word line 12 4 . The drain of the access transistor 150 is coupled to the bottom electrode element 32 of the sidewall memory cell 135 having a top electrode component 134 and a bottom electrode component 132. Top electrode element 134 is coupled to bit line 141. It can be seen that the common source line 128 is shared by the two columns of memory cells, and is arranged in a column in the Y direction in the circuit diagram of the description. In another embodiment, the access transistor can be replaced by a diode or other structure to control current to a particular device in the array to read or write data. 2 is a simplified block diagram of an integrated circuit of the RJRAM architecture according to an embodiment of the present invention. The integrated circuit 275 includes a memory array implemented on a semiconductor substrate using a bistable resistive random access memory cell with sidewall activation terminals. A column of decoders 261 is coupled to a plurality of word lines 262 and arranged in columns in memory array 260. A terminal decoder 263 is coupled to a plurality of bit lines 264 disposed along the terminals in the memory array 260 to be read and programmed by the side wall terminal memory cells in the memory array 260. An address is supplied to the terminal decoder 263 and a column of decoder 261 on the bus 265. The sense amplifier and data write structure at block 266 is via data sink 1329356

The three-numbered: TW3061PA flow bank 267 is coupled to the terminal decoder 263. The data is supplied from the write line 271 to the data write structure in block 266 from the input/output of the integrated circuit 275 or other negative sources internal or external to the integrated circuit 275. In the illustrated embodiment, 'including other circuits on the integrated circuit', such as a general-purpose processing, or a circuit for a special purpose application, or a combination of modules, which can provide, bistable, reciprocating random access memory The system supported by the body unit array has a single day. The data is supplied from the sense output block 272 via the data output line 272 to the input/output port of the integrated circuit 275 or to the inside or outside of the integrated circuit 275: points of other data points. In this example, only the biasing device %9 is used to utilize a controller to dissipate the application of the supply voltage 268, such as reading, programming, wiping p, 4 = verifying, and verifying the voltage. This controller can be implemented using the Control II special purpose logic circuit in this technique. In an alternate embodiment, 'peanut uranium~ contains a general purpose processor that can be implemented in the same integrated circuit to control the operation of the device. In another embodiment, a combination of a special logic circuit and a general purpose logic circuit is used to present only the controller. Figure 3 is a simplified process diagram such as 〇, which illustrates the manufacture of a single memory limb that is both early and corpse-infused; Fe Le: T-plug (w-拴) or via bistable resistive The reference step of the process of taking the body is as follows: the via window or the contact hole is formed by the <冤兀 member 310, 319 α being disposed in the ^ and the barrier material 320. A tungsten material 330 filling machine: grinding Ξ = Γ 32 () between the layers of the window ... grinding techniques such as chemistry, such as rods or back to the surface of the tungsten material 330 after deposition on the surface 340 '亍. In an implementation 丨tij W, the critical dimension (CD) of the tungsten plug (W-plug) 330 12 1329356

'Sanda number _ TW3〇61PA • The following design: 〇.13μπι technology node, w·plug CD window or hole between Ο.ίμιη to 〇.25μιη range. Figure 4 is a process diagram 400 showing the next step in fabricating a bistable resistive random access memory' which is to perform a recess etch of the tungsten plug component 430. The recess etch process of the tungsten plug component 430 can be performed by SF6 dry etching, or other chemicals including Ar and/or Ν2 and/or 〇2. The aspect ratio of the groove silver engraving is about 1, for example, the critical dimension of 200 nm has a depth of about 200 nm. After the etching of the groove, a barrier isotropic etching process is etched by the barrier material 320 to remove the portion. Ti or TiN to form a barrier element 420. A suitable etching technique for the isotropic etching of the barrier material is dry etching with chemical chlorine (C12) and/or tri-carbide (BCD and/or other 'such as hydrogen (Ar). A solvent such as EKC265 can be used. Or other wet cleaning to remove the polymer residue during the etching of the barrier material. Figure 5 is a process diagram of Figure 5, which illustrates that tungsten oxide (w〇x) is etched by a dielectric spacer, a dry oxygen The plasma etching and the wet removal are formed. In the dielectric barrier etching, the process involves depositing a dielectric film and etching the dielectric spacers 51, 512. The dielectric film is deposited by chemical vapor deposition (CVD) technology. The tungsten plug 70 is on the 43. The suitable material for realizing the dielectric film includes yttrium oxide 〇2, nitrogen 矽S1N or SiON. The dielectric film has the property of conformal property. The basic thickness of the dielectric film is A dielectric film is deposited on the tungsten plug element 43A from about 50 nm to about 100 nm, and then etched to form a dielectric spacer 51〇, S1 0' to the chemical substance 匚4 and/or C4FS. The money is engraved as a suitable for the dielectric spacer. The money is engraved on the upper surface of the crane bolt element 430 and has some micro-tungsten grooves. Ensure sufficient over-etching - 13 ^ 329 356

2^1§: TW3061PA After the dielectric spacer is etched, the WOX element 520 is dried by oxygen (〇2) plasma to remove I. Examples of oxygen-electric dry removal include 〇2 gas electropolymerization chemistry, or 混合2 plasma mixing chemistry, such as (VN2 or 〇2/N2/H2. 〇2 plasma is suitable _ mixed chemistry including 〇 2^ 2. 〇2/N2/H2 or pure 〇2 gas and a plasma: two straight plasma, magnetic field enhanced reactive ion plasma, or downstream plasma. The parameters of the downstream plasma's include a pressure of about 1500 mTorr. The power is about 3,000 sccm/200 sccm, the temperature is about 150 ° C, and the duration is about 4 sec. 2 A wet removal step is performed to remove the polymer produced during the dielectric spacer etching process. The removal compound is an aqueous organic mixture, such as EKC265 solvent or other similar or similar mixture type. Several of the electrical equipment have been sufficiently removed, and the wet removal step is selective. Figure 6 is a process diagram of Figure 6 The next step of fabricating a bistable snubber-type random access memory having bit line formation. An optional step is to deposit a barrier layer 610 over the dielectric elements 310, 312 and dielectric gap using chemical vapor deposition. Wall 51〇, 512. For example, titanium nitride (TiN) or (TaN) is a suitable material for realizing the barrier layer 610. If the bit line layer has sufficient adhesion when deposited, the barrier layer 61 is an optional step if the deposition of the barrier layer is performed. The bit line layer 620 is deposited on the barrier layer 610. If the deposition of the barrier layer 610 is omitted, the bit line layer 620 is directly deposited on the dielectric elements 31, 312 and the dielectric spacers 510, 512. The material used to implement the bit line layer 620 includes polycrystalline Si, W, Cu, or AlCu. If polycrystalline Si is used to implement the bit line layer 620, a large amount of doping is required to reduce the amount of resistance.

Sanda number: TW3061PA Process diagram 600 shows a simplified memory cell with memory layer structure 85〇 and top county π line 710' which includes only bit line layer 62〇 or bit 70 line layer 620 and barrier layer 6_ combination, with dielectric spacers 510, 512, and " electrical components 310, 312. Figure 7 is a process diagram showing the fabrication of a bistable resistive random access memory connected to a selected ft. The memory layer structure 85A is coupled to the P-N diode 72A, which is then coupled to the bottom bit 70 line 730. Suitable materials for achieving the bottom bit line layer 730 include polycrystalline Si, W, Cu, or AlCu. ♦ FIG. 8 is a process diagram illustrating a first embodiment of a memory structure 8 具有 having a multi-dimensional memory layer and a tungsten oxide region for a multi-cell function. In this embodiment, the memory structure 8〇〇 includes two memory layers, a third memory layer 810 and a second memory layer 850. First memory layer 810 is coupled to N-P diode 820, which is then coupled to bottom bit line 83A. The first memory layer structure 810 includes a tungsten oxide region 816, a tungsten plug component 812, and a barrier element 814. The tungsten oxide region 816 extends into the main surface of the ballast element M2 or a first electrode 812. Barrier element 814 surrounds tungsten detector element 812. The tungsten oxide region 816 in the first memory layer structure 810 is electrically contacted to a second bit line 860 or a second electrode that is coupled to the first memory layer structure 8. The second bit line 860 includes only the bit line 730, or a combination of the bit line 73A and the barrier layer 862. The second bit line 86A of this embodiment provides a dual purpose, the first being the top bit line combined with the first memory layer structure 81A, and the second being the second memory layer structure 85〇. Bottom bit line β 1329356

Sanda number: TW3061PA The second bit line 860 is electrically connected to the top of the p_N diode 720, which is then electrically coupled to the second memory layer structure 850. The second memory layer structure 850 includes a tungsten oxide region 520, a crane plug element ο and a barrier element 42 〇 0 oxygen • a tungsten region 52 〇 extending into the main surface of the tungsten plug element or the first electrode 430. The barrier element 420 is surrounded The tungsten plug component 430. The tungsten oxide region 520 in the second memory layer structure 850 is electrically connected to the top bit line or the third bit line 71A, or the first and second first hidden layer structures 71. The second electrode 71. The third bit line 71 〇 includes only φ with a bit line 620 ′ or a combination of the bit line 620 and the barrier layer 610. The critical dimension of the active region (ie, the tungsten oxide region 52 〇 The size of the tungsten plug member 430 and the thickness of the dielectric spacers 51, 512. In this embodiment, the critical dimension of the tungsten oxide region 520 is smaller than the size of the tungsten plug member 43. The key to the tungsten oxide region 520. The size is also smaller than the size of the p_N diode 720. The relationship between the critical dimension of the tungsten oxide region 520, the critical dimension of the tungsten plug component 430, and the thickness of the PN diode 720 can be expressed by the following mathematical formula: dA~dw - 2 * The parameter dA represents the key size of the crane 520, “The key dimensions of the 430 representing the plug structure, and the parameter tD represents the critical dimension of the Ρ·Ν diode 720. The critical dimension of the β Ρ-Ν diode 72〇 is larger than the critical dimension of the tungsten oxide region 52〇, mathematical representation For dA>dW. In one embodiment, for example, the critical dimension of the 卩_|^ diode 720 is approximately 1⁄2 times the critical dimension of the tungsten oxide region 520, expressed as a mathematical expression > l〇*dA. Other exemplary key dimensions for the aforementioned parameters are but not limited to, the critical dimension of the Ρ·Ν diode 6 = 关键3 μπι critical dimension of the component is dw=〇 3 , the thickness of the dielectric spacer

Sanda number: TW3061PA • Key size ^, leg, and key dimensions of the tungsten oxide area ^, postal. Figure 9 is a process diagram illustrating a second embodiment of a memory structure having a multi-layer cell function and a plurality of memory layers and a yttrium oxide region. The memory structure 900 includes a first memory layer structure and a second memory layer structure 950. The first memory layer structure (10) includes an oxide field 816 extending from the main surface of the crane structure (4) surrounded by the barrier element 922. The third memory layer structure 95 includes an oxidized crane region no, which covers the main surface of the crane structure 96 that is surrounded by the barrier element 962. The Lu structures 920, 960 each have a size that is small enough to cause the intermediate step described in Figure 5 to be skipped during the fabrication of the s-resonant structure. The size of the tungsten plug structure 92〇, 960 is about the same as the critical dimension of the respective living dip, that is, the tungsten oxide region 816 and the tungsten oxide region 52〇. A second bit line 98, located above the tungsten oxide region 816 and below the P-N diode 430, has a barrier element 982 that is similar in size to the bit line component 720. Fig. 10 is a process diagram for explaining a third embodiment of the memory structure 1 具有 for the function of the multi-layer cell having the δ δ ** layer and the tungsten monoxide region. The memory structure 1000 includes a first memory layer structure 1〇1〇 and a first memory structure 1050. The first memory layer structure 1〇1〇 includes a oxidized crane region 816, a tungsten plug structure having a first plug portion 1〇2〇 and a second plug portion 1〇22, and the outer wall portion of the second plug is The barrier element 1〇24 is surrounded. The critical dimension of the first plug portion 1062 is a critical dimension similar to the active region, i.e., the tungsten oxide region 520, the tungsten oxide portion 816 extends from the major surface of the top surface of the first plug portion 1020. The first lG2G has a smaller size than the second plug portion 1022. 17 1329356

: TW3061PA system H non-self ^ second plug part 1Q22 can use self-alignment to use two micro-pair non-self-aligning process, base structure, first-plug part 1〇" close the door _ size two苐二_ size. The second plug portion 1022 self-alignment process involves reducing some of the steps. This reduction of the tantalum of the 3 contacts is reduced in some embodiments.

Covering a portion of the interlayer contact is formed by y ^ ^ Fi mwhn ^ σ g by removing the material from the contact between the interlayers of the uncovered dielectric structure to reduce the surface. One of the cross-sections is reduced. W" The contact between the contact points of the wound layer is performed as follows. The dielectric layer that is touched by the acoustic layer is at least partially covered by the dielectric layer at least partially by inter-layer (4) (four) $ a layer. Forming - the new dielectric layer is removed, leaving less interlayer contacts: one embodiment of the second is to engrave part of the new dielectric layer: V is reduced by the cross section Key Cover of the Contact 1: Touch =: The mechanical polishing (CMP) process is formed by a dielectric structure: the surface and opening of the contact of the cover. 02 Plasma oxidation is used to form a tungsten oxide region 520 and a tungsten oxide region 816. For more information on the self-alignment process and the CMP process, see U.S. Patent Application Serial No. 11/426,213, filed on Jun. 23, 1989, entitled, "Programmable Resistive RAM and Manufacturing

Method", the patent application is incorporated by reference in its entirety. Figure 11 is a diagram 1100 illustrating a multi-layered single 1329356 for the read current of the memory structure 8 为 with the tungsten oxide region 520 as the active region in the first embodiment.

'Sanda number: TW3061PA _兀 control example. Fig. 1110 shows the amount of current in the x-axis Π12 and the γ-axis indicates the number of times the port is taken 1114. The active region, i.e., the tungsten oxide region 52 〇, can operate in four states (2 bits/cell) for each memory layer, as defined by the amount of read current. The four different states in the control of the multi-level cell are determined by the read current. A first data line 1120 represents a first state ("〇" state), a second data line 1122 represents a second state ("1" state), and a third data line 1124 represents a third state ( "-1" state)' and the fourth data line 1126 represents a fourth state ("_2" state). The highest read current rush requires a south current for the read operation. The activation zone annihilation # 少 'for example, to 1/10 size' can reduce the current density of the diode to less than 103 A/cm 2 . In one embodiment, the four states of the read current are each .4 nA, 40 nA, 0.4 μΑ, and 2 μΑ. The invention can be extended to the memory cell split read current window with multi-bits, for example, the 4-bit state is 16 representation in the 〆纪忆 listening unit. The following is a brief overview of a four-type resistive memory material suitable for use in implementing the memory structure of the present invention. Applicable to the embodiment of the present invention, the 〆 pear remembrance material is a giant magnetoresistance ("CMR") material, such as prxcayMn〇3 'where _ x:y = 0.5 : 0.5, or other having X : 0~1 ; y : composition of 〇~1. You can choose to use CMR materials containing manganese oxide. An exemplary method of forming a CMR material is to use a PVD sputtering or a controlled plating method with Ar, N2, 〇2, and/or He as a source gas at a pressure of 1 mTorr to 100 mTorr. The temperature of the deposition can be determined from room temperature to 6 〇〇〇 C ' depending on the processing conditions of the post-deposition. A measuring tube having an aspect ratio of 5 can be used to improve the filling performance. To improve fill performance, DC bias voltages of tens of voltages to hundreds of voltages are also used. On the other hand, DC hemiplegia and benchmarking 1329356

Sanda number: TW3061PA. The tube can be used at the same time. A magnetic field of tens of Gauss to as high as one Tesla (1 〇, 〇〇〇 Gauss) can be applied to improve the magnetic crystalline phase. Alternatively, the annealing treatment may be performed after vacuum or Ν2 gas or 〇2/N2 atmosphere to improve the crystalline state of the CMR material. The annealing temperature is substantially between 400 ° C and 600 ° C and a desorption time of less than 2 hours. The thickness of the CMR material depends on the design of the unit structure. A CMR thickness of 1 〇 nm to 200 ηπι can be used as the core material. A buffer layer of ybc(R) (YBaCu(R) 3, which is a type of thermotropic superconducting material) is generally used to promote the crystalline state of the # CMR material. YBCO is deposited prior to deposition of the CMR material. The thickness of yb ranges from 30 um to 200 um. The second type of memory material is a two-element compound such as Nix〇y; TixQy ·,

AlxOy, WxOy ' ZnxOy ′ ZrxOy ; CuxOj^, where x : y = 〇 5 : 0.5 ′ or other composition having x : 0 〜 1 ; y : 0 〜1. An exemplary formation method is to use a PVD Tibetan mirror or a magnetic control method for killing money, using αγ, ν2, 〇2, and/or He as a reaction gas and under a pressure of 1 mTorr. The metal oxide is used as the dry standard, such as NixOy; Tix〇y; AlxOy; Wx0y; ZuxC)y, ZrxOy; CuxOy et al. The deposition is usually carried out at room temperature. A gauge tube with an aspect ratio of 1-5 can be used to improve fill performance. To improve the fill performance, a DC bias of tens of voltages to hundreds of voltages can also be used. The DC bias and the calibrator can be used simultaneously if required. A deposition annealing treatment may be optionally performed after vacuum or A atmosphere or CVN2 mixed atmosphere to improve the oxygen distribution of the metal oxide. The annealing temperature is at 400. (: to 600 ° C range and an annealing time of less than 2 hours. An alternative method of formation is to use PVD sputtering or magnetron plating 20 1329356

'Sanda number: TW3061PA - Method' is based on Ar / 〇 2, Α γ / Ν 2 / 〇 2, pure 〇 2, He / 〇 2, He / N2 / 〇 2, etc. as a reaction gas and at 1 mTorr -100 Under the pressure of millitorn, metal oxides are used as targets [such as Ni, Ti, A, W, Zn, Zr, Cu, etc. The deposition is usually carried out at room temperature. A gauge tube with an aspect ratio of 1-5 can be used to improve • fill performance. To improve the filling performance, a DC bias of several tens of voltages to several hundreds of voltages can also be used. The DC bias and the measuring tube can be used simultaneously if required. It is optional to carry out a deposition annealing treatment in a vacuum or N2 atmosphere or a 〇2/乂 mixed atmosphere to improve the oxygen distribution of the metal oxide. The annealing temperature is in the range of • 400 ° C to 600 ° C and an annealing time of less than 2 hours. Another method of formation uses the oxidation of a high temperature oxidation system such as a high temperature furnace or a rapid heat pulse ("RTP") system. The temperature ranges from 2 〇〇 ° C to 700. (The range is between pure 〇2 or 〇2/N2 mixed gas at a pressure of several millitorr to 1 atm. The time may range from several minutes to several hours. Another oxidation method is plasma oxidation. An RF or DC source plasma of a pure 〇24Αγ/〇2 mixed gas or a Αγ/Ν2/02 mixed gas at a pressure of 1 mTorr to 1 Torr to oxidize a metal surface such as Ni, Ti, WW, The oxidation time of Ζη, ® Zr, or Cu can range from a few seconds to several minutes. The oxidation temperature can range from room temperature to 3 〇〇〇C depending on the plasma oxidation temperature. The material is a polymer material such as a mixed polymer of TCNQ or PCBM-TCNQ doped with Cu, C60, Ag, etc. One method of formation is by thermal evaporation, electron beam evaporation, or molecular beam epitaxy ("MBE") evaporation of the system. A solid TCNQ and dopant particles are co-evaporated in a single reaction chamber. Solid TCNQ and dopant particles are placed in a boat or 21 1329356

Sanda number: TW3061PA A boat or a ceramic boat. A high current or an electron beam melting source is applied to mix and vaporize the material onto the wafer. No reactive chemistry or gas. The deposition was carried out at a pressure of 1 Torr to 1 Torr to 1 Torr. The wafer temperature is from room temperature to 200. (: Between ranges. It is optional to perform a deposition annealing treatment in a vacuum or helium atmosphere to improve the composition distribution of the polymer material. The annealing temperature is between 1 and 3 〇〇〇c in an annealing time of less than 1 hour. A technique for forming a polymer type memory material is to use a spin coating of a ginseng-TCNQ solution at a rotation speed of less than 100 rpm. After spin coating, a 'tower wafer (basically at room temperature or less than 2 〇) The temperature of 〇〇c is a period of time sufficient for the solid to form. This support time depends on the time and formation of the range from a few minutes to several days. The fourth type is a chalcogenide material such as GexSbyTez 'where x : y : z =2 ·· 2 : 5 ' or other composition having X : 0 - 5 ; y : 〇 ~ 5 ; z : 〇 ~ 10 . It is optional to use GeSbTe with doping, such as ν·, Si· , Ti-, or its element doping. / Lu Shicheng chalcogen compound material is exemplified by the use of PVD splash clock or magnetron plating method, which uses Ar, N2, and / or He source gases in the 丨The ear is under a pressure of 100 mTorr. The deposition is usually at room temperature. It is possible to use a measuring tube having an aspect ratio of U to improve the filling performance. To improve the filling property, a DC bias of several tens of voltages to several hundreds of voltages can be used. On the other hand, DC bias and measurement The quasi-tube can be used at the same time. The deposition annealing treatment can be carried out in a vacuum or N2 atmosphere to improve the crystal state of the chalcogenide material. The annealing temperature is from 1 to 22 I329356

Sanda number: TW3061PA 'The annealing time is less than 30 minutes between the ranges. The thickness of the chalcogenide material depends on the design of the unit structure. Generally, sulfur having a thickness higher than 8 nm has a phase change characteristic of the material of the compound, so that the material exhibits at least two stable resistance types. An embodiment of the bistable RRAM300 memory cell may include a phase change memory material as the first resistive random access memory layer 310 and a second resistive random access memory layer 320 including a chalcogenide compound Type materials and other materials. The chalcogen element includes any of four elements of oxygen (0), sulfur (S), selenium (Se), and tellurium (Te) constituting the Group VI part of the periodic table. A chalcogenide compound contains a compound of a chalcogen element and another positively charged element or substituent. The chalcogenide alloy contains a combination of a chalcogenide compound and other materials, such as a transition metal. The monochalcogenide alloy usually contains at least one element of the sixth row of the periodic table, such as germanium (Ge) and tin (Sn). Generally, the chalcogenide alloy includes a combination containing at least one of (Sb), gallium (Ga), indium (In), and silver (Ag). Many phase change memory materials have been described in the technical literature, including alloys: Ga/Sb, In/Sb, In/Se, Sb/Te, Ge/Te, Ge/Sb/Te, _In/Sb/Te, Ga/Se/Te, Sn/Sb/Te, In/Sb/Ge, Ag/InISb/Te, Ge/Sn/Sb/Te, Ge/Sb/Se/Te, and Te/Ge/Sb/S. In the Ge/Sb/Te alloy family, a wide range of alloy compositions are available. The composition is characterized by TeaGebSbioow+w. One researcher has described that the most effective alloy is that the average concentration of Te in the deposited material is less than 70%, representatively less than about 6%, and ranges from as low as about 23% up to about 58% Te, And most preferably about 48% to 58% Te. The Ge concentration in the material is above about 5% and in the range of an average of from about 8% to about 30%, the remainder is typically 5%. 23 1329356

'Santa Number: TW3061PA The concentration is optimally between about 8% and about 40%. The remainder of the main constituent elements in the composition is Sb. These percentages are all 1% of the atomic percentage of the constituent elements. (Ovshinsky, U.S. Patent No. 5,687,112, pp. 10-11.) Special alloys evaluated by another researcher include Ge2Sb2Te5, GeSb2Te4, and GeSb4Te7, (Noboru Yamada, "Potential of Ge-Sb-Te Phase-Change Optical Disks for

High-Data-Rate Recording"> SPIE v. 3109 « pp. 28-37 (1997). More comprehensively, transition metals such as chromium (c〇, iron (Fe), nickel (Ni), niobium (Nb), palladium (Pd), platinum (Pt) and mixtures or alloys thereof can be combined with Ge/Sb /Te is combined to form a phase change alloy having a stabilizing resistance property. A specific example of a material that can be used as a suffix material is provided in 〇vshinsky, U.S. Patent No. 5,687,112, No. 11-13, which is incorporated herein by reference. The phase change alloy can be transformed between a first structural state and a second structural state, the material of the first structural cancer is a substantially amorphous solid phase, and the material of the second structural state is in the activation channel region of the unit. The local rule is a substantially crystalline solid phase unit β. These alloys are at least two-state. The term amorphous is used to describe a relatively small, relatively chaotic structure of a specific single crystal, which has detectable properties such as crystallinity. The shape of the high-resistance. The term "crystalline" is used to mean that the catalyst is more complex than the amorphous structure, and the tangent factory has a detectable 41⁄2, such as a lower resistivity than the amorphous one. Spectrum across all amorphous and fully crystalline forms , the Ministry: the same with the detectable state of electrical conversion. Others affected by the amorphous and: 曰曰 shape reduction changes (4) characteristics of the package (four) sub-sequence, free electronic reading and live reduction. Materials can be in the (four) state phase or Mixing at least two solid phases 24 1329356

'Sanda Number: TW3061PA Inter-substance conversion provides a gray-scale band in a completely amorphous and fully crystalline form. The electrical properties in the material change accordingly. The phase change alloy can be switched from one state to the other by using an electrical pulse. It has been observed that a shorter, higher amplitude pulse tends to change the phase change material to a substantially amorphous form. A longer, lower amplitude pulse tends to change the phase change material to a substantially crystalline form. The energy in a shorter, higher amplitude pulse is high enough to cause the bond of the crystalline structure to break' and is short enough to prevent the atoms from rearranging into a crystalline form. It can be determined without undue experimentation • A suitable pulse data sheet, especially for specific phase change alloys. In the disclosure below, the phase change material refers to GST and it will be appreciated that other types of phase change materials can be used. The material described herein that can be used to implement the pCRAM is Ge2Sb2Te5. Other programmable resistive memory materials that can be used in other embodiments of the invention include N2-doped GST, GexSby, or other materials that can be altered using different crystalline phases to determine the resistive type; prxCayMn03, PrSrMn03, ZK)X'W0X, TiOx' ALOx, or other material that can be used to change the resistance of the electrical mode; tetracyanoquinodimethane (TCNQ), methane fullerene 6,6-phenyl C61-methyl butyrate (PCBM), TCNQ - PCBM, Cu-TCNQ, Ag-TCNQ, C6〇-TCNQ, TCNQ doped with other metals, or other polymeric materials having a two-state or multi-state resistive state controlled by electrical pulses. For additional information on the manufacture, component materials, use, and operation of phase change random access memory devices, see U.S. Patent Application Serial No. 11/155,067, filed on Jun. 17, 2005, entitled " " Thin 25 1329356

* Sanda number: TW3061PA 'Layer Fuse Phase Change RAM and Manufacturing Method", the full text of which is included in this case. The invention has been described in connection with the preferred embodiments. Various changes and retouchings can be made without departing from the spirit and scope of the present invention. Therefore, the description and the drawings are intended to be illustrative of the technical scope of the invention, and the scope of the invention is defined by the scope of the appended claims.

26 1329356

Sanda number: TW3061PA [Simple description of the drawing] Fig. 1 is a circuit diagram of the bistable resistive random access memory array of the present invention. Figure 2 is a simplified block diagram of an integrated circuit of a bistable resistive random access memory architecture in accordance with an embodiment of the present invention. Figure 3 is a simplified process diagram of the present invention to illustrate the steps of fabricating a bistable resistive random access memory device having a standard tungsten plug (W-plug) or via window in a single memory cell. • Figure 4 is a process diagram of the present invention showing the next step in fabricating a bistable resistive random access memory having a recessed etched tungsten structure. Figure 5 is a process diagram of the present invention illustrating the tungsten oxide (WOx) region formed by a dielectric spacer etch, a dry oxygen plasma etch, and a wet removal. Figure 6 is a process diagram of the present invention showing the next step in fabricating a bistable resistive random access memory having bit line formation. Figure 7 is a process diagram of the present invention showing the next step in fabricating a bistable resistive random access memory connected to a selected device. Figure 8 is a process diagram of a process of the present invention illustrating a first embodiment of a memory structure having a multi-memory layer and a tungsten oxide region for use in a multi-layer cell function. Figure 9 is a process diagram of the present invention illustrating a second embodiment of a memory structure having a multi-memory layer and a tungsten oxide region for use in a multi-layer cell function. Figure 10 is a process diagram of the present invention, which is illustrated for use in a multi-layer unit work 27 1329356

* Sanda number: TW3061PA * A third embodiment of a memory structure having multiple memory layers and a tungsten oxide region. Fig. 11 is a view for explaining the control of the multi-layer unit for reading current in the memory structure in which the tungsten oxide region's domain is the active region in the first embodiment of the present invention.

[Main component symbol description] 100 bistable resistive random access memory array 123, 124 word line 128 source line 132 bottom electrode element 134 top electrode element 135 memory unit 141, 142 bit line 146 block 150 151 ' 152 ' 153 access transistor 200 integrated circuit 260 memory array 261 column decoder 262 word line 263 terminal decoder 264 bit line 265 bus 266 block 267 material bus 268 bias supply supply Voltage 269 Biasing device 271 Write line 272 Gloss output line 275 Integrated circuit 300 Process diagram 310 > 312 Dielectric element 320 Barrier material 330 Crane material 340 Crane material surface 400 Process diagram 420 Barrier element 28 1329356

Sanda Number: :TW3061PA 430 Crane Inspection Component 500 Process Diagram 510 '512 Dielectric Clearance Wall 520 Emulsified Crane Element 600 Process Diagram 610 Barrier Layer 620 Bit Line Layer 700 Process Diagram 710 Top Bit Line 720 PN Diode 730 Bottom bit line 800 process diagram 810 first memory layer 812 tungsten plug element or first electrode 814 barrier element 816 tungsten oxide region 830 bottom bit line 820 NP diode 850 second memory layer structure 860 second bit line 862 barrier layer 900 process diagram 910 first memory layer structure 920 tungsten plug structure 922 barrier element 950 second memory layer structure 960 tungsten plug structure 980 second bit line 982 barrier element 1000 process diagram 1010 first memory layer structure 1020 First plug portion 1022 Second plug portion 1024 Barrier element 1050 Second memory structure 1062 First plug portion 1100 Figure 1110 X-axis current amount 1112 Y-axis read times 1120 First data line 1122 Second data Line 1124 third data line 1126 fourth data line 29

Claims (1)

4: TW3061PA X. Patent application scope: 1. A memory structure having a multi-memory layer, comprising: a first-first layer having a first electrode and a oxidized surface having a main surface In the crane region, the oxidized town region extends from the desired surface of the first electrode and electrically connects the first electrode and the second electrode to the first electrode to have a size substantially similar to the size of the tungsten oxide region; a second memory layer structure coupled to the first memory layer structure, the memory layer structure having a first electrode having a major surface and a tungsten oxide region, the tungsten oxide region being the main surface of the first electrode Extending to the second memory layer structure and electrically connecting the first electrode of the second memory layer structure and the second electrode of the second memory layer structure, the first electrode of the second memory layer structure Having a size that is substantially similar to the size of the tungsten oxide region of the second memory layer structure. 2. The memory structure of claim 1, wherein the tungsten oxide region provides a multi-layered function for operation in the first memory layer. 3. The memory structure of claim 1, wherein the first electrode comprises a plug structure filled with tungsten. 4. The memory structure of claim 3, further comprising a barrier material surrounding the outer surface of the crane in the plug structure. 5. The memory structure of claim 1, further comprising an N-P diode electrically coupled to the first electrode of the first memory layer structure. 30 1329356 Sanda number: TW3061PA 6. The memory structure as described in claim 5, further comprising a first bit line electrically coupled to the N-P diode. 7. The memory structure of claim 5, further comprising a P-N diode electrically coupled to the first electrode of the second memory layer structure. 8. The memory structure of claim 7, further comprising a second bit line electrically coupled between the yttrium oxide region of the first memory layer structure and the P-N diode. The memory structure of claim 8, further comprising a third bit line electrically coupled to the tungsten oxide region of the second memory layer structure. 10. A memory structure having a plurality of memory layers, comprising: a first memory layer structure having a first electrode having a major surface and a tungsten oxide region extending into the first electrode The main surface is electrically connected between the first electrode and the second electrode; and an oil layer first structure is coupled to the first memory layer structure, and the second memory layer structure has a main a first electrode and a tungsten oxide region of the surface, the tungsten oxide region extending into the main surface of the first electrode to the second memory layer structure and the first electrode and the second portion of the second memory layer structure The second electrode of the memory layer structure is electrically connected. 11. The memory structure of claim 1, wherein the tungsten oxide region provides a multi-layered function for operation in the first memory layer. A memory structure as described in claim 1, wherein the first electrode comprises a plug structure filled with tungsten. The memory structure of claim 12, further comprising a barrier material surrounding the outer surface of the tungsten in the plug structure. 14. The memory structure of claim 1, further comprising electrically coupling a diode to the first electrode of the first memory layer structure. 15. The memory structure of claim 14, further comprising a first bit line electrically coupled to the N-P diode. 16. The memory structure of claim 2, further comprising a P_N diode electrically coupled to the first electrode of the second memory layer structure. 17. The memory structure of claim 1, wherein the second bit line is electrically coupled to the tungsten oxide region of the first memory layer structure and the p_N diode. + 18. The memory structure of claim 17, wherein the third bit line is electrically coupled to the tungsten oxide region of the second memory. 1^. - The memory structure of the gel has a memory layer of the sinusoidal layer, the six-figure. The first memory layer structure has a first electrode having a main surface and an oxidation domain, and the tungsten oxide region is composed of The main surface of the first electrode Φ extends and electrically between the first electrode and the second electrode, the first-the-plug structure, the wire structure, and the second-shaped portion having the size The portion of the _2 part 32 1329356 i up to TW3061PA has a smaller value than the size of the second portion, the tungsten oxide region having a substantially similar size to the first electrode. a size; and a p second memory layer structure having a first electrode having a major surface and a tungsten oxide region extending from the major surface of the first electrode to the second memory layer structure and The first electrode of the second memory layer structure is electrically connected to the second electrode of the second memory layer structure, and the first electrode of the second memory layer structure has a structure substantially similar to the second memory layer structure. This size of the tungsten oxide region One of the first electrodes of the first alpha-resonant layer structure has a check structure having a ---------------------- In the plug structure of the second memory layer structure, the size of a plug portion is smaller than the size of the second plug portion in the plug structure of the second memory layer structure = structure The first electrode has a first dimension substantially = a first dimension in the oxidized town region of the second memory layer structure. 20. The memory structure of claim </ RTI> wherein the first plug portion is self-aligned to the second plug portion. 2! The memory structure of the patent application method is such that the first plug portion is non-self-aligned to the second plug portion. 22. A method of manufacturing a memory device, comprising: a dielectric element t-check structure 'which is surrounded by a barrier material--the inspection section and placed on the top portion of the plug material and the barrier Material, which uses a 33 1329356 • Sanda number: TW3061PA &quot; a chemical dry etch followed by a second chemical wet groove etch; forming a dielectric spacer on a major surface of the etch plug material; The oxygen plasma removes the tungsten oxide region to enter the major surface of the etch plug material; and 'forms a one-dimensional line to the dielectric spacer and over the tungsten oxide region. 23. The method of claim 22, wherein the first chemical dry etch comprises an SF6 dry etch. • 24. The method of claim 22, wherein the second chemical groove name comprises a directional title using a chlorine, a trichlorinated shed or an argon barrier. 25. The method of claim 22, wherein the dry oxygen plasma removal comprises 02/N2 or 02 claw 2 melon 2 mixed chemistry. 26. The method of claim 22, wherein the dry oxygen plasma removes a plasma comprising pure oxygen gas and one of a direct plasma, a magnetic field enhanced reactive ion plasma, or a downstream plasma. • 27. The method of claim 22, wherein the bit line comprises a bit line on the barrier layer. 34