TWI321356B - Phase change memory cells with dual access devices - Google Patents

Description

达达编号号: TW3099PA IX. Description of the Invention: [Technical Field] The present invention relates to a high-density memory element having a phase change memory material and a method of operating the same, the memory material of which includes a chalcogenide system Materials and other materials. *' [Prior Art] Phase change memory material is a material widely used in reading and writing optical discs. These materials have at least two solid phases including, for example, a generally amorphous amorpous and a generally crystalline solid phase. The laser pulse allows the read/write disc to be switched between different phases to read the different optical characteristics of the two phases. Phase change memory materials, such as chalcogenide materials and similar materials, can also change their sorrow by applying an appropriate level of current to the integrated circuit. Generally, the amorphous sorrow resistance is south of the 'like crystal sorrow resistance*, which can be quickly sensed to display its data. These features have been studied for programmable ® impedance materials to form random access memory for reading and writing non-volatile memory circuits. The amorphous state can be changed to a crystalline state under low current operation. Changing from a crystalline state to an amorphous state, used herein as a reset, typically requires operation at a higher current, including a short, high current density pulse to melt or break down the crystalline structure, Thereafter, the phase change material rapidly cools, stops the phase change procedure, and stabilizes at least a portion of the phase change structure in an amorphous state. It is generally desirable to minimize the size of the cell from the crystalline state to the two-dimensional or TW3〇99Pa amorphous state. Reducing the phase change material in the memory cell is small for the heavy pole and the phase change bake material. The money area can reduce the reset current of the liquid, and the current value of the phase change material unit can be as small as a small component. The current is still high density, even if it is a design limit. 8. A low voltage integrated circuit that greets the phase change memory material to memory the elements of the memory cell array; =, type 'structure with phase change includes access to the transistor, word line to == = with reset operation. Typical: Array = Item _ 〇 3 disclosed in the "Gap sulphur secrets" and Mr. Wu in the US patent No. 65_ =, in, SI pairs, shown, including the shape of the two phase guide body\ The second array structure is shown in Figure 3 (called the insulating transistor) and the Japanese body (in, 5〇3 in each access power (four) where the conductive plug is formed == the window opening. The semiconductor is used to separate Access requirements' or the need to isolate adjacent access transistors. A high-density array architecture such as (4) et al. (7) proposed a "random, L8V, and MHz synchronization phase change random. Access memory (four) cliff)". It is necessary to propose an array having a high-density component, which is used to apply a 4-mesh high-current riding component at a low level 1321356

Three hands: TW3099PA voltage for reset operation. SUMMARY OF THE INVENTION A first embodiment of the present invention is a self-aligning memory element that includes a memory unit that can be switched between a plurality of electrical states by application of energy. The memory element includes a substrate and first, second, third, and fourth word lines on the substrate and arranged in a first direction. The word line has a top surface and a side surface, and at least one of the word lines is covered by a dielectric material. First, second and third gaps are defined between the dielectric materials. The memory element also includes a plurality of end points of the plurality of access elements located in the substrate, a first end point directly below a second gap; a second end point directly below each of the first and third gaps . The first and second source lines are located in the first and third gaps and are electrically connected to one of the second terminals. A first electrode is located in the second gap and electrically connected to the first end point. A memory cell is located in the second gap above the first electrode and electrically connected thereto. A second electrode is positioned over and in contact with the memory unit and is arranged in a second direction that is perpendicular to the first direction. The first electrode, the memory unit, and the second electrode are self aligned. In some embodiments, the access element includes first and second transistors having a common drain. In some examples, the word lines are separated by a distance that is a minimum lithographic distance such that at least a portion of the gap is a lithographic size gap, and at least a portion of the memory unit has a lithography Size width. The self-aligned memory element of the present invention includes a memory unit that can be switched between different electrical states by application of energy. An example of a method of forming the self-aligned memory element will be described later. Forming first, second, third and fourth word line conductors on a substrate, each word line conductor having 1321356

Sanda number: TW3099PA The top surface of a word line and the side of the word line. A plurality of dielectric sidewall spacers are formed on the sides of the word lines, the sidewall spacers being separated from each other by the first, second, and third gaps that expose the substrate. Forming first and second end points of an access element in the bases of the first, second, and third gaps, a first end point directly below the second gap, and a second end point directly formed in each of the first ends Below the first and third gaps. A source line is formed in the first and third gaps, and is electrically connected to one of the second end points. A first electrode is formed in the second gap electrically connected to the first end point. A memory material is deposited in the second gap to form a first unit that electrically contacts the first electrode. A second electrode is formed which electrically contacts the memory unit. In some embodiments, the step of forming a dielectric sidewall spacer is performed such that the word lines are separated by a distance equal to the minimum lithographic distance, and the dielectric sidewall spacer defines the first, second, and third The spacers, at least one of the spacers being a sub-lithographic size gap. In this embodiment, the memory cell has a width defined by the second gap, and at least a portion of the width is a sub-lithographic size width. The above-described memory cell and access control element structure has a phase change memory cell which can be operated at a low voltage, and therefore, a high density, high capacity memory array can be fabricated. In order to make the above description of the present invention more comprehensible, the following detailed description of the preferred embodiments and the accompanying drawings will be described in detail as follows: [Embodiment] The present invention will be described in detail with reference to specific embodiments and methods. described as follows. The invention is not limited to the disclosed embodiments and methods, but may be embodied in other features, components, methods and embodiments. Preferred 1321356

"Canda's number: TW309卯A - The examples are intended to illustrate the invention and are not to be construed as limiting the scope of the invention. Those with ordinary knowledge can make various equivalent changes and refinements based on the following description. Further, the same members are denoted by the same reference numerals throughout the embodiments. Phase change memory cells with dual access elements and their arrays, as well as methods of making and operating them, will be described in detail in conjunction with Figures 1 through 23. : Fig. 1 is a diagram showing a memory array having a double word line and a dual source. A pole line and a self-aligning contact/memory unit between the memory cell electrode and the access array. In the drawings, four memory cells containing memory cells 35, 36, 45, and 46 are a small fraction of an array of millions of memory cells. It is illustrated by a memory cell containing memory cells 3 5 and 36. It can be seen that the memory cell containing the memory unit 35 includes an upper electrode 34 and a 'lower electrode 32. The memory unit 35 contains a phase change material for electrically connecting the upper and lower electrodes 34, 32. Similarly, the memory cell containing the memory unit 36 includes an upper electrode 37 and a lower electrode 33. The upper electrodes 37 and 34 are coupled to the bit line 41. The memory cells containing memory cells 45 and 46 are also connected in the same manner. As shown in Fig. 3, each memory cell has a phase change region near its lower electrode. Referring to Fig. 1, the directions in which the common source lines 28a, 28b, and 28c and the word lines 23a, 23b, 23c, and 23d are arranged are substantially parallel to the Y direction (the arrangement in the X direction parallel to the general word line). The direction in which the bit lines 41 and 42 are arranged is substantially parallel to the X direction. Thus, the Y decoder and the word line driver 24 having the set, reset and read modes are coupled to the word lines 23a, 23b, 23c, 23d. Set, reset and read modes

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'Santa Number: TW3099PA • The current source (current s〇UrCe) 43 of the bit line, decoder and sense amplifier (not shown) are coupled to bit lines 41 and 42. The common source lines 28a, 2A and @28c' are coupled to the source line termination circuit (terminating, such as the ground terminal. In some embodiments, the source line termination circuit includes a plurality of bias voltages The 'way' is used to apply a non-grounded bias to the source line, which includes biasing circuits such as voltage and current sources and decoding circuits. . . . of the memory cells in the array shown with the first and second Therefore, the power-down electrode 32 of the memory cell including the memory unit 35 is coupled to the drain D53 of the access transistor 53 and the drain D52 of the access transistor 52. The source terminals S52 and S53 of the crystals 52 and 53 are coupled to the source lines 28a and 28b, respectively. The gate of the access transistor 52 is coupled to the word line 23a. The gate of the access transistor 53 is accessed. The g53 is coupled to the word line 23b. Similarly, the lower electrode 33 of the memory cell containing the memory cell % is coupled to the drain of the access transistor 5 and the access transistor 51. The source terminals of the crystals 5A and 51 are coupled to the source lines 28b and 28c, respectively. The gate of the access transistor 5 is coupled to the word line 23C. The gate of the crystal 51 is coupled to the word line 23d. It can be seen from the figure that the common source line 28b is shared by two columns of memory cells arranged in the γ direction in the drawing. When operating, the current source 43 and the character are operated. The line driver 24 is operated in a low power, read mode, - or multiple intermediate current setting mode, and high current reset mode. During the high current reset mode, a current is applied to the bit line 41 and at the pre-line The conductors 23a and 23b apply a voltage to establish a passage through the selected memory cell (e.g., a memory cell containing the memory unit 35) 11 1321356

The three-numbered TW3099PA current path 51a is used to turn on the access transistors 52 and 53 so that the current passes through the source line 28a and the source line 28b at the same time. The double word line conductors 23a and 23b and the double source line conductors 28a and 28b are easy to establish a low resistance path to the ground than using only a single source line conductor. Therefore, during the high current reset mode, the current source can operate at a low voltage and can more efficiently provide coupled power to the memory cells that need to reach a reset state. Conversely, during the low current read mode, current is applied to the bit line 41 to establish a current path 51b through the selected memory cell (please refer to the memory cell containing the memory unit 36) and applied to the word line conductor 23d. Sufficient to turn on the voltage of the access transistor 51, current can flow to the source line conductor 28c. The voltage of the word line conductor 23c is maintained at a level which is sufficient to turn off the access transistor 50 and block the current flow to the source line conductor 28b. This provides low capacitance to the circuit used in the low current read mode and allows the read mode operation to be faster. During the set mode, one or more intermediate current levels are used to enable only one access transistor, as described in the above read mode. Alternatively, during the setup mode, two access transistors can be used depending on the particular target design, as described above for the reset mode. Embodiments of memory cells 35, 36, 45, 46 include phase change memory materials including chalcogenide type materials and other materials. The chalcogen element includes any of the four elements of oxygen, sulfur, selenium and tellurium of the fourth group of the periodic table. The chalcogen compound includes a chalcogen element and an electropositive element or a compound of a radical. The chalcogen compound alloy includes a chalcogen compound and other materials such as a combination of transition metals

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Sanda number: TW3099PA. Typically, chalcogenide alloys include one or more elements of Group VI of the Periodic Table, such as cerium and zinc. Generally, the chalcogenide alloy includes a combination of one or more of bismuth (Sb), gallium (Ge), indium (In), and silver (Ag). A variety of phase change memory materials have been disclosed in the scientific literature, including alloys of Ga/Sb, In/Sb, In/Se, Sb/Te, Ge/Te, Ge/Se/Te, In/Sb/Te, Ge/Se. /Te, Sn/Sb/Te, In/Sb/Ge, Ag/In/Sb/Te, Ge/Sn/Sb/Te, Ge/Sb/Se/Te, and Te/Ge/Sb/S. In the Ge/Sb/Te alloy population, the range of alloy compositions that can be implemented is very broad. Its composition can be expressed by TeaGebSbIQ (Ka+b). Researchers have studied that most of the useful alloys have an average concentration of Te in the deposited material of preferably less than 70%, typically less than 60%, typically ranging from about 23% to 58%, more preferably about 48°/. To 58%. The average concentration of Ge in the material is greater than 5% and ranges from 8% to about 30°/. 'usually less than 50%. Preferably, the concentration of Ge ranges from about 8% to about 40%. The main constituent element remaining in the composition is Sb. These percentages are atomic percentages, and the atoms of all the constituent elements are 100%. (Ovshinsky '112 patent, lines 10-11). Specific alloys studied by other researchers include Ge2SbTe5, GeSb2Te4, and

GeSb4Te7 ° (Noboru Yamada, Ge-Sb-Te phase change optical disc potential with high data rate, SPIE 3109, pp. 28-37, 1997). In general, transition metals such as chromium (Cr), iron (Fe), nickel (Ni), and sharp (Nb), palladium (Pd) platinum (Pt), and mixtures or alloys thereof, can be synthesized with Ge/sb/Te 钇A phase change alloy with anti-stylulation properties. Specific examples of the brother-remembering material that can be used are as described in 〇vshinsky' 112, lines 11-13, the examples of which are incorporated herein by reference.

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- Sanda number: TW3099PA ^ In the local order of the active channel region of the 5 cryptic cell, the phase change alloy can be switched between the first structural state and the second structural state. The first structural state is One is a generally amorphous solid material; the second structural state is a generally crystalline solid material. Some of these alloys are at least bistable. "Amorphous" means a structure having a relatively low order, which is more detectable than a single crystal, such as a higher resistance than a crystalline phase. ''Junction: Crystal' indicates a relatively high order structure, which is more ordered than amorphous, and has detectable characteristics such as lower resistance than amorphous phase. Typical phase change material • can be completely Conversion between different detectable states of the entire range of the spectrum between the amorphous and fully crystalline states. Other properties of the material affected by the amorphous phase and the crystalline phase include atomic alignment; density of free electrons and Activation energy. The material can be converted to a different solid phase, or converted into two 'or more solid phases, providing a gray scale between the completely amorphous and fully crystalline states. The electrical properties of the material are also Change. * Phase change alloys can be changed from one phase to another by applying electrical pluses. Short and high amplitude pulses can change the # phase change material to a generally amorphous state. Low-amplitude pulses can change the phase-change material to a general crystalline phase. Short and high-amplitude pulses are enough to break the bond of the crystal structure; short enough to avoid recrystallization of the atom into a crystalline state. The profile can be determined empirically or by analog (model ling) and applied specifically to a particular phase change alloy. In the inner valley below, the phase change material is represented by GST, while other types of phase change materials are also usable. The material used for pCRAM here is Ge2Sb2Te5 0 1321356

- Sanda Number: TW3099PA - The following four impedance memory materials are briefly described. 1. Chalcogen compound material GexSbyTez X * y * z=2· 2· 5 or other composition x: 〇~5; y: 〇~5; z: 0~10 GeSbTe has doping, for example, N-, Si-, Ti- or can use • other elements. Forming method: Ar, N2, and/or He or the like is used as a reaction gas by a PVD sputtering or a magnetic sputtering method at a pressure of 1 mTorr to 100 mTorr. The deposition process is usually carried out at room temperature. The use of a collimating tube with an aspect ratio of 1 to 5 improves the efficiency of the trench filling. In addition, tens to hundreds of volts of DC bias can be used to enhance trench fill efficiency. On the other hand, it is common to use both DC bias and collimation tubes. 'Normally, tempering after thermal deposition in a vacuum or N2 environment can increase the crystalline state of the chalcogenide material. The temperature range for tempering is usually between 100 and 400 degrees Celsius and the tempering time is less than 30 seconds. # The thickness of the chalcogenide material varies depending on the design of the memory cell structure. Generally, a chalcogenide material having a thickness greater than 8 nm may have a phase change characteristic to impart at least two stable impedance states to the material. 2. Super giant magnetoresistance (CMR) impedance material PrxCayMn03 X: y=0.5: 0.5 or other composition is x: 〇~1; y: 〇~1 Other CMR materials including Μη oxide can be used. 15 1321356

Sanda No.: TW3099PA Forming method: Ar, N2 and/or He are used as reaction gases at a pressure of 1 mTorr to 100 mTorr by PVD sputtering or magnetic sputtering. The temperature of the deposition process depends on the tempering conditions after deposition, usually from room temperature to 600 degrees Celsius. The use of a collimating tube with an aspect ratio of 1 to 5 improves the efficiency of the trench filling. In addition, DC bias voltages of tens to hundreds of volts can be used to enhance trench fill efficiency. On the other hand, it is common to use both a DC bias and a collimating tube. To increase the magnetic crystal phase, a magnetic field of tens to 10,000 gauss can be applied. Generally, after deposition, thermal tempering in a vacuum or a mixture of N2 or 爪2 claw 2 improves the crystalline state of the CMR material. The tempering temperature range is usually between 400 and 600 degrees Celsius, and the tempering time is less than 2 hours. The thickness of the CMR material varies depending on the design of the memory cell structure. Generally, a CMR material having a thickness of 1 〇 nm to 200 nm can be used as a core material. Generally, a buffer layer of YBCO (YBaCu03, a high-temperature superconductor material) can be used to increase the crystal state of the CMR material. YBCO is typically deposited prior to deposition of the CMR material and has a thickness ranging from 30 nm to 200 nm. 3. Two-element compound

NixOy; TixOy; AlxOy; WxOy; ZnxOy; ZrxOy; CuxOy et al x: y=0.5: 0.5 Other composition x: 0~1; y: 0~1 Formation method: 1321356

Sanda number: TW3099PA 1. Deposition: using PVD sputtering or magnetic sputtering, using Ar, N2, 02, and/or He as a reaction gas at a pressure of 1 mTorr to 100 mTorr, using metal oxidation Objects such as NixOy, TixOy, AlxOy, WxOy, ZnxOy, ZrxOy, CuxOy, etc. are used as targets. The deposition process is usually carried out at room temperature. The use of a collimating tube with an aspect ratio of 1 to 5 improves the efficiency of the trench filling. In addition, DC bias voltages of tens to hundreds of volts can be used to enhance trench fill efficiency. DC bias and collimation tubes can be used at the same time if needed. Generally, after the deposition, thermal tempering in a vacuum or a mixture of N2 or 爪2 claw 2 can increase the oxygen distribution of the metal oxide. The tempering temperature range is usually between 400 and 600 degrees Celsius, and the tempering time is less than 2 hours. 2. Reactive deposition: Ar/02, Ar/N2/02, pure 02, He/02, He/N2/02 by PVD sputtering or magnetic sputtering at a pressure of 1 mTorr to 100 mTorr As a reaction gas, a metal such as Ni, Ti, Al, W, Zn, Zr, Cu or the like is used as a target. The deposition process is usually carried out at room temperature. The use of a collimating tube with an aspect ratio of 1 to 5 improves the efficiency of the trench filling. In addition, DC bias voltages of tens to hundreds of volts can be used to enhance trench fill efficiency. DC bias and collimation tubes can be used at the same time if needed. Typically, thermal tempering after deposition in a vacuum or N2 or 02/N2 mixture increases the oxygen distribution of the metal oxide. The tempering temperature range is usually between 400 and 600 degrees Celsius and the tempering time is less than 2 hours. 3. Oxidation: with a high temperature oxidation system, such as a furnace tube or RTP system, with a temperature range of 200 degrees Celsius to 700 degrees Celsius with pure 02 17 1321356

Sanda number: TW3099PA • or n2/o2 mixed gas, with a pressure of several millitorr to 1 atm, for a deposition process of several minutes to several hours. Other oxidation methods are plasma oxidation, oxidizing metal in an RF or DC power plasma with a pure 02 or Αγ/02 mixture or a Αγ/Ν2/〇2 mixture gas pressure of 1 mTorr to 100 mTorr. Surfaces such as Ni, Ti, Al, W, Zn, Zr, Cu, and the like. The time of oxidation ranges from a few seconds to a few minutes. The temperature range of oxidation varies depending on the degree of plasma oxidation, from room temperature to 300 degrees Celsius. 4. Polymer materials

_ TCNQ PCBM-TCNQ mixed polymer with Cu, C60, Ag, etc. Forming method: 1. Evaporation: deposition process by thermal evaporation, electron beam evaporation or molecular beam epitaxy (MBE) system. The solid TCNQ and the dopant pellet are co-evaporated in a single chamber. The solid TCNQ and doped particles are placed in a boat or a boat or a ceramic boat. A high current or electron beam is applied to dissolve the material source' to mix and deposit the material on the wafer. The reaction chemicals or gases are not contained in the chamber. The deposition pressure is 10·4 Torr to 1 〇_1(). The temperature range of the crystal is from room temperature to 200 degrees Celsius. Generally, thermal tempering after deposition in a vacuum or N2 environment can increase the composition distribution of the polymer material. The tempering temperature range is usually from room temperature to 300 degrees, and the tempering time is less than one hour. 2. Spin coating: The doped TCNQ solution was coated by a spin coater at a rate of less than 1000 rpm. After coating, the wafer is allowed to stand in a solid state at room temperature or below 200 degrees Celsius. The time to rest is a few minutes 1321356

Sanda number: TW3099PA to several days, depending on the temperature and the conditions of formation. Examples of the formation of a chalcogenide material by PVD sputtering or magnetic sputtering are deposited, for example, with Ar, N2, and/or He as a gas source at a pressure of 1 mTorr to 100 mTorr. The deposition is usually carried out at room temperature. A collimating tube with an aspect ratio of 1 to 5 can be used to enhance the efficiency of the trench filling. In addition, DC bias voltages of tens to hundreds of volts can be used to enhance trench fill efficiency. On the other hand, DC bias and collimating tubes can be used simultaneously. Generally, thermal tempering after deposition in a vacuum or N2 environment can increase the crystalline state of the chalcogenide material. The tempering temperature range is usually between 100 and 400 degrees Celsius and the tempering time is less than 30 seconds. The thickness of the chalcogenide material varies depending on the design of the memory cell structure. Typically, the chalcogenide material has a thickness greater than 8 nm with phase change characteristics such that the material has at least two stable impedance states. The desired material is of the appropriate minimum thickness. 2 is a schematic block diagram of an integrated circuit in accordance with an embodiment of the invention. The integrated circuit 75 includes a memory array 60 on a semiconductor substrate having phase change memory cells that are self-aligned with contact windows and insulated lines. A column decoder 61 having read, set, and reset modes is coupled to the plurality of pairs of word lines 62 and arranged in the column direction of the memory cell array 60. The row decoder 63 is coupled to a plurality of bit lines 64 and arranged in the row direction of the memory cell array 60 for reading, setting, and resetting the memory cells of the memory array 60. The address is routed via bus bar 65 to row decoder 63 and column decoder 61. The sense amplifier and data input structure in block 66 includes current sources for read, set, and reset modes, which are 1321356

The three-digit number: TW3099PA is coupled to the row decoder 63 through the data bus 67. The data is supplied to the data input structure of block 66 from the input/output port on the integrated circuit 75 or from other sources internal or external to the integrated circuit 75 through the data input line 71. In the illustrated embodiment, the integrated circuit 75 may include other circuits 74, such as a general processor or a special purpose processor, or a system with a system chip function supported by a phase change memory cell array. combination. The data is transferred from the sense amplifier in block 66 to the input/output port of the integrated circuit 75 via the data output line 72, or to other data destinations internal or external to the integrated circuit 75. The controller in this example uses a bias arrangement state machine 69 to control the applied bias arrangement supply voltage, as well as current source 68 such as read, set, reset, and The voltage and/or current of the word line and the bit line are changed, and the operation of the double word line/source line is controlled by the access control processor as shown in FIG. The controller can use conventional logic circuits for special purposes. In another embodiment, the controller includes a general purpose processor that can be configured on the same integrated circuit to control the operation of the component by executing a computer program. In still another embodiment, a special purpose logic circuit and a general processor can be used as the controller. Figures 3 through 7 illustrate phase change random access memory (PCRAM) memory cells and self-aligned contact windows/memory cells/source lines and access transistors, as shown in Figures 8-21. . Memory cells are formed on the semiconductor substrate 20. A pair of access transistors 52 and 53 include end points formed as n-type source regions S52 and S53 in the p-type substrate 20 and as η 20 1321356

- Sanda number: TW3099PA - The size of the memory cell can be reduced to 16F2 to 8F2, 4F2, typically about 6F2 ’ F represents the minimum feature size of the process used. Thereafter, a layer of conductive layer 90 is deposited over the structure of Figure 8, typically a town or other suitable electrically conductive material such as Ti or TiN to form the structure of Figure 9. After the conductive layer 90 is etched back, the conductive member 91 shown in Fig. 10 is formed. Next, an insulating dielectric layer 92 is deposited over the structure of FIG. 10: A typical material is cerium oxide to form the structure shown in FIG. Then, the ground dielectric layer 93 shown in Fig. 12 is formed by chemical mechanical polishing. Referring to Fig. 13, a mask layer 94 is formed on the structure shown in Fig. 12, and the mask layer is aligned with the source of the predetermined access transistor. Referring to FIG. 14, etching removes the ground dielectric layer 93 that is not covered by the mask layer 94, leaving the etched dielectric layer 96 above the source, but barely exposed above the drain. Covered conductive member 91. Fig. 15 is a view showing the deposition of the phase change memory material 98 on the structure shown in Fig. 14, in which the memory material is in contact with the conductive member 91 covered, and the conductive member is in contact with the drain. Figure 16 is a schematic view showing the formation of a first subassembly of the memory material 98 of Figure 15 after the chemical mechanical polishing step. Figure 17 is a schematic view showing the deposition of a metal bit line layer 100 on the structure shown in Figure 16 to form a second sub-assembly. 18 and 19 are schematic views showing the formation of the second mask layer 102 on the metal bit line layer 100 in the structure shown in Fig. 17. Referring to Fig. 20, similar to Fig. 5, the structure of Fig. 19 is etched by the second mask 102 until the substrate 20 is exposed. 23 2321356

Sanda number: TW3099PA to form a bit line stack structure 104 separated by trenches 106. As shown in Figures 4, 6 and 7, the etching process terminates in a dielectric layer 81 overlying the word line 23 and a dielectric layer 86 overlying the source line 28. Figure 21 is a side elevational view of the second mask layer 102 after removing the second mask layer 102. Next, a process of filling the dielectric layer and a process of chemical mechanical polishing are performed to form the structures shown in Figs. Fig. 22 is a schematic view showing another access element including a diode. Referring to FIG. 22, the first memory cell 350 includes an upper electrode 334, a memory unit 335, and a lower electrode 332. The second memory cell 351 is also shown. The first word line conductor 321 and the second word line conductor 322 are coupled to a word line driver 320 that can perform set, reset, and read modes. The first bit line 341 and the second bit line 342 are coupled to a biasable power supply 340 that can be set, reset, and read mode, and a sense amplifier and data input structure (not shown). When the diodes 317 and 318 function as dual access elements of the memory cell 351, the diode 315 and the diode 316 serve as dual access elements of the <memory cell 350. The lower electrode 332 of the memory cell 350 is coupled to the anode of the diode 315 and the anode of the diode 316. The cathode of the diode 315 is coupled to the word line conductor 321; the cathode of the diode 316 is coupled to the word line conductor 322. In this example, the word line conductors 321 and 322 are simultaneously used as the word line and the source line, which are different from the separated lines in the embodiment of Fig. 1 as the source line (28a, 28b, 28c). And word lines (23a, 23b, 23c, 23d). During operation, during reset mode, word lines 321 and 322 are set to a low voltage, such as ground, or other voltage sufficient to cause diodes 315, 316 to conduct. In this mode, word lines 321 and 322 are treated as

(S 24 1321356 Ξ达号: TW3099PA source line, current through memory cell 350 at the same time along the Bodhisattva - _ 3" square tongue Miao tong m / U to the Yuan 4 line conductor 321 and 322 'produce one of the reset nucleus Between the relatively low resistance paths, only one of the word lines 321 and 322 is asserted. ^ The mode of the mode is β and the mode is in the low mode. Only the word lines 321, 322 t are + long. < - Set to be only the pressure. As described above, in some embodiments, the word lines 321 and 322 can be simultaneously set in the low power house during the _ _ private sigh.

Fig. 23 is a diagram showing the basic operation method of the memory element, which is, for example, the structure having the double word line/source line of Fig. 3/the flow shown in the 23rd embodiment of the embodiment. It is carried out under the state machine 69 which controls Fig. 2. The program is executed in accordance with the instructions to access a selected memory cell (500). When an instruction is received, the program will determine the mode of access (501). If the access mode is read mode, the control logic causes the word line to drive iimx so that the current drives the left word line via the left access element and the selected memory cell voltage. The right word line A voltage (502) is then applied to prevent current from passing through the right access element. Next, a read bias pulse (503) is applied to the bit line corresponding to the selected memory cell. Finally, the data of the selected memory cell is sensed (504). If the access mode is the setting mode, the operation is similar. The control logic causes the word line driver to drive the left word line with a voltage sufficient to cause current to pass through the left access element and the selected memory cell, and the right sub-line is applied to avoid current flow through the right side. Take the voltage of the component (505). Thereafter, a set bias pulse is applied to the bit line corresponding to the selected memory cell (506). Finally, change the resources of the selected memory cell 25

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Ξ达号: TW3099PA material (507). If the mode of access is the reset mode, the control logic causes the word line driver to simultaneously drive the left and right word lines (508) with a voltage sufficient to cause parallel flow through the left and right access elements. Next, a reset bias pulse (509) is applied to the bit line. Finally, the data of the selected memory cell is changed (510). As described above, in another embodiment, during the set mode, or during one or more of the set modes of the multi-level memory cells, the control logic can simultaneously drive the word lines in the manner of the reset mode described above. Of course, there are many materials that can be used in the structure shown in Figure 3. For example, a copper metallization process or other types of metallization processes, including aluminum, titanium nitride, and tungsten-based materials, may be employed. Further, a non-metallic conductive material such as doped polycrystalline stone may also be used. The electrode material in the illustrated embodiment is preferably TiN or TaN. Alternatively, the electrode may be TiAIN or TaAIN ' or may comprise one or more elements, for example selected from the group consisting of Ti, W, Mo, Al, Ta, Cu, Pt, Ir, La, Ni, and Ru and alloys thereof. Ethnic group. Dielectric materials include cerium oxide, polyamidamine, tantalum nitride or other dielectric trench fill materials. In one embodiment, the trench fill layer comprises a material that is more thermally and electrically insulating to provide thermal and electrical insulation of the phase change memory cell. The low temperature dielectric material, such as a tantalum nitride layer or a tantalum oxide layer, can be formed using a process temperature of less than 200 degrees Celsius. Plasma Enhanced Chemical Gas Phase Deposition (PECVD) is a suitable method for forming ruthenium dioxide. In some cases, it may be necessary to use a higher temperature process such as high 26 1321356

Sanda number: TW3099PA " Density plasma chemical vapor deposition (HDPCVD) to deposit dielectric materials. Further, the minimum feature size of the various photomasks formed and patterned in the current photomask lithography process is 0.2 micron (200 nm) and 0.14 micron gas 0.09 micron. As the lithography process evolves, embodiments of the process can employ narrower minimum feature sizes. In addition, a sub-lithography process can be employed to achieve a line width of 40 nm or less. In some embodiments, in addition to the disclosed dielectric material, the structure of the thermally insulative memory cell 35 is included, or the structure of the thermally insulative memory cell can be replaced by a structure that is thermally insulated. Representative materials for the layer of thermal insulation include Si, C, 0, F, and combinations of bismuth elements. Usable - Examples of thermal insulating materials include Si〇2, SiCOH, polyamidamine, polyamine, and fluorocarbon polymers. Examples of other materials that can be used for thermal insulation include fluorinated Si 〇 2, silsesquioxane, polyaryl fluorene, polyparaphenylene benzene, fluorinated polymers, fluorinated non-fluorene Crystalline carbon, diamond-like reverse, oxidized oxidized stone, mesoporous silica, porous sesquioxane, porous polyarylene, and porous polyarylene ether. In another embodiment, the thermal insulation structure includes a fill gas gap in the dielectric trench fill material of the adjacent delta memory unit for thermal insulation. Thermal and electrical insulation A single layer or a combination of layers can be used. The above, the following, the apex, the bottom, the top, the bottom, and the like, which are used in the above description, are merely used to make the present invention easier to understand, and are not intended to limit the present invention. Although the invention has been described above in terms of a preferred embodiment, it is not intended to limit the invention. Those of ordinary skill in the art to which the present invention pertains,

27 1321356

达达号·· TW3099PA can be used for various changes and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of the invention is defined by the scope of the appended claims. Any or all of the patents, patent applications, and published materials described above are incorporated by reference in this application.

·: S 28 1321356

• Sanda Number: TW3099PA * [Simplified Schematic] Figure 1 is a schematic diagram showing a phase change memory cell memory array with dual source lines and double word lines. Figure 2 is a block diagram showing integrated circuit components including a phase change memory cell memory array having dual source lines and double word lines and other circuitry. Figure 3 is a cross-sectional view of a memory element taken along a parallel line and through a bit line in accordance with the present invention. #图4 is a top view of the third drawing. Figures 5, 6, and 7 are side views showing the tangent along Figs. 5-5, 6-6, and 7-7. _ Figure 8 is a diagram showing the word lines covered by the dielectric layer on the substrate. Figure 8A is a diagram showing the deposition of a nitride layer on the structure of Figure 8. 8B is a result of etching the structure of FIG. 8A, which leaves sidewall spacers on the sidewalls of the word lines, and forms sidewall gaps between the sidewall spacers, and forms a source of aligned sidewall gaps. Bungee jumping. • Figure 9 is a diagram showing the deposition of a conductive layer on the structure shown in Figure 8. Figure 10 is a graph showing the results of etching back the conductive layer of Figure 9. Figure 11 is a diagram showing the deposition of a dielectric layer on the structure of Figure 10. Fig. 12 is a view showing the structure of Fig. 11 after mechanical grinding. Fig. 13 is a view showing the formation of a mask layer on the structure shown in Fig. 12. Fig. 14 is a view showing the result of etching the structure shown in Fig. 13. Figure 15 is a diagram showing the deposition of a memory material (S) 29 1321356 on the structure shown in Figure 14.

- Ξ达号: TW3099PA • Material. Figure 16 is a graph showing the results of a chemical mechanical polishing process of a memory material. Figure 17 is a diagram showing the deposition of a metal bit line layer on the structure shown in Figure 16. Figures 18 and 19 are diagrams showing the formation of a second: mask layer on the structure shown in Figure 17. Figure 20 is a diagram showing the etching of Figure 19 to the surface of the substrate to form a bit line. Figure 21 is a side elevational view of the second mask layer of the structure shown in Figure 20. Figure 22 is a diagram showing another phase change memory cell including a double word line and a double bit line (also referred to as a source). Fig. 23 is a flow block diagram showing the operation method of the memory element.

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Sanda number: TW3099PA [Description of main component symbols] 12: Sidewall gap 14: Distance 20: Base 23a, 23b, 23c, 23d, 321, 322: Word line 23, 24: Word line driver: 28a, 28b, 28c : common source line. 29: source line termination circuit _ 32, 33, 332: lower electrode 34, 37: upper electrode 35, 36, 45, 46: memory unit 3 8 : phase change region 41, 42, 341, 342: Bit line 4 3: Set, reset, and read current sources 50, 51, 52, 53: access transistors 51a, 51b: current path • 60: phase change memory array 61 with dual source lines: Column decoder 62, 64: bit line 63: row decoder 66: data in sense amplification/structure 65, 67: bus bar 68: current source 69: state machine 31 1321356

Sanda number: TW3099PA 71: Input line 72: Output line 74: Other circuit 75: Integrated circuit 79: Distance 80, 81: Top cover layer 82: Clearance wall 84: Gate oxide layer 86, 93, 96: Dielectric layer 88, 106: trench 90: conductive layer 91: conductive member 92: insulating dielectric layer 94, 102: mask layer 98: phase change memory material 100: metal bit line 104: bit line stack structure 315, 316, 317 318: diode 320: word line driver 335: memory unit 340: bias source 350, 351, 500: memory cell 501: mode 502, 505: drive left word line 32 1321356

- Sanda number: TW3099PA-503: Applying a read bias pulse 504 on the bit line: sensing data 506: applying a set bias pulse 507, 510 on the bit line: changing data 508: driving the left and right word lines 509: Apply a reset bias pulse on the bit line: S, S51, S52, S53: source D, D52/D53: drain φ G52, G53: gate 5-5, 6-6, 7-7: Section line

33

Claims (1)

1321356 - Sanda number: TW3099PA - X. Patent application scope: 1. A self-aligning memory element, comprising a memory unit, which can be switched between a plurality of electrical states by applying energy, the memory The component includes: a substrate; the first, second, third, and fourth word lines are located on the substrate, and are arranged in a first direction, the word lines having a plurality of top surfaces and a plurality of sides, wherein At least one top surface is covered by a dielectric material, and first, second and third gaps are defined between the dielectric materials; a plurality of end points of the plurality of access elements are located in the substrate, a first end point Directly below the second gap, and a second end point is directly formed under each of the first and the third gaps; 'the first and second source lines are located in the first and third gaps And electrically connecting one of the second terminals; a first electrode is located in the second gap and electrically connected to the first end point, • a memory unit is located in the second gap Located above the first electrode and The first electrode is electrically connected; the second electrode is located above and connected to the memory unit, and is arranged along a second direction, the second direction is perpendicular to the first direction, the first electrode, the memory unit and The second electrode is self aligned. 2. The self-aligning memory element of claim 1, wherein the second electrode comprises a one-dimensional wire conductor. The method for forming a self-aligned memory element according to claim 9 wherein the step of forming the (b) is performed such that the word line conductors are separated by a distance. The distance is equal to the minimum lithography distance, and the first, the second, and the third gap are defined by the dielectric sidewall spacers, and at least a portion of the gaps are sub-lithographic size gaps, and the memory unit has A width defined by at least a portion of the second gap, and at least a portion of the width is a sub-lithographic size width. 12. The method of forming a self-aligning memory element according to claim 8 , further comprising the steps of: filling a dielectric material in the gaps; and removing the second gap after the step (e) At least a portion of the dielectric material is exposed to expose the first electrode. 13. The method of forming a self-aligning memory element of claim 8, wherein: the memory material deposition step forms a first component, and further comprising: planarizing the first component to form a Flattening the second component of the upper surface, and wherein the second electrode forming step comprises: depositing a second electrode material on the flat upper surface; forming a plurality of second electrode mask layers on the second electrode material; Forming a plurality of trenches between the second electrode mask layers; and removing the second electrode mask layer, and further comprising: depositing a dielectric material in the trench. 37