WO2018205915A1 - 一种基于VOx选通管的相变存储单元 - Google Patents

一种基于VOx选通管的相变存储单元 Download PDF

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WO2018205915A1
WO2018205915A1 PCT/CN2018/085935 CN2018085935W WO2018205915A1 WO 2018205915 A1 WO2018205915 A1 WO 2018205915A1 CN 2018085935 W CN2018085935 W CN 2018085935W WO 2018205915 A1 WO2018205915 A1 WO 2018205915A1
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phase change
layer
electrode layer
state
temperature
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French (fr)
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缪向水
童浩
马立樊
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华中科技大学
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Priority to US16/679,355 priority Critical patent/US11056644B2/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • H10N70/235—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect between different crystalline phases, e.g. cubic and hexagonal
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0097—Erasing, e.g. resetting, circuits or methods
    • H—ELECTRICITY
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    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/021—Formation of switching materials, e.g. deposition of layers
    • H10N70/026—Formation of switching materials, e.g. deposition of layers by physical vapor deposition, e.g. sputtering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/041—Modification of switching materials after formation, e.g. doping
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8833—Binary metal oxides, e.g. TaOx
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/0092—Write characterized by the shape, e.g. form, length, amplitude of the write pulse
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/10—Resistive cells; Technology aspects
    • G11C2213/15—Current-voltage curve
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/50—Resistive cell structure aspects
    • G11C2213/52—Structure characterized by the electrode material, shape, etc.
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/73—Array where access device function, e.g. diode function, being merged with memorizing function of memory element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8825—Selenides, e.g. GeSe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8828—Tellurides, e.g. GeSbTe

Definitions

  • the present invention belongs to the field of semiconductor memory technology, and more particularly to a phase change memory cell based on a VO x strobe.
  • Phase change memory PCM is one of the most promising replacements for Flash memory as one of the next generation of non-volatile memories.
  • the phase change memory cell can realize a reversible transition of a crystalline state and an amorphous state under a voltage pulse using a sulfur-based compound as a phase change material. Applying an electrical pulse of medium amplitude, longer pulse width, and slower pulse falling edge, the phase change material can be changed from amorphous to crystalline, used to write data from "0" to "1"; The higher amplitude, narrower pulse width, and steeper electrical pulses on the falling edge cause the phase change material to change from crystalline to amorphous for erasing data.
  • Today's high-performance systems require memory with higher density of storage space and smaller area size. Due to the leakage current of the phase change unit and the large Reset current required, the gate also becomes a phase change memory.
  • FIG. 1 shows a conventional 1T1R structure.
  • the strobe is generally MOSFET or BJT; the principle of the MOSFET as the strobe of the phase change unit is to control the gate voltage to form a conductive channel to control the switching of the source and drain.
  • the advantage is that the voltage drop is small, but if Providing a higher Reset current (current required for the amorphous phase change of the phase change material) requires increasing the channel width, and at small sizes, the MOSFET cannot meet the requirements of low noise current due to the limitation of the additional strobe The cell area and the memory density of the phase change memory are difficult to continue to increase.
  • BJT as a gating tube can provide sufficient Reset current at high density, but at high current, the current amplification factor of BJT will be reduced, and the manufacturing process cost is high.
  • the diode 1D1R structure since the diode preparation process has many etching stripping steps and requires a high temperature of 800 ° C, the preparation conditions are high, and it is difficult to realize the 3D stacking of the memory cells. Therefore, it is still difficult to find a high-density 3D stack integrated gating tube which is simple in preparation process and can be prepared at low temperature, which can effectively reduce leakage current and facilitate phase change memory.
  • the present invention provides a phase change memory unit based on a VO x strobe tube, which realizes strobing of a phase change memory unit by controlling a switch of VO x , and adopts a 1D1T structure.
  • the preparation process of the invention is simpler, does not require high temperature conditions, saves cost, and is advantageous for high-density integration and large-scale commercialization of phase change memory.
  • the present invention provides a phase change memory cell based on a VO x gate, comprising: a lower electrode layer, a VO x gate layer, a phase change functional layer, and an upper electrode layer disposed in sequence; when in the upper electrode layer and When a voltage is applied between the lower electrode layers, the VO x gate layer can achieve a transition between a high resistance state and a low resistance state.
  • the material of the phase change functional layer is any one of GeTe, SbTe, BiTe, SnTe, AsTe, GeSe, SbSe, BiSe, SnSe, AsSe, InSe, GeSbTe, and AgInSbTe, and any one of the above compounds is doped with S Or a mixture of N or O or Cu or Si or Au elements.
  • the materials used for the upper electrode layer and the lower electrode layer are TiW, Pt, Au, W or other inert electrodes which are not easily reacted with oxygen.
  • VO x in the range of X of the gate layer VO x material is 1.9 to 2.1.
  • the threshold voltage V VO x th gate layer is smaller than the erase operation voltage V Set the phase change of the functional layer.
  • the VO x gate layer has an area size of 100 nm 2 to 30 ⁇ m 2 .
  • the insulating state resistance of the VO x material of the gate layer is greater than the metal resistance, and the ratio of the insulating state resistance to the metal state resistance is greater than 100.
  • the present invention also provides an operation method based on the phase change memory unit described above, comprising the steps of:
  • VO x By applying a strong electric pulse is greater than the threshold voltage V th between the upper electrode layer and the lower electrode layer, VO x so that the temperature rise of the gate layer above the phase transition temperature, VO x material is made of an insulating state
  • the monoclinic system is transformed into a metallic tetragonal system
  • the temperature of the VO x gate layer falls below the phase transition temperature, and the VO x material returns to the high resistance insulation. State; that is, the VO x material can achieve reversible transformation under the action of thermal energy;
  • the temperature of the phase change functional layer is raised to the melting temperature by applying a pulse signal having a strength greater than V Reset and a falling edge of 10 ns between the upper electrode layer and the lower electrode layer.
  • a pulse signal having a strength greater than V Reset and a falling edge of 10 ns between the upper electrode layer and the lower electrode layer.
  • the above causes the long-range order state of the crystalline state to be destroyed, and the extremely fast falling edge causes the phase change material to rapidly cool below the crystallization temperature.
  • the phase change material is in a low-resistance amorphous phase transition when it is less than crystallization.
  • the functional layer is in a low resistance state;
  • the temperature of the phase change material is made by applying a pulse signal between the upper electrode layer and the lower electrode layer between V Reset and V Set and having a pulse width of 200 ns. Raise below the melting temperature above the crystallization temperature and maintain 200 ns to ensure complete crystallization of the material.
  • the phase change material changes from a high resistance state to a low resistance state, and the phase change functional layer is in a high resistance state, using a phase change functional layer different.
  • the resistance state is used to store data.
  • the threshold voltage of the VO x gate layer is smaller than the erase operation voltage V Set of the phase change unit.
  • the present invention also provides a method for preparing a VO x gate layer in the above phase change memory cell, comprising: depositing a layer of vanadium oxide by ion beam sputtering or magnetron sputtering and then placing the material into nitrogen or argon gas. After annealing in the atmosphere, the VO x gate layer is obtained after naturally cooling to room temperature.
  • phase change memory cell based on VO x gate provided by the present invention has many steps in the preparation process of the diode, requiring two times of photolithography and two etching, magazine diffusion, and metallization. and annealing process is higher than 800 0 C, the high temperature detrimental to the process stack structure in three-dimensional (3D) direction; VO x preparation process is simple, can be prepared only after sputtering and annealing process after a lithography
  • the low-temperature process conditions can achieve 3D stack integration, low cost, and facilitate high-density storage of phase change memory.
  • the minimum size area can be reduced to 4F 2 , and the minimum size area of the 1T1R structure using the MOS tube is 8F 2 , and a higher Reset current is required (the current required for the phase change material to be amorphized) Therefore, the channel width needs to be increased.
  • the method provided by the invention has the advantages of smaller size area and simple preparation process, and can be stacked in the 3D direction, which is advantageous for high-density integration of the memory unit.
  • the metal insulator transition (MIT) of VO x is used to realize the switching function of the gate. It can provide an on-state current density of up to 10 6 A/cm 2 and a switching time of less than 20 ns, and its switching characteristics can be stably maintained with reduced size. BJT and MOS tubes cannot ensure high switching while increasing storage density. Ratio or high Reset current.
  • the phase change memory cell based on the VO x gate provided by the present invention is a first application of the VO x material in the phase change memory, and is useful for accelerating and accelerating the commercialization of the large-capacity phase change memory.
  • 1 is a schematic structural view of a conventional 1T1R MOS gate strobe phase change memory cell.
  • FIG. 2 is a schematic structural diagram of a VO x gate phase change memory unit provided by the present invention.
  • FIG. 3 is an IV characteristic curve of VO x used in the present invention, which is divided into a boosting process and a step-down process, and can realize the magnitude control of the gate current of the phase change memory cell.
  • RV characteristic curve of VO x used in the present invention is a RV characteristic curve of VO x used in the present invention, which is divided into a boosting process and a step-down process, and can realize conversion between VO x high resistance and low resistance.
  • Figure 5 is a phase change cell IV characteristic curve without the addition of a VO x gate layer.
  • Figure 6 is an I-V characteristic curve of the overall structure of the present invention.
  • Fig. 7 is a graph showing the function test of the phase change unit of the present invention.
  • 1 is a lower electrode layer
  • 2 is a VO x gate layer
  • 3 is a phase change functional layer
  • 4 is an upper electrode layer
  • 5 is a phase change resistor
  • 6 is a transistor.
  • the present invention provides a phase change memory cell based on a VO x strobe tube; by switching a VO x on and off state by applying a voltage, the strobe of the phase change memory can be effectively controlled.
  • VO x is used as a gating material for a phase change memory cell. State control is achieved by applying a voltage to the VO x gate layer.
  • the phase change memory cell based on the VO x gate includes: a lower electrode layer, a VO x gate layer, a phase change function layer, and an upper electrode layer which are sequentially disposed; when in the upper electrode layer and the lower electrode layer When a voltage is applied between them, the VO x gate layer can achieve a transition between a high resistance state and a low resistance state.
  • a voltage is applied to the upper electrode layer and the lower electrode layer, and the VO x gate layer should have a switching characteristic to ensure conversion between a high resistance state and a low resistance state.
  • a strong electrical pulse greater than V th is applied, the heat generated can cause the VO x temperature to rise above its phase transition temperature, and the material will change from an insulating monoclinic system to a metallic tetragonal system; when a When the electric pulse is less than V hold , the temperature drops below the phase transition temperature, and the material returns to the high-resistance insulation state, that is, the VO x material can be reversibly transformed by thermal energy.
  • the phase change function layer realizes data storage. When the write pulse is applied, the phase change function layer is in a low resistance state; when the erase pulse is applied, the phase change function layer is in a high resistance state, and the phase change function layer is used in different resistance states. To achieve the storage of data.
  • VO x having phase change characteristics when such VO x having phase change characteristics is prepared, a vanadium oxide thin film material is first sputtered on the substrate by ion beam sputtering, direct current magnetron sputtering or radio frequency magnetron sputtering, and then Annealed in a protective gas atmosphere such as nitrogen or argon, and then naturally cooled.
  • a protective gas atmosphere such as nitrogen or argon
  • the VO x material of the present invention is prepared.
  • the sputtering method has higher energy for depositing atoms by sputtering, and thus the film is dense and has good adhesion.
  • the control property of the composition is good when the VO x film is prepared.
  • the melting point of metal vanadium is 1890 ⁇ 10 ° C.
  • the evaporation deposition method requires a high substrate temperature to evaporate, and the sputtering method can conveniently utilize the sputtering of high melting point materials.
  • the PLD method can obtain a film of higher quality, it is difficult to form a large-area uniform film and the device is relatively expensive, and is not suitable for mass production, and the sputtering method is suitable for mass production.
  • (1) The sol-gel method can form a film on a large-area non-planar substrate, but it is quite difficult to prepare a high-quality VO x film with high orientation and good switching characteristics, and the film characteristics are difficult to control.
  • the density of the film is poor, the thickness is not easy to control, and there are defects such as bubbles or cracking, and it is easy to cause pollution.
  • Chemical vapor deposition requires the use of rare and toxic gases, which is unsafe for workers and environmentally friendly;
  • Molecular beam epitaxy and atomic layer deposition techniques are expensive and difficult to operate, which is not conducive to batch and industrial production.
  • Figure 3 is a VI curve of a VO x cell, gradually increasing the voltage applied to VO x , and when the voltage reaches the threshold voltage V th , the current through VO x sharply increases, at which time VO x is converted from a semiconductor high-resistance state to a metal In the low-resistance state, the strobe is turned on; conversely, when the voltage applied to VO x is gradually reduced, when the voltage is reduced to the holding voltage Vhold , the current passing through VO 2 is drastically reduced, and VO x is returned to this time.
  • the semiconductor is in a high-impedance state and the gate is closed.
  • a 1D1R structure that does not require an additional transistor is used, which is smaller in size and advantageous in achieving 3D stacking than the 1T1R structure.
  • the preparation process of VO x is very simple. Compared with the diode prepared under high temperature conditions, VO x can be obtained after sputtering at room temperature and then post-annealing process, which simplifies the preparation process and saves cost.
  • the threshold voltage of VO x is much smaller than the phase change threshold voltage V pc of the phase change unit, so that the phase change memory cell has a larger operation window.
  • the switching ratio of VO x can be up to 10 4 orders of magnitude, which can effectively reduce leakage current and provide a large enough Reset drive current.
  • Figure 3 is a typical IV characteristic curve for a VO x material
  • Figure 4 is a typical RV curve thereof. Referring to these two figures, it can be seen that when a voltage is applied to VO x , when the voltage reaches 2.2V, VO x changes from high resistance to low resistance, and the ratio of the open circuit to the off current is close to three orders of magnitude. The voltage is called the threshold voltage V th .
  • the threshold voltage Vth of VO x is related to the specific parameters of the preparation process, and the Vth is in the range of oxygen concentration in which VO x having phase change characteristics can be prepared and during VO x sputtering.
  • the oxygen concentration is positively correlated.
  • the insulation resistance of the VO x material constituting the gate layer is greater than the metal resistance, and the ratio of the insulation resistance to the metal resistance is greater than 100.
  • the ratio of the insulation resistance to the metal resistance is greater than 10000.
  • the ratio of the resistance ratio is related to the selection of specific parameters in the preparation process. As the oxygen concentration increases, the resistance ratio decreases.
  • the size of the resistor is related to the size of the gate layer. The smaller the size, the smaller the switching resistance of the gate layer and the larger the switching ratio. Therefore, the present invention has better gate characteristics in a small-sized high-density memory array. .
  • the phase transition temperature of the VO x material constituting the gate layer is around 68 ° C.
  • the phase transition temperature of VO x may be from 60 ° C to 80 ° C.
  • Figure 5 is a typical IV characteristic curve of the phase change material GST. It can be seen from the figure that when the applied voltage reaches the phase change voltage V Set of the phase change material, the heat generated by the phase change material can raise the phase change material above the crystallization temperature. And to maintain sufficient atomic relaxation time, the material will change from disordered amorphous state to ordered crystalline state resistance value will change sharply.
  • the ratio of the amorphous resistance to the crystalline resistance is greater than 10; in particular, the ratio of the amorphous resistance to the crystalline resistance is greater than 100,000.
  • the phase change voltage V Set of the phase change material is related to the doping concentration, and doping N and Si with the phase change material can increase the crystallization temperature, thereby increasing the V Set .
  • phase change memory unit based on a VO x strobe tube provided by an embodiment of the present invention
  • a specific example is as follows:
  • Figure 6 is a graph showing the gating process of the invention.
  • the current When the voltage is gradually increased from zero, the current also increases.
  • the threshold voltage Vth When the voltage reaches the threshold voltage Vth , the current jumps sharply, indicating that this time.
  • VO x changes from an off state to an on state, the overall resistance is drastically reduced, and the gate is opened.
  • the strobe tube When the strobe tube is opened, the applied voltage is continuously increased.
  • the circuit jumps again and sharply increases. This is because the applied voltage reaches the phase change voltage of the GST phase change material.
  • the GST is converted from an amorphous state to a crystalline state, and the resistance is reduced, thereby realizing the erasing operation of the phase change unit.
  • gating tube voltage V th of the threshold voltage V Set the phase change compared to the phase change cell is much smaller, so that the phase change cell has a larger operating window.
  • Figure 7 is a test function for testing the invention.
  • a setting pulse to the cell. Since the phase change voltage of GST is 4.6V, we apply a rub pulse with a amplitude of 6V and a pulse width of 500ns. Comparing the two curves in the figure, the scanning voltage range is 0-2V. After the rubbing pulse is applied, the GST has changed from amorphous to crystalline. As long as the reading voltage is slightly larger than the threshold voltage (0.9V), its current storage state can be Distinguish by resistance value.

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Abstract

本发明公开了一种基于 VOx选通管的相变存储单元，包括下电极层、VOx选通层、相变功能层和上电极层。本发明采用了 VOx来实现相变功能层的选通，可以在相变功能层选通的基础上实现数据的存储。通过给 VOx施加电压来控制其状态切换，可以达到在低电压时相变存储单元为未选通状态、在高电压时为选通状态的目的。本发明通过 VOx的开关控制可以有效的减小相变存储器阵列的漏电流，提供足够高的 Reset 电流；本发明不需要高温工艺条件，简化了相变存储器的制备工艺，节约成本，为高集成度的相变存储器商用化提供了可能。

Description

一种基于VO x选通管的相变存储单元 【技术领域】
本发明属于半导体存储技术领域，更具体地，涉及一种基于VO x选通管的相变存储单元。
【背景技术】
相变存储器PCM是现在最有希望取代Flash存储器成为下一代的非易失性存储器之一。相变存储器单元以硫系化合物为相变材料在电压脉冲下可以实现为晶态和者非晶态的可逆转变。施加一个幅值中等，脉宽较长，脉冲下降沿较缓的电脉冲，可以使相变材料从非晶态转变为晶态，用来将数据从“0”写为“1”；施加一个幅值较高，脉宽较窄，下降沿陡峭的电脉冲，会使相变材料从晶态转变为非晶态，用来擦除数据。现在的高性能系统要求存储器具有更高密度的存储空间和更小的面积尺寸，由于相变单元存在有漏电流及所需要的Reset电流较大等问题，因此，选通管也成为相变存储器海量存储的关键因素之一。
图1为传统的1T1R结构。选通管一般用MOSFET或者BJT；MOSFET作为相变单元的选通管的原理是通过控制栅压来行成导电沟道从而控制源漏极的开关，其优点是电压降很小，但是如果要提供较高Reset电流(相变材料发生非晶变化所需电流)，则需要增加其沟道宽度，且在小尺寸时，MOSFET不能满足低噪声电流的要求，由于受限于额外选通管的单元面积，相变存储器的存储密度难以继续提升。用BJT作为选通管能够在高密度下提供足够的Reset电流，但是在高电流情况下BJT的电流放大系数将会降低，而且制备工艺成本高。采用二极管的1D1R结构时，因为二极管制备工艺刻蚀剥离步骤多且需要800℃高温的原因，制备条件要求高，难以实现存储单元的3D堆叠。因此，找到一种制备工艺简单且可以低温制备，既可以有 效减小漏电流，又有利于相变存储器的高密度3D堆叠集成的选通管，仍是一个难点。
【发明内容】
针对现有技术的以上缺陷或改进需求，本发明提供了一种基于VO x选通管的相变存储单元，通过控制VO x的开关来实现相变存储单元的选通，采取1D1T结构，能实现3D堆叠，由此解决传统1T1R结构相变存储器存储密度低，传统二极管的1D1R制备工艺需要高温的技术问题。相比较与1T1R结构和传统二极管的1D1R结构，本发明的制备工艺更加简单，不需要高温条件，节约成本，有利于相变存储器的高密度集成和大规模商用化。
本发明提供了一种基于VO x选通管的相变存储单元，包括：依次设置的下电极层、VO x选通层、相变功能层和上电极层；当在所述上电极层和所述下电极层之间施加电压时，所述VO x选通层能实现高阻态和低阻态之间的转换。
更进一步地，相变功能层的材料为GeTe、SbTe、BiTe、SnTe、AsTe、GeSe、SbSe、BiSe、SnSe、AsSe、InSe、GeSbTe和AgInSbTe中的任意一种以及上述任意一种化合物掺杂S或N或O或Cu或Si或Au元素形成的混合物。
更进一步地，上电极层和下电极层采用的材料为TiW、Pt、Au、W或其他不易与氧气反应的惰性电极。
更进一步地，VO x选通层中VO x材料的X的取值范围为1.9～2.1。
更进一步地，VO x选通层的阈值电压V th小于相变功能层的擦除操作电压V Set。
更进一步地，VO x选通层的面积大小为100nm 2～30μm 2。
更进一步地，选通层的VO x材料的绝缘态电阻大于金属态电阻，绝缘态电阻与金属态电阻的比值大于100。
本发明还提供了一种基于上述的相变存储单元的操作方法，包括下述 步骤：
通过在所述上电极层和所述下电极层之间施加一个大于阈值电压V th的强电脉冲，使得VO x选通层的温度升到其相变温度以上，VO x材料由绝缘态的单斜晶系转变为金属态的四方晶系；
通过在所述上电极层和所述下电极层之间施加一个小于保持电压V hold的电脉冲，使得VO x选通层的温度降到相变温度以下，VO x材料重新回到高阻绝缘态；即该VO x材料可以在热能作用下实现可逆转变；
当需要进行写入操作时，通过在所述上电极层和所述下电极层之间施加一个强度大于V Reset而下降沿为10ns的脉冲信号，使得相变功能层的温度升高到熔化温度以上，使得晶态的长程有序状态遭到破坏，之后极快的下降沿让相变材料迅速冷却到结晶温度以下，此时相变材料来不及晶化就处于高阻值的非晶态相变功能层处于低阻态；
当需要进行擦除操作时，通过在所述上电极层和所述下电极层之间施加一个强度介于V Reset和V Set之间且脉宽为200ns的脉冲信号，使得相变材料的温度升到晶化温度之上熔化温度以下并保持200ns确保材料完全晶化，此时相变材料由高阻态转变为低阻态，相变功能层处于高阻态，利用相变功能层不同的阻值状态来实现数据的存储。
更进一步地，VO x选通层的阈值电压小于相变单元的擦除操作电压V Set。
本发明还提供了一种制备上述的相变存储单元中VO x选通层的方法，包括：采用离子束溅射或磁控溅射沉积一层氧化钒再将该材料放入氮气或者氩气氛围中退火后，自然冷却到室温后获得所述VO x选通层。
总体而言，通过本发明所构思的以上技术方案与现有技术相比，具有以下有益效果：
(1)本发明提供的基于VO x选通管的相变存储单元和传统二极管选通管相比，二极管的制备工艺步骤繁多，需要两次次光刻和两次腐蚀、杂志 扩散、金属化和高于800 0C的退火工艺，高温工艺过程不利于其结构在三维(3D)方向的堆叠；VO x制备工艺十分简单，只需要在一次光刻后进行溅射和后退火工艺即可制备，低温工艺条件可以实现3D堆叠集成，成本低，有利于实现相变存储器的高密度存储。
(2)采用1D1R的结构，可以将最小尺寸面积缩小到4F 2，采用MOS管的1T1R结构的最小尺寸面积为8F 2，并且在需要更高Reset电流(相变材料发生非晶化所需电流)，则需要增加沟道宽度，本发明提供的方法有尺寸面积更小且制备工艺简单的优越性，可以在3D方向进行堆叠，有利于存储单元的高密度集成。
(3)利用VO x的金属绝缘体转变(MIT)来实现选通管的开关功能。能够提供高达10 6A/cm 2的开态电流密度和小于20ns的开关时间，并且其开关特性在尺寸减小的情况下可以稳定保持，BJT和MOS管无法在提高存储密度的同时保证高开关比或高Reset电流。
(4)本发明提供的基于VO x选通管的相变存储单元，是VO x材料在相变存储器方面的一次应用，对大容量相变存储器的商用化有启发和加速推进的作用。
【附图说明】
图1是传统1T1R的MOS管选通相变存储单元的结构示意图。
图2是本发明提供的VO x选通相变存储单元的结构示意图。
图3是本发明使用的VO x的I-V特性曲线，分为升压过程和降压过程，能够实现对相变存储单元选通电流的大小控制。
图4是本发明使用的VO x的R-V特性曲线，分为升压过程和降压过程，能够实现VO x高阻与低阻之间的转换。
图5是没有加入VO x选通层的相变单元I-V特性曲线。
图6是本发明整体结构的I-V特性曲线。
图7是本发明相变单元功能测试曲线图。
图中1为下电极层，2为VO x选通层，3为相变功能层，4为上电极层，5为相变电阻，6为晶体管。
【具体实施方式】
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。此外，下面所描述的本发明各个实施方式中所涉及到的技术特征只要彼此之间未构成冲突就可以相互组合。
为实现上述目的，本发明提供了一种基于VO x选通管的相变存储单元；通过施加电压的方法来切换VO x的开启和关闭状态，可以有效的控制相变存储器的选通。其中，使用VO x来作为相变存储单元的选通材料。通过施加电压到VO x选通层，实现对其状态控制。
如图2所示，基于VO x选通管的相变存储单元包括：依次设置的下电极层、VO x选通层、相变功能层和上电极层；当在上电极层和下电极层之间施加电压时，VO x选通层能实现高阻态和低阻态之间的转换。
具体地，在上电极层和下电极层施加电压，VO x选通层应具有开关特性，以保证能够实现高阻态和低阻态之间的转换。当施加一个大于V th的强电脉冲时，产生的热量可以使VO x温度升到其相变温度以上，材料会由绝缘态的单斜晶系转变为金属态的四方晶系；当施加一个小于V hold的电脉冲时，温度降到相变温度以下，材料会重新回到高阻绝缘态，即该VO x材料可以在热能作用下实现可逆转变。相变功能层实现数据的存储，在施加写入脉冲时，相变功能层处于低阻态；施加擦除脉冲时，相变功能层处于高阻态，利用相变功能层不同的阻值状态来实现数据的存储。
在本发明实施例中，制备这种具有相变特性的VO x时，先在衬底上用离子束溅射、直流磁控溅射或射频磁控溅射一层氧化钒薄膜材料，再在氮气或氩气等保护气氛围中退火，然后自然冷。这样便制备得到本发明的VO x 材料。溅射法和常规的蒸发法相比，(1)溅射法沉积原子的能量较高，因此所制薄膜的组织致密、附着力较好。(2)制备VO x薄膜时对成分的控制性能较好。(3)金属钒的熔点为1890±10℃，蒸发沉积方法需要很高的基底温度才能使之蒸发，而溅射法可以方便地利用高熔点物质的溅射。与PLD法相比，PLD法虽能获得质量较高的薄膜，难以形成大面积均匀薄膜且设备相对较贵，不适合批量生产，而溅射法则适合批量生产。与其他方法相比：(1)溶胶一凝胶方法可以在大面积非平面基底上成膜，但制备高取向、开关特性好的高质量VO x膜相当困难，薄膜特性较难控制，所制薄膜致密度差，厚度不易控制，容易存在气泡或开裂等缺陷，而且容易造成污染；(2)化学气相沉积需要用到稀有、有毒气体，造成工作人员不安全，且不利于环保；(3)分子束外延、原子层沉积技术设备昂贵，操作困难，不利于批量和工业化生产。
图3是VO x单元的V-I曲线，逐渐增加在VO x上施加的电压，当电压达到阈值电压V th时，通过VO x的电流急剧增大，此时VO x由半导体高阻态转变为金属低阻态，选通管开启；相反的，逐渐减小施加在VO x上的电压时，当电压减小到保持电压V hold时，通过VO 2的电流急剧减小，此时VO x返回到半导体高阻态，选通管关闭。
在本发明实施例中，采用的是不需要额外晶体管的1D1R结构，相比较与1T1R结构，尺寸更小且有利于实现3D堆叠。VO x的制备工艺十分简单，与需要高温条件下制备的二极管相比，VO x在室温条件下溅射后再进行后退火工艺即可得到，简化制备工艺，节约成本。VO x的阈值电压，远小于相变单元的相变临界电压V pc，使得相变存储单元有较大的操作窗口。VO x的开关比可以高达10 4数量级，能有效减小漏电流并提供足够大的Reset驱动电流。
图3是VO x材料的典型I-V特性曲线，图4是其典型R-V曲线。参考这两图，可以看出当在VO x上施加电压时，在电压达到2.2V时，VO x由高 阻转变到低阻，开态电路与关态电流比值接近3个数量级，将此临界电压称为阈值电压V th。
在本发明实施例中，VO x的阈值电压V th与其制备工艺的具体参数有关，在能够制备出具有相变特性的VO x的氧气浓度范围内，V th的大小与VO x溅射过程中氧气浓度大小呈正相关，特别的，VO x选通层单元面积尺寸越小，V th越小。
在本发明实施例中，构成选通层的VO x材料的绝缘态电阻大于金属态电阻，绝缘态电阻与金属态电阻的比值大于100，特别地，绝缘态电阻与金属态电阻的比值大于10000。电阻比值大小与制备工艺中具体参数的选择有关，随着氧气浓度的增加，电阻比值减小。同时电阻的大小与选通层面积尺寸有关，尺寸越小，选通层的开关电阻越小，开关比也越大，所以本发明在小尺寸的高密度存储阵列中具有更优秀的选通特性。
在本发明实施例中，构成选通层的VO x材料的相变温度在68℃附近，特别地，VO x的相变温度可在60℃～80℃。
图5是相变材料GST的典型I-V特性曲线，从图上可以看到，当外加电压达到相变材料的相变电压V Set时，其产生的热量可使相变材料上升至晶化温度以上并维持足够的原子驰豫时间，材料会由无序的非晶态转变为有序的晶态电阻值会发生急剧变化。
在本发明实施例中，非晶态电阻与晶态电阻的比值大于10；特别地，非晶态电阻与晶态电阻的比值大于100000。
在本发明实施例中，相变材料的相变电压V Set与掺杂浓度有关，对相变材料掺杂N、Si可以提高晶化温度，从而使V Set增大。
为了更进一步的说明本发明实施例提供的一种基于VO x选通管的相变存储单元，现结合具体实例详述如下：
图6是测试该发明的选通过程曲线，当电压从零逐渐增大的过程中，电流也随之增加，在电压达到阈值电压V th时，电流发生了跳变急剧增大， 说明此时VO x由关态转变为开态，整体的电阻急剧减小，选通管打开。在选通管打开的情况下，继续增加施加电压，当电压增加到相变电压V Set时，电路再次发生跳变急剧增大，此时是因为外加电压达到GST相变材料的相变电压，GST由非晶态转换为晶态，电阻减小，实现了相变单元的擦除操作。并且选通管的阈值电压V th与相变单元的相变电压V Set相比小很多，使得相变单元有较大的操作窗口。
图7是测试该发明的读取功能曲线，为了研究TiWGST/VO 2/TiW的读取功能，我们给单元施加一个擦除脉冲(Setting pulse)。因为GST的相变电压为4.6V，我们施加一个幅值6V，脉宽500ns的擦脉冲。对比图中两条曲线，扫描电压范围0-2V，在施加擦脉冲后，GST已经由非晶态转变为晶态，只要读取电压略大于阈值电压(0.9V)时，其当前存储状态可以通过电阻值区别。
本领域的技术人员容易理解，以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (10)

  1. 一种基于VO x选通管的相变存储单元，其特征在于，包括：依次设置的下电极层、VO x选通层、相变功能层和上电极层；当在所述上电极层和所述下电极层之间施加电压时，所述VO x选通层能实现高阻态和低阻态之间的转换。
  2. 如权利要求1所述相变存储单元，其特征在于，所述相变功能层的材料为GeTe、SbTe、BiTe、SnTe、AsTe、GeSe、SbSe、BiSe、SnSe、AsSe、InSe、GeSbTe和AgInSbTe中的任意一种以及上述任意一种化合物掺杂S或N或O或Cu或Si或Au元素形成的混合物。
  3. 如权利要求1或2所述的相变存储单元，其特征在于，所述上电极层和下电极层采用的材料为TiW、Pt、Au、W或其他不易与氧气反应的惰性电极。
  4. 如权利要求1-3任一项所述的相变存储单元，其特征在于，所述VO x选通层中VO x材料的X的取值范围为1.9～2.1。
  5. 如权利要求1-4任一项所述的相变存储单元，其特征在于，所述VO x选通层的阈值电压V th小于相变功能层的擦除操作电压V Set。
  6. 如权利要求1-5任一项所述的相变存储单元，其特征在于，VO x选通层的面积大小为100nm 2～30μm 2。
  7. 如权利要求1-6任一项所述的相变存储单元，其特征在于，选通层的VO x材料的绝缘态电阻大于金属态电阻，绝缘态电阻与金属态电阻的比值大于100。
  8. 一种基于权利要求1所述的相变存储单元的操作方法，其特征在于，包括下述步骤：
    通过在所述上电极层和所述下电极层之间施加一个大于阈值电压V th的强电脉冲，使得VO x选通层的温度升到其相变温度以上，VO x材料由绝 缘态的单斜晶系转变为金属态的四方晶系；
    通过在所述上电极层和所述下电极层之间施加一个小于保持电压V hold的电脉冲，使得VO x选通层的温度降到相变温度以下，VO x材料重新回到高阻绝缘态；
    当需要进行写入操作时，通过在所述上电极层和所述下电极层之间施加一个强度大于V Reset下降沿为10ns的脉冲信号，使得相变功能层的温度升高到熔化温度以上，使得晶态的长程有序状态遭到破坏，之后极快的下降沿让相变材料迅速冷却到结晶温度以下，此时相变材料来不及晶化就处于高阻值的非晶态相变功能层处于低阻态；
    当需要进行擦除操作时，通过在所述上电极层和所述下电极层之间施加一个强度介于V Reset和V Set之间且脉宽为200ns的脉冲信号，使得相变材料的温度升到晶化温度之上熔化温度以下并保持一段时间来确保材料完全晶化，此时相变材料由高阻态转变为低阻态，相变功能层处于高阻态，利用相变功能层不同的阻值状态来实现数据的存储。
  9. 如权利要求8所述的操作方法，其特征在于，所述VO x选通层的阈值电压小于相变单元的擦除操作电压V Set。
  10. 一种制备权利要求1所述的相变存储单元中VO x选通层的方法，其特征在于，包括：采用离子束溅射或磁控溅射沉积一层氧化钒再将该材料放入氮气或者氩气氛围中退火后，自然冷却到室温后获得所述VO x选通层。
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