WO2023193295A1 - 显示面板及其制备方法 - Google Patents

显示面板及其制备方法 Download PDF

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Publication number
WO2023193295A1
WO2023193295A1 PCT/CN2022/087682 CN2022087682W WO2023193295A1 WO 2023193295 A1 WO2023193295 A1 WO 2023193295A1 CN 2022087682 W CN2022087682 W CN 2022087682W WO 2023193295 A1 WO2023193295 A1 WO 2023193295A1
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Prior art keywords
electrode
layer
display panel
active pattern
lightly doped
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PCT/CN2022/087682
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English (en)
French (fr)
Inventor
宋继越
艾飞
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武汉华星光电技术有限公司
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Priority to US17/771,508 priority Critical patent/US20240142837A1/en
Publication of WO2023193295A1 publication Critical patent/WO2023193295A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
    • G02F1/13318—Circuits comprising a photodetector
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays

Definitions

  • the present application relates to the field of light-sensitive display technology, and specifically to a display panel and a display panel preparation method.
  • Photoelectric detection sensors are widely used and can be used in non-contact measurement, fingerprint recognition, ambient light detection, communications and other aspects.
  • the panel industry in addition to high resolution, wide viewing angle, low power consumption and other requirements for displays, people also put forward other requirements for display panels.
  • Enriching panel functions, increasing human-computer interaction, and improving the competitiveness of display panels are currently one of the main development directions of display panels.
  • the ambient light detection function can automatically adjust the screen brightness according to the brightness of the external environment. It can also automatically turn on the flash or fill in the light when taking pictures according to the external environment.
  • Today's ambient light sensors basically use external plug-in methods, which inevitably increases the cost of production. Therefore, integrating ambient light sensors into the array substrate with a smaller number of masks to achieve low-cost integration of ambient light detection has become a hot topic of public concern for panel manufacturers and terminal manufacturers.
  • Embodiments of the present application provide a display panel and a display panel preparation method, which can alleviate the technical problems of short life and poor luminous efficiency of existing light-emitting devices.
  • the display panel includes an array substrate, and the array substrate includes:
  • the photosensitive device includes a first electrode, a second electrode, a second active layer, a connecting electrode, and a barrier member;
  • the second active pattern includes a second intrinsic part, a second heavily doped part, a third Two lightly doped parts, the second electrode is electrically connected to the second heavily doped part, the first electrode is electrically connected to the second lightly doped part through the connecting electrode, and the connecting electrode is The second lightly doped portion contacts;
  • the orthographic projection of the blocking member on the substrate overlaps with the orthographic projection of the second intrinsic part on the substrate, and the second intrinsic part surrounds the second lightly doped part.
  • the second heavily doped part is arranged around the second intrinsic part.
  • the display panel further includes an interlayer insulating layer, a flat layer, and a passivation layer.
  • the interlayer insulating layer is disposed above the substrate, and the flat layer is disposed Above the interlayer insulating layer, the passivation layer is disposed on the flat layer, and the second electrode is connected to the second heavily doped portion through a first via hole.
  • connection electrode includes the first part located in the second via hole, the second part located in the third via hole and connected to the The first part and the third part of the second part, the first part is connected to the second lightly doped part, the second part is connected to the first electrode, the first part and the second The parts are respectively arranged along the film thickness direction.
  • the first electrode, the second electrode, the connection electrode, and the second active pattern form a vertical heterojunction structure.
  • the area of the contact surface between the connecting electrode and the second lightly doped part is smaller than the surface of the second lightly doped part facing the connecting electrode. area.
  • the ratio of the area of the bottom surface of the second via hole to the upper surface area of the second lightly doped part ranges from 0.85:1 to 1:1.
  • the contact surface is the light-receiving surface of the vertical heterojunction structure.
  • the blocking member is an annular structure.
  • the thin film transistor device includes a first active pattern, a gate electrode, a source electrode, and a drain electrode disposed above the substrate, and the gate electrode is disposed on the Above the first active pattern, the source electrode and the drain electrode are arranged above the gate electrode.
  • the first active pattern includes a first intrinsic part, a first heavily doped part, a first lightly doped part. part, the first lightly doped part is arranged around the first intrinsic part, the first heavily doped part is arranged around the first lightly doped part, the first active pattern and the third Two active patterns are set on the same layer.
  • the first active pattern and the second active pattern are made of the same material.
  • the barrier is provided in the same layer as the gate.
  • the barrier and the gate are made of the same material.
  • the second electrode, the first electrode, the source electrode, and the drain electrode are arranged in the same layer.
  • the display panel further includes a third electrode disposed on the passivation layer, the third electrode is connected to the source electrode, and the connection electrode is connected to the source electrode.
  • the third electrode is arranged on the same layer.
  • the third electrode is an anode
  • the connection electrode and the anode are made of copper, silver, lithium, ytterbium, magnesium, aluminum, indium, ITO, and IZO , at least one of AZO.
  • the display panel further includes a fourth electrode, the fourth electrode is disposed on the flat layer, and the connection electrode is disposed in the same layer as the fourth electrode.
  • the fourth electrode is a cathode
  • the connecting electrode and the cathode are made of copper, silver, lithium, ytterbium, magnesium, aluminum, indium, ITO, IZO, AZO at least one of them.
  • Embodiments of the present application provide a display panel preparation method, including:
  • An active layer is prepared above the substrate, and the active layer includes a first active pattern and a second active pattern arranged on the same layer;
  • a gate insulation layer, a gate electrode layer, and an interlayer insulation layer are prepared above the active layer.
  • the gate electrode layer includes a gate electrode and a barrier member.
  • the gate electrode is arranged corresponding to the first active pattern.
  • the blocking member is provided corresponding to the second active pattern;
  • a source electrode, a drain electrode, a first electrode, and a second electrode are prepared above the interlayer insulating layer;
  • a flat layer and a connecting electrode are prepared above the source and drain layer, wherein the source electrode, the drain electrode, and the gate electrode constitute a thin film transistor device, and the first electrode, the second electrode, and the gate electrode constitute a thin film transistor device.
  • the connection electrode and the second active pattern constitute a photosensitive device.
  • the step of preparing the source, the drain, the first electrode, and the second electrode further includes: preparing a source and drain layer on the interlayer insulating layer,
  • the source and drain layer includes the source electrode, the drain electrode, the first electrode, and the second electrode arranged in the same layer.
  • the step of preparing the gate layer further includes: preparing the gate layer above the substrate, and the gate layer includes a same-layer configuration.
  • the gate electrode and the barrier member are provided correspondingly to the first active pattern, and the barrier member is provided correspondingly to the second active pattern, wherein the barrier member is a ring structure.
  • the orthographic projection of the blocking member on the substrate overlaps with the orthographic projection of the second intrinsic part on the substrate, so that the second active pattern includes the second lightly doped part, the second intrinsic part, and the second intrinsic part.
  • Characteristic part, second heavily doped part, the second intrinsic part is arranged around the second lightly doped part, the second heavily doped part is arranged around the second intrinsic part, and the dark state of the photosensitive device is reduced through the second intrinsic part. current to improve sensitivity.
  • Figure 1 is a schematic cross-sectional view of a display panel provided by an embodiment of the present application.
  • Figure 2 is a schematic top view of a photosensitive device in a display panel provided by an embodiment of the present application
  • Figure 3 is a schematic flow chart of a display panel preparation method provided by an embodiment of the present application.
  • 4A to 4G are schematic cross-sectional views of a display panel manufacturing method provided by embodiments of the present application.
  • the photosensitive device is installed outside the display panel in an external way, which increases the cost of production; and how to integrate the photosensitive device inside the display panel with a smaller number of photomasks becomes a major problem in various aspects of the display panel.
  • the display panel provided by this application includes a substrate 10, a thin film transistor device 1 disposed above the substrate 10, and a photosensitive device 2.
  • the thin film transistor device 1 includes a thin film transistor device 1 disposed above the substrate 10.
  • the first active pattern 401 includes a first intrinsic part 4011, a first heavily doped part 4012, and a first lightly doped part 4013.
  • the photosensitive device 2 includes a first electrode 804, a second electrode 803, a second active pattern 402, and a connection electrode 130.
  • the second active pattern 402 includes a second intrinsic part 4021 and a second heavily doped part. 4022.
  • the second lightly doped part 4023, the second electrode 803 is electrically connected to the second heavily doped part 4022, and the first electrode 804 is electrically connected to the second lightly doped part 4023, wherein,
  • the first active pattern 401 and the second active pattern 402 are arranged in the same layer.
  • the present application reduces the number of photomasks required to integrate the photosensitive device 2 into the display panel and reduces the cost. cost.
  • the blocking member 602, the first electrode 804, the second electrode 803, and the connecting electrode 130 of the photosensitive device 2 can be prepared by sharing a photomask with the existing film layer of the thin film transistor device 1; specifically, the The second active pattern 402 and the first active pattern 401 may be arranged in the same layer, the barrier member 602 and the gate electrode 601 may be arranged in the same layer, the first electrode 804, the second electrode 803 and The source electrode 801 and the drain electrode 802 can be arranged on the same layer, and the connection electrode 130 and the third electrode 120/fourth electrode 100 can be arranged on the same layer; at this time, the photosensitive device can be placed without adding a photomask. 2 integrated into the display panel.
  • the photosensitive device 2 can be a light sensor, used for receiving light signals, and can be used for non-contact measurement, fingerprint identification, ambient light detection, communication, etc.
  • the functions of the display panel are enriched and the functions of the display panel are increased. Improve human-computer interaction and improve the competitiveness of display panels.
  • the display panel of this application can be an OLED display panel or a liquid crystal display panel; the following description mainly takes the FFS liquid crystal display panel as an example.
  • the first electrode 804, the second electrode 803, the connection electrode 130, and the second active pattern 402 form a vertical heterojunction structure.
  • connection electrode includes the first part located in the second via hole H2, the second part located in the third via hole H3, and a connecting electrode connecting the first part and the second part.
  • the third part, the first part is connected to the second lightly doped part 4023, the second part is connected to the first electrode 804, the first part and the second part are respectively arranged along the film thickness direction. .
  • the contact surface is the light-receiving surface of the vertical heterojunction structure, and the area of the contact surface is smaller than the area of the surface of the second lightly doped portion 4023 facing the connection electrode 130 .
  • the display panel may be an OLED display panel.
  • the OLED display panel includes a substrate 10 , an array layer, a flat layer 90 , and an anode and a cathode disposed above the flat layer 90 .
  • connection electrode 130 may be disposed in the same layer as the anode or the cathode.
  • connection electrode 130 can share the same photomask with any one of the plurality of electrodes, and there is no need to add an additional photomask for preparing the connection electrode 130, thereby reducing costs.
  • the display panel may be an FFS liquid crystal display panel.
  • the liquid crystal display panel includes an array substrate.
  • the array substrate includes a substrate 10, a light shielding layer 20, and a buffer layer 30. , active layer 40, gate insulating layer 50, gate electrode layer, interlayer insulating layer 70, source and drain layers, planarization layer 90, fourth electrode layer 100, passivation layer 110, and third electrode layer.
  • the active layer 40 includes a first active pattern 401 and a second active pattern 402; taking the second active pattern 402 as an example, the second active pattern 402 is located in the photosensitive device 2, and the second active pattern 402 is located in the photosensitive device 2.
  • the two active patterns 402 include a second intrinsic part 4021, a second heavily doped part 4022, and a second lightly doped part 4023; wherein the second intrinsic part 4021 is a semiconductor, and the second heavily doped part 4022 is a conductor; the resistance value of the second intrinsic part 4021 is greater than the resistance value of the second lightly doped part 4023 is greater than the resistance value of the second heavily doped part 4022; therefore, N is blocked by the barrier 602 - Ions are lightly doped, and the blocking member 602 corresponds to the second intrinsic part 4021, which can increase the impedance of the overall second active pattern 402, thereby reducing the dark state current of the photosensitive device 2 and improving the detection sensitivity; the first active The pattern 401 is similar to the second active pattern
  • the proportion of the second intrinsic portion 4021 in the second active pattern 402 can be controlled, thereby further reducing the dark state current of the photosensitive device 2 and improving the detection sensitivity.
  • the gate layer may include a gate 601 and a barrier 602 arranged in the same layer.
  • the source and drain layers may include a source electrode 801, a drain electrode 802, a first electrode 804, and a second electrode 803 arranged in the same layer.
  • the fourth electrode 100 layer may include the fourth electrode 100 and the connection electrode 130 arranged in the same layer, or the third electrode layer may include the third electrode 120 and the connecting electrode 130 arranged in the same layer. Connect electrode 130.
  • the film thickness of the light-shielding layer 20 ranges from 500 angstroms to 5000 angstroms.
  • the preparation material may be at least one of Mo, Al, Cu, Ti or alloys.
  • the thickness of the buffer layer 30 ranges from 1000 angstroms to 5000 angstroms.
  • the buffer layer 30 is a layer of SiOx, a layer of SiNx or a SiNx/SiOx stacked structure.
  • the preparation material of the active layer 40 includes poly-Si.
  • the gate insulating layer is a layer of SiOx, a layer of SiNx, or a SiNx/SiOx stack structure, with a thickness ranging from 1000 angstroms to 5000 angstroms.
  • the interlayer insulating layer 70 is made of at least one material selected from SiOx, SiNx, SiON, and metal oxide.
  • the interlayer insulating layer 70 may be a SiNx/SiOx stacked structure.
  • the source and drain layer is made of at least one material selected from the group consisting of Mo, Ti, Al, Cu, Ag, and alloys.
  • the second electrode 803 is connected to the second heavily doped part 4022 through a first via hole H1
  • the first electrode 804 is connected to the connection electrode 130 through a second via hole H2.
  • the connection electrode 130 is connected to the second lightly doped part 4023 through the third via hole H3, the second electrode 803, the first electrode 804, the source electrode 801, and the drain electrode 802 are the same. Layer settings.
  • the first electrode 804, the second electrode 803, the connection electrode 130, and the second active pattern 402 constitute a heterojunction vertical structure.
  • the heterojunction vertical structure increases the degree of freedom in designing the area. .
  • the photosensitive area of the photosensitive device 2 that receives light has freely adjustable characteristics, which is equal to the contact area between the connecting electrode 130 and the second lightly doped portion 4023.
  • the surface area of the lightly doped portion 4023 can adjust the maximum value of the photosensitive area; by adjusting the contact area between the connecting electrode 130 and the second lightly doped portion 4023, the size of the photosensitive area can be adjusted.
  • the display panel further includes a third electrode 120 disposed above the thin film transistor device 1, the third electrode 120 is connected to the source electrode 801/drain electrode 802, and the connection electrode 130 is arranged in the same layer as the third electrode 120 .
  • the second intrinsic part 4021 is arranged around the second lightly doped part 4023, and the second heavily doped part 4022 is arranged around the second intrinsic part 4021.
  • the A blocking member 602 is provided above the second intrinsic part 4021 , and the blocking member 602 is provided in the same layer as the gate electrode 601 .
  • the blocking member 602 may be an annular structure.
  • the second intrinsic part 4021 is formed below the blocking member 602, and the resistance of the second intrinsic part 4021 is lighter than that of the second intrinsic part 4021. /The heavily doped part is large, which can reduce the dark state current of the device and improve the detection sensitivity.
  • the blocking member 602 is a ring-shaped structure, and the orthographic projection of the blocking member 602 on the substrate 10 is the same as the orthogonal projection of the second intrinsic part 4021 on the substrate 10 . Projections overlap.
  • the blocking member 602 is positioned in alignment with the second intrinsic portion 4021 .
  • connection electrode 130 is in contact with the second lightly doped portion 4023 through a contact surface, and the area of the contact surface is smaller than that of the second lightly doped portion 4023 toward the connection electrode 130 The area of one side of the surface.
  • the first active pattern 401 and the second active pattern 402 are made of the same material.
  • the barrier 602 and the gate 601 are made of the same material.
  • the first electrode 804 and the second electrode 803 are made of the same material as the source electrode 801 and the drain electrode 802 .
  • connection electrode 130 is made of the same material as the third electrode 120 and the fourth electrode 100 .
  • connection electrode 130, the third electrode 120, and the fourth electrode 100 are made of at least one of copper, silver, lithium, ytterbium, magnesium, aluminum, indium, ITO, IZO, and AZO.
  • an embodiment of the present application provides a display panel preparation method, including:
  • An active layer 40 is prepared above the substrate 10.
  • the active layer 40 includes a first active pattern 401 and a second active pattern 402 arranged on the same layer;
  • a gate insulating layer 50, a gate electrode layer, and an interlayer insulating layer 70 are prepared above the active layer 40.
  • the gate electrode layer includes a gate electrode 601 and a barrier member 602.
  • the gate electrode 601 and the third An active pattern 401 is provided correspondingly, and the blocking member 602 is provided correspondingly to the second active pattern 402;
  • S4 Prepare a source electrode 801, a drain electrode 802, a first electrode 804, and a second electrode 803 on the interlayer insulating layer 70;
  • S5 Prepare a flat layer 90 and a connection electrode 130 above the source and drain layers, wherein the source electrode 801, the drain electrode 802, and the gate electrode 601 constitute the thin film transistor device 1, and the first electrode 804.
  • the second electrode 803, the connection electrode 130, and the second active pattern 402 constitute the photosensitive device 2.
  • the display panel preparation method is an FFS liquid crystal display panel preparation method
  • the FFS liquid crystal display panel includes an array substrate. Please refer to FIGS. 4A to 4G for the array substrate preparation method.
  • a substrate 10 is provided, and a light-shielding layer 20 is prepared on the substrate 10 .
  • a buffer layer 30 is prepared on the substrate 10 and the light-shielding layer 20, and a buffer layer 30 is prepared on the buffer layer 30.
  • the a-Si layer is converted into poly-Si, and an exposure etching method is used to prepare the active layer 40.
  • the active layer 40 includes a first active pattern 401 and a second active pattern 401.
  • the first active pattern 401 and the second active pattern 402 are doped with phosphorus ions to prepare the first heavily doped portion 4012 of the first active pattern 401 and the second portion of the second active pattern 402. Double doping part 4022.
  • a gate insulating layer 50 is prepared on the buffer layer 30 and the active layer 40.
  • a gate layer is prepared on the top of the screen.
  • the gate layer includes a gate electrode 601 and a barrier member 602. N- ions are implanted through the gate electrode 601 and the barrier member 602 to shield the first lightly doped active pattern 401.
  • the dark-state current of the device is reduced, and the sensitivity of the photosensitive device 2 is improved.
  • an interlayer insulating layer 70 is prepared on the gate insulating layer 50 and the gate electrode layer, and the interlayer insulating layer 70 is prepared.
  • the insulating layer 70 is patterned to obtain the first via hole H1.
  • the plurality of via holes correspond to the first heavily doped portion 4012 and the second heavily doped portion 4022 respectively.
  • the step of patterning to obtain the first via hole H1 includes: obtaining the first via hole H1 through an exposure and etching method.
  • the interlayer insulating layer 70 may be a SiNx/SiOx stacked structure.
  • a source-drain layer is prepared on the interlayer insulating layer 70.
  • the source-drain layer includes sources arranged in the same layer. electrode 801, drain electrode 802, first electrode 804, and second electrode 803; wherein, the source electrode 801/drain electrode 802 and the first heavily doped part 4012 are respectively connected through two through holes, and the second electrode 803 is connected to the second heavily doped part 4022 through the first via hole H1.
  • a flat layer 90 is prepared on the interlayer insulating layer 70 and the source and drain layer.
  • a fourth electrode 100 is prepared on the fourth electrode 100 and a passivation layer 110 is prepared on the fourth electrode 100 and the flat layer 90 ; and the flat layer 90 and the passivation layer 110 are patterned to form a second via hole. H2, third via hole H3.
  • the aperture of the second via hole H2 can be adaptively adjusted according to the required photosensitive area, which increases the degree of freedom in designing the area.
  • the area of the bottom surface of the second via hole H2 is equal to Or slightly smaller than the upper surface area of the second lightly doped portion 4023; for example, when the area of the bottom surface of the second via hole H2 is slightly smaller than the upper surface area of the second lightly doped portion 4023, the second via hole H2
  • the ratio of the area of the bottom surface to the upper surface area of the second lightly doped portion 4023 ranges from 0.85:1 to 1:1.
  • the flat layer 90 may be made of organic materials, or may be made of inorganic insulating layer materials such as SINx and SiOx.
  • the aperture of the second via hole H2 can be adaptively adjusted according to the required photosensitive area, which increases the freedom of designing the photosensitive area.
  • a third electrode layer is prepared on the passivation layer 110.
  • the third electrode layer includes a third electrode 120 and a connecting layer. Electrode 130.
  • connection electrode 130 and the second lightly doped portion 4023 are connected through the second via hole H2, and the connection electrode 130 and the first electrode 804 are connected through the third via hole H3.
  • connection electrode 130 can also be prepared in the same layer as the fourth electrode 100 , that is, when the fourth electrode 100 is prepared, the same photomask is used to simultaneously prepare the connection electrode 130 .
  • the step of preparing the gate layer further includes: preparing the gate layer above the substrate 10 , and the gate layer includes a gate electrode 601 and a gate electrode 601 arranged on the same layer.
  • the barrier member 602, the gate electrode 601 is provided correspondingly to the first active pattern 401, and the barrier member 602 is provided correspondingly to the second active pattern 402, wherein the barrier member 602 is a ring-shaped structure.
  • the step of preparing the source electrode 801, the drain electrode 802, the first electrode 804, and the second electrode 803 further includes: preparing a source and drain layer on the interlayer insulating layer 70, so The source and drain layers include the source electrode 801, the drain electrode 802, the first electrode 804, and the second electrode 803 arranged in the same layer.
  • the method further includes: preparing an electrode layer above the source and drain layer.
  • the electrode layer includes a third electrode 120 and the connection electrode 130 arranged in the same layer.
  • the third electrode 120 The source electrode 801 and the drain electrode 802 are connected through a through hole penetrating the planar layer 90 .
  • connection electrode 130 and the third electrode 120 using the same photomask, one photomask can be further saved, the number of photomasks can be reduced, and the cost can be reduced.
  • the blocking member 602 and the gate 601 share a photomask
  • the second active pattern 402 and the first active pattern 401 share a photomask.
  • the second electrode 803, the source electrode 801, and the drain electrode 802 share a photomask
  • the connection electrode 130 and the third electrode 120/fourth electrode 100 share a photomask.
  • the method further includes: forming a first via hole H1, a second via hole H2, and a third via hole H3 in the display panel, so that the second electrode 803 passes through the first via hole H1 and the third via hole H3.
  • the second heavily doped part 4022 is connected, so that the first electrode 804 is connected to the connection electrode 130 through the second via hole H2, and the connection electrode 130 is connected to the second lightly doped part through the third via hole H3.
  • Department 4023 connection is
  • the above display panel preparation method mainly uses the LTPS process as an example.
  • the application is not limited to the LTPS process and can also be used for a-Si, IGZO and other processes.
  • the photosensitive device 2 can be integrated into the display panel or on the display panel without increasing the number of masks. inside the array substrate.
  • This application also proposes a display device and a display module, wherein the display module may include the above-mentioned FFS display panel and a backplane, a plastic frame, and an optical film arranged on one side of the FFS display panel. Light guide plate/diffusion sheet, etc.
  • the display device also includes the above-mentioned display panel, which will not be described again here.
  • Embodiments of the present application provide a display panel.
  • the display panel includes a substrate, a thin film transistor device disposed above the substrate, and a photosensitive device.
  • the thin film transistor device includes a first active device disposed above the substrate. pattern, gate, source, and drain, the first active pattern includes a first intrinsic part, a first heavily doped part, and a first lightly doped part, and the photosensitive device includes a first electrode, a second electrode, a second active pattern, and a connecting electrode.
  • the second active pattern includes a second intrinsic part, a second heavily doped part, and a second lightly doped part.
  • the second electrode is connected to the second heavily doped part.
  • the doped part is electrically connected, and the first electrode is electrically connected to the second lightly doped part.
  • the orthographic projection of the blocking member on the substrate is consistent with the second intrinsic part on the substrate.
  • the orthographic projection on the top overlaps, so that the second active pattern includes a second lightly doped part, a second intrinsic part, and a second heavily doped part.
  • the second intrinsic part is arranged around the second lightly doped part, and the second heavily doped part.
  • the doping part is arranged around the second intrinsic part, and the second intrinsic part reduces the dark state current of the photosensitive device and improves the sensitivity.
  • the first electrode and the second electrode of the photosensitive device are arranged in the same layer as the source and drain of the thin film transistor device, and the first electrode, the second electrode, the source and the drain are prepared by using the same photomask.
  • the connecting electrode of the photosensitive device is arranged in the same layer as the third electrode/fourth electrode above the thin film transistor device, and the connecting electrode and the third electrode/fourth electrode are prepared by using the same photomask; the blocking of the photosensitive device
  • the blocking member and the gate electrode of the thin film transistor device are arranged in the same layer, and the blocking member and the gate electrode are prepared by using the same photomask; therefore, the photosensitive device can be integrated into the display panel without adding a photomask.

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Abstract

一种显示面板，其包括感光器件（2），感光器件（2）包括阻挡件（602）和第二有源图案（402）；第二有源图案（402）包括第二轻掺杂部（4023）、围绕第二轻掺杂部（4023）设置的第二本征部（4021）、围绕第二本征部（4021）设置的第二重掺杂部（4022），在膜层厚度方向上，阻挡件（602）与第二本征部（4021）重叠设置；通过第二本征部（4021）降低感光器件（2）的暗态电流，提升灵敏度。

Description

显示面板及其制备方法 技术领域
本申请涉及光感显示技术领域，具体涉及一种显示面板、一种显示面板制备方法。
背景技术
光电探测传感器应用十分广泛，可用于无接触量测，指纹识别，环境光检测，通信等各方面。随着面板产业的迅猛发展，人们除了对显示器高分辨、宽视角、低功耗等要求外，也对显示面板提出了其它要求。丰富面板功能，增加人机互动，提高显示面板的竞争力，是目前显示面板的主要发展方向之一。其中环境光检测功能可以根据外部环境的亮度自动调节屏幕亮度，也可以根据外界的环境，在拍照时自动打开闪光灯或者进行补光。现在的环境光传感器基本都采用外挂方式，这样无法避免地增加了制作的成本。因此，以较少的光罩数量，将环境光传感器集成于阵列基板内部，从而实现低成本坏境光检测的集成，已成为各面板厂商和终端厂商所公共关注的热点。
因此，现有显示面板存在感光器件较难低成本的集成在显示面板内的技术问题。
技术问题
因此，现有显示面板存在感光器件较难低成本的集成在显示面板内的技术问题。
技术解决方案
本申请实施例提供一种显示面板、一种显示面板制备方法，可以 缓解现有发光器件存在寿命短且发光效率不佳的技术问题。
本申请实施例提供一种显示面板，所述显示面板包括阵列基板，所述阵列基板包括：
衬底；
薄膜晶体管器件；
感光器件，所述感光器件包括第一电极、第二电极、第二有源层、连接电极、阻挡件，所述第二有源图案包括第二本征部、第二重掺杂部、第二轻掺杂部，所述第二电极与所述第二重掺杂部电连接，所述第一电极通过所述连接电极与所述第二轻掺杂部电连接，所述连接电极与所述第二轻掺杂部接触；
其中，所述阻挡件在所述衬底上的正投影与所述第二本征部在所述衬底上的正投影重叠，所述第二本征部围绕所述第二轻掺杂部设置，所述第二重掺杂部围绕所述第二本征部设置。
可选的，在本申请的一些实施例中，所述显示面板还包括层间绝缘层、平坦层、钝化层，所述层间绝缘层设置于所述衬底上方，所述平坦层设置于所述层间绝缘层上方的，所述钝化层设置于所述平坦层上，所述第二电极通过第一过孔与所述第二重掺杂部连接。
可选的，在本申请的一些实施例中，所述连接电极包括位于所述第二过孔内的所述第一部分、位于所述第三过孔内的所述第二部分以及连接所述第一部分和所述第二部分的第三部分，所述第一部分与所述第二轻掺杂部连接，所述第二部分与所述第一电极连接，所述第一部分和所述第二部分分别沿膜厚方向设置。
可选的，在本申请的一些实施例中，所述第一电极、所述第二电极、所述连接电极、所述第二有源图案构成垂直异质结结构。
可选的，在本申请的一些实施例中，所述连接电极与所述第二轻掺杂部接触的接触面的面积小于所述第二轻掺杂部朝向所述连接电极一侧表面的面积。
可选的，在本申请的一些实施例中，所述第二过孔底面的面积与所述第二轻掺杂部的上表面积的比值范围为0.85：1至1:1。
可选的，在本申请的一些实施例中，所述接触面为所述垂直异质结结构的受光面。
可选的，在本申请的一些实施例中，所述阻挡件为环状结构。
可选的，在本申请的一些实施例中，所述薄膜晶体管器件包括设置于所述衬底上方的第一有源图案、栅极、源极、漏极，所述栅极设置于所述第一有源图案上方，所述源极、所述漏极设置于所述栅极上方，所述第一有源图案包括第一本征部、第一重掺杂部、第一轻掺杂部，所述第一轻掺杂部围绕所述第一本征部设置，所述第一重掺杂部围绕所述第一轻掺杂部设置，所述第一有源图案与所述第二有源图案同层设置。
可选的，在本申请的一些实施例中，所述第一有源图案与所述第二有源图案的制备材料相同。
可选的，在本申请的一些实施例中，所述阻挡件与所述栅极同层设置。
可选的，在本申请的一些实施例中，所述阻挡件与所述栅极的制备材料相同。
可选的，在本申请的一些实施例中，所述第二电极、所述第一电极、所述源极、漏极同层设置。
可选的，在本申请的一些实施例中，所述显示面板还包括设置于所述钝化层上的第三电极，所述第三电极与所述源极连接，所述连接电极与所述第三电极同层设置。
可选的，在本申请的一些实施例中，所述第三电极为阳极，所述连接电极、所述阳极的制备材料为铜、银、锂、镱、镁、铝、铟、ITO、IZO、AZO中的至少一种。
可选的，在本申请的一些实施例中，所述显示面板还包括第四电极，所述第四电极设置于所述平坦层上，所述连接电极与所述第四电极同层设置。
可选的，在本申请的一些实施例中，第四电极为阴极，所述连接电极、所述阴极的制备材料为铜、银、锂、镱、镁、铝、铟、ITO、IZO、 AZO中的至少一种。
本申请实施例提供一种显示面板制备方法，包括：
提供一衬底；
在所述衬底上方制备得到有源层，所述有源层包括同层设置的第一有源图案和第二有源图案；
在所述有源层上方制备得到栅绝缘层、栅极层、层间绝缘层，所述栅极层包括栅极和阻挡件，所述栅极与所述第一有源图案对应设置，所述阻挡件与所述第二有源图案对应设置；
在所述层间绝缘层上方制备得到源极、漏极、第一电极、第二电极；
在所述源漏极层上方制备得到平坦层、连接电极，其中，所述源极、所述漏极、所述栅极构成薄膜晶体管器件，所述第一电极、所述第二电极、所述连接电极、所述第二有源图案构成感光器件。
可选的，在本申请的一些实施例中，在制备得到源极、漏极、第一电极、第二电极的步骤中还包括：在所述层间绝缘层上制备得到源漏极层，所述源漏极层包括同层设置的所述源极、所述漏极、所述第一电极、所述第二电极。
可选的，在本申请的一些实施例中，在制备得到所述栅极层的步骤中还包括：在所述衬底上方制备得到所述栅极层，所述栅极层包括同层设置的栅极和阻挡件，所述栅极与所述第一有源图案对应设置，所述阻挡件与所述第二有源图案对应设置，其中，所述阻挡件为环状结构。
有益效果
通过在感光器件内设置阻挡件，阻挡件在衬底上的正投影与第二本征部在衬底上的正投影重叠，使第二有源图案包括第二轻掺杂部、第二本征部、第二重掺杂部，第二本征部围绕第二轻掺杂部设置，第二重掺杂部围绕第二本征部设置，通过第二本征部降低感光器件的暗 态电流，提升灵敏度。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的显示面板的截面示意图；
图2是本申请实施例提供的显示面板内感光器件的俯视示意图；
图3是本申请实施例提供的显示面板制备方法的流程示意图；
图4A至图4G是本申请实施例提供的显示面板制备方法的截面示意图。
附图标记说明：
Figure PCTCN2022087682-appb-000001
Figure PCTCN2022087682-appb-000002
本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。此外，应当理解的是，此处所描述的具体实施方式仅用于说明和解释本申请，并不用于限制本申请。在本申请中，在未作相反说明的情况下，使用的方位词如“上”和“下”通常是指装置实际使用或工作状态下的上和下，具体为附图中的图面方向；而“内”和“外”则是针对装置的轮廓而言的。
在现有显示面板中，感光器件采用外挂的方式设置于所述显示面板外部，外挂的方式增加了制作的成本；而如何以较少的光罩数量，将感光器件集成于显示面板内部成为各面板厂商和终端厂商所公共关注的热点、重点。
因此，亟需一种能减少光罩数量、降低成本的显示面板，同时其内部集成有感光器件。
请参阅图1，本申请提供的显示面板包括衬底10、设置于所述衬底10上方的薄膜晶体管器件1和感光器件2，所述薄膜晶体管器件1包括设置于所述衬底10上方的第一有源图案401、栅极601、源极801、漏极802，所述第一有源图案401包括第一本征部4011、第一重掺杂部4012、第一轻掺杂部4013，所述感光器件2包括第一电极804、第二电极803、第二有源图案402、连接电极130，所述第二有源图案402包括第二本征部4021、第二重掺杂部4022、第二轻掺杂部4023，所述第二电极803与所述第二重掺杂部4022电连接，所述第一电极804与所述第二轻掺杂部4023电连接，其中，所述第一有源图案401与所述第二有源图案402同层设置。
本申请通过将感光器件2的第二有源图案402与薄膜晶体管器件1的第一有源图案401同层设置，减少了将感光器件2集成在显示面板内所需的光罩数量，降低了成本。
其中，所述感光器件2的阻挡件602、第一电极804、第二电极803、连接电极130均可以与所述薄膜晶体管器件1的现有膜层共用光罩制备得到；具体的，所述第二有源图案402与所述第一有源图案401可以同层设置，所述阻挡件602与所述栅极601可以同层设置，所述第一电极804、所述第二电极803与所述源极801、所述漏极802可以同层设置，所述连接电极130与所述第三电极120/第四电极100可以同层设置；此时，无需增加光罩即可将感光器件2集成于所述显示面板内。
其中，所述感光器件2可以为光感传感器，用于接收光信号，可用于无接触量测、指纹识别、环境光检测、通信等，通过集成感光器件2，丰富了显示面板的功能，增加了人机互动，提高显示面板的竞争力。
现结合具体实施例对本申请的技术方案进行描述。
本申请显示面板可以为OLED显示面板、也可以为液晶显示面板；下述主要以FFS液晶显示面板为例进行说明。
在一种实施例中，所述第一电极804、所述第二电极803、所述连接电极130、所述第二有源图案402构成垂直异质结结构。
其中，所述连接电极包括位于所述第二过孔H2内的所述第一部分、位于所述第三过孔H3内的所述第二部分以及连接所述第一部分和所述第二部分的第三部分，所述第一部分与所述第二轻掺杂部4023连接，所述第二部分与所述第一电极804连接，所述第一部分和所述第二部分分别沿膜厚方向设置。
在一种实施例中，所述接触面为所述垂直异质结结构的受光面，所述接触面的面积小于所述第二轻掺杂部4023朝向所述连接电极130一侧表面的面积。
在一种实施例中，所述显示面板可以为OLED显示面板，所述OLED显示面板包括衬底10、阵列层、平坦层90，以及设置于所述平坦层90上方的阳极、阴极。
其中，所述连接电极130可以与所述阳极或所述阴极同层设置。
可以理解的是，所述连接电极130可以与所述多个电极中的任一者共用同一光罩，无需额外增加光罩用于制备得到连接电极130，降低了成本。
请参阅图1、图2，在一些实施例中，所述显示面板可以为FFS液晶显示面板，所述液晶显示面板包括阵列基板，所述阵列基板包括衬底10、遮光层20、缓冲层30、有源层40、栅绝缘层50、栅极层、层间绝缘层70、源漏极层、平坦层90、第四电极100层、钝化层110、第三电极层。
其中，有源层40包括第一有源图案401和第二有源图案402；以第二有源图案402为例进行说明，所述第二有源图案402位于感光器件2内，所述第二有源图案402包括第二本征部4021、第二重掺杂部4022、第二轻掺杂部4023；其中，所述第二本征部4021为半导体，所述第二重掺杂部4022为导体；所述第二本征部4021的电阻值大于所述第二轻掺杂部4023的电阻值大于所述第二重掺杂部4022的电阻值；因此，通过阻挡件602阻挡N-离子轻掺杂，阻挡件602与第二本征部4021对应，可以使整体第二有源图案402的阻抗增加，从而降低感光器件2暗态电流，提升检测灵敏度；所述第一有源图案401与第二有源图案402相似，在此不再赘述。
可以理解的是，通过控制阻挡件602的阻挡面积，可以控制所述第二有源图案402中第二本征部4021的占比，从而进一步降低感光器件2暗态电流，提升检测灵敏度。
其中，所述栅极层可以包括同层设置的栅极601和阻挡件602。
其中，所述源漏极层可以包括同层设置的源极801、漏极802、第一电极804、第二电极803。
其中，可以所述第四电极100层包括同层设置的所述第四电极 100、所述连接电极130，也可以所述第三电极层包括同层设置的所述第三电极120、所述连接电极130。
在一种实施例中，所述遮光层20的膜层厚度范围为500埃至5000埃。
其中，其制备材料可以是Mo，Al，Cu，Ti或合金中的至少一种。
在一种实施例中，所述缓冲层30的厚度范围为1000埃至5000埃。
其中，所述缓冲层30为一层SiOx或一层SiNx或SiNx/SiOx叠层结构。
在一种实施例中，所述有源层40的制备材料包括poly-Si。
在一种实施例中，所述栅极绝缘层为一层SiOx或一层SiNx或SiNx/SiOx叠层结构，其厚度范围为1000埃至5000埃。
在一种实施例中，所述层间绝缘层70的制备材料包括SiOx、SiNx、SiON、金属氧化物中的至少一种。
其中，所述层间绝缘层70可以为SiNx/SiOx叠层结构。
在一种实施例中，所述源漏极层的制备材料包括Mo、Ti、Al、Cu、Ag、合金中的至少一种。
在一种实施例中，所述第二电极803通过第一过孔H1与所述第二重掺杂部4022连接，所述第一电极804通过第二过孔H2与所述连接电极130连接，所述连接电极130通过第三过孔H3与所述第二轻掺杂部4023连接，所述第二电极803、所述第一电极804、所述源极801、所述漏极802同层设置。
其中，所述第一电极804、所述第二电极803、所述连接电极130、所述第二有源图案402构成异质结垂直结构，通过异质结垂直结构增加了设计面积的自由度。
可以理解的是，所述感光器件2的接收光线的感光面积具有可自由调节的特性，其等于所述连接电极130与所述第二轻掺杂部4023的接触面积，通过控制所述第二轻掺杂部4023的表面积，可以调节所述感光面积的最大值；通过调节所述连接电极130与所述第二轻掺 杂部4023的接触面积，则可以调节所述感光面积的大小。
在一种实施例中，所述显示面板还包括设置于所述薄膜晶体管器件1上方的第三电极120，所述第三电极120与所述源极801/漏极802连接，所述连接电极130与所述第三电极120同层设置。
在一种实施例中，所述第二本征部4021围绕所述第二轻掺杂部4023设置，所述第二重掺杂部4022围绕所述第二本征部4021设置，在所述第二本征部4021上方设置有阻挡件602，所述阻挡件602与所述栅极601同层设置。
其中，所述阻挡件602可以为环状结构。
可以理解的是，通过增加阻挡件602遮挡，遮挡磷离子轻掺杂，阻挡件602下方对应形成所述第二本征部4021，所述第二本征部4021的电阻较所述第二轻/重掺杂部大，能降低器件的暗态电流，提升检测灵敏度。
在一种实施例中，所述阻挡件602为环状结构，所述阻挡件602在所述衬底10上的正投影与所述第二本征部4021在所述衬底10上的正投影重叠。
其中，所述阻挡件602与所述第二本征部4021对位设置。
在一种实施例中，所述连接电极130通过一接触面与所述第二轻掺杂部4023接触，所述接触面的面积小于所述第二轻掺杂部4023朝向所述连接电极130一侧表面的面积。
在一种实施例中，所述第一有源图案401与所述第二有源图案402的制备材料相同。
在一种实施例中，所述阻挡件602与所述栅极601的制备材料相同。
在一种实施例中，所述第一电极804、所述第二电极803与所述源极801、所述漏极802的制备材料相同。
在一种实施例中，所述连接电极130与所述第三电极120、所述第四电极100的制备材料相同。
其中，所述连接电极130、所述第三电极120、所述第四电极100 的制备材料为铜、银、锂、镱、镁、铝、铟、ITO、IZO、AZO中的至少一种。
请参阅图3，本申请实施例提供一种显示面板制备方法，包括：
S1：提供一衬底10；
S2：在所述衬底10上方制备得到有源层40，所述有源层40包括同层设置的第一有源图案401和第二有源图案402；
S3：在所述有源层40上方制备得到栅绝缘层50、栅极层、层间绝缘层70，所述栅极层包括栅极601和阻挡件602，所述栅极601与所述第一有源图案401对应设置，所述阻挡件602与所述第二有源图案402对应设置；
S4：在所述层间绝缘层70上方制备得到源极801、漏极802、第一电极804、第二电极803；
S5：在所述源漏极层上方制备得到平坦层90、连接电极130，其中，所述源极801、所述漏极802、所述栅极601构成薄膜晶体管器件1，所述第一电极804、所述第二电极803、所述连接电极130、所述第二有源图案402构成感光器件2。
在一些实施例中，所述显示面板制备方法为FFS液晶显示面板制备方法，所述FFS液晶显示面板包括阵列基板，请参阅图4A至图4G，为所述阵列基板制备方法。
具体的，在一种实施例中，请参阅图4A，提供衬底10，在所述衬底10上制备得到遮光层20。
具体的，在一种实施例中，请参阅图4B，在图4A的基础上，在所述衬底10、所述遮光层20上制备得到缓冲层30，在所述缓冲层30上制备一层a-Si，经过准分子激光退火之后，将a-Si转变为poly-Si，并采用曝光蚀刻方法制备得到有源层40，所述有源层40包括第一有源图案401和第二有源图案402，对第一有源图案401和第二有源图案402进行磷离子掺杂，制备得到第一有源图案401的第一重掺杂部4012和第二有源图案402的第二重掺杂部4022。
具体的，在一种实施例中，请参阅图4C，在图4B的基础上，在 所述缓冲层30、所述有源层40上制备得到栅绝缘层50，在所述栅绝缘层50上制备得到栅极层，所述栅极层包括栅极601和阻挡件602，通过栅极601和阻挡件602遮挡进行N-离子植入，制备得到第一有源图案401的第一轻掺杂部4013和第二有源图案402的第二轻掺杂部4023。
其中，通过增加环状阻挡件602对N-掺杂离子进行遮挡，降低了器件的暗态电流，提升了感光器件2的灵敏度。
具体的，在一种实施例中，请参阅图4D，在图4C的基础上，在所述栅绝缘层50、所述栅极层上制备得到层间绝缘层70，并对所述层间绝缘层70图案化得到第一过孔H1。
其中，所述多个过孔分别对应所述第一重掺杂部4012、第二重掺杂部4022。
其中，所述图案化得到第一过孔H1的步骤包括：通过曝光蚀刻方法得到所述第一过孔H1。
其中，所述层间绝缘层70可为SiNx/SiOx叠层结构。
具体的，在一种实施例中，请参阅图4E，在图4D的基础上，在所述层间绝缘层70上制备得到源漏极层，所述源漏极层包括同层设置的源极801、漏极802、第一电极804、第二电极803；其中，所述源极801/漏极802与所述第一重掺杂部4012分别通过两通孔连接，所述第二电极803与所述第二重掺杂部4022通过第一过孔H1连接。
具体的，在一种实施例中，请参阅图4F，在图4E的基础上，在所述层间绝缘层70、所述源漏极层上制备得到平坦层90，在所述平坦层90上制备得到第四电极100，在所述第四电极100、所述平坦层90上制备得到钝化层110；并对所述平坦层90、所述钝化层110图案化形成第二过孔H2、第三过孔H3。
其中，所述第二过孔H2的孔径可根据需求的感光面积进行适应性调节，增加了设计面积的自由度，当需要较大的感光面积时，所述第二过孔H2底面的面积等于或略小于所述第二轻掺杂部4023的上表面积；例如所述第二过孔H2底面的面积略小于所述第二轻掺杂部 4023的上表面积时，所述第二过孔H2底面的面积与所述第二轻掺杂部4023的上表面积的比值范围为0.85：1至1:1。
其中，所述平坦层90可以采用有机材料制备得到，也可以采用SINx、SiOx等无机绝缘层材料制备得到。
在本实施例中，所述第二过孔H2的孔径可根据需求的感光面积进行适应性调节，增加了感光面积设计的自由度。
具体的，在一种实施例中，请参阅图4G，在图4F的基础上，在所述钝化层110上制备得到第三电极层，所述第三电极层包括第三电极120和连接电极130。
其中，所述连接电极130与所述第二轻掺杂部4023通过所述第二过孔H2连接，所述连接电极130与所述第一电极804通过所述第三过孔H3连接。
在一种实施例中，连接电极130还可以与所述第四电极100同层制备得到，即在制备得到所述第四电极100时，同步采用同一光罩制备得到所述连接电极130。
在一种实施例中，在制备得到所述栅极层的步骤中还包括：在所述衬底10上方制备得到所述栅极层，所述栅极层包括同层设置的栅极601和阻挡件602，所述栅极601与所述第一有源图案401对应设置，所述阻挡件602与所述第二有源图案402对应设置，其中，所述阻挡件602为环状结构。
可以理解的是，通过将所述阻挡件602与所述栅极601用同一道光罩制备得到，可以节省一道光罩，减少光罩数量，降低成本。
在一种实施例中，在制备得到源极801、漏极802、第一电极804、第二电极803的步骤中还包括：在所述层间绝缘层70上制备得到源漏极层，所述源漏极层包括同层设置的所述源极801、所述漏极802、所述第一电极804、所述第二电极803。
可以理解的是，通过将所述第一电极804、所述第二电极803与所述源极801、所述漏极802用同一道光罩制备得到，可以进一步的节省一道光罩，减少光罩数量，降低成本。
在一种实施例中，还包括：在所述源漏极层上方制备得到一电极层，所述电极层包括同层设置的第三电极120和所述连接电极130，所述第三电极120通过一贯穿所述平坦层90的通孔与所述源极801/漏极802连接。
可以理解的是，通过将所述连接电极130与所述第三电极120用同一道光罩制备得到，可以更进一步的节省一道光罩，减少光罩数量，降低成本。
需要注意的是，优选的，当所述第二有源图案402与所述第一有源图案401共用一道光罩，所述阻挡件602与所述栅极601共用一道光罩，所述第一电极804、所述第二电极803与所述源极801、所述漏极802共用一道光罩，且所述连接电极130与所述第三电极120/第四电极100共用一道光罩时，将所述感光器件2集成于所述阵列基板或所述显示面板内时，无需额外增加光罩，实现了在不增加光罩、不增加工序的前提下，以更低的成本将感光器件2集成于显示面板内。
在一种实施例中，还包括：通过在显示面板内形成第一过孔H1、第二过孔H2、第三过孔H3，使所述第二电极803通过第一过孔H1与所述第二重掺杂部4022连接，使所述第一电极804通过第二过孔H2与所述连接电极130连接，使所述连接电极130通过第三过孔H3与所述第二轻掺杂部4023连接。
上述显示面板制备方法主要采用LTPS工艺举例说明，但本申请不限于LTPS工艺，也可用于a-Si、IGZO等工艺，可以不增加光罩数量实现感光器件2集成于所述显示面板内或所述阵列基板内。
本申请还提出了一种显示装置、一种显示模组，其中，所述显示模组可以包括上述FFS显示面板以及设置于所述FFS显示面板一侧的背板、胶框、光学膜片、导光板/扩散片等。所述显示装置也包括上述显示面板，此处不再赘述。
本申请实施例提供了一种显示面板，显示面板包括衬底、设置于所述衬底上方的薄膜晶体管器件和感光器件，所述薄膜晶体管器件包 括设置于所述衬底上方的第一有源图案、栅极、源极、漏极，所述第一有源图案包括第一本征部、第一重掺杂部、第一轻掺杂部，所述感光器件包括第一电极、第二电极、第二有源图案、连接电极，所述第二有源图案包括第二本征部、第二重掺杂部、第二轻掺杂部，所述第二电极与所述第二重掺杂部电连接，所述第一电极与所述第二轻掺杂部电连接，通过在感光器件内设置阻挡件，阻挡件在衬底上的正投影与第二本征部在衬底上的正投影重叠，使第二有源图案包括第二轻掺杂部、第二本征部、第二重掺杂部，第二本征部围绕第二轻掺杂部设置，第二重掺杂部围绕第二本征部设置，通过第二本征部降低感光器件的暗态电流，提升灵敏度。
优选的，所述感光器件的第一电极、第二电极与所述薄膜晶体管器件的源极、漏极同层设置，第一电极、第二电极、源极、漏极采用同一道光罩制备得到；所述感光器件的连接电极与所述薄膜晶体管器件上方的第三电极/第四电极同层设置，连接电极、第三电极/第四电极采用同一道光罩制备得到；所述感光器件的阻挡件与所述薄膜晶体管器件的栅极同层设置，所述阻挡件与所述栅极采用同一道光罩制备得到；因此，无需增加光罩即可将感光器件集成于显示面板内。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例所提供的一种显示面板、一种显示面板制备方法进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种显示面板，包括阵列基板，阵列基板包括：
    衬底；
    薄膜晶体管器件；
    感光器件，所述感光器件包括第一电极、第二电极、第二有源层、连接电极、阻挡件，所述第二有源图案包括第二本征部、第二重掺杂部、第二轻掺杂部，所述第二电极与所述第二重掺杂部电连接，所述第一电极通过所述连接电极与所述第二轻掺杂部电连接，所述连接电极与所述第二轻掺杂部接触；
    其中，所述阻挡件在所述衬底上的正投影与所述第二本征部在所述衬底上的正投影重叠，所述第二本征部围绕所述第二轻掺杂部设置，所述第二重掺杂部围绕所述第二本征部设置。
  2. 如权利要求1所述的显示面板，其中，所述显示面板还包括层间绝缘层、平坦层、钝化层，所述层间绝缘层设置于所述衬底上方，所述平坦层设置于所述层间绝缘层上方的，所述钝化层设置于所述平坦层上，所述第二电极通过第一过孔与所述第二重掺杂部连接。
  3. 如权利要求2所述的显示面板，其中，所述连接电极包括位于所述第二过孔内的所述第一部分、位于所述第三过孔内的所述第二部分以及连接所述第一部分和所述第二部分的第三部分，所述第一部分与所述第二轻掺杂部连接，所述第二部分与所述第一电极连接，所述第一部分和所述第二部分分别沿膜厚方向设置。
  4. 如权利要求3所述的显示面板，其中，所述第一电极、所述第二电极、所述连接电极、所述第二有源图案构成垂直异质结结构。
  5. 如权利要求4所述的显示面板，其中，所述连接电极与所述第二轻掺杂部接触的接触面的面积小于所述第二轻掺杂部朝向所述连接电极一侧表面的面积。
  6. 如权利要求5所述的显示面板，其中，所述第二过孔底面的面积与所述第二轻掺杂部的上表面积的比值范围为0.85：1至1:1。
  7. 如权利要求5所述的显示面板，其中，所述接触面为所述垂直异质结结构的受光面。
  8. 如权利要求3所述的显示面板，其中，所述阻挡件为环状结构。
  9. 如权利要求8所述的显示面板，其中，所述薄膜晶体管器件包括设置于所述衬底上方的第一有源图案、栅极、源极、漏极，所述栅极设置于所述第一有源图案上方，所述源极、所述漏极设置于所述栅极上方，所述第一有源图案包括第一本征部、第一重掺杂部、第一轻掺杂部，所述第一轻掺杂部围绕所述第一本征部设置，所述第一重掺杂部围绕所述第一轻掺杂部设置，所述第一有源图案与所述第二有源图案同层设置。
  10. 如权利要求9所述的显示面板，其中，所述第一有源图案与所述第二有源图案的制备材料相同。
  11. 如权利要求10所述的显示面板，其中，所述阻挡件与所述栅极同层设置。
  12. 如权利要求11所述的显示面板，其中，所述阻挡件与所述栅极的制备材料相同。
  13. 如权利要求9所述的显示面板，其中，所述第二电极、所述第一电极、所述源极、漏极同层设置。
  14. 如权利要求3所述的显示面板，其中，所述显示面板还包括设置于所述钝化层上的第三电极，所述第三电极与所述源极连接，所述连接电极与所述第三电极同层设置。
  15. 如权利要求14所述的显示面板，其中，所述第三电极为阳极，所述连接电极、所述阳极的制备材料为铜、银、锂、镱、镁、铝、铟、ITO、IZO、AZO中的至少一种。
  16. 如权利要求3所述的显示面板，其中，所述显示面板还包括第四电极，所述第四电极设置于所述平坦层上，所述连接电极与所述第四电极同层设置。
  17. 如权利要求16所述的显示面板，其中，第四电极为阴极， 所述连接电极、所述阴极的制备材料为铜、银、锂、镱、镁、铝、铟、ITO、IZO、AZO中的至少一种。
  18. 一种显示面板制备方法，其包括：
    提供一衬底；
    在所述衬底上方制备得到有源层，所述有源层包括同层设置的第一有源图案和第二有源图案；
    在所述有源层上方制备得到栅绝缘层、栅极层、层间绝缘层，所述栅极层包括栅极和阻挡件，所述栅极与所述第一有源图案对应设置，所述阻挡件与所述第二有源图案对应设置；
    在所述层间绝缘层上方制备得到源极、漏极、第一电极、第二电极；在所述层间绝缘层上方制备得到源极、漏极、第一电极、第二电极；
    在所述源漏极层上方制备得到平坦层、连接电极，其中，所述源极、所述漏极、所述栅极构成薄膜晶体管器件，所述第一电极、所述第二电极、所述连接电极、所述第二有源图案构成感光器件。
  19. 如权利要求18所述的显示面板制备方法，其中，在制备得到源极、漏极、第一电极、第二电极的步骤中还包括：在所述层间绝缘层上制备得到源漏极层，所述源漏极层包括同层设置的所述源极、所述漏极、所述第一电极、所述第二电极。
  20. 如权利要求18所述的显示面板制备方法，其中，在制备得到所述栅极层的步骤中还包括：在所述衬底上方制备得到所述栅极层，所述栅极层包括同层设置的栅极和阻挡件，所述栅极与所述第一有源图案对应设置，所述阻挡件与所述第二有源图案对应设置，其中，所述阻挡件为环状结构。
PCT/CN2022/087682 2022-04-08 2022-04-19 显示面板及其制备方法 WO2023193295A1 (zh)

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