WO2023189161A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2023189161A1
WO2023189161A1 PCT/JP2023/007747 JP2023007747W WO2023189161A1 WO 2023189161 A1 WO2023189161 A1 WO 2023189161A1 JP 2023007747 W JP2023007747 W JP 2023007747W WO 2023189161 A1 WO2023189161 A1 WO 2023189161A1
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Prior art keywords
region
trench
semiconductor device
layer
main surface
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English (en)
French (fr)
Japanese (ja)
Inventor
章太 泉
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Rohm Co Ltd
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Rohm Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/835—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] comprising LDMOS
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/83125—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] the IGFETs characterised by having shared source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment

Definitions

  • the present disclosure relates to a semiconductor device.
  • Patent Document 1 discloses a semiconductor device including a p-type region, a first p epitaxial region, an n-type buried region, a second p epitaxial region, and a DTI structure (deep trench isolation structure).
  • a first p-type epitaxial layer is formed on the p-type region.
  • the n-type buried region is formed over the first p epitaxial region.
  • the second p epitaxial region is formed over the n-type buried region.
  • the DTI structure surrounds a region where a high voltage lateral MOS transistor is formed in a plan view. The DTI structure passes through the second p-epitaxial region, the n-type buried region and the first p-epitaxial region to reach the p-type region.
  • An embodiment of the present disclosure provides a semiconductor device that can reduce the element area while suppressing a decrease in breakdown voltage.
  • a semiconductor device includes a chip having a main surface, a trench that defines a first region on one side and a second region on the other side of the chip in cross-sectional view, and a sidewall and a bottom of the trench. a plurality of trench insulation structures covering a wall, the plurality of trench insulation structures integral with each other; a drift region of a first conductivity type that provides a current path connecting the region and the second region.
  • FIG. 1 is a schematic plan view of a semiconductor device according to an embodiment of the present disclosure.
  • FIG. 2 is an enlarged view of the area surrounded by the two-dot chain line II in FIG.
  • FIG. 3 is a diagram showing a cross section taken along line III-III in FIG.
  • FIG. 4 is an enlarged view of the portion surrounded by the two-dot chain line IV in FIG.
  • FIG. 5 is an enlarged view of the main part of FIG. 4.
  • FIG. 6 is a diagram showing a flow of the manufacturing process of the semiconductor device.
  • FIG. 7A is a schematic cross-sectional view showing a part of the manufacturing process of the semiconductor device.
  • FIG. 7B is a diagram showing the next step after FIG. 7A.
  • FIG. 7C is a diagram showing the next step after FIG. 7B.
  • FIG. 7D is a diagram showing the next step after FIG. 7C.
  • FIG. 8 is a diagram showing a modification of the semiconductor device.
  • FIG. 1 is a schematic plan view of a semiconductor device 1 according to an embodiment of the present disclosure.
  • FIG. 2 is an enlarged view of the area surrounded by the two-dot chain line II in FIG.
  • FIG. 3 is a diagram showing a cross section taken along line III-III in FIG.
  • FIG. 4 is an enlarged view of the portion surrounded by the two-dot chain line IV in FIG.
  • FIG. 5 is an enlarged view of the main part of FIG. 4.
  • the semiconductor device 1 includes a rectangular parallelepiped-shaped semiconductor chip 2.
  • the semiconductor chip 2 is made of a Si (silicon) chip.
  • the semiconductor chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. are doing.
  • the first main surface 3 and the second main surface 4 are formed into a rectangular shape in a plan view (hereinafter simply referred to as "plan view") when viewed from the normal direction Z thereof.
  • the normal direction Z is also the thickness direction of the semiconductor chip 2.
  • the first side surface 5A and the second side surface 5B extend in a first direction ) is facing.
  • the third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X.
  • the semiconductor device 1 includes a p-type first layer 6 , a p-type or n-type second layer 7 , and an n-type third layer 8 formed in a semiconductor chip 2 .
  • the first layer 6 may also be referred to as a "base layer”.
  • the second layer 7 may also be referred to as a "device forming layer.”
  • the third layer 8 may also be referred to as a "buried layer.”
  • the first layer 6 , the second layer 7 and the third layer 8 may be considered as constituent elements of the semiconductor chip 2 .
  • the first layer 6 is formed in a region on the second main surface 4 side in the semiconductor chip 2, and forms part of the second main surface 4 and the first to fourth side surfaces 5A to 5D.
  • the first layer 6 may have a concentration gradient in which the p-type impurity concentration on the first main surface 3 side is lower than the p-type impurity concentration on the second main surface 4 side.
  • the first layer 6 may have a stacked structure including a high concentration layer and a low concentration layer stacked in this order from the second main surface 4 side.
  • the first layer 6 may have a thickness of, for example, 100 ⁇ m or more and 600 ⁇ m or less.
  • the first layer 6 may be made of a p-type semiconductor substrate (Si substrate).
  • the second layer 7 is formed in a region on the first main surface 3 side in the semiconductor chip 2, and forms part of the first main surface 3 and the first to fourth side surfaces 5A to 5D.
  • the conductivity type (n type or p type) of the second layer 7 is arbitrary and selected according to the specifications of the semiconductor device 1. In this embodiment, an example in which the second layer 7 has an n-type conductivity will be described, but this is not intended to limit the conductivity type of the second layer 7 to the n-type.
  • the second layer 7 may have a uniform n-type impurity concentration in the thickness direction, or may have an n-type impurity concentration gradient that increases toward the first main surface 3.
  • the second layer 7 may be made of an n-type epitaxial layer (Si epitaxial layer).
  • the third layer 8 is interposed in the region between the first layer 6 and the second layer 7 in the semiconductor chip 2, and forms part of the first to fourth side surfaces 5A to 5D of the semiconductor chip 2.
  • the third layer 8 forms a pn junction J at the boundary with the first layer 6. That is, in the semiconductor chip 2, in the middle part in the thickness direction between the first main surface 3 and the second main surface 4, there is a part extending in the horizontal direction along the first main surface 3 (orthogonal direction to the thickness direction).
  • a pn-junction portion J (a pn-junction portion) is formed.
  • the pn junction J may also be referred to as a "pn-connection portion" or "a pn-boundary portion.”
  • the third layer 8 has a higher n-type impurity concentration than the second layer 7.
  • the third layer 8 may have a concentration gradient in which the n-type impurity concentration on the first main surface 3 side is higher than the n-type impurity concentration on the second main surface 4 side.
  • the third layer 8 may have a thickness of, for example, 0.1 ⁇ m or more and 10 ⁇ m or less.
  • the third layer 8 may be made of an n-type epitaxial layer (Si epitaxial layer).
  • the semiconductor device 1 includes a plurality of element regions 9 provided on the first main surface 3 (second layer 7).
  • the plurality of element regions 9 are regions in which various functional elements are formed.
  • the plurality of element regions 9 are each partitioned inwardly of the first main surface 3 at intervals from the first to fourth side surfaces 5A to 5D in plan view.
  • the number, arrangement, and shape of the element regions 9 are arbitrary, and are not limited to a specific number, arrangement, and shape.
  • the plurality of functional elements may each include at least one of a semiconductor switching element, a semiconductor rectifying element, and a passive element.
  • Semiconductor switching elements include JFET (Junction Field Effect Transistor), MISFET (Metal Insulator Semiconductor Field Effect Transistor), BJT (Bipolar Junction Transistor), and IGBT (Insulated Gate Bipolar Junction Transistor (insulated gate bipolar transistor).
  • the semiconductor rectifying element may include at least one of a pn junction diode, a pin junction diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode.
  • Passive elements may include at least one of a resistor, a capacitor, an inductor, and a fuse.
  • the plurality of element regions 9 include at least one transistor region 9A. The structure of the transistor region 9A side will be specifically explained below.
  • the semiconductor device 1 includes an element isolation structure 10 that partitions a transistor region 9A on the first main surface 3.
  • the element isolation structure 10 defines transistor regions 9A having a predetermined shape in a plan view.
  • the element isolation structure 10 may also be referred to as a "trench electrode structure.”
  • element isolation structure 10 is formed in a band shape extending along transistor region 9A in plan view.
  • the element isolation structure 10 is formed into an annular shape (quadrangular annular shape in this embodiment) in plan view, and partitions a transistor region 9A having a predetermined shape (quadrangular shape in this embodiment).
  • the four corners of the element isolation structure 10 have a round shape that curves away from the transistor region 9A in plan view.
  • the planar shape of the element isolation structure 10 (the planar shape of the transistor region 9A) is arbitrary.
  • the element isolation structure 10 may be formed in a polygonal ring shape, a circular ring shape, or an elliptical ring shape in a plan view, and may partition a transistor region 9A having a polygonal shape, a circular shape, or an elliptical shape in a plan view.
  • element isolation structure 10 has a trench width W1.
  • the trench width W1 is a width in a direction perpendicular to the direction in which the element isolation structure 10 extends in plan view.
  • the trench width W1 may be 0.5 ⁇ m or more and 10 ⁇ m or less.
  • element isolation structure 10 is formed on first main surface 3 so as to penetrate pn junction J, and defines transistor region 9A on first main surface 3. Specifically, the element isolation structure 10 penetrates the second layer 7 and the third layer 8 to reach the first layer 6, and defines transistor regions 9A in the second layer 7. In this embodiment, the element isolation structure 10 extends from the first main surface 3 toward the second main surface 4 side so as to reach the first layer 6, and penetrates the second layer 7 and the third layer 8. .
  • the element isolation structure 10 includes an inner peripheral wall on the side of the transistor region 9A, an outer peripheral wall on the opposite side of the inner peripheral wall (the peripheral edge side of the semiconductor chip 2), and a bottom wall connecting the inner peripheral wall and the outer peripheral wall.
  • the element isolation structure 10 is electrically connected to the semiconductor chip 2 at the bottom wall and electrically insulated from the semiconductor chip 2 at the side walls (inner peripheral wall and outer peripheral wall). That is, the element isolation structure 10 has a lower end portion electrically connected to the semiconductor chip 2.
  • the element isolation structure 10 is electrically connected to the first layer 6 and electrically insulated from the second layer 7 and the third layer 8. In other words, the element isolation structure 10 is fixed at the same potential as the first layer 6.
  • the element isolation structure 10 includes an element isolation trench 13, an element isolation insulating film 14, and an element isolation electrode 15.
  • element isolation trench 13 is formed in an annular shape in plan view.
  • the width of the element isolation trench 13 may be the trench width W1 described above.
  • element isolation trench 13 is formed on the first main surface 3 side of semiconductor chip 2 so as to penetrate pn junction J. Specifically, the element isolation trench 13 penetrates through the second layer 7 and the third layer 8 to reach the first layer 6.
  • the element isolation trench 13 has an inner peripheral wall 16 on the side of the transistor region 9A, an outer peripheral wall 17 on the opposite side of the inner peripheral wall 16 (the peripheral edge side of the semiconductor chip 2), and a bottom wall 18 connecting the inner peripheral wall 16 and the outer peripheral wall 17.
  • the inner peripheral wall 16 and the outer peripheral wall 17 may be respectively referred to as an "inner wall” and an “outer wall", or a "first side wall” and a "second side wall”.
  • the element isolation insulating film 14 covers the inner peripheral wall 16 and outer peripheral wall 17 of the element isolation trench 13 so that the semiconductor chip 2 is exposed from the bottom wall 18 of the element isolation trench 13. Specifically, the element isolation insulating film 14 exposes the first layer 6 from the bottom wall 18 of the element isolation trench 13. It is preferable that the element isolation insulating film 14 covers the entire inner peripheral wall 16 and the entire outer peripheral wall 17 of the element isolation trench 13. The region where the bottom wall 18 of the element isolation trench 13 is exposed may be the contact hole 11 of the element isolation insulating film 14.
  • the element isolation insulating film 14 may include a silicon oxide film.
  • the element isolation insulating film 14 preferably includes a silicon oxide film made of an oxide of the semiconductor chip 2.
  • the element isolation electrode 15 is buried in the element isolation trench 13 with the element isolation insulating film 14 in between, and is electrically connected to the semiconductor chip 2 at the bottom wall 18 of the element isolation trench 13. Specifically, the element isolation electrode 15 is electrically connected to the first layer 6 through the contact hole 11 and is electrically insulated from the second layer 7 and the third layer 8 by the element isolation insulating film 14. There is.
  • element isolation electrode 15 includes conductive polysilicon.
  • the element isolation electrode 15 preferably includes conductive polysilicon of the same conductivity type as the first layer 6 (p-type in this embodiment).
  • the p-type impurity of the element isolation electrode 15 is preferably boron.
  • an element isolation contact 79 may be connected to the element isolation electrode 15. Thereby, the potential of the element isolation electrode 15 can be controlled via wiring (not shown).
  • the semiconductor device 1 further includes a sinker layer 12 formed on the second layer 7.
  • the sinker layer 12 extends in the depth direction of the element isolation trench 13 and is in contact with the third layer 8 and the element isolation insulating film 14 . More specifically, the sinker layer 12 is formed in an annular shape along the inner circumferential wall 16 and the outer circumferential wall 17 of the element isolation trench 13, and extends in the depth direction of the element isolation trench 13 as shown in FIG. The entire surface is in contact with the element isolation insulating film 14.
  • the sinker layer 12 may have a thickness of 0.5 ⁇ m to 5 ⁇ m in a direction perpendicular to the depth direction of the isolation trench 13.
  • a contact region 19 is formed at the end of the sinker layer 12 on the first main surface 3 side along the inner peripheral wall 16 . Contact region 19 is exposed from first main surface 3 . As shown in FIG. 2, the contact region 19 is formed linearly along a part of the element isolation trench 13 and is in contact with the element isolation insulating film 14.
  • the sinker layer 12 has the same conductivity type as the third layer 8, and is n-type in this embodiment. Contact region 19 similarly has the same conductivity type as third layer 8, which in this embodiment is n + type.
  • the impurity concentration of contact region 19 may be higher than that of sinker layer 12 .
  • semiconductor device 1 includes a planar gate MISFET 30 as an example of a functional element formed in transistor region 9A.
  • the MISFET 30 can be classified into HV (high voltage)-MISFET (for example, 100 V or more and 1000 V or less), MV (middle voltage)-MISFET (for example, 30 V or more and 100 V or less), and It can take the form of any one of LV (low voltage)-MISFETs (for example, 1V or more and 30V or less).
  • MISFET 30 includes a first trench isolation structure 20 and a second trench isolation structure 21 formed in transistor region 9A.
  • the first trench isolation structure 20 may be referred to as a shallow trench structure or an STI (shallow trench isolation) structure.
  • the first trench isolation structure 20 is formed in the second layer 7 at a distance from the third layer 8 in the thickness direction of the second layer 7 .
  • the first trench isolation structure 20 is formed along the periphery of the sinker layer 12 and is in contact with the sinker layer 12 .
  • the first trench isolation structure 20 surrounds the second trench isolation structure 21 in the second layer 7 .
  • First trench isolation structure 20 includes a shallow trench 22 and a buried insulator 23 .
  • the shallow trench 22 is formed on the first main surface 3.
  • the buried insulator 23 is buried in the shallow trench 22.
  • the second trench isolation structure 21 divides the transistor region 9A into an outer first region 24 and an inner second region 25.
  • the second trench isolation structure 21 is formed in an annular shape in plan view.
  • the inner region surrounded by the annular second trench isolation structure 21 is the second region 25, and the outer region surrounding the annular second trench isolation structure 21 is the first region 24.
  • second trench isolation structure 21 includes a trench 26 and a trench isolation structure 27.
  • the trench 26 is formed in an annular shape in plan view.
  • the width W2 of the trench 26 is the width in a direction perpendicular to the direction in which the second trench isolation structure 21 extends in plan view (see FIG. 2).
  • the width W2 of the trench 26 is larger than the trench width W1 and the width of the shallow trench 22.
  • the trench width W2 may be 20 ⁇ m or more and 100 ⁇ m or less.
  • the trench 26 is formed in the second layer 7 at a distance from the third layer 8 in the thickness direction of the second layer 7 . Trench 26 has a greater depth than shallow trench 22.
  • the trench 26 includes an inner peripheral wall 28 on the second region 25 side, an outer peripheral wall 29 on the opposite side of the inner peripheral wall 28 (the peripheral edge side of the semiconductor chip 2), and a bottom wall 31 connecting the inner peripheral wall 28 and the outer peripheral wall 29.
  • the inner peripheral wall 28 and the outer peripheral wall 29 may be respectively referred to as an "inner wall” and an “outer wall”, or a "first side wall” and a "second side wall”.
  • the trench insulation structure 27 includes a plurality of trench insulation structures 27 that integrally cover the peripheral walls 28, 29 and the bottom wall 31 of the trench 26.
  • the plurality of trench insulation structures 27 may be differentiated into individual trench insulation structures 27 by protrusions 34 formed on the bottom wall 31 of the trench 26 .
  • the protruding portion 34 protrudes upward from the lower end of the trench insulating structure 27 into the interior of the trench insulating structure 27 in the depth direction of the trench 26 .
  • the protrusion 34 is embedded in the trench insulation structure 27 .
  • a recess 35 corresponding to the shape of the protrusion 34 is formed at the lower end of the trench insulation structure 27 (see FIG. 5).
  • the protrusion 34 is formed in an annular shape along the circumferential direction of the annular trench 26 so as to overlap the trench insulation structure 27 in a plan view. Since the protrusion 34 is continuous over the entire circumference of the trench 26 in plan view, it may also be referred to as a "ring-shaped protrusion”. Therefore, the recess 35 corresponding to the shape of the protrusion 34 may be referred to as an "annular groove”.
  • a plurality of protrusions 34 are formed.
  • the plurality of protrusions 34 are formed concentrically in order from the inner circumferential wall 28 to the outer circumferential wall 29 of the trench 26 . That is, a plurality of protrusions 34 surrounding the second region 25 in plan view are formed.
  • the portions of the trench insulation structure 27 on the regions between adjacent projections 34 may each be an individual unit 36 of the trench insulation structure 27 .
  • Each individual unit 36 is formed vertically in the depth direction of the trench 26 from the bottom wall 31 of the trench 26 to the first main surface 3 .
  • the plurality of individual units 36 of the trench insulation structure 27 are not physically separated from each other, but are integrated in the horizontal direction along the first main surface 3. In other words, in this embodiment, the plurality of trench insulation structures 27 are not physically separated, but are conceptually distinguished by the plurality of protrusions 34.
  • Each individual unit 36 of the trench insulation structure 27 is formed along a buried line 37 extending upward in the depth direction of the trench 26 from the region between adjacent protrusions 34 .
  • the buried line 37 is an imaginary line extending upward from the center between adjacent protrusions 34, and is shown as a broken line in FIGS. 2 to 5.
  • the trench insulation structure 27 includes a first structure 38 and a second structure 39 as a plurality of individual units 36 .
  • the first structure 38 is unevenly distributed on the second region 25 side with respect to the central portion between the first region 24 and the second region 25.
  • the plurality of trench insulation structures 27 (six in FIG. 4) only the trench insulation structure 27 at the end on the second region 25 side is the first structure 38, and the rest are the second structures 39. be.
  • the second structure 39 is formed in a larger proportion on the first region 24 side than on the second region 25 side with respect to the central portion between the first region 24 and the second region 25 . Further, referring to FIG.
  • the first width W3 of the first structure 38 is larger than the second width W4 of the second structure 39.
  • the first width W3 and the second width W4 may be defined by the pitch between adjacent protrusions 34.
  • the width of the extreme trench insulation structure 27 may be the width between the peripheral walls 28, 29 of the trench 26 and the protrusion 34 closest to the peripheral walls 28, 29.
  • the number of the first structures 38 and the second structures 39 may be adjusted as appropriate depending on the breakdown voltage required of the semiconductor device 1. For example, if the semiconductor device 1 requires a high breakdown voltage, the number of first structures 38 and second structures 39 may be increased as much as possible.
  • trench insulation structure 27 includes a buried insulator 40 and a buried conductor 41.
  • the buried insulator 40 is an insulator portion of the trench insulation structure 27 and is integrated between the first structure 38 and the second structure 39.
  • embedded insulator 40 may include a first film portion 42 having relatively high density and a second film portion 43 having lower density than first film portion 42. good.
  • a clearly defined film interface may exist between the first film part 42 and the second film part 43 as shown in FIG. 5, or it may not exist as shown in FIG. good.
  • the denseness of the film can be compared, for example, by etching the first film part 42 and the second film part 43 with a common etching gas or etching solution, and based on the difference in etching rate at that time. For example, when the first film part 42 and the second film part 43 are etched with a common etching gas or etching solution, the etching rate of the first film part 42 having relatively high density is higher than that of the second film part 43. may be slower than the etching rate. Note that when the buried insulator 40 is made of silicon oxide, hydrofluoric acid (HF) can be used as a common etching gas.
  • HF hydrofluoric acid
  • the first film part 42 has a recess 44 extending in the depth direction of the trench 26, and the second film part 43 is formed along the inner wall of the recess 44.
  • a buried conductor 41 is embedded in the recess 44 .
  • the embedded conductor 41 is exposed on the first main surface 3.
  • Embedded conductor 41 is made of conductive polysilicon in this embodiment.
  • the embedded conductor 41 may have a shape that tapers at the upper part near the first main surface 3, as shown in FIG.
  • the first film part 42 has a recess 45 extending in the depth direction of the trench 26, and the second film part 43 is embedded in the recess 45.
  • the buried insulator 40 has a first portion 46 on the first region 24 side with respect to the buried conductor 41; A second portion 47 on the second region 25 side with respect to the buried conductor 41 may be included.
  • the thickness T1 of the first portion 46 may be larger than the thickness T2 of the second portion 47.
  • n-type drift region 48 is formed in the second layer 7 in the transistor region 9A.
  • Drift region 48 is formed along peripheral walls 28, 29 and bottom wall 31 of trench 26 so as to form a current path connecting first region 24 and second region 25.
  • Drift region 48 is in contact with buried insulator 40 throughout the depth direction of trench 26, as shown in FIG.
  • Drift region 48 may have a thickness of 0.5 ⁇ m to 5 ⁇ m in a direction perpendicular to the depth direction of trench 26.
  • the impurity concentration of the drift region 48 may be the same as the impurity concentration of the sinker layer 12.
  • drift region 48 is formed in an annular shape in plan view, and is exposed from first main surface 3 in both first region 24 and second region 25.
  • drift region 48 may branch from first main surface 3 toward the depth direction of trench 26.
  • a part of the second layer 7 may be sandwiched between the pair of drift regions 48 in a cross-sectional view.
  • a portion of the second layer 7 may be a protrusion 49 that protrudes into the second region 25 from a position below the trench 26 toward the first main surface 3 .
  • a drain region 50 is formed in the first region 24 at the end of the drift region 48 on the first main surface 3 side. Drain region 50 is electrically connected to drift region 48 . Drain region 50 is sandwiched between first trench isolation structure 20 and second trench isolation structure 21 . Drain region 50 is in contact with buried insulator 40 and buried insulator 23 . A drain contact region 51 is formed in the surface layer portion of the drain region 50 . Drain contact region 51 is exposed from first main surface 3 . Drain contact region 51 is formed linearly along a portion of trench 26, as shown in FIG. Drain region 50 has the same conductivity type as drift region 48, which in this embodiment is n-type. Drain contact region 51 similarly has the same conductivity type as drift region 48, which in this embodiment is n + type. The impurity concentration of drain contact region 51 may be higher than that of drain region 50.
  • a body region 52 is formed in the second region 25 at the end of the drift region 48 on the first main surface 3 side.
  • Body region 52 is electrically connected to drift region 48 .
  • Body region 52 is formed in an inner region of second region 25 spaced apart from second trench isolation structure 21 .
  • the body region 52 may be formed to cross the protrusion 49 between the pair of drift regions 48 in a cross-sectional view.
  • the body region 52 may form a pn junction with the protrusion 49.
  • a source region 53 and a body contact region 54 are formed in the surface layer of the body region 52 .
  • the source region 53 is formed at a distance from the outer peripheral edge of the body region 52 on the inner side.
  • source region 53 may have a rectangular shape that extends along the longitudinal direction of rectangular body region 52 and crosses from one end of body region 52 in the longitudinal direction to the other end in plan view. good.
  • Channel region 55 is formed between the outer periphery of body region 52 and the outer periphery of source region 53 in the surface layer portion of body region 52 .
  • body region 52 is p-type and source region 53 is n + type.
  • the body contact region 54 is formed in the center of the source region 53 and connected to the body region 52. Referring to FIG. 2, body contact region 54 may have a rectangular shape extending along the longitudinal direction of source region 53 and formed in an inner region of source region 53. Referring to FIG. In this embodiment, body contact region 54 is surrounded by source region 53 in plan view.
  • planar gate structure 56 is further formed in the second region 25.
  • planar gate structure 56 is formed on first main surface 3 so as to cover channel region 55, and controls whether channel region 55 is turned on or off.
  • the planar gate structure 56 is formed so as to span the source region 53 and the second trench isolation structure 21 .
  • Planar gate structure 56 may cover a portion of trench isolation structure 27 of second trench isolation structure 21 .
  • the planar gate structure 56 includes a gate insulating film 57 and a gate electrode 58 stacked in this order from the first main surface 3 side.
  • Gate insulating film 57 may include a silicon oxide film.
  • the gate insulating film 57 preferably includes a silicon oxide film made of an oxide of the semiconductor chip 2 .
  • gate electrode 58 may be formed in an annular shape in plan view.
  • gate electrode 58 includes conductive polysilicon.
  • Gate electrode 58 preferably includes n-type conductive polysilicon.
  • the n-type impurity of the gate electrode 58 is preferably phosphorus or arsenic.
  • the gate electrode 58 may have p-type conductivity. In this case, the p-type impurity of the gate electrode 58 is preferably boron.
  • an interlayer insulating film 59 is formed on the first main surface 3 so as to cover the planar gate structure 56.
  • Interlayer insulating film 59 is made of silicon oxide, for example.
  • a plurality of interconnections 60 to 62 are formed on the interlayer insulating film 59.
  • Each of the plurality of wirings 60 to 62 may include a drain wiring 60, a source wiring 61, and a field plate wiring 62.
  • the drain wiring 60 is connected to the drain contact region 51 via a drain contact 63 embedded in the interlayer insulating film 59.
  • Source wiring 61 is connected to source region 53 and body contact region 54 via source contact 64 embedded in interlayer insulating film 59 .
  • Field plate wiring 62 is connected to buried conductor 41 via field plate contact 65 buried in interlayer insulating film 59 . Therefore, embedded conductor 41 may be referred to as a field plate.
  • the potential of the buried conductor 41 may be greater than or equal to the potential of the source region 53 and less than or equal to the potential of the drain region 50. Further, by omitting field plate wiring 62 and field plate contact 65, buried conductor 41 may be in an electrically floating state.
  • FIG. 6 is a diagram showing the flow of the manufacturing process of the semiconductor device 1.
  • 7A to 7D are schematic cross-sectional views showing a part of the manufacturing process of the semiconductor device 1 in order of process.
  • a p-type semiconductor wafer (first layer 6) that will become the basis of the semiconductor chip 2 is prepared, and a semiconductor wafer 66 (see FIGS. 7A to 7D) is prepared.
  • a buried layer (third layer 8) and second layer 7 are formed (step S1).
  • an n-type impurity for example, phosphorus
  • the second layer 7 is formed on the first layer 6 by epitaxially growing silicon while introducing n-type impurities.
  • the n-type impurity implanted into the surface portion of the first layer 6 is diffused to both sides of the semiconductor wafer 66 in the thickness direction.
  • a third layer 8 (buried layer) is formed between the first layer 6 and the second layer 7.
  • the obtained semiconductor wafer 66 has the above-described first main surface 3 and second main surface 4.
  • a hard mask for example, silicon oxide
  • the second layer 7 and the third layer 8 are formed through the hard mask. selectively etched.
  • element isolation trenches 13 are formed, and transistor regions 9A are defined in the first layer 6 (step S2).
  • the bottom of the element isolation trench 13 is located in the middle of the third layer 8 in the thickness direction.
  • n-type impurities are selectively implanted into the inner walls (inner peripheral wall 16, outer peripheral wall 17, and bottom wall 18) of element isolation trench 13 and first main surface 3 of transistor region 9A.
  • the n-type impurity is implanted at a tilt angle ⁇ of 3° to 7° with respect to the normal n direction of the first main surface 3.
  • n-type impurities can be efficiently implanted into the inner peripheral wall 16 and outer peripheral wall 17 of the element isolation trench 13.
  • phosphorus (P) or the like can be used as the n-type impurity.
  • step S4 additional etching is performed on the element isolation trench 13 (step S4).
  • the element isolation trench 13 is further dug down, and the bottom wall 18 of the element isolation trench 13 reaches the first layer 6.
  • this additional etching step can be omitted.
  • the element isolation trench 13 may be formed by the etching process in step S2 so that the bottom wall 18 reaches the first layer 6.
  • element isolation insulating film 14 is formed on the inner walls (inner peripheral wall 16, outer peripheral wall 17, and bottom wall 18) of element isolation trench 13 (step S5).
  • the element isolation insulating film 14 is formed, for example, by thermal oxidation treatment. Due to the heat generated during the formation of the element isolation insulating film 14, the n-type impurities in the inner peripheral wall 16 and outer peripheral wall 17 of the element isolation trench 13 and the n-type impurity in the transistor region 9A are diffused, and the sinker layer 12 and the drift region 48 are formed. be done.
  • step S6 a portion of the element isolation insulating film 14 on the bottom wall 18 of the element isolation trench 13 is removed by etching. As a result, a contact hole 11 is formed. Next, the element isolation electrode 15 is embedded in the element isolation trench 13 (step S6).
  • a hard mask 67 is formed on the first main surface 3 of the semiconductor wafer 66 (step S7).
  • the hard mask 67 has a first opening 68 and a second opening 69 corresponding to the shapes of a main trench 71 and a subtrench 72, respectively, which will be described later.
  • a deep trench 70 is formed in the semiconductor wafer 66 (step S8). Deep trench 70 is formed in drift region 48 and has a bottom inside drift region 48 .
  • the first main surface 3 side of the semiconductor wafer 66 is partitioned into a first region 24 and a second region 25 by the deep trench 70 .
  • the deep trench 70 includes a plurality of annular deep trenches 70 that are arranged concentrically with each other and physically separated from each other.
  • the deep trench 70 includes a main trench 71 at the end of the second region 25 side, and a plurality of subtrenches 72 that are arranged outside the main trench 71 and have a width narrower than the main trench 71. It may also be a trench group 73.
  • FIG. 7A three sub-trenches 72 are formed outside the main trench 71.
  • the number of sub-trenches 72 may be adjusted according to the number of second structures 39 described above.
  • the width of main trench 71 may be, for example, 2.5 ⁇ m or more and 3 ⁇ m or less, and the width of sub-trench 72 may be, for example, 1 ⁇ m or more and 1.5 ⁇ m or less.
  • each semiconductor wall portion 74 is formed in a band shape along the circumferential direction of the trench group 73 in plan view, and forms a boundary between adjacent deep trenches 70 .
  • the thickness of the semiconductor wall portion 74 is preferably, for example, 1 ⁇ m or less. Thereby, the semiconductor wall portion 74 can be easily transformed into the insulator wall portion 76 in the next thermal oxidation step.
  • the semiconductor wafer 66 is subjected to thermal oxidation treatment.
  • the first insulating film 75 (first film portion 42) is formed on the bottom wall and side wall of the deep trench 70 (step S9).
  • the first insulating film 75 may also be referred to as a "thermal oxide film” or a "liner oxide film”.
  • the semiconductor wall portion 74 is oxidized from both sides of the adjacent deep trenches 70, thereby changing into an insulator and being formed as an insulator wall portion 76.
  • the insulator wall portion 76 may also be referred to as a boundary insulating film that forms a boundary between adjacent deep trenches 70 .
  • the insulator wall portion 76 is formed by altering the quality of the semiconductor wall portion 74, it may have the same thickness as the semiconductor wall portion 74.
  • the lower part of the semiconductor wall 74 is not partially transformed into an insulator, so that the inside and upper part of the insulator wall 76 is A protruding portion 34 is formed that protrudes toward the substrate.
  • an insulating material is deposited on the semiconductor wafer 66 by, for example, CVD.
  • the gas used in the CVD method may be, for example, TEOS (Tetra Ethyl Ortho Silicate) gas.
  • An insulating material backfills subtrench 72 and is deposited along the inner surface of main trench 71.
  • a buried insulating film 77 embedded in the recess 45 of the sub-trench 72 is formed, and a second insulating film 78 is formed along the inner surface of the recess 44 of the main trench 71 (step S10).
  • the buried insulating film 77 and the second insulating film 78 correspond to the second film portion 43 described above.
  • a conductive material is deposited on the semiconductor wafer 66 by, for example, CVD.
  • the conductive material is polysilicon in this embodiment.
  • the conductive material backfills the recess 44 of the main trench 71.
  • the buried conductor 41 is formed in the main trench 71 (step S11).
  • the next step is to form the MISFET 30 in the transistor region 9A.
  • a first trench isolation structure 20 STI
  • step S12 a first trench isolation structure 20
  • step S13 device structures such as the body region 52, drain region 50, source region 53, etc. are formed (step S13), and a planar gate structure 56 is formed.
  • the semiconductor wafer 66 is then divided into the size of each semiconductor chip 2. Thereafter, if necessary, the semiconductor chip 2 is bonded to a lead frame and sealed with a sealing resin, thereby obtaining the semiconductor device 1.
  • the drift region 48 is formed along the peripheral walls 28, 29 and the bottom wall 31 of the trench 26, and the depth direction of the trench 26 can be used as the drift region 48.
  • the horizontal source-drain distance along the first main surface 3 can be shortened by the depth of the trench 26.
  • the element area can be reduced, so that on-resistance can be lowered.
  • the drift region 48 along the peripheral walls 28, 2 of the trench 26 it is possible to prevent the total length of the drift region 48 from becoming short, thereby suppressing a decrease in breakdown voltage.
  • the electric field between the source and drain can be alleviated.
  • all trench insulation structures 27 may be first structures 38 including buried conductors 41.
  • the potential of the plurality of buried conductors 41 has a potential gradient that decreases in steps from the first region 24 to the second region 25 within the range of the potential difference between the drain region 50 and the source region 53. may be formed.
  • the first potential V1>the second potential V2>the third potential V3 may be satisfied.
  • the first conductivity type is n type and the second conductivity type is p type, but even if the first conductivity type is p type and the second conductivity type is n type, good.
  • the specific configuration in this case can be obtained by replacing the n-type region with a p-type region and replacing the p-type region with an n-type region in the above description and the accompanying drawings.
  • an example was described in which the n-type was expressed as the "first conductivity type” and the p-type was expressed as the "second conductivity type,” but these are changed in order to clarify the order of explanation.
  • the n-type may be expressed as the "second conductivity type” and the p-type may be expressed as the "first conductivity type.”
  • Appendix 1-4 The semiconductor device according to appendix 1-3, wherein at least one of the trench insulation structures includes a first structure including conductive polysilicon buried in a depth direction of the trench.
  • At least one of the trench insulation structures includes a second structure including a buried insulation film buried in the depth direction of the trench, Supplementary Note 1-4, wherein the second structure is formed in a larger proportion on the first region side than on the second region side with respect to a central portion between the first region and the second region.
  • Appendix 1-9 The semiconductor device according to any one of Appendixes 1-3 to 1-7 related to Appendix 1-2, wherein the conductive polysilicon is in an electrically floating state.
  • the plurality of trench insulation structures are any one of Supplementary notes 1-1 to 1-3, including a first structure having a first width and a second structure having a second width smaller than the first width.
  • the semiconductor device described in is any one of Supplementary notes 1-1 to 1-3, including a first structure having a first width and a second structure having a second width smaller than the first width.
  • Appendix 1-12 The semiconductor device according to Appendix 1-10 or Appendix 1-11, wherein the first structure includes conductive polysilicon embedded in an insulator.
  • the plurality of trench insulation structures form a potential gradient that decreases stepwise from the drain region side to the source region side in a range of potential difference between the drain region and the source region. 1-15.
  • Element region 9A Transistor region 10: Element isolation structure 11: Contact hole 12: Sinker layer 13: Element isolation trench 14: Element isolation insulating film 15: Element isolation electrode 16: Inner peripheral wall 17: Outer peripheral wall 18: Bottom wall 19: Contact region 20: First trench isolation structure 21: Second trench isolation structure 22: Shallow trench 23: Buried insulator 24: First region 25: Second region 26: Trench 27: Trench insulation structure 28 : Inner wall 29 : Outer wall 31 : Bottom wall 34 : Protrusion 35 : Recess 36 : Individual unit 37 : Embedded line 38 : First structure 39 : Second structure 40 : Embedded insulator 41 : Embedded conductor 42 : First Film part 43 : Second film part 44 : Re

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US20220140141A1 (en) * 2019-02-07 2022-05-05 Rohm Co., Ltd. Semiconductor device

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JP2005019614A (ja) * 2003-06-25 2005-01-20 Fuji Electric Device Technology Co Ltd 半導体装置の製造方法
JP2005303253A (ja) * 2004-03-18 2005-10-27 Fuji Electric Device Technology Co Ltd 半導体装置の製造方法
JP2006173357A (ja) * 2004-12-15 2006-06-29 Fuji Electric Device Technology Co Ltd 半導体装置およびその製造方法
JP2010080892A (ja) * 2008-09-29 2010-04-08 Rohm Co Ltd 半導体装置および半導体装置の製造方法

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JP2005019614A (ja) * 2003-06-25 2005-01-20 Fuji Electric Device Technology Co Ltd 半導体装置の製造方法
JP2005303253A (ja) * 2004-03-18 2005-10-27 Fuji Electric Device Technology Co Ltd 半導体装置の製造方法
JP2006173357A (ja) * 2004-12-15 2006-06-29 Fuji Electric Device Technology Co Ltd 半導体装置およびその製造方法
JP2010080892A (ja) * 2008-09-29 2010-04-08 Rohm Co Ltd 半導体装置および半導体装置の製造方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220140141A1 (en) * 2019-02-07 2022-05-05 Rohm Co., Ltd. Semiconductor device
US12100764B2 (en) * 2019-02-07 2024-09-24 Rohm Co., Ltd. Semiconductor device

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