WO2023178996A1 - 半导体结构及其制备方法、半导体器件 - Google Patents

半导体结构及其制备方法、半导体器件 Download PDF

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Publication number
WO2023178996A1
WO2023178996A1 PCT/CN2022/125123 CN2022125123W WO2023178996A1 WO 2023178996 A1 WO2023178996 A1 WO 2023178996A1 CN 2022125123 W CN2022125123 W CN 2022125123W WO 2023178996 A1 WO2023178996 A1 WO 2023178996A1
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dielectric layer
bit line
layer
substrate
node contact
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PCT/CN2022/125123
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English (en)
French (fr)
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陈晓鹏
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长鑫存储技术有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present disclosure relates to the technical field of semiconductor manufacturing, and in particular, to a semiconductor structure, a preparation method thereof, and a semiconductor device.
  • the part of the bit line structure that is not in contact with the active area is located above the substrate, and its bottom is wide, occupying the space of the storage node contact structure.
  • Such a structural shape is easy to be removed after pickling. , causing the remaining silicon nitride to recess into the bit line contact trench, so that during the process of forming the node contact hole, the plasma cannot gather to the side of the active area, resulting in the node contact hole being unable to open.
  • a semiconductor structure, a manufacturing method thereof, and a semiconductor device are provided.
  • the first aspect of the present disclosure proposes a semiconductor structure, including: a substrate, a bit line structure and a dielectric layer.
  • the substrate includes active regions and isolation structures arranged at intervals; the bit line structures are arranged in parallel and spaced rows.
  • the bit line structure includes a first part and a second part; the dielectric layer covers the upper surface and side surfaces of the bit line structure, and covers the upper surface of the substrate, wherein the top of the dielectric layer on the substrate near the bottom of the first part The surface is no lower than the top surface of the dielectric layer on the substrate near the bottom of the second part.
  • the first portion is located above and electrically connected to the active area, and the second portion is located above the isolation structure.
  • the semiconductor structure further includes: a node contact structure located between two adjacent bit line structures, penetrating the dielectric layer on the substrate, and electrically connected to the active area located below the node contact structure.
  • the node contact structure includes a conductive layer and the dielectric layer includes a silicon nitride layer.
  • a second aspect of the present disclosure provides a semiconductor device including the semiconductor structure in any of the preceding embodiments.
  • a third aspect of the present disclosure proposes a method for preparing a semiconductor structure, including: providing a substrate, including active regions and isolation structures arranged at intervals; and forming a plurality of parallel spaced rows on the substrate.
  • cloth bit line structure the bit line structure includes a first part and a second part; forming a dielectric layer, the dielectric layer covers the surface of the bit line structure, and covers the upper surface of the substrate; forming a protective layer, the protective layer covers the surface of the dielectric layer ;Remove part of the dielectric layer located on the sidewall of the bit line structure; remove part of the dielectric layer on the substrate so that the top surface of the remaining dielectric layer on both sides of the bottom of the first part is not lower than the top surface of the remaining dielectric layer on both sides of the bottom of the second part noodle.
  • the first portion is located above and electrically connected to the active area, and the second portion is located above the isolation structure.
  • removing part of the dielectric layer located on the sidewall of the bit line structure includes: removing the protective layer located on the side wall of the bit line structure; using a trimming etching process to remove part of the dielectric layer located on the side wall of the bit line structure; passing through cleaning gas, cleaning the resulting structure.
  • the purge gas includes an inert gas.
  • removing the protective layer and part of the dielectric layer on the substrate includes: removing the protective layer above the substrate; etching the dielectric layer on the substrate using a directional etching process to remove part of the dielectric layer, so that the first part The top surface of the remaining dielectric layer on both sides is higher than or flush with the top surface of the remaining dielectric layer on both sides of the second part.
  • the directional etching process includes a plasma directional etching process.
  • the dielectric layer includes a silicon nitride layer
  • the protective layer includes a photoresist layer
  • the method further includes: forming node contact holes between adjacent bit line structures, and the node contact holes expose the active area.
  • forming a node contact hole between adjacent bit line structures includes: forming a filling layer, the filling layer fills the gap between the adjacent bit line structures, and the top surface of the filling layer is in contact with the top surface of the bit line structure. The surface is flush; an opening is formed in the filling layer, and the opening penetrates the filling layer to expose the upper surface of the substrate; a node contact hole is formed to expose the active area.
  • the method before forming the node contact hole, further includes: removing the protective layer on top of the bit line structure; and forming sidewall structures on opposite sides of the bit line structure.
  • forming a node contact hole between adjacent bit line structures includes: forming a filling layer, the filling layer fills the gap between the adjacent bit line structures, and the top surface of the filling layer is in contact with the top surface of the bit line structure. The surface is flush; an opening is formed in the filling layer, and the opening penetrates the filling layer to expose part of the upper surface of the dielectric layer; a node contact hole is formed to expose the active area.
  • the node contact hole after forming the node contact hole, it further includes: forming a node contact structure in the node contact hole, and the node contact structure is electrically connected to the active area.
  • Embodiments of the present disclosure may/at least have the following advantages:
  • the top surface of the dielectric layer near the bottom of the first part is higher than or flush with the top surface of the dielectric layer near the bottom of the second part, it can be used in subsequent processes.
  • the etching process will not be biased to both sides of the first part and the node contact hole will not be able to expose the active area, which provides greater controllability and process window for the etching process of the node contact hole. , which solves the problem that the node contact hole cannot be opened.
  • the semiconductor structure, its preparation method, and the semiconductor device provided by the embodiments of the present disclosure can prevent the etching process from being biased to both sides of the first part when the node contact hole is formed in the subsequent process, resulting in the node contact hole being unable to be exposed. out of the active area, providing greater controllability and process window for the etching process of node contact holes, and solving the problem that node contact holes cannot be opened.
  • Figure 1 is a schematic cross-sectional structural diagram of a semiconductor structure in an embodiment of the present disclosure
  • Figure 2 is a top view of the semiconductor structure shown in Figure 1;
  • Figure 3 is a schematic cross-sectional structural diagram of a semiconductor structure in another embodiment of the present disclosure.
  • Figure 4 is a schematic cross-sectional structural diagram of a semiconductor structure in yet another embodiment of the present disclosure.
  • Figure 5 is a flow chart of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure
  • FIG. 6 is a schematic cross-sectional view of a semiconductor structure after a bit line structure is formed on a substrate in an embodiment of the present disclosure
  • FIG. 7 is a schematic cross-sectional view of a semiconductor structure after forming a dielectric layer in an embodiment of the present disclosure
  • Figure 8 is a schematic cross-sectional view of a semiconductor structure after forming a protective layer in an embodiment of the present disclosure
  • Figure 9 is a schematic cross-sectional structural diagram of the semiconductor structure after removing part of the dielectric layer on the sidewall of the bit line structure in an embodiment of the present disclosure
  • Figure 10a is a schematic cross-sectional structural diagram of a semiconductor structure after directional etching of a dielectric layer on a substrate in an embodiment of the present disclosure
  • Figure 10b is a schematic cross-sectional structural diagram of a semiconductor structure after directional etching of a dielectric layer on a substrate in another embodiment of the present disclosure
  • FIG. 11 is a schematic cross-sectional view of the semiconductor structure after removing the protective layer on top of the bit line structure in an embodiment of the present disclosure
  • FIG. 12 is a schematic cross-sectional view of the semiconductor structure after the sidewall structure is formed in an embodiment of the present disclosure
  • Figure 13 is a schematic cross-sectional view of a semiconductor structure after forming a filling layer in an embodiment of the present disclosure
  • FIG. 14 is a schematic cross-sectional view of the semiconductor structure after forming openings in the filling layer according to an embodiment of the present disclosure
  • FIG. 15 is a schematic cross-sectional view of the semiconductor structure after node contact holes are formed in an embodiment of the present disclosure
  • FIG. 16 is a schematic cross-sectional structural diagram of a semiconductor structure after forming a node contact structure in an embodiment of the present disclosure.
  • the part of the bit line structure that is not electrically connected to the active area is located above the substrate, and its bottom is wider, occupying the space of the storage node contact structure.
  • Such a structural topography is easy to change after pickling. , causing the remaining silicon nitride to recess into the bit line contact trench, so that during the process of forming the node contact hole, the plasma cannot gather to the active area side, resulting in the node contact hole being unable to open, and the final node contact structure formed There is no electrical connection to the active area.
  • one embodiment of the present disclosure discloses a semiconductor structure, as shown in FIG. 1 , including a substrate 10, a bit line structure 20 and a dielectric layer 30.
  • the substrate 10 includes active regions arranged at intervals. 11 and the isolation structure 12.
  • the bit line structures 20 are arranged in parallel and spaced apart on the substrate 10.
  • the bit line structure 20 includes a first part 21 and a second part 22; the dielectric layer 30 covers the upper surface and side surfaces of the bit line structure 20, and covers The upper surface of the substrate 10 , wherein the top surface of the dielectric layer 30 on the substrate 10 near the bottom of the first part 21 is not lower than, for example, higher than or flush with the top surface of the dielectric layer 30 on the substrate 10 near the bottom of the second part 22 .
  • the top surface of the dielectric layer 30 near the bottom of the first part 21 is higher or flush with the top surface of the dielectric layer 30 near the bottom of the second part 22, which can make the etching process easier when the node contact hole is formed in the subsequent process. It will not be biased to both sides of the first part 21 so that the node contact hole cannot expose the active area 11, which provides greater controllability and process window for the etching process of the node contact hole, and solves the problem that the node contact hole cannot be opened. The problem.
  • the substrate 10 includes active areas 11 and isolation structures 12 arranged in an array, and the active areas 11 are located between adjacent isolation structures 12.
  • the isolation structure 12 includes a horizontal portion 121 covering the upper surface of the active area 11 .
  • FIG. 2 is a top view of the semiconductor structure shown in FIG. 1 .
  • the bit line structure 20 is arranged in parallel on the substrate 10 and includes a first part 21 and a second part 22 .
  • the first part 21 is located in the bit line contact trench 23, and the bit line contact trench 23 exposes the upper surface of the active area 11, so that the first part 21 is electrically connected to the active area 11;
  • the second part 22 is located in the isolation structure 12 Above the horizontal portion 121 of the isolation structure 12 , the second portion 22 of the bit line structure 20 is isolated from the active area 11 .
  • the first bit line structure and the second bit line structure are two adjacent bit line structures 20.
  • the first part 21 of the first bit line structure and the second bit line can be cut along the direction AA' in Figure 2
  • a schematic cross-sectional structure is obtained as shown in Figure 1 .
  • the bit line structure 20 may include a bit line conductive layer (not shown in the figure) and a bit line insulating layer (not shown in the figure) stacked in sequence from bottom to top.
  • the bit line conductive layer includes a polysilicon layer, a barrier metal layer and a conductor metal layer stacked in sequence from bottom to top.
  • the bit line conductive layer includes a conductive metal layer and a barrier metal layer wrapping the bottom and side surfaces of the conductive metal layer.
  • the conductive metal layer can be, for example, a tungsten layer or a copper layer; the barrier metal layer, for example, can be a titanium layer or a titanium nitride layer.
  • the bit line insulation layer may be a nitride layer, such as a silicon nitride layer.
  • the dielectric layer 30 covers the upper surface of the substrate 10 and the upper surface and side surfaces of the bit line structure 20 , and fills the bit line contact trench 23 .
  • the dielectric layer 30 may include, but is not limited to, a silicon nitride layer.
  • the dielectric layer 30 on both sides of the bottom of the first part 21 on the substrate 10 is flush with the top surface of the dielectric layer 30 on both sides of the bottom of the second part 22 .
  • the top surface of the dielectric layer 30 on both sides of the bottom of the first part 21 on the substrate 10 may be higher than the dielectric layer on both sides of the bottom of the second part 22 on the substrate 10 .
  • the semiconductor structure further includes a node contact structure 40 located between two adjacent bit line structures 20 .
  • the node contact structure 40 penetrates the dielectric layer 30 on the substrate 10 and the top of the substrate 10 , and is electrically connected to the active area 11 located below the node contact structure 40 .
  • the node contact structure 40 may include a material layer with better electrical conductivity, such as a polysilicon layer or a metal layer.
  • spacer structures 60 are also provided on both sides of the bit line structure 20 , as shown in FIG. 4 .
  • the spacer structure 60 may include a first insulating layer 61 and a second insulating layer 62, wherein the first insulating layer 61 is located on opposite sides of the bit line structure 20, and the second insulating layer covers the bit line structure 20 and the first insulating layer. Layer 61.
  • the first insulating layer 61 may be a high-dielectric material layer with a dielectric constant greater than 3.9, such as a silicon dioxide layer, and the second insulating layer 62 may be an insulating protective layer 50 with relatively high hardness, such as a silicon nitride layer.
  • An embodiment of the present disclosure also discloses a semiconductor device, including the semiconductor structure in any of the foregoing embodiments.
  • the semiconductor device may be a DRAM memory, or any other semiconductor device including the node contact structure 40 .
  • the semiconductor structure in any of the above embodiments to a DRAM memory, the situation that the node contact hole cannot be opened can be greatly improved, so that the node contact structure 40 in the array area and the active area 11 have good electrical connection, and the product yield is improved.
  • one embodiment of the present disclosure also discloses a method for preparing a semiconductor structure, including:
  • S10 Provide a substrate 10, which includes active regions 11 and isolation structures 12 arranged at intervals; a plurality of bit line structures 20 arranged in parallel and spaced apart are formed on the substrate 10, and the bit line structures 20 include a first part 21 and Part II 22;
  • S20 Form a dielectric layer 30, which covers the surface of the bit line structure 20 and the upper surface of the substrate 10;
  • S50 Remove part of the dielectric layer 30 on the substrate 10 so that the top surface of the remaining dielectric layer 30 on both sides of the bottom of the first part 21 is higher than or flush with the top surface of the remaining dielectric layer 30 on both sides of the bottom of the second part 22.
  • the dielectric layer 30 can be thinned step by step; wherein, the dielectric layer 30 on both sides of the bottom of the bit line structure 20 is thinned.
  • the top surface of the remaining dielectric layer 30 on both sides of the bottom of the first part 21 is controlled to be higher than or flush with the top surface of the remaining dielectric layer 30 on both sides of the bottom of the second part 22, so that it is easier to form the node contact hole. Opening exposes the active area 11 in the substrate 10 and improves the difficulty of opening the node contact hole.
  • the substrate 10 in step S10 includes spaced apart isolation structures 12 and active regions 11 .
  • the material of the isolation structure 12 may include, but is not limited to, silicon oxide, silicon nitride, etc., and the substrate 10 may include, but is not limited to, the silicon substrate 10 .
  • the isolation structure 12 also includes a horizontal portion 121 located above the active area 11 and covering the upper surface of the active area 11 .
  • bit line contact trench 23 is formed in the horizontal portion 121 of the isolation structure 12 , and the bit line contact trench 23 exposes the upper surface of the active region 11 .
  • the first part 21 of the bit line structure 20 is located in the bit line contact trench 23 and is electrically connected to the active area 11 ; the second part 22 of the bit line structure 20 is located outside the bit line contact trench 23 and is located at the horizontal part of the isolation structure 12 121 on.
  • the bit line structure 20 may include a bit line conductive layer and a bit line insulating layer sequentially stacked from bottom to top.
  • the bit line conductive layer may include a conductive metal layer and a barrier metal layer wrapping the bottom and side surfaces of the conductive metal layer.
  • the wire metal layer can be made of a metal conductive material with low resistivity, such as W (tungsten), molybdenum (Mo), Ti (titanium), Cu (copper) or Au (gold).
  • W tungsten
  • Mo molybdenum
  • Ti titanium
  • Cu copper
  • Au gold
  • chemical vapor phase can be used The deposition process forms the bit line conductive layer.
  • the barrier metal layer may be made of a material layer that has a good blocking effect on metals and semiconductor materials, such as a titanium nitride layer, a cobalt layer, a platinum layer or a titanium tungsten layer.
  • the barrier metal layer also needs to be highly conductive and have good adhesion between the semiconductor and the metal.
  • the barrier metal layer may be formed using a chemical vapor deposition process, an atomic layer deposition process, a plasma vapor deposition process, or a rapid thermal oxidation process.
  • the bit line insulation layer may be a nitride layer, such as silicon nitride.
  • the materials for making each of the above layers can also be selected according to actual conditions, and are not limited by this disclosure.
  • a dielectric layer 30 is formed to cover the surface of the bit line structure 20 and the upper surface of the substrate 10 .
  • dielectric layer 30 fills bit line contact trench 23.
  • the material of the dielectric layer 30 may include but is not limited to a nitride layer, such as a silicon nitride layer.
  • the dielectric layer 30 may be formed on the surface of the bit line structure 20 and the upper surface of the substrate 10 using a chemical vapor deposition process, an atomic layer deposition process or a plasma vapor deposition process.
  • a protective layer 50 is formed on the surface of the dielectric layer 30.
  • the protective layer 50 can be used to protect the dielectric layer 30 in a specific area from being etched.
  • the protective layer 50 may be a photoresist layer.
  • the steps of forming a photoresist layer on the surface of the dielectric layer 30 may include: placing the wafer with the semiconductor structure on a heating plate and baking it at 180 to 250°C for 30 to 80 seconds; Buffer cooling at °C for 15 to 60 seconds; place the wafer on the rapid cooling plate for rapid cooling; form a photoresist layer on the wafer.
  • the dielectric layer 30 can be thinned in stages and in different regions. For example, only the protective layer 50 on the surface of the area to be etched is removed, and then the area to be etched can be etched and removed.
  • the protective layer 50 may be a photoresist layer.
  • step S40 part of the dielectric layer 30 located on the sidewall of the bit line structure 20 is removed to obtain the structure shown in FIG. 9 .
  • specific steps include:
  • S42 Use a trim etching process to remove part of the dielectric layer 30 located on the sidewall of the bit line structure 20.
  • the protective layer 50 is a photoresist layer and the dielectric layer 30 is a silicon nitride layer.
  • the photoresist layer located on the side wall of the bit line structure 20 can be removed first to expose the silicon nitride layer located on the side wall of the bit line structure 20; then a trim etch process (trim etch) is used to etch the silicon nitride layer. Reduce the thickness of the silicon nitride layer. Since the top of the bit line structure 20 and the top of the dielectric layer 30 on the substrate 10 are still covered by the photoresist layer, the trim etching process does not affect the thickness of the silicon nitride layer at these two locations.
  • the cleaning gas is introduced to clean up the by-products of the trimming and etching process.
  • the surface of the semiconductor structure can be cleaned by a cleaning device.
  • the cleaning device may include, for example, a gas purging unit and a gas suction unit.
  • the cleaning device is installed outside the process chamber.
  • the cleaning gas can be introduced into the process chamber through the gas purging unit to purge the by-products remaining on the surface of the semiconductor structure.
  • the gas suction unit is opened to start pumping and exhausting.
  • the wind sucks out the particles suspended in the process chamber.
  • Purge gases include, but are not limited to, inert gases.
  • the cleaning gas may be at least one of nitrogen, helium (He), neon (Ne), argon (Ar), krypton (Kr) or xenon (Xe).
  • the dielectric layer 30 on the upper surface of the substrate 10 can be protected from the influence of the trim etching process; and, after the trim etching process is used to thin the dielectric layer 30 on the sidewalls of the bit line structure 20, the dielectric layer 30 on the upper surface of the substrate 10 can be protected. Injecting the cleaning gas to remove the by-products produced by the trimming etching process can prevent the residues from affecting the subsequent etching process.
  • step S50 the step of removing part of the dielectric layer 30 on the substrate 10 includes:
  • S52 Use a directional etching process to etch the dielectric layer 30 on the substrate 10, and remove part of the dielectric layer 30, so that the top surface of the remaining dielectric layer 30 on both sides of the first part 21 is higher than or flush with the two sides of the second part 22.
  • the top surface of the dielectric layer 30 remaining on the side is shown in Figure 10a or Figure 10b.
  • the directional etching process may include, but is not limited to, a plasma directional etching process.
  • a plasma directional etching process is used to control the directional plasma to bombard the dielectric layer 30 on the upper surface of the substrate 10 to reduce the thickness of the dielectric layer 30 .
  • the plasma directional etching process can directionally adjust the etching degree of different areas of the dielectric layer 30 and adjust the height of different locations of the dielectric layer 30 .
  • the dielectric layer 30 is a silicon nitride layer.
  • the silicon nitride layer on both sides of the bottom of the first part 21 and the silicon nitride layer on both sides of the second part 22 can be etched to the same extent, so that the thinned silicon nitride layer has a smooth surface.
  • the etching process will not be biased to both sides of the bottom of the first part 21 , so that the formed node contact holes can smoothly The active area 11 underneath the second part is exposed.
  • the silicon nitride layer on both sides of the bottom of the second part 22 may be etched to a greater extent, and the silicon nitride layer on both sides of the bottom of the first part 21 may be etched to a smaller extent. Etch so that the top surface of the silicon nitride layer on both sides of the bottom of the first part 21 is higher than the top surface of the silicon nitride layer on both sides of the bottom of the second part 22, as shown in Figure 10b.
  • the etching process may be biased toward the dielectric layer 30 on both sides of the bottom of the second part 22 , so that the formed node contact hole can more easily expose the active area 11 under the second part 22 .
  • the dielectric layer 30 on both sides of the bottom of the bit line structure 20 can be directionally corrected, so that when the node contact hole is etched to form the node contact hole in the subsequent process, the plasma can be Leading more to the active area 11 ensures that the node contact hole can be opened, thereby increasing the controllability and process window of the etching process.
  • the method further includes:
  • S60 Form node contact holes between adjacent bit line structures 20, and the node contact holes expose the active area 11.
  • it also includes:
  • S62 Form sidewall structures 60 on opposite sides of the bit line structure 20, as shown in Figure 12.
  • the spacer structure 60 may include a first insulating layer 61 and a second insulating layer 62, wherein the first insulating layer 61 is located on opposite sides of the bit line structure 20, and the second insulating layer covers the bit line structure 20 and the first insulating layer.
  • Layer 61 may include a first insulating layer 61 and a second insulating layer 62, wherein the first insulating layer 61 is located on opposite sides of the bit line structure 20, and the second insulating layer covers the bit line structure 20 and the first insulating layer.
  • the process steps of forming the spacer structure 60 include:
  • S621 Form the first insulating layer 61 on two opposite sides of the bit line structure 20.
  • a first insulating material layer may be formed on the surface of the remaining dielectric layer 30 .
  • the first insulating material layer may be a high dielectric material layer with a dielectric constant greater than 3.9, such as a silicon dioxide layer.
  • the first insulating material layer located on the upper surface of the dielectric layer 30 is removed to obtain the first insulating layer 61 located on opposite sides of the bit line structure.
  • the process of forming the first insulating material layer may include, but is not limited to, a chemical vapor deposition process, an atomic layer deposition process, a plasma vapor deposition process, or a rapid thermal oxidation process.
  • S622 Form the second insulation layer 62 to cover the top surface of the bit line structure 20 and the first insulation layer 61.
  • a second insulating material layer may be formed on the surface of the resulting structure to cover the first insulating layer 61 and the upper surface of the dielectric layer 30, and then the second insulating material layer above the dielectric layer 30 on the surface of the substrate 10 is removed, A second insulating layer 62 covering the bit line structure 20 and the first insulating layer 61 is formed.
  • the second insulating material layer may be an insulating protective layer with relatively high hardness, such as a silicon nitride layer.
  • the step of forming node contact holes 41 between adjacent bit line structures 20 includes:
  • filling layer 70 may include, but is not limited to, a silicon dioxide layer.
  • a deposition process may be used to form a silicon dioxide layer in the gaps between the bit line structures 20 .
  • the silicon dioxide layer fills the gaps and covers the upper surface of the bit line structures 20 .
  • the upper surface of the silicon dioxide layer is polished using a chemical mechanical polishing process until the top of the bit line structure 20 is exposed to obtain the filling layer 70 .
  • the filling layer 70 may also be a layer of other materials different from the material of the second insulating layer 62 .
  • S64 Form an opening 71 in the filling layer 70.
  • the opening 71 penetrates the filling layer 70 and exposes part of the upper surface of the dielectric layer 30, as shown in FIG. 14.
  • a patterned photoresist layer may be first formed on the top surface of the resulting structure, and the pattern in the patterned photoresist layer defines the position and size of each opening 71 . Then, an etching process is used to etch the filling layer 70 based on the patterned photoresist layer, forming an opening 71 in the filling layer 70 to expose part of the upper surface of the dielectric layer 30 .
  • the dielectric layer 30 is a silicon nitride layer, and gas for etching silicon nitride can be added during the etching process to ensure that the silicon nitride layer can be opened. After the dielectric layer 30 is opened, etching continues downward to expose the active region 11 .
  • the dielectric layer 30 on both sides of the bottom of the first part 21 and the dielectric layer 30 on both sides of the second part 22 are directionally etched to reduce the thickness of the dielectric layer 30 while controlling the realization of the first part 21
  • the height of the dielectric layer 30 on both sides of the bottom is equal to or greater than the height of the dielectric layer 30 on both sides of the second part 22, so that when the node contact hole 41 is formed, the node contact hole 41 can be opened relatively easily to expose the active area 11 and solve the problem. This solves the problem that the node contact hole 41 cannot be opened due to space occupied by the bit line structure 20 .
  • the node contact hole 41 after forming the node contact hole 41 , it also includes forming a node contact structure 40 in the node contact hole 41 , and the node contact structure 40 is electrically connected to the active area 11 , as shown in FIG. 16 .
  • the node contact structure 40 may include a material layer with better electrical conductivity, such as a polysilicon layer.
  • a polysilicon layer may be deposited in the node contact hole 41 using a chemical vapor deposition process, an atomic layer deposition process, a plasma vapor deposition process or a rapid thermal oxidation process to serve as the node contact structure 40 .
  • the upper surface of the polysilicon layer may be lower than the upper surface of the bit line structure 20 or flush with the upper surface of the bit line structure 20 .
  • a directional etching process is used to modify the surface of the dielectric layer 30 on both sides of the bottom of the bit line structure 20 to make the node contact hole 41 easier to open.
  • the prepared node contact structure 40 is in contact with the active
  • the area 11 maintains a good electrical connection, which effectively solves the problem of product failure caused by the node contact hole 41 not being opened, and improves the product yield.
  • step S40 may include step S41, step S42 and step S43. These steps or stages do not necessarily have to be executed at the same time, but can be executed at different times.
  • the execution order of these steps or stages does not necessarily need to be sequential, but can be combined with other steps or steps in other steps or At least part of the phases are performed in rotation or alternately.
  • the present disclosure also discloses a method for manufacturing a semiconductor device, including a method for manufacturing the semiconductor structure in any of the above embodiments.
  • the semiconductor device may be a DRAM memory, or any other semiconductor device including a node contact structure.
  • the preparation process of semiconductor devices by adopting the above-mentioned preparation method of semiconductor structures, it is possible to ensure that the node contact holes are opened even when the size of the device is continuously reduced, and to ensure that the node contact structure can be electrically connected to the active area.

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Abstract

本公开涉及一种半导体结构及其制备方法、半导体器件。半导体结构包括衬底、位线结构和介质层，衬底中包括间隔排布的有源区和隔离结构；位线结构平行间隔排布于衬底上，位线结构包括第一部分和第二部分；介质层覆盖位线结构的上表面和侧面，且覆盖衬底的上表面，其中，衬底上靠近第一部分底部的介质层顶面不低于衬底上靠近第二部分底部的介质层顶面。

Description

半导体结构及其制备方法、半导体器件
相关申请的交叉引用
本公开要求于2022年03月22日提交中国专利局、申请号为202210282075.8、申请名称为“半导体结构及其制备方法、半导体器件”的中国专利申请的优先权，所述专利申请的全部内容通过引用结合在本公开中。
技术领域
本公开涉及半导体制造技术领域，特别是涉及一种半导体结构及其制备方法、半导体器件。
背景技术
随着半导体工艺的进步，器件尺寸越来越小，位线之间的节点接触结构也越来越小。
传统的位线结构制备工艺中，位线结构中未与有源区接触的部分位于衬底上方，其底部较宽，挤占了存储节点接触结构的空间，这样的结构形貌容易在酸洗之后，使得残留的氮化硅向位线接触沟槽内凹陷，从而在形成节点接触孔的过程中，等离子体无法聚集向有源区一侧，导致节点接触孔无法打开。
发明内容
根据本公开的各种实施例，提供一种半导体结构及其制备方法、半导体器件。
根据一些实施例，本公开的第一方面提出一种半导体结构，包括：衬底、位线结构和介质层，衬底中包括间隔排布的有源区和隔离结构；位线结构平行间隔排布于衬底上，位线结构包括第一部分和第二部分；介质层覆盖位线结构的上表面和侧面，且覆盖衬底的上表面，其中，衬底上靠近第一部分底部的介质层顶面不低于衬底上靠近第二部分底部的介质层顶面。
根据一些实施例，第一部分位于有源区上方且与有源区电连接，第二部分位于隔离结构的上方。
根据一些实施例，半导体结构还包括：节点接触结构，位于相邻的两个位线结构之间，贯穿衬底上的介质层，且与位于节点接触结构下方的有源区电连接。
根据一些实施例，节点接触结构包括导电层，介质层包括氮化硅层。
根据一些实施例，本公开的第二方面提出一种半导体器件，包括前述任一实施例中的半导体结构。
根据一些实施例，本公开的第三方面提出一种半导体结构的制备方法，包括：提供衬底，衬底中包括间隔排布的有源区和隔离结构；衬底上形成有若干平行间隔排布的位线结构，位线结构包括第一部分和第二部分；形成介质层，介质层包覆位线结构的表面，并覆盖衬底的上表面；形成保护层，保护层覆盖介质层的表面；去除位于位线结构侧壁的部分介质层；去除衬底上的部分介质层，使得第一部分底部两侧残留的介质层的顶面不低于第二部分底部两侧残留的介质层的顶面。
根据一些实施例，第一部分位于有源区上方且与有源区电连接，第二部分位于隔离结构的上方。
根据一些实施例，去除位于位线结构侧壁的部分介质层，包括：去除位于位线结构侧壁的保护层；采用修整刻蚀工艺去除位于位线结构侧壁的部分介质层；通入清扫气体，对所得结构进行清扫。
根据一些实施例，清扫气体包括惰性气体。
根据一些实施例，去除衬底上的保护层和部分介质层，包括：去除衬底上方的保护层；采用定向刻蚀工艺刻蚀衬底上的介质层，去除部分介质层，以使得第一部分两侧残留的介质层的顶面高于或齐平于第二部分两侧残留的介质层的顶面。
根据一些实施例，定向刻蚀工艺包括等离子体定向刻蚀工艺。
根据一些实施例，介质层包括氮化硅层，保护层包括光刻胶层。
根据一些实施例，去除衬底上的保护层和部分介质层之后，还包括：于相邻位线结构之间形成节点接触孔，节点接触孔暴露出有源区。
根据一些实施例，于相邻位线结构之间形成节点接触孔，包括：形成填充层，填充层填满相邻位线结构之间的间隙，且填充层的顶面与位线结构的顶面齐平；于填充层中形成开口，开口贯穿填充层，暴露出衬底的上表面；形成节点接触孔，以暴露出有源区。
根据一些实施例，形成节点接触孔之前，还包括：去除位线结构顶部的保护层；于位线结构相对的两侧形成侧墙结构。
根据一些实施例，于相邻位线结构之间形成节点接触孔，包括：形成填充层，填充层填满相邻位线结构之间的间隙，且填充层的顶面与位线结构的顶面齐平；于填充层中形成开口，开口贯穿填充层，暴露出介质层的部分上表面；形成节点接触孔，以暴露出有源区。
根据一些实施例，形成节点接触孔之后，还包括：于节点接触孔中形成节点接触结构，节点接触结构与有源区电连接。
本公开实施例可以/至少具有以下优点：
在本公开实施例提供的半导体结构及其制备方法、半导体器件中，由于靠近第一部分底部的介质层顶面高于或齐平于靠近第二部分底部的介质层顶面，可以在后续工艺中形成节点接触孔时，使得刻蚀工艺不会偏向于第一部分的两侧而导致节点接触孔无法暴露出有源区，为节点接触孔的刻蚀工艺提供了更大的可控性和工艺窗口，解决了节点接触孔无法打开的问题。
综上，本公开实施例提供的半导体结构及其制备方法、半导体器件，可以在后续工艺中形成节点接触孔时，使得刻蚀工艺不会偏向于第一部分的两侧而导致节点接触孔无法暴露出有源区，为节点接触孔的刻蚀工艺提供了更大的可控性和工艺窗口，解决了节点接触孔无法打开的问题。
本公开的一个或多个实施例的细节在下面的附图和描述中提出。本公开的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开实施例的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开一实施例中半导体结构的截面结构示意图；
图2为图1所示半导体结构的俯视图；
图3为本公开另一实施例中半导体结构的截面结构示意图；
图4为本公开又一实施例中半导体结构的截面结构示意图；
图5为本公开一实施例中半导体结构的制备方法的流程框图；
图6为本公开一实施例中于衬底上形成位线结构后的半导体结构的截面结构示意图；
图7为本公开一实施例中形成介质层后的半导体结构的截面结构示意图；
图8为本公开一实施例中形成保护层后的半导体结构的截面结构示意图；
图9为本公开一实施例中去除位线结构侧壁的部分介质层后的半导体结构的截面结 构示意图；
图10a为本公开一实施例中对衬底上的介质层进行定向刻蚀后的半导体结构的截面结构示意图；
图10b为本公开另一实施例中对衬底上的介质层进行定向刻蚀后的半导体结构的截面结构示意图；
图11为本公开一实施例中去除位线结构顶部的保护层后的半导体结构的截面结构示意图；
图12为本公开一实施例中形成侧墙结构后的半导体结构的截面结构示意图；
图13为本公开一实施例中形成填充层后的半导体结构的截面结构示意图；
图14为本公开一实施例中于填充层中形成开口后的半导体结构的截面结构示意图；
图15为本公开一实施例中形成节点接触孔后的半导体结构的截面结构示意图；
图16为本公开一实施例中形成节点接触结构后的半导体结构的截面结构示意图。
具体实施方式
为了便于理解本公开，下面将参照相关附图对本公开进行更全面的描述。附图中给出了本公开的较佳的实施例。但是，本公开可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本公开的公开内容的理解更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本公开的技术领域的技术人员通常理解的含义相同。本文中在本公开的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本公开。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
在描述位置关系时，除非另有规定，否则当一元件例如层、膜或基板被指为在另一膜层“上”时，其能直接在其他膜层上或亦可存在中间膜层。进一步说，当层被指为在另一层“下”时，其可直接在下方，亦可存在一或多个中间层。亦可以理解的是，当层被指为在两层“之间”时，其可为两层之间的唯一层，或亦可存在一或多个中间层。
在使用本文中描述的“包括”、“具有”、和“包含”的情况下，除非使用了明确的限定用语，例如“仅”、“由……组成”等，否则还可以添加另一部件。除非相反地提及，否则单数形式的术语可以包括复数形式，并不能理解为其数量为一个。
随着半导体工艺的进步，器件尺寸越来越小。在DRAM存储器件的阵列区域中，位线结构未与有源区电连接的部分位于衬底上方，其底部较宽，挤占了存储节点接触结构的空间，这样的结构形貌容易在酸洗之后，使得残留的氮化硅向位线接触沟槽内凹陷，从而在形成节点接触孔的过程中，等离子体无法聚集向有源区一侧，导致节点接触孔无法打开，最终形成的节点接触结构无法与有源区电连接。
为了解决上述问题，本公开的一个实施例公开了一种半导体结构，如图1所示，包括衬底10、位线结构20和介质层30，衬底10中包括间隔排布的有源区11和隔离结构12，位线结构20平行间隔排布于衬底10上，位线结构20包括第一部分21和第二部分22；介质层30覆盖位线结构20的上表面和侧面，且覆盖衬底10的上表面，其中，衬底10上靠近第一部分21底部的介质层30顶面不低于例如高于或齐平于衬底10上靠近第二部分22底部的介质层30顶面。
上述半导体结构中，靠近第一部分21底部的介质层30顶面高于或齐平于靠近第二部分22底部的介质层30顶面，可以在后续工艺中形成节点接触孔时，使得刻蚀工艺不会偏向于第一部分21的两侧而导致节点接触孔无法暴露出有源区11，为节点接触孔的刻蚀工艺提供了更大的可控性和工艺窗口，解决了节点接触孔无法打开的问题。
示例地，如图1所示，衬底10中包括阵列排布的有源区11和隔离结构12，有源区 11位于相邻的隔离结构12之间。隔离结构12包括水平部121，覆盖有源区11的上表面。
图2为图1所示半导体结构的俯视图。结合图1和图2可知，位线结构20平行排布于衬底10上，包括第一部分21和第二部分22。其中，第一部分21位于位线接触沟槽23中，位线接触沟槽23暴露出有源区11的上表面，使得第一部分21与有源区11电连接；第二部分22位于隔离结构12的水平部121上方，隔离结构12的水平部121将位线结构20的第二部分22与有源区11隔离开。示例地，第一位线结构和第二位线结构为相邻的两个位线结构20，沿图2中的AA’方向可以截取到第一位线结构的第一部分21以及第二位线结构的第二部分22，得到如图1所示的截面结构示意图。
在一些实施例中，位线结构20可以包括从下至上依次叠置的位线导电层(图中未示出)和位线绝缘层(图中未示出)。其中，位线导电层包括从下至上依次叠置的多晶硅层、阻挡金属层和导线金属层。可选地，在一些其他实施例中，位线导电层包括导线金属层以及包裹导线金属层底面和侧面的阻挡金属层。作为示例，导线金属层例如可以为钨层或铜层；阻挡金属层例如可以为钛层或氮化钛层。位线绝缘层可以为氮化物层，例如氮化硅层。
介质层30覆盖衬底10的上表面以及位线结构20的上表面和侧面，并填满位线接触沟槽23。示例地，介质层30可以包括但不限于氮化硅层。
在一些实施例中，如图1所示，衬底10上靠近第一部分21底部两侧的介质层30与靠近第二部分22底部两侧的介质层30的顶面齐平，在后续工艺中形成节点接触孔时，可以更加容易刻蚀穿透介质层30和衬底10的顶部，暴露出靠近第二部分22的有源区11，以完全打开节点接触孔，提高了刻蚀工艺的可控性和工艺窗口。
可选地，在一些实施例中，如图3所示，衬底10上靠近第一部分21底部两侧的介质层30顶面可以高于衬底10上靠近第二部分22底部两侧的介质层30顶面。在后续工艺中形成节点接触孔时，等离子体可以更多地聚向第二部分22的底部两侧，加快对第二部分22底部两侧介质层30的刻蚀速度，从而更容易打开节点接触孔，暴露出第二部分22下方的有源区11。
在一些实施例中，如图4所示，半导体结构还包括节点接触结构40，位于相邻的两个位线结构20之间。节点接触结构40贯穿衬底10上的介质层30以及衬底10的顶部，与位于节点接触结构40下方的有源区11电连接。
示例地，节点接触结构40可以包括导电性能较佳的材料层，例如多晶硅层或金属层。可选地，在一些实施例中，为了更好地将位线结构20与节点接触结构40隔开，位线结构20两侧还设置有侧墙结构60，如图4所示。示例地，侧墙结构60可以包括第一绝缘层61和第二绝缘层62，其中，第一绝缘层61位于位线结构20相对的两侧，第二绝缘覆盖位线结构20和第一绝缘层61。示例地，第一绝缘层61可以是介电常数大于3.9的高介电材料层，例如二氧化硅层，第二绝缘层62可以是硬度较高的绝缘保护层50，例如氮化硅层。
本公开的一个实施例还公开了一种半导体器件，包括前述任一实施例中的半导体结构。
示例地，半导体器件可以是DRAM存储器，或者是其他任意一种包含节点接触结构40的半导体器件。通过将上述任一实施例中半导体结构应用于DRAM存储器，可以大幅改善节点接触孔无法打开的情况，使得阵列区域的节点接触结构40与有源区11具有良好的电连接，提高产品良率。
如图5所示，本公开的一个实施例还公开了一种半导体结构的制备方法，包括：
S10：提供衬底10，衬底10中包括间隔排布的有源区11和隔离结构12；衬底10上形成有若干平行间隔排布的位线结构20，位线结构20包括第一部分21和第二部分22；
S20：形成介质层30，介质层30包覆位线结构20的表面，并覆盖衬底10的上表面；
S30：形成保护层50，保护层50覆盖介质层30的表面；
S40：去除位于位线结构20侧壁的部分介质层30；
S50：去除衬底10上的部分介质层30，使得第一部分21底部两侧残留的介质层30的 顶面高于或齐平于第二部分22底部两侧残留的介质层30的顶面。
上述半导体结构的制备方法，通过在介质层30的表面形成保护层50，可以分步骤地对介质层30进行减薄处理；其中，在对位线结构20底部两侧的介质层30进行减薄时，控制第一部分21底部两侧残留的介质层30的顶面高于或齐平于第二部分22底部两侧残留的介质层30的顶面，从而可以在形成节点接触孔时，更加容易打开，暴露出衬底10中的有源区11，改善节点接触孔难以打开的情况。
示例地，如图6所示，步骤S10中的衬底10包括间隔排布的隔离结构12和有源区11。作为示例，隔离结构12的材质可以包括但不仅限于氧化硅、氮化硅等等，衬底10可以包括但不仅限于硅衬底10。隔离结构12还包括位于有源区11上方的水平部121，覆盖有源区11的上表面。
示例地，隔离结构12的水平部121内至少形成有一个位线接触沟槽23，位线接触沟槽23暴露出有源区11的上表面。位线结构20的第一部分21位于位线接触沟槽23中，与有源区11电连接；位线结构20的第二部分22位于位线接触沟槽23外，位于隔离结构12的水平部121上。
作为示例，位线结构20可以包括从下至上依次叠置的位线导电层和位线绝缘层。其中，位线导电层可以包括导线金属层以及包裹导线金属层底面和侧面的阻挡金属层。导线金属层的制作材料可以为电阻率较低的金属导电材料，例如W(钨)、钼(Mo)、Ti(钛)、Cu(铜)或Au(金)，作为示例，可以采用化学气相沉积工艺形成位线导电层。阻挡金属层的制作材料可以是对金属和半导体材料具有良好阻挡作用的材料层，例如氮化钛层、钴层、铂层或钛钨层。阻挡金属层还需要具有高导电性，以及在半导体和金属之间具有良好的附着性。作为示例，可以采用化学气相沉积工艺、原子层沉积工艺、等离子蒸汽沉积工艺或快速热氧化工艺形成阻挡金属层。位线绝缘层可以为氮化物层，例如氮化硅。上述各层的制作材料也可以根据实际情况选择，本公开不进行限定。
在步骤S20中，如图7所示，形成介质层30，以覆盖位线结构20的表面和衬底10的上表面。在一些实施例中，介质层30填满位线接触沟槽23。
示例地，介质层30的材质可以包括但不限于氮化物层，例如氮化硅层。可以采用化学气相沉积工艺、原子层沉积工艺或等离子蒸汽沉积工艺在位线结构20的表面和衬底10的上表面形成介质层30。
在步骤S30中，如图8所示，于介质层30的表面形成保护层50。保护层50可用于保护特定区域的介质层30不被刻蚀。
示例地，保护层50可以是光刻胶层。于介质层30的表面形成光刻胶层的步骤可以包括：将带有半导体结构的晶圆放在加热盘上在180至250℃下进行烘烤30至80s时间；将晶圆在50至120℃下缓冲冷却15至60s；将晶圆放置在快速冷却盘上进行快速；在晶圆上形成光刻胶层。
通过在介质层30的表面形成保护层50，可以实现分阶段、分区域地对介质层30进行减薄。例如，只需将待刻蚀区域表面的保护层50去除，即可对待刻蚀区域进行刻蚀和去除。示例地，保护层50可以是光刻胶层。
在步骤S40中，去除位于位线结构20侧壁的部分介质层30，得到图9所示的结构。示例地，具体步骤包括：
S41：去除位于位线结构20侧壁的保护层50。
S42：采用修整刻蚀工艺去除位于位线结构20侧壁的部分介质层30。
S43：通入清扫气体，对所得结构进行清扫。
示例地，以保护层50为光刻胶层、介质层30为氮化硅层为例进行说明。可以先将位于位线结构20侧壁的光刻胶层去除，以暴露出位于位线结构20侧壁的氮化硅层；然后采用修整刻蚀工艺(trim etch)刻蚀氮化硅层，减小氮化硅层的厚度。由于位线结构20的 顶部以及衬底10上的介质层30顶部仍被光刻胶层覆盖，因此，修整刻蚀工艺不影响这两处位置的氮化硅层厚度。最后，通入清扫气体，将修整刻蚀工艺的副产物清扫干净。示例地，可以通过清扫装置对半导体结构的表面进行清扫。清扫装置例如可以包括气体吹扫单元和气体吸除单元。将清扫装置安装至工艺腔室外部，通过气体吹扫单元可以向工艺腔室中通入清扫气体，对半导体结构表面残留的副产物进行吹扫，同时打开气体吸除单元，启动抽气和排风，把悬浮在工艺腔室中的颗粒吸出。清扫气体包括但不限于惰性气体。示例地，清扫气体可以为氮气、氦气(He)、氖气(Ne)、氩气(Ar)、氪气(Kr)或氙气(Xe)中的至少一种。
通过形成保护层50，可以保护衬底10上表面的介质层30不受修整刻蚀工艺的影响；并且，在采用修整刻蚀工艺将位线结构20侧壁的介质层30减薄之后，通入清扫气体清除修整刻蚀工艺产生的副产物，可以防止残留物对后续刻蚀工艺产生影响。
在步骤S50中，去除衬底10上的部分介质层30的步骤包括：
S51：去除衬底10上方的保护层50；
S52：采用定向刻蚀工艺刻蚀衬底10上的介质层30，去除部分介质层30，以使得第一部分21两侧残留的介质层30的顶面高于或齐平于第二部分22两侧残留的介质层30的顶面，如图10a或图10b所示。
示例地，定向刻蚀工艺可以包括但不限于等离子体定向刻蚀工艺。去除保护层50之后，采用等离子体定向刻蚀工艺，控制定向等离子体轰击衬底10上表面的介质层30，减薄介质层30的厚度。相比于无方向性的酸洗工艺，等离子体定向刻蚀工艺可以定向调节对介质层30不同区域的刻蚀程度，调节介质层30不同位置的高度。
以介质层30为氮化硅层进行说明。在一些实施例中，可以对第一部分21底部两侧的氮化硅层和第二部分22两侧的氮化硅层进行同等程度的刻蚀，使得减薄后的氮化硅层具有平整的表面，如图10a所示，靠近第一部分21底部的介质层30顶面齐平于靠近第二部分22底部的介质层30顶面。由于相邻两个位线结构20之间的介质层具有平整的顶面，在形成节点接触孔时，刻蚀工艺不会偏向第一部分21底部的两侧，使得形成的节点接触孔能够顺利地暴露出第二部分下方的有源区11。
可选地，在一些实施例中，可以对第二部分22底部两侧的氮化硅层进行较大程度的刻蚀，对第一部分21底部两侧的氮化硅层进行较小程度的刻蚀，以使得第一部分21底部两侧的氮化硅层的顶面高于第二部分22底部两侧的氮化硅层的顶面，如图10b所示。在形成节点接触孔时，刻蚀工艺可以偏向第二部分22底部两侧的介质层30，使得形成的节点接触孔更加容易地暴露出第二部分22下方的有源区11。
在上述半导体结构的制备方法中，通过采用定向刻蚀工艺，可以对位线结构20底部两侧的介质层30进行定向修正，使得在后续工艺中刻蚀形成节点接触孔时，等离子体可以被更多地引向有源区11，确保可以打开节点接触孔，增大了刻蚀工艺的可控性和工艺窗口。
在一些实施例中，去除衬底10上的保护层50和部分介质层30之后，还包括：
S60：于相邻位线结构20之间形成节点接触孔，节点接触孔暴露出有源区11。可选地，形成节点接触孔之前，还包括：
S61：去除位线结构20顶部的保护层50，如图11所示。
S62：于位线结构20相对的两侧形成侧墙结构60，如图12所示。
示例地，侧墙结构60可以包括第一绝缘层61和第二绝缘层62，其中，第一绝缘层61位于位线结构20相对的两侧，第二绝缘覆盖位线结构20和第一绝缘层61。
在一些实施例中，形成侧墙结构60的工艺步骤包括：
S621：于位线结构20相对的两侧形成第一绝缘层61。
示例地，由于衬底10的上表面、位线结构20的顶部和侧壁被残留的介质层30覆盖， 因此，可以先在残留的介质层30表面形成第一绝缘材料层。第一绝缘材料层可以是介电常数大于3.9的高介电材料层，例如二氧化硅层。然后，将位于介质层30上表面的第一绝缘材料层去除，得到位于位线结构相对两侧的第一绝缘层61。示例地，形成第一绝缘材料层的工艺可以包括但不限于化学气相沉积工艺、原子层沉积工艺、等离子蒸汽沉积工艺或快速热氧化工艺。
S622：形成第二绝缘层62，以覆盖位线结构20的顶面和第一绝缘层61。
示例地，可以先于所得结构的表面形成第二绝缘材料层，以覆盖第一绝缘层61和介质层30的上表面，然后去除衬底10表面的介质层30上方的第二绝缘材料层，形成包覆位线结构20和第一绝缘层61的第二绝缘层62。第二绝缘材料层可以是硬度较高的绝缘保护层，例如氮化硅层。
在一些实施例中，如图13-图15，于相邻位线结构20之间形成节点接触孔41的步骤包括：
S63：形成填充层70，填充层70填满相邻位线结构20之间的间隙，且填充层70的顶面与位线结构20的顶面齐平，如图13所示。
示例地，填充层70可以包括但不限于二氧化硅层。可以采用沉积工艺于位线结构20之间的间隙中形成二氧化硅层，二氧化硅层填满间隙且覆盖位线结构20的上表面。采用化学机械研磨工艺研磨二氧化硅层的上表面，直至暴露出位线结构20的顶部，得到填充层70。可选地，填充层70还可以是与第二绝缘层62的材质不同的其他材料层。
S64：于填充层70中形成开口71，开口71贯穿填充层70，暴露出介质层30的部分上表面，如图14所示。
示例地，可以先在所得结构的顶面形成图案化光阻层，图案化光阻层中的图案定义出各个开口71的位置和大小。然后采用刻蚀工艺，基于图案化光阻层刻蚀填充层70，于填充层70中形成开口71，暴露出介质层30的部分上表面。
S65：形成节点接触孔41，以暴露出有源区11，如图15所示。
作为示例，介质层30为氮化硅层，可以在刻蚀工艺中加入刻蚀氮化硅的气体，以确保氮化硅层能够被打开。打开介质层30后，继续向下刻蚀，以暴露出有源区11。
在形成节点接触孔41之前，通过对第一部分21底部两侧的介质层30和第二部分22两侧的介质层30进行定向刻蚀，在降低介质层30的厚度同时，控制实现第一部分21底部两侧的介质层30高度等于或大于第二部分22两侧的介质层30高度，从而可以在形成节点接触孔41时，较为容易地打开节点接触孔41，暴露出有源区11，解决了由于位线结构20挤占空间而造成节点接触孔41无法打开的问题。
在一些实施例中，形成节点接触孔41之后，还包括：于节点接触孔41中形成节点接触结构40，节点接触结构40与有源区11电连接，如图16所示。
示例地，节点接触结构40可以包括导电性能较佳的材料层，例如多晶硅层。作为示例，可以采用化学气相沉积工艺、原子层沉积工艺、等离子蒸汽沉积工艺或快速热氧化工艺于节点接触孔41内沉积多晶硅层，以作为节点接触结构40。可选地，多晶硅层的上表面可以低于位线结构20的上表面，或者与位线结构20的上表面齐平。
在上述半导体结构的制备方法中，利用定向刻蚀工艺对位线结构20底部两侧的介质层30表面进行修整，使得节点接触孔41更加易于打开，制备得到的节点接触结构40均与有源区11保持良好的电连接，有效解决了节点接触孔41没有打开而导致产品失效的问题，提高了产品良率。
应该理解的是，虽然图5所示流程图中的各个步骤按照箭头的指示依次显示，但是这些步骤并不是必然按照箭头指示的顺序依次执行。除非本文中有明确的说明，这些步骤的执行并没有严格的顺序限制，这些步骤可以以其它的顺序执行。而且，图5中的至少一部分步骤可以包括多个步骤或者多个阶段，例如，步骤S40可以包括步骤S41、步骤S42和 步骤S43。这些步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，这些步骤或者阶段的执行顺序也不必然是依次进行，而是可以与其它步骤或者其它步骤中的步骤或者阶段的至少一部分轮流或者交替地执行。
本公开还公开了一种半导体器件的制备方法，包括上述任一实施例中的半导体结构的制备方法。
示例地，半导体器件可以是DRAM存储器，或者其他任意一种包含节点接触结构的半导体器件。在半导体器件的制备过程中，通过采用上述半导体结构的制备方法，可以在器件尺寸不断减小的情况下仍然保证节点接触孔的打开，确保节点接触结构可以与有源区电连接。
请注意，上述实施例仅出于说明性目的而不意味对本公开的限制。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本公开的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本公开构思的前提下，还可以做出若干变形和改进，这些都属于本公开的保护范围。因此，本公开专利的保护范围应以所附权利要求为准。

Claims (16)

  1. 一种半导体结构，包括：
    衬底，所述衬底中包括间隔排布的有源区和隔离结构；
    位线结构，平行间隔排布于所述衬底上，所述位线结构包括第一部分和第二部分；
    介质层，覆盖所述位线结构的上表面和侧面，且覆盖所述衬底的上表面，其中，所述衬底上靠近所述第一部分底部的介质层顶面不低于所述衬底上靠近所述第二部分底部的介质层顶面。
  2. 根据权利要求1所述的半导体结构，其中，所述第一部分位于所述有源区上方且与所述有源区电连接，所述第二部分位于所述隔离结构的上方。
  3. 根据权利要求1或2所述的半导体结构，其中，还包括：
    节点接触结构，位于相邻的两个位线结构之间，贯穿所述衬底上的所述介质层，且与位于所述节点接触结构下方的有源区电连接。
  4. 根据权利要求3所述的半导体结构，其中，所述节点接触结构包括导电层，所述介质层包括氮化硅层。
  5. 一种半导体器件，包括如权利要求1-4任一项所述的半导体结构。
  6. 一种半导体结构的制备方法，包括：
    提供衬底，所述衬底中包括间隔排布的有源区和隔离结构；所述衬底上形成有若干平行间隔排布的位线结构，所述位线结构包括第一部分和第二部分；
    形成介质层，所述介质层包覆所述位线结构的表面，并覆盖所述衬底的上表面；
    形成保护层，所述保护层覆盖所述介质层的表面；
    去除位于所述位线结构侧壁的部分所述介质层；
    去除所述衬底上的部分所述介质层，使得所述第一部分底部两侧残留的所述介质层的顶面不低于所述第二部分底部两侧残留的所述介质层的顶面。
  7. 根据权利要求6所述的半导体结构的制备方法，其中，所述第一部分位于所述有源区上方且与所述有源区电连接，所述第二部分位于所述隔离结构的上方。
  8. 根据权利要求6所述的半导体结构的制备方法，其中，所述去除位于所述位线结构侧壁的部分所述介质层，包括：
    去除位于所述位线结构侧壁的所述保护层；
    采用修整刻蚀工艺去除位于所述位线结构侧壁的部分所述介质层；
    通入清扫气体，对所得结构进行清扫。
  9. 根据权利要求8所述的半导体结构的制备方法，其中，所述清扫气体包括惰性气体。
  10. 根据权利要求6所述的半导体结构的制备方法，其中，所述去除所述衬底上的所述保护层和部分所述介质层，包括：
    去除所述衬底上方的所述保护层；
    采用定向刻蚀工艺刻蚀所述衬底上的所述介质层，去除部分所述介质层，以使得所述 第一部分两侧残留的所述介质层的顶面高于或齐平于所述第二部分两侧残留的所述介质层的顶面。
  11. 根据权利要求10所述的半导体结构的制备方法，其中，所述定向刻蚀工艺包括等离子体定向刻蚀工艺。
  12. 根据权利要求6所述的半导体结构的制备方法，其中，所述介质层包括氮化硅层，所述保护层包括光刻胶层。
  13. 根据权利要求6-12任一项所述的半导体结构的制备方法，其中，所述去除所述衬底上的所述保护层和部分所述介质层之后，还包括：
    于相邻所述位线结构之间形成节点接触孔，所述节点接触孔暴露出所述有源区。
  14. 根据权利要求13所述的半导体结构的制备方法，其中，形成所述节点接触孔之前，还包括：
    去除所述位线结构顶部的所述保护层；
    于所述位线结构相对的两侧形成侧墙结构。
  15. 根据权利要求14所述的半导体结构的制备方法，其中，所述于相邻所述位线结构之间形成节点接触孔，包括：
    形成填充层，所述填充层填满相邻所述位线结构之间的间隙，且所述填充层的顶面与所述位线结构的顶面齐平；
    于所述填充层中形成开口，所述开口贯穿所述填充层，暴露出所述介质层的部分上表面；
    形成所述节点接触孔，以暴露出所述有源区。
  16. 根据权利要求15所述的半导体结构的制备方法，其中，形成所述节点接触孔之后，还包括：
    于所述节点接触孔中形成节点接触结构，所述节点接触结构与所述有源区电连接。
PCT/CN2022/125123 2022-03-22 2022-10-13 半导体结构及其制备方法、半导体器件 WO2023178996A1 (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040178433A1 (en) * 2003-03-15 2004-09-16 Yun Cheol-Ju DRAM memory cell and method of manufacturing the same
CN112992905A (zh) * 2021-03-24 2021-06-18 长鑫存储技术有限公司 存储器件电容接点结构及其制备方法
CN113035873A (zh) * 2021-03-08 2021-06-25 长鑫存储技术有限公司 半导体结构及其制作方法
CN113471149A (zh) * 2021-07-01 2021-10-01 长鑫存储技术有限公司 半导体结构及其制备方法
CN114093870A (zh) * 2020-08-25 2022-02-25 长鑫存储技术有限公司 半导体结构及其制作方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040178433A1 (en) * 2003-03-15 2004-09-16 Yun Cheol-Ju DRAM memory cell and method of manufacturing the same
CN114093870A (zh) * 2020-08-25 2022-02-25 长鑫存储技术有限公司 半导体结构及其制作方法
CN113035873A (zh) * 2021-03-08 2021-06-25 长鑫存储技术有限公司 半导体结构及其制作方法
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