WO2023176118A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2023176118A1
WO2023176118A1 PCT/JP2023/000741 JP2023000741W WO2023176118A1 WO 2023176118 A1 WO2023176118 A1 WO 2023176118A1 JP 2023000741 W JP2023000741 W JP 2023000741W WO 2023176118 A1 WO2023176118 A1 WO 2023176118A1
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WIPO (PCT)
Prior art keywords
field plate
trench
semiconductor device
electrode
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2023/000741
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English (en)
French (fr)
Japanese (ja)
Inventor
賢樹 長田
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Rohm Co Ltd
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Rohm Co Ltd
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Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to CN202380026624.8A priority Critical patent/CN118843942A/zh
Priority to JP2024507532A priority patent/JPWO2023176118A1/ja
Priority to DE112023001369.1T priority patent/DE112023001369T5/de
Publication of WO2023176118A1 publication Critical patent/WO2023176118A1/ja
Priority to US18/822,512 priority patent/US20240421199A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H10D64/112—Field plates comprising multiple field plate segments
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H10D64/117—Recessed field plates, e.g. trench field plates or buried field plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/252—Source or drain electrodes for field-effect devices for vertical or pseudo-vertical devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 

Definitions

  • the present disclosure relates to a semiconductor device.
  • Patent Document 1 discloses a MISFET having a trench gate structure.
  • the trench gate structure includes a gate trench, an insulating layer, a bottom electrode, and an opening electrode.
  • Patent Document 1 describes that by applying a reference voltage to the bottom side electrode and applying a gate voltage to the opening side electrode, the switching speed can be improved while suppressing a decrease in the withstand voltage of the MISFET.
  • MISFETs having a trench gate structure there is a need for a technology that further improves breakdown voltage while suppressing increases in gate-drain parasitic capacitance and gate-source parasitic capacitance.
  • a semiconductor device includes a semiconductor layer, a gate trench formed in the semiconductor layer and arranged in a mesh shape in a plan view, and a gate trench formed in the semiconductor layer and in the gate trench in a plan view.
  • a field plate trench surrounded by and spaced apart from the gate trench; an insulating layer formed on the semiconductor layer; an upper surface disposed within the gate trench and covered by the insulating layer; and a field plate trench opposite the upper surface.
  • a first field plate electrode disposed within the gate trench below the bottom surface of the gate electrode; a first field plate electrode disposed within the field plate trench and having a top surface covered by the insulating layer; and a source electrode formed on the insulating layer. The first field plate electrode and the second field plate electrode are electrically connected to the source electrode.
  • the semiconductor device of the present disclosure it is possible to improve breakdown voltage while suppressing increases in gate-drain parasitic capacitance and gate-source parasitic capacitance.
  • FIG. 1 is a schematic plan view of an exemplary semiconductor device according to one embodiment.
  • FIG. 2 is a schematic cross-sectional view of the gate trench taken along line F2-F2 in FIG.
  • FIG. 3 is an enlarged plan view of the semiconductor device of FIG. 1.
  • FIG. 4 is a schematic cross-sectional view of the field plate trench taken along line F4-F4 in FIG.
  • FIG. 5 is a schematic plan view of a semiconductor device of a comparative example.
  • FIG. 6 is a schematic cross-sectional view of a field plate trench of a semiconductor device according to a first modification.
  • FIG. 7 is a schematic plan view of an exemplary semiconductor device according to a second modification.
  • FIG. 8 is a schematic plan view of an exemplary semiconductor device according to a third modification.
  • FIG. 9 is an enlarged plan view of the semiconductor device of FIG. 8.
  • FIG. 10 is a schematic plan view of an exemplary semiconductor device according to a fourth modification.
  • FIG. 1 is a schematic plan view of an exemplary semiconductor device 10 according to one embodiment.
  • planar view used in the present disclosure refers to viewing the semiconductor device 10 in the Z-axis direction of the mutually orthogonal XYZ axes shown in FIG. Unless explicitly stated otherwise, “planar view” refers to viewing the semiconductor device 10 from above along the Z-axis.
  • the semiconductor device 10 is, for example, a metal-insulator-semiconductor field-effect transistor (MISFET) having a trench gate structure.
  • Semiconductor device 10 includes a semiconductor layer 12 and a gate trench 14 formed in semiconductor layer 12.
  • FIG. 1 shows an active region of a semiconductor device 10.
  • the semiconductor layer 12 can be formed from silicon (Si), for example.
  • the semiconductor layer 12 includes a first surface 12A perpendicular to the Z-axis shown in FIG. 1, and a second surface 12B opposite to the first surface 12A (see FIG. 2).
  • the gate trench 14 is formed in the semiconductor layer 12 and is arranged in a mesh shape when viewed from above.
  • the gate trench 14 includes a horizontal gate trench portion 14X that extends in the X-axis direction and has a width in the Y-axis direction in plan view, and a vertical gate trench portion 14Y that extends in the Y-axis direction and has a width in the X-axis direction in plan view. Contains.
  • the gate trench 14 can have a mesh-like pattern as shown in FIG.
  • the Y-axis direction is also referred to as a first direction
  • the X-axis direction is also referred to as a second direction. Therefore, the second direction is perpendicular to the first direction.
  • the semiconductor layer 12 can include a plurality of unit mesh regions M surrounded by gate trenches 14 arranged in a mesh shape in plan view.
  • each of the plurality of unit mesh regions M may have a square shape in plan view.
  • the plurality of unit mesh regions M are aligned in the X-axis direction, but are arranged in an alternately offset manner in the Y-axis direction.
  • the horizontal gate trench portion 14X and the vertical gate trench portion 14Y do not intersect in a cross shape, but form a T-junction.
  • Such a mesh arrangement may be advantageous in the manufacturing process of the semiconductor device 10.
  • the plurality of unit mesh regions M may be aligned in both the X-axis direction and the Y-axis direction.
  • FIG. 2 is a schematic cross-sectional view of the semiconductor device 10 of FIG. 1 taken along line F2-F2.
  • FIG. 2 shows a cross section of the vertical gate trench portion 14Y along the width direction (X-axis direction). Although illustration is omitted, it is understood that the cross section of the horizontal gate trench portion 14X along the width direction (Y-axis direction) is the same as that in FIG. 2 except that it is rotated by 90 degrees within the XY plane. sea bream.
  • the semiconductor layer 12 can include a semiconductor substrate 16 including a first surface 12A of the semiconductor layer 12, and an epitaxial layer 18 formed on the semiconductor substrate 16 and including a second surface 12B of the semiconductor layer 12.
  • the semiconductor substrate 16 may be a Si substrate.
  • the semiconductor substrate 16 corresponds to the drain region of the MISFET.
  • Epitaxial layer 18 may be a Si layer epitaxially grown on a Si substrate.
  • Epitaxial layer 18 can include a drift region 20 , a body region 22 formed on drift region 20 , and a source region 24 formed on body region 22 .
  • Source region 24 may include second surface 12B of semiconductor layer 12.
  • the drain region (semiconductor substrate 16) may be an n-type region containing n-type impurities.
  • the n-type impurity concentration of the drain region (semiconductor substrate 16) can be set to 1 ⁇ 10 18 cm ⁇ 3 or more and 1 ⁇ 10 20 cm ⁇ 3 or less.
  • the drain region (semiconductor substrate 16) may have a thickness of 50 ⁇ m or more and 450 ⁇ m or less.
  • Drift region 20 may be an n-type region containing n-type impurities at a lower concentration than the drain region (semiconductor substrate 16).
  • the n-type impurity concentration of the drift region 20 can be set to 1 ⁇ 10 15 cm ⁇ 3 or more and 1 ⁇ 10 18 cm ⁇ 3 or less.
  • Drift region 20 may have a thickness of 1 ⁇ m or more and 25 ⁇ m or less.
  • Body region 22 may be a p-type region containing p-type impurities.
  • the p-type impurity concentration of the body region 22 can be set to 1 ⁇ 10 16 cm ⁇ 3 or more and 1 ⁇ 10 18 cm ⁇ 3 or less.
  • Body region 22 may have a thickness of 0.2 ⁇ m or more and 1.0 ⁇ m or less.
  • Source region 24 may be an n-type region containing a higher concentration of n-type impurities than drift region 20 .
  • the n-type impurity concentration of the source region 24 can be set to 1 ⁇ 10 19 cm ⁇ 3 or more and 1 ⁇ 10 21 cm ⁇ 3 or less.
  • the source region 24 may have a thickness of 0.1 ⁇ m or more and 1 ⁇ m or less.
  • the n-type is also referred to as a first conductivity type, and the p-type is also referred to as a second conductivity type.
  • the n-type impurity may be, for example, phosphorus (P) or arsenic (As).
  • the p-type impurity may be, for example, boron (B), aluminum (Al), or the like.
  • the gate trench 14 has an opening in the second surface 12B of the semiconductor layer 12 and has a depth in the Z-axis direction. Gate trench 14 extends through source region 24 and body region 22 of semiconductor layer 12 to drift region 20 . Gate trench 14 has sidewalls 14A and a bottom wall 14B, and bottom wall 14B is adjacent to drift region 20. The depth of the gate trench 14 may be 1 ⁇ m or more and 10 ⁇ m or less.
  • the sidewall 14A of the gate trench 14 may extend in a direction perpendicular to the second surface 12B of the semiconductor layer 12 (Z-axis direction), or may be inclined. In one example, the sidewall 14A may be inclined with respect to the Z-axis direction so that the width of the gate trench 14 becomes smaller toward the bottom wall 14B. Further, the bottom wall 14B of the gate trench 14 does not necessarily have to be flat, and may be partially or entirely curved, for example.
  • Semiconductor device 10 further includes an insulating layer 26 formed on semiconductor layer 12.
  • the insulating layer 26 can be formed from a silicon oxide film (SiO 2 ), for example.
  • Insulating layer 26 may additionally or alternatively include a layer formed from an insulating material other than SiO2 , such as silicon nitride (SiN).
  • the semiconductor device 10 further includes a gate electrode 28 and a first field plate electrode 30 arranged within the gate trench 14.
  • the gate electrode 28 may be an electrode configured to be applied with a gate voltage
  • the first field plate electrode 30 may be an electrode configured to be applied with a reference voltage (or source voltage).
  • the trench in which the gate electrode 28 is arranged is referred to as a gate trench 14.
  • the gate electrode 28 includes a top surface 28A covered with the insulating layer 26 and a bottom surface 28B opposite to the top surface 28A.
  • the first field plate electrode 30 is arranged in the gate trench 14 below the bottom surface 28B of the gate electrode 28 (between the bottom surface 28B of the gate electrode 28 and the bottom wall 14B of the gate trench 14). At least a portion of the bottom surface 28B of the gate electrode 28 faces the first field plate electrode 30 with the insulating layer 26 in between.
  • the upper surface 28A of the gate electrode 28 can be located below the second surface 12B of the semiconductor layer 12.
  • the top surface 28A and bottom surface 28B of the gate electrode 28 may be flat or curved.
  • the gate electrode 28 may or may not have a uniform width regardless of its position in the Z-axis direction.
  • the bottom portion of the gate electrode 28 including the bottom surface 28B may have a smaller width than other portions.
  • the first field plate electrode 30 is surrounded by an insulating layer 26 (a lower insulating section 34 to be described later).
  • First field plate electrode 30 may have a smaller width than gate electrode 28. Since the first field plate electrode 30 has a relatively small width, the thickness of the insulating layer 26 (lower insulating portion 34) surrounding the first field plate electrode 30 is relatively large. Thereby, electric field concentration within the gate trench 14 can be alleviated.
  • the gate electrode 28 may be located at a position such that the interface between the drift region 20 and the body region 22 is not lower than the bottom surface 28B of the gate electrode 28 in the Z-axis direction.
  • the interface between the drift region 20 and the body region 22 may be aligned with the bottom surface 28B of the gate electrode 28 in the Z-axis direction, or may be located above the bottom surface 28B.
  • Gate electrode 28 and first field plate electrode 30 may be formed from conductive polysilicon, in one example.
  • the insulating layer 26 may include a gate insulating portion 32 interposed between the gate electrode 28 and the semiconductor layer 12 and covering the sidewall 14A of the gate trench 14.
  • the gate electrode 28 and the semiconductor layer 12 are separated from each other by a gate insulating section 32.
  • a predetermined voltage is applied to the gate electrode 28
  • a channel is formed in the p-type body region 22 adjacent to the gate insulating portion 32.
  • the semiconductor device 10 can control the flow of electrons in the Z-axis direction between the n-type source region 24 and the n-type drift region 20 via this channel.
  • the insulating layer 26 may further include a lower insulating portion 34 that covers the side wall 14A and bottom wall 14B of the gate trench 14 between the first field plate electrode 30 and the semiconductor layer 12.
  • the lower insulating part 34 can be formed thicker than the gate insulating part 32 on the side wall 14A of the gate trench 14.
  • the insulating layer 26 may further include an intermediate insulating portion 36 located between the top surface 30A of the first field plate electrode 30 and the bottom surface 28B of the gate electrode 28.
  • the semiconductor device 10 further includes a source electrode 38 formed on the insulating layer 26.
  • the source electrode 38 is not formed directly on the source region 24 of the semiconductor layer 12, but is formed on the insulating layer 26, which has the advantage that it is less likely to be affected by voltage fluctuations in the source region 24.
  • the first field plate electrode 30 can be coupled to the source electrode 38 in a region not shown (for example, a peripheral region surrounding the active region shown in FIG. 1). Therefore, the first field plate electrode 30 is electrically connected to the source electrode 38.
  • the source electrode 38 is formed from at least one of titanium (Ti), nickel (Ni), gold (Au), silver (Ag), copper (Cu), aluminum (Al), Cu alloy, and Al alloy. be able to.
  • the semiconductor device 10 can further include a drain electrode 40 formed on the first surface 12A of the semiconductor layer 12.
  • the drain electrode 40 is adjacent to and electrically connected to the drain region (semiconductor substrate 16).
  • Drain electrode 40 can be formed from at least one of Ti, Ni, Au, Ag, Cu, Al, Cu alloy, and Al alloy.
  • FIG. 3 is an enlarged plan view of the semiconductor device 10 shown in FIG. FIG. 3 shows a region F3 surrounded by a dashed line in FIG. 1, which includes one unit mesh region M surrounded by a gate trench 14. As shown in FIG. Note that the following explanation can be applied to other unit mesh regions M as well.
  • the semiconductor device 10 further includes a field plate trench 42 formed in the semiconductor layer 12.
  • the field plate trench 42 may be one of a plurality of field plate trenches 42 arranged in each of a plurality of unit mesh regions M included in the semiconductor layer 12 .
  • Field plate trench 42 is surrounded by gate trench 14 in plan view and is spaced apart from gate trench 14 . That is, the field plate trench 42 is not in communication with the gate trench 14.
  • the field plate trench 42 may be formed in a cross shape in a plan view. In the example of FIG.
  • the field plate trench 42 includes a horizontal field plate trench portion 42X that extends in the X-axis direction and has a width in the Y-axis direction in plan view, and a horizontal field plate trench portion 42X that extends in the Y-axis direction and has a width in the X-axis direction in plan view.
  • a vertical field plate trench portion 42Y having a vertical field plate trench portion 42Y.
  • the gate trench 14 includes a vertical gate trench portion 14Y extending in the Y-axis direction. Since the field plate trench 42 is surrounded by the gate trench 14 in plan view, the vertical field plate trench portions 42Y and the vertical gate trench portions 14Y are arranged alternately in the X-axis direction. In other words, both the gate trench 14 and the field plate trench 42 include portions extending in the Y-axis direction, and these portions are arranged alternately in the X-axis direction orthogonal to the Y-axis direction.
  • the gate trench 14 includes a lateral gate trench portion 14X extending in the X-axis direction. Since the field plate trench 42 is surrounded by the gate trench 14 in plan view, the lateral field plate trench portions 42X and the lateral gate trench portions 14X are arranged alternately in the Y-axis direction. In other words, both the gate trench 14 and the field plate trench 42 include portions extending in the X-axis direction, and these portions are arranged alternately in the Y-axis direction orthogonal to the X-axis direction.
  • the semiconductor device 10 can further include a first contact plug 44 and a second contact plug 46.
  • the first contact plug 44 is arranged so as to overlap the field plate trench 42 in plan view.
  • the first contact plug 44 may be disposed within the field plate trench 42 in plan view.
  • the second contact plug 46 is arranged between the gate trench 14 and the field plate trench 42 in plan view.
  • the first contact plug 44 may be formed in a cross shape in plan view.
  • the shape and arrangement of the first contact plug 44 are not limited to the example shown in FIG. 1, and may have other shapes or arrangements.
  • one or more rectangular first contact plugs 44 may be arranged on the field plate trench 42 which is cross-shaped in plan view.
  • second contact plugs 46 are arranged point-symmetrically with respect to the center of the unit mesh area M.
  • Each of the second contact plugs 46 may have a square shape in plan view.
  • the shape and arrangement of the second contact plug 46 are not limited to the example shown in FIG. 1, and may have other shapes or arrangements.
  • second contact plug 46 may be located closer to field plate trench 42 than in the example of FIG.
  • Each of the first contact plug 44 and the second contact plug 46 can be formed from any metal material.
  • each contact plug 44, 46 may be formed from at least one of tungsten (W), Ti, and titanium nitride (TiN).
  • FIG. 4 is a schematic cross-sectional view of the semiconductor device 10 of FIG. 3 taken along line F4-F4.
  • FIG. 4 shows a cross section along the width direction (X-axis direction) of the vertical field plate trench portion 42Y. Although illustration is omitted, it is understood that the cross section along the width direction (Y-axis direction) of the horizontal field plate trench portion 42X is the same as that in FIG. 4 except that it is rotated by 90 degrees within the XY plane. I want to be The cross-section shown in FIG. 4 also shows two second contact plugs 46. As shown in FIG.
  • the description of the semiconductor layer 12 in which the field plate trench 42 is formed is the same as that described above with reference to FIG.
  • the semiconductor layer 12 may further include a contact region 48 disposed adjacent to the bottom of the second contact plug 46 .
  • Contact region 48 may be a p-type region containing p-type impurities.
  • the p-type impurity concentration of the contact region 48 is higher than that of the body region 22, and can be set to 1 ⁇ 10 19 cm ⁇ 3 or more and 1 ⁇ 10 21 cm ⁇ 3 or less.
  • the field plate trench 42 has an opening in the second surface 12B of the semiconductor layer 12 and has a depth in the Z-axis direction. Field plate trench 42 extends through source region 24 and body region 22 of semiconductor layer 12 to drift region 20 . Field plate trench 42 has sidewalls 42A and a bottom wall 42B, with bottom wall 42B adjacent to drift region 20. The depth of the field plate trench 42 may be greater than or equal to 1 ⁇ m and less than or equal to 10 ⁇ m.
  • the sidewall 42A of the field plate trench 42 may or may not extend in a direction perpendicular to the second surface 12B of the semiconductor layer 12 (Z-axis direction).
  • the sidewall 42A may be inclined with respect to the Z-axis direction so that the width of the field plate trench 42 becomes smaller toward the bottom wall 42B.
  • the bottom wall 42B of the field plate trench 42 does not necessarily have to be flat, and may be partially or entirely curved, for example.
  • the width of the field plate trench 42 may be equal to or different from the width of the gate trench 14. Further, the depth of the field plate trench 42 may be equal to or different from the depth of the gate trench 14. For example, the width of the field plate trench 42 may be greater than the width of the gate trench 14, and the depth of the field plate trench 42 may be greater than the depth of the gate trench 14.
  • the semiconductor device 10 further includes a second field plate electrode 50 disposed within the field plate trench 42.
  • the second field plate electrode 50 may be an electrode configured to receive a reference voltage (or source voltage).
  • the trench in which the second field plate electrode 50 is arranged is referred to as a field plate trench 42.
  • the field plate trench 42 can also be called a trench in which the gate electrode 28 (see FIG. 2) is not arranged.
  • the second field plate electrode 50 includes a top surface 50A covered with the insulating layer 26 and a bottom surface 50B opposite to the top surface 50A.
  • the upper surface 50A of the second field plate electrode 50 may be located below the second surface 12B of the semiconductor layer 12.
  • the second field plate electrode 50 is surrounded by an insulating layer 26 .
  • the top surface 50A and bottom surface 50B of the second field plate electrode 50 may be flat or curved. Furthermore, the second field plate electrode 50 may or may not have a uniform width regardless of its position in the Z-axis direction. For example, the second field plate electrode 50 may have a smaller width closer to the bottom wall 42B of the field plate trench 42. Additionally, the second field plate electrode 50 may have a smaller width than the gate electrode 28 (see FIG. 2).
  • the second field plate electrode 50 can be formed from conductive polysilicon, in one example.
  • the first contact plug 44 is configured to couple the second field plate electrode 50 to the source electrode 38.
  • the first contact plug 44 extends through the insulating layer 26 between the upper surface 50A of the second field plate electrode 50 and the source electrode 38. Therefore, second field plate electrode 50 is electrically connected to source electrode 38.
  • the first contact plug 44 may have a smaller width than the second field plate electrode 50.
  • the second contact plug 46 is configured to couple the semiconductor layer 12 to the source electrode 38.
  • the second contact plug 46 is in contact with a contact region 48 formed within the semiconductor layer 12 .
  • the second contact plug 46 can electrically connect the contact region 48 to the source electrode 38 .
  • the second contact plug 46 extends through the insulating layer 26 between the semiconductor layer 12 and the source electrode 38.
  • the second contact plug 46 penetrates the source region 24 in the semiconductor layer 12 and extends to the body region 22 .
  • the semiconductor device 10 of this embodiment includes a gate trench 14 arranged in a mesh shape in a plan view, and a field plate trench 42 surrounded by the gate trench 14 and spaced apart from the gate trench 14 in a plan view.
  • a gate electrode 28 and a first field plate electrode 30 are arranged within the gate trench 14 .
  • a second field plate electrode 50 is arranged within the field plate trench 42 .
  • the first field plate electrode 30 and the second field plate electrode 50 are electrically connected to the source electrode 38.
  • the breakdown voltage of the semiconductor device 10 can be improved.
  • the gate electrode 28 is not arranged in the field plate trench 42, by arranging the field plate trench 42, increases in gate-drain parasitic capacitance and gate-source parasitic capacitance can be suppressed.
  • the breakdown voltage of the semiconductor device 10 can be improved.
  • FIG. 5 is a schematic plan view of a semiconductor device 100 of a comparative example.
  • the semiconductor device 100 includes gate trenches 102 arranged in a mesh shape in a plan view, like the gate trenches 14 of the semiconductor device 10.
  • Semiconductor device 100 does not include a trench that includes only an electrode to which a reference voltage (or source voltage) is applied, such as field plate trench 42 of semiconductor device 10 . Therefore, gate trenches 102 are arranged at a relatively high density. In other words, in the semiconductor device 100, the dimension of one side of the unit mesh region M' surrounded by the gate trench 102 (assumed to be A) is relatively small.
  • a second contact plug 46 may be disposed in each unit mesh region M'.
  • a gate electrode 28 and a first field plate electrode 30 similar to those shown in FIG. 2 are arranged within the gate trench 102.
  • the breakdown voltage of the semiconductor device 100 can be improved.
  • the semiconductor device 100 since the gate electrode 28 is also arranged in the gate trench 102, the semiconductor device 100 has relatively large gate-drain parasitic capacitance and gate-source parasitic capacitance.
  • the semiconductor device 10 shown in FIG. 1 is comparable to the semiconductor device 100 shown in FIG. It is expected to have the effect of improving pressure resistance. This is because the first field plate electrode 30 in the gate trench 14 and the second field plate electrode 50 in the field plate trench 42 can surround a region having an area equivalent to the unit mesh region M'. Since the gate electrode 28 is not arranged in the field plate trench 42 provided in the semiconductor device 10, the gate-drain parasitic capacitance and the gate-source parasitic capacitance in the semiconductor device 10 should be smaller than those in the semiconductor device 100. Can be done.
  • the semiconductor device 10 of this embodiment has the following advantages.
  • the semiconductor device 10 includes a gate trench 14 arranged in a mesh shape in a plan view, and a field plate trench 42 surrounded by the gate trench 14 and spaced apart from the gate trench 14 in a plan view.
  • a gate electrode 28 and a first field plate electrode 30 are arranged within the gate trench 14 .
  • a second field plate electrode 50 is arranged within the field plate trench 42 .
  • the first field plate electrode 30 and the second field plate electrode 50 are electrically connected to the source electrode 38. Therefore, the breakdown voltage of the semiconductor device 10 can be improved while suppressing increases in the gate-drain parasitic capacitance and the gate-source parasitic capacitance.
  • the semiconductor device 10 may further include a first contact plug 44 configured to couple the second field plate electrode 50 to the source electrode 38.
  • the first contact plug 44 extends through the insulating layer 26 between the upper surface 50A of the second field plate electrode 50 and the source electrode 38.
  • the field plate trench 42 may be formed in a cross shape in plan view. Thereby, local electric field concentration in the unit mesh region M can be alleviated relatively uniformly.
  • the semiconductor layer 12 includes a first conductivity type contact region 48, and the contact region 48 is in contact with the second contact plug 46. Thereby, electrical connection between the source electrode 38 and the semiconductor layer 12 via the second contact plug 46 can be ensured.
  • FIG. 6 is a schematic cross-sectional view of the field plate trench 42 of the semiconductor device 200 according to the first modification.
  • the same components as those of the semiconductor device 10 are given the same reference numerals. Furthermore, detailed description of the same components as those of the semiconductor device 10 will be omitted.
  • the semiconductor device 200 further includes a third field plate electrode 202.
  • the third field plate electrode 202 is arranged below the bottom surface 50B of the second field plate electrode 50 within the field plate trench 42. More specifically, the third field plate electrode 202 is arranged between the bottom surface 50B of the second field plate electrode 50 and the bottom wall 42B of the field plate trench 42.
  • the second field plate electrode 50 and the third field plate electrode 202 of the semiconductor device 200 can have shapes similar to the gate electrode 28 and the first field plate electrode 30 shown in FIG. 2, respectively.
  • the first contact plug 44 is further configured to couple the third field plate electrode 202 to the source electrode 38.
  • the first contact plug 44 extends through the second field plate electrode 50 to the third field plate electrode 202 .
  • the first contact plug 44 may extend below the upper surface 202A of the third field plate electrode 202.
  • the second field plate electrode 50 and the third field plate electrode 202 are electrically connected to the source electrode 38, so like the semiconductor device 10, the breakdown voltage can be improved. Further, the second field plate electrode 50 and the third field plate electrode 202 in the field plate trench 42 can be formed by the same manufacturing process as the gate electrode 28 and the first field plate electrode 30 in the gate trench 14. Therefore, the semiconductor device 200 can be realized through a relatively simplified manufacturing process.
  • FIG. 7 is a schematic plan view of an exemplary semiconductor device 300 according to a second modification.
  • the same components as those of the semiconductor device 10 are given the same reference numerals. Furthermore, detailed description of the same components as those of the semiconductor device 10 will be omitted.
  • FIG. 7 shows a region including one unit mesh region M surrounded by gate trenches 14. As shown in FIG.
  • the field plate trench 42 includes a first trench 302 extending in the Y-axis direction in plan view, and a second trench 304 extending in the X-axis direction in plan view and spaced apart from the first trench 302. and a third trench 306.
  • the first trench 302 extends between the second trench 304 and the third trench 306 in plan view.
  • the field plate trench 42 may include a plurality of independent trenches 302, 304, 306.
  • the first contact plug 44 can be arranged so as to overlap each trench 302, 304, 306 in plan view.
  • FIG. 8 is a schematic plan view of an exemplary semiconductor device 400 according to a third modification.
  • the same components as those of the semiconductor device 10 are given the same reference numerals. Furthermore, detailed description of the same components as those of the semiconductor device 10 will be omitted.
  • the unit mesh region M surrounded by the gate trenches 14 arranged in a mesh shape in a plan view has a rectangular shape in a plan view.
  • the dimension of the unit mesh region M in the X-axis direction is smaller than the dimension of the unit mesh region M in the Y-axis direction.
  • FIG. 9 is an enlarged plan view of the semiconductor device 400 of FIG. 8.
  • FIG. 9 shows a region F9 surrounded by a dashed line in FIG. 8, which includes one unit mesh region M surrounded by the gate trench 14. As shown in FIG.
  • the field plate trench 42 may be formed in a rectangular shape in plan view.
  • the field plate trench 42 extends in the X-axis direction and has a width in the Y-axis direction in plan view. That is, the longitudinal direction of the field plate trench 42 is the X-axis direction.
  • the field plate trench 42 is arranged near the center of the unit mesh area M.
  • the first contact plug 44 is arranged so as to overlap the field plate trench 42 in plan view.
  • the first contact plug 44 like the field plate trench 42, extends in the X-axis direction and has a width in the Y-axis direction in plan view.
  • the second contact plug 46 is arranged between the gate trench 14 and the field plate trench 42 in plan view.
  • a square-shaped second contact plug 46 is arranged in the middle between the gate trench 14 and the field plate trench 42 in the Y-axis direction.
  • Two second contact plugs 46 are arranged in each unit mesh area M.
  • FIG. 10 is a schematic plan view of an exemplary semiconductor device 500 according to a fourth modification.
  • the same components as those of the semiconductor device 10 are given the same reference numerals. Furthermore, detailed description of the same components as those of the semiconductor device 10 will be omitted.
  • FIG. 10 shows a region including one unit mesh region M surrounded by gate trenches 14. As shown in FIG.
  • the second contact plug 46 extends in the Y-axis direction in plan view and has a width in the X-axis direction. That is, the longitudinal direction of the second contact plug 46 is the Y-axis direction.
  • a line-shaped second contact plug 46 is used. It is arranged near the field plate trench 42 between the gate trench 14 and the field plate trench 42. Two second contact plugs 46 are arranged in each unit mesh area M.
  • the shape of the unit mesh area M is not limited to a rectangular shape in plan view.
  • the unit mesh area M may be triangular or hexagonal in plan view.
  • the conductivity type of each region within the semiconductor layer 12 may be reversed. That is, the p-type region may be made into an n-type region, and the n-type region may be made into a p-type region.
  • the term “on” includes the meanings of “on” and “over” unless the context clearly indicates otherwise.
  • the phrase “the first layer is formed on the second layer” refers to the fact that in some embodiments the first layer may be directly disposed on the second layer in contact with the second layer, but in other embodiments. It is contemplated that the first layer may be placed above the second layer without contacting the second layer. That is, the term “on” does not exclude structures in which other layers are formed between the first layer and the second layer.
  • the Z-axis direction used in this specification does not necessarily need to be a vertical direction, nor does it need to completely coincide with the vertical direction.
  • the X-axis direction may be a vertical direction
  • the Y-axis direction may be a vertical direction.
  • FIG. 1 (Additional note 2) further comprising a first contact plug (44) configured to couple the second field plate electrode (50) to the source electrode (38);
  • the first contact plug (44) extends through the insulating layer (26) between the upper surface (50A) of the second field plate electrode (50) and the source electrode (38).
  • Appendix 5 The semiconductor device according to any one of appendices 1 to 3, wherein the field plate trench (42) is formed in a rectangular shape in plan view.
  • the field plate trench (42) includes a first trench (302) extending in a first direction in a plan view, and a first trench (302) extending in a second direction orthogonal to the first direction in a plan view. 302), the first trench (302) includes a second trench (304) and a third trench (306) separated from each other in a plan view.
  • the semiconductor device according to any one of Supplementary Notes 1 to 3, which extends between.
  • the semiconductor layer (12) includes a second conductivity type drift region (20), a first conductivity type body region (22) formed on the drift region (20), and a first conductivity type body region (22) formed on the body region (22). a second conductivity type source region (24) formed in The gate trench (14) and the field plate trench (42) extend through the source region (24) and the body region (22) to the drift region (20), The semiconductor device according to any one of the above.
  • Appendix 8 further comprising a second contact plug (46) configured to couple the semiconductor layer (12) to the source electrode (38), the second contact plug (46) connecting the semiconductor layer (12) and the source electrode (38);
  • the semiconductor device according to any one of appendices 1 to 7, which extends through the insulating layer (26) between the source electrode (38) and the insulating layer (26).
  • the second field plate electrode (50) includes a bottom surface (50B) opposite to the top surface (50A),
  • the semiconductor device includes: Supplementary Notes 2 to 10, further comprising a third field plate electrode (202) disposed below the bottom surface (50B) of the second field plate electrode (50) in the field plate trench (42).
  • the semiconductor device according to any one of the above.
  • the first contact plug (44) is further configured to couple the third field plate electrode (202) to the source electrode (38) and extends through the second field plate electrode (50).
  • the semiconductor layer (12) includes a plurality of unit mesh regions (M) surrounded by the gate trench (14), each of the plurality of unit mesh regions (M) having a rectangular shape in plan view.
  • the semiconductor device according to any one of Supplementary Notes 1 to 12.
  • the semiconductor layer (12) includes a plurality of unit mesh regions (M) surrounded by the gate trench (14), each of the plurality of unit mesh regions (M) having a square shape in a plan view.
  • the semiconductor device according to any one of Supplementary Notes 1 to 12.
  • Appendix 15 15. The semiconductor device according to appendix 13 or 14, wherein the field plate trench (42) is one of a plurality of field plate trenches (42) arranged in each of the plurality of unit mesh regions (M).

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DE112023001369.1T DE112023001369T5 (de) 2022-03-14 2023-01-13 Halbleiterbauteil
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JP2024043424A (ja) * 2022-09-16 2024-03-29 サンケン電気株式会社 半導体装置

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EP4270487A1 (en) * 2022-04-28 2023-11-01 Infineon Technologies Austria AG Power transistor device and method of fabricating a transistor device

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JP2017045776A (ja) * 2015-08-24 2017-03-02 ローム株式会社 半導体装置およびその製造方法
JP2017112134A (ja) * 2015-12-14 2017-06-22 富士電機株式会社 半導体装置
JP2019057537A (ja) * 2017-09-19 2019-04-11 株式会社東芝 半導体装置
JP2020167333A (ja) * 2019-03-29 2020-10-08 ローム株式会社 半導体装置

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Publication number Priority date Publication date Assignee Title
JP2017045776A (ja) * 2015-08-24 2017-03-02 ローム株式会社 半導体装置およびその製造方法
JP2017112134A (ja) * 2015-12-14 2017-06-22 富士電機株式会社 半導体装置
JP2019057537A (ja) * 2017-09-19 2019-04-11 株式会社東芝 半導体装置
JP2020167333A (ja) * 2019-03-29 2020-10-08 ローム株式会社 半導体装置

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2024043424A (ja) * 2022-09-16 2024-03-29 サンケン電気株式会社 半導体装置
JP7841399B2 (ja) 2022-09-16 2026-04-07 サンケン電気株式会社 半導体装置

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