WO2023175827A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2023175827A1
WO2023175827A1 PCT/JP2022/012234 JP2022012234W WO2023175827A1 WO 2023175827 A1 WO2023175827 A1 WO 2023175827A1 JP 2022012234 W JP2022012234 W JP 2022012234W WO 2023175827 A1 WO2023175827 A1 WO 2023175827A1
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WO
WIPO (PCT)
Prior art keywords
layer
conductivity type
semiconductor
grooves
contact layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2022/012234
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English (en)
French (fr)
Japanese (ja)
Inventor
喜之 小川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
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Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to US18/723,091 priority Critical patent/US20250087970A1/en
Priority to CN202280093159.5A priority patent/CN118830155A/zh
Priority to PCT/JP2022/012234 priority patent/WO2023175827A1/ja
Priority to JP2024507340A priority patent/JPWO2023175827A1/ja
Publication of WO2023175827A1 publication Critical patent/WO2023175827A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
    • H01S5/2205—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure comprising special burying or current confinement layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/026—Monolithically integrated components, e.g. waveguides, monitoring photo-detectors, drivers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
    • H01S5/2202—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure by making a groove in the upper laser structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
    • H01S5/223—Buried stripe structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/30—Structure or shape of the active region; Materials used for the active region
    • H01S5/34—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers
    • H01S5/343—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser
    • H01S5/34306—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser emitting light at a wavelength longer than 1000nm, e.g. InP based 1300 and 1500nm lasers

Definitions

  • the present disclosure relates to a semiconductor device, and particularly to a semiconductor device with improved electrostatic discharge (ESD) breakdown resistance.
  • ESD electrostatic discharge
  • Semiconductor devices may be damaged by ESD. If it is an integrated circuit, it is possible to increase the ESD breakdown capacity by incorporating a protection circuit, but in the case of a discrete element such as a semiconductor laser element, it is necessary to rely on the ESD breakdown capacity of the element itself.
  • Patent Document 1 discloses that, separately from the resonator section, a p-type/i-type/p-type structure is formed in the case of a p-type substrate, and an n-type/i-type/n-type structure is formed in the case of an n-type substrate.
  • a semiconductor laser device with improved ESD breakdown resistance using the structure has been disclosed.
  • the present disclosure has been made to solve the above problems, and aims to provide a semiconductor device that does not require an increase in the number of man-hours and has improved ESD breakdown resistance.
  • a semiconductor device includes a semiconductor substrate of a first conductivity type in which a back electrode is formed on the back surface, a lower cladding layer of the first conductivity type formed on the front surface of the semiconductor substrate, and a lower cladding layer of the first conductivity type.
  • the layers of the second conductivity type, the first conductivity type, and the second conductivity type are laminated, and the first two grooves are formed in the composite layer consisting of the layers from the block layer to the contact layer, and a ridge portion is formed.
  • the contact layer above the contact layer and the contact layer sandwiched between the first two grooves are connected by a first electrode.
  • Another semiconductor device includes a semiconductor substrate of a first conductivity type in which a back electrode is formed on the back surface, a lower cladding layer of the first conductivity type formed on the front surface of the semiconductor substrate, and a lower cladding layer of the first conductivity type formed on the front surface of the semiconductor substrate.
  • an MQW section formed on the cladding layer; a ridge section having a second conductivity type upper cladding layer formed on the MQW section; and a block layer embedded on the semiconductor substrate on both sides of the ridge section.
  • a contact layer formed on an upper cladding layer further formed on the ridge portion and the block layer, and the semiconductor layer consisting of the semiconductor substrate, the block layer and the contact layer has a first conductive layer formed at least from below.
  • the layers of the mold, the second conductivity type, the first conductivity type, and the second conductivity type are laminated, and the first two grooves are formed in the composite layer consisting of the layers from the block layer to the contact layer.
  • Two second grooves are formed in the composite layer, and the contact layer above the ridge portion and the first region of the contact layer sandwiched between the second two grooves are connected by the first electrode.
  • a second region of the contact layer sandwiched between the second two grooves and a contact layer sandwiched between the first two grooves are connected by a second electrode.
  • a semiconductor device with improved ESD breakdown resistance can be obtained without increasing the number of man-hours.
  • FIG. 1 is a perspective view of a semiconductor device according to a first embodiment;
  • FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment.
  • 1 is a cross-sectional view showing a method for manufacturing a semiconductor device according to a first embodiment;
  • FIG. 1 is a cross-sectional view showing a method for manufacturing a semiconductor device according to a first embodiment;
  • FIG. 1 is a cross-sectional view showing a method for manufacturing a semiconductor device according to a first embodiment;
  • FIG. 1 is a cross-sectional view showing a method for manufacturing a semiconductor device according to a first embodiment;
  • FIG. 1 is a cross-sectional view showing a method for manufacturing a semiconductor device according to a first embodiment;
  • FIG. 1 is a cross-sectional view showing a method for manufacturing a semiconductor device according to a first embodiment;
  • FIG. 1 is a cross-sectional view showing a method for manufacturing a semiconductor device according to a first embodiment;
  • FIG. 1 is a cross-sectional view showing a method for manufacturing a semiconductor device according to a first embodiment
  • FIG. FIG. 2 is a perspective view of a semiconductor device according to a second embodiment.
  • FIG. 2 is a cross-sectional view of a semiconductor device according to a second embodiment.
  • FIG. 3 is a cross-sectional view of a semiconductor device according to a third embodiment.
  • FIG. 4 is a cross-sectional view of a semiconductor device according to a fourth embodiment.
  • Embodiment 1 The semiconductor device 10 according to the first embodiment is a distributed feedback (DFB) semiconductor laser element.
  • a perspective view of the semiconductor device 10 is shown in FIG.
  • a cross-sectional view taken along line AA in FIG. 1 is shown in FIG. Note that the dimensions and scale of each part in the drawings, including these, may differ from drawing to drawing.
  • DFB distributed feedback
  • the semiconductor device 10 includes a semiconductor substrate 12.
  • the semiconductor substrate 12 is made of p-type InP.
  • a back electrode 14 is formed on the back surface of the semiconductor substrate 12 .
  • a ridge portion 22 is formed on the surface of the semiconductor substrate 12.
  • the ridge portion 22 includes a lower cladding layer 16 , an MQW portion 18 formed on the lower cladding layer 16 , and an upper cladding layer 20 formed on the MQW portion 18 .
  • the lower cladding layer 16 is made of p-type InP.
  • the MQW section 18 is made of InP and includes multiple quantum wells (MQW).
  • the upper cladding layer 20 is made of n-type InP.
  • the ridge portion 22 is a resonator in which laser light resonates.
  • Block layers 36 are embedded on both sides of the ridge portion 22.
  • the block layer 36 is embedded on the semiconductor substrate 12 on both sides of the ridge portion 22, and includes, from below, a first semiconductor layer 28 of a first conductivity type, a second semiconductor layer 30 of a second conductivity type, and a second semiconductor layer 30 of an i-type conductivity type.
  • An i-type semiconductor layer 32 and a first conductivity type third semiconductor layer 34 are stacked.
  • the i-type semiconductor layer here refers to a semiconductor layer into which carriers are not injected. All of these layers are made of InP.
  • the blocking layer 36 is a current confinement layer that allows current to flow only to the ridge portion 22. Note that the i-type semiconductor layer 32 may not be provided. Further, an i-type semiconductor layer may be inserted between any of the layers constituting the block layer 36. This inserted layer may be an i-type semiconductor layer doped with Fe.
  • a contact layer 38 in which n-type InP and n-type InGaAs are laminated is formed on the upper cladding layer 20 which is further formed on the ridge portion 22 and the block layer 36.
  • Two grooves 26 are dug in the block layers 36 on the left and right sides of the ridge portion 22 so as to sandwich the ridge portion 22 therebetween. These grooves 26 provide electrical isolation between the ridge portion 22 and other portions.
  • Two first grooves 42 are formed in a composite layer 40 consisting of layers from the block layer 36 to the contact layer 38.
  • the semiconductor layer from the contact layer 38 to the semiconductor substrate 12 in the region between the first two grooves 42 is a voltage clamp section 46 that clamps the voltage.
  • This semiconductor layer may include at least p-type, n-type, p-type, and n-type layers laminated from the bottom.
  • the first semiconductor layer 28 is p-type
  • the second semiconductor layer 30 is n-type
  • the third semiconductor layer 34 is p-type
  • the contact layer 38 is n-type. Note that one of the two grooves 26 and one of the first two grooves 42 may be the same groove.
  • An insulating film 48 is formed on the contact layer 38 and the groove.
  • the insulating film 48 has an opening above the ridge portion 22 and the voltage clamp portion 46 .
  • the contact layer 38 sandwiched between the first two grooves 42 and the contact layer 38 above the ridge portion 22 are connected by a first electrode 50. Further, the lower part of the voltage clamp part 46 sandwiched between the first two grooves 42 and the lower part of the ridge part 22 are electrically connected via the back electrode 14. Therefore, the voltage clamp section 46 and the ridge section 22 are electrically connected in parallel.
  • the first electrode 50 is connected to a pad electrode 52.
  • a lower cladding layer 16, an MQW section 18, and an upper cladding layer 20 are sequentially formed on a semiconductor substrate 12 on which a back electrode 14 is formed.
  • the portions from the upper cladding layer 20 to the lower cladding layer 16 are etched, leaving the ridge portion 22.
  • block layers 36 are embedded on both sides of the ridge portion 22.
  • the upper cladding layer 20 and the contact layer 38 are formed on the ridge portion 22 and the block layer 36.
  • grooves are formed on both sides of the ridge portion 22 and the voltage clamp portion 46 by etching.
  • the first two grooves 42 are formed in this step.
  • an insulating film 48 is formed on the contact layer 38 and the groove.
  • the semiconductor device 10 of FIG. 1 is formed.
  • the ridge section 22 can be protected from ESD, and the ESD breakdown resistance of the semiconductor device is improved. can.
  • the voltage clamp section is formed using the contact layer, the blocking layer as the current confinement layer, and the semiconductor substrate, and the first two grooves are also formed at the same time as the grooves on the left and right sides of the ridge section. Therefore, there is no increase in man-hours.
  • Embodiment 2 Unlike the first embodiment, in the semiconductor device 210 according to the second embodiment, a resistor section 262 is connected between the ridge section 222 and the voltage clamp section 46. A perspective view of the semiconductor device 210 is shown in FIG. A cross-sectional view taken along line BB in FIG. 9 is shown in FIG.
  • Two second grooves 244 are formed in the composite layer 40.
  • the composite layer 40 sandwiched between the second two grooves is the resistance section 262.
  • the ends of the resistive portion 262 are the first region 254 and the second region 256 of the contact layer 38 sandwiched between the second two grooves 244 .
  • one of the first two grooves 42 and one of the second two grooves 244 may be the same groove.
  • the contact layer 38 on the ridge portion 222 and the first region 254 are connected by the first electrode 50, and the second region 256 and the contact layer 38 sandwiched between the first two grooves 42 are connected to the first region 254.
  • the two electrodes 258 are connected to each other. That is, the resistor section 262 is connected between the ridge section 222 and the voltage clamp section 46.
  • the ESD breakdown resistance of the semiconductor device can be further improved.
  • the resistance portion is formed using the contact layer to the block layer as the current confinement layer, and the second two grooves are also formed at the same time as the grooves on the left and right sides of the ridge portion. Therefore, there is no increase in man-hours.
  • Embodiment 3 Unlike the first embodiment, the semiconductor device 310 according to the third embodiment deletes the i-type semiconductor layer forming the block layer 336 and replaces the second semiconductor layer with an i-type semiconductor layer 360 doped with Fe. ing. A cross-sectional view of the semiconductor device 310 is shown in FIG.
  • the voltage clamp section 346 has such a structure, it has the effect of clamping the voltage, and has the same effect as the first embodiment. Further, by doping the i-type semiconductor layer 360 with Fe, the current confinement effect is enhanced.
  • the semiconductor device has an electro-absorption (EA) modulator section (EA section 464) connected to the DFB section.
  • EA electro-absorption
  • the basic configuration of the EA section 464 is the same as that of the DFB section, and the voltage applied to the EA electrode 466 modulates the laser light generated in the DFB section. Specifically, the laser beam generated at the ridge portion of the DFB section is modulated by the ridge section 422 of the EA section 464.
  • FIG. 464 A cross-sectional view of the EA section 464 is shown in FIG. Unlike the DFB section, in the EA section 464, the side surface of the ridge section 422 is covered with an insulating film 448.
  • the voltage clamp section 446 has the effect of clamping the voltage, and has the same effect as in the first embodiment.
  • the semiconductor substrate is p-type and the contact layer is n-type, but the semiconductor substrate may be n-type and the contact layer may be p-type.
  • the semiconductor substrate may be n-type and the contact layer may be p-type.
  • the semiconductor substrate may be n-type and the contact layer may be p-type.
  • the semiconductor substrate may be n-type and the contact layer may be p-type.
  • the semiconductor substrate may be n-type and the contact layer may be p-type.
  • the semiconductor substrate is of the first conductivity type and the contact layer is of the second conductivity type.
  • the semiconductor substrate is of the first conductivity type and the contact layer is of the second conductivity type.
  • the first conductivity type is p type and the second conductivity type is n type
  • the first conductivity type is n type and the second conductivity type is p type.
  • the fact that pn inversion is possible and that it can be expressed as a first conductivity type and a second conductivity type applies to all embodiment
  • 10,210,310 semiconductor device 12, semiconductor substrate, 14 back electrode, 16,416 lower cladding layer, 18,418 MQW part, 20,420 upper cladding layer, 22,222,422 ridge part, 26,426 groove, 28 First semiconductor layer, 30 Second semiconductor layer, 32,360 i-type semiconductor layer, 34 Third semiconductor layer, 36,336 Block layer, 38 Contact layer, 40 Composite layer, 42 First two grooves , 244 second two grooves, 46, 346, 446 voltage clamp section, 48, 448 insulating film, 50 first electrode, 52, 452 pad electrode, 254 first region, 256 second region, 258 2 electrode, 262 resistance part, 464 EA part, 466 EA electrode

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Geometry (AREA)
  • Semiconductor Lasers (AREA)
PCT/JP2022/012234 2022-03-17 2022-03-17 半導体装置 Ceased WO2023175827A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US18/723,091 US20250087970A1 (en) 2022-03-17 2022-03-17 Semiconductor apparatus
CN202280093159.5A CN118830155A (zh) 2022-03-17 2022-03-17 半导体装置
PCT/JP2022/012234 WO2023175827A1 (ja) 2022-03-17 2022-03-17 半導体装置
JP2024507340A JPWO2023175827A1 (https=) 2022-03-17 2022-03-17

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2022/012234 WO2023175827A1 (ja) 2022-03-17 2022-03-17 半導体装置

Publications (1)

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WO2023175827A1 true WO2023175827A1 (ja) 2023-09-21

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PCT/JP2022/012234 Ceased WO2023175827A1 (ja) 2022-03-17 2022-03-17 半導体装置

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JP (1) JPWO2023175827A1 (https=)
CN (1) CN118830155A (https=)
WO (1) WO2023175827A1 (https=)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11186661A (ja) * 1997-12-24 1999-07-09 Hitachi Ltd 変調器付半導体レーザ
JP2010287604A (ja) * 2009-06-09 2010-12-24 Nec Corp 導波路型光素子及びその製造方法
US20140233595A1 (en) * 2013-02-15 2014-08-21 Avago Technologies General Ip (Singapore) Pte. Ltd. Vertical Cavity Surface Emitting Laser With An Integrated Protection Diode
JP2019054107A (ja) * 2017-09-14 2019-04-04 日本電信電話株式会社 半導体光素子
JP2019134140A (ja) * 2018-02-02 2019-08-08 住友電気工業株式会社 半導体面発光装置
JP2019201169A (ja) * 2018-05-18 2019-11-21 富士ゼロックス株式会社 発光素子アレイ、発光素子アレイの製造方法、および光伝送装置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3941296B2 (ja) * 1999-09-20 2007-07-04 三菱電機株式会社 変調器と変調器付き半導体レーザ装置並びにその製造方法
JP5573386B2 (ja) * 2010-06-10 2014-08-20 三菱電機株式会社 半導体光集積素子及びその製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11186661A (ja) * 1997-12-24 1999-07-09 Hitachi Ltd 変調器付半導体レーザ
JP2010287604A (ja) * 2009-06-09 2010-12-24 Nec Corp 導波路型光素子及びその製造方法
US20140233595A1 (en) * 2013-02-15 2014-08-21 Avago Technologies General Ip (Singapore) Pte. Ltd. Vertical Cavity Surface Emitting Laser With An Integrated Protection Diode
JP2019054107A (ja) * 2017-09-14 2019-04-04 日本電信電話株式会社 半導体光素子
JP2019134140A (ja) * 2018-02-02 2019-08-08 住友電気工業株式会社 半導体面発光装置
JP2019201169A (ja) * 2018-05-18 2019-11-21 富士ゼロックス株式会社 発光素子アレイ、発光素子アレイの製造方法、および光伝送装置

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US20250087970A1 (en) 2025-03-13

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