WO2023173603A1 - 一种存储器及其制备方法 - Google Patents

一种存储器及其制备方法 Download PDF

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Publication number
WO2023173603A1
WO2023173603A1 PCT/CN2022/097926 CN2022097926W WO2023173603A1 WO 2023173603 A1 WO2023173603 A1 WO 2023173603A1 CN 2022097926 W CN2022097926 W CN 2022097926W WO 2023173603 A1 WO2023173603 A1 WO 2023173603A1
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Prior art keywords
layer
substrate
oxide semiconductor
source
integrated circuit
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PCT/CN2022/097926
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English (en)
French (fr)
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杨蒙蒙
白杰
肖德元
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长鑫存储技术有限公司
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Priority to EP22792732.4A priority Critical patent/EP4270478A4/en
Priority to US17/933,264 priority patent/US20230011186A1/en
Publication of WO2023173603A1 publication Critical patent/WO2023173603A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B80/00—Assemblies of multiple devices comprising at least one memory device covered by this subclass

Definitions

  • Embodiments of the present disclosure relate to, but are not limited to, a memory and a preparation method thereof.
  • DRAM Dynamic Random Access Memory
  • the peripheral circuit structure and the storage circuit structure are usually formed on the same substrate, and the required substrate area is large, resulting in a significant increase in manufacturing costs.
  • the memory size is large and the array efficiency is low.
  • An embodiment of the present disclosure provides a memory, which includes:
  • a plurality of stacked semiconductor structures including:
  • the first substrate includes peripheral circuit structures
  • a first integrated circuit layer is provided on the first substrate, and the first integrated circuit layer is electrically connected to the peripheral circuit structure;
  • a second substrate is provided on the first integrated circuit layer, a first dielectric layer is provided between the first integrated circuit layer and the second substrate, and the second substrate includes a memory circuit structure;
  • the first substrate and the second substrate include semiconductor layers.
  • the first substrate includes a first oxide semiconductor layer
  • the second substrate includes a second oxide semiconductor layer
  • the thickness of the first oxide semiconductor layer is greater than the thickness of the second oxide semiconductor layer.
  • the second oxide semiconductor layer includes an amorphous structure.
  • the semiconductor structure further includes a second dielectric layer located between the first substrate and the first integrated circuit layer, and a third dielectric layer located within the first dielectric layer.
  • the first substrate further includes a gate layer and first source/drain layers and second source/drain layers located on both sides of the gate layer. layer, the first source/drain layer and the second source/drain layer are located on the first oxide semiconductor layer; wherein the first oxide semiconductor layer serves as a channel layer of the peripheral circuit structure, The first source/drain layer and the second source/drain layer are electrically connected to the first integrated circuit layer through the second conductive plug.
  • the second substrate further includes an isolation structure, a plurality of word lines extending along the first direction, and a plurality of bit lines extending along the second direction; wherein, the isolation structure
  • the second oxide semiconductor layer is defined as a plurality of discrete active areas, a plurality of word lines pass through the active area and the isolation area, and each active area includes a third in the middle A source/drain region and second source/drain regions located on both sides, the bit line is electrically connected to the first source/drain region.
  • the semiconductor structure further includes a storage capacitor layer for storing information and a second integrated circuit layer located above the storage capacitor layer; the storage capacitor layer is located on the third above the two substrates and electrically connected to the second source/drain region; the second integrated circuit layer is located above the storage capacitor layer and electrically connected to the storage capacitor layer.
  • the doping concentration in the second oxide semiconductor layer may be less than or equal to the doping concentration in the first oxide semiconductor layer.
  • An embodiment of the present disclosure also provides a method for preparing a memory, the method including:
  • first substrate including peripheral circuit structures
  • the second substrate including a memory circuit structure
  • the first substrate and the second substrate include semiconductor layers.
  • the first substrate includes a first oxide semiconductor layer, a gate layer, and first source/drain layers and second source/drain layers located on both sides of the gate layer. layer; forming the first substrate, including: forming the first oxide semiconductor layer, the first oxide semiconductor layer serving as a channel layer of the peripheral circuit structure; forming on the first oxide semiconductor layer the first source/drain layer and the second source/drain layer; the gate layer is formed between the first source/drain layer and the second source/drain layer.
  • the method before forming the first integrated circuit layer on the first substrate, the method further includes: forming a second dielectric layer on the first substrate; Second conductive plugs are formed in the two dielectric layers, and the first source/drain layer and the second source/drain layer are electrically connected to the first integrated circuit layer through the second conductive plugs.
  • the second substrate includes a second oxide semiconductor layer, an isolation layer, a plurality of word lines extending along a first direction, and a plurality of bit lines extending along a second direction;
  • Forming the second substrate includes: forming a second oxide semiconductor layer and an isolation layer, wherein the isolation layer defines the second oxide semiconductor layer into a plurality of discrete active regions; forming a second oxide semiconductor layer through the isolation layer;
  • a plurality of the word lines in the active area and the isolation area, each of the active areas includes a first source/drain area located in the middle and a second source/drain area located on both sides; in the active area
  • a plurality of bit lines are formed on the region and the isolation region, and the bit lines are electrically connected to the first source/drain region.
  • the memory further includes a storage capacitor layer for storing information and a second integrated circuit layer located on the storage capacitor layer; the method further includes: The storage capacitor layer is formed above the two substrates; the second integrated circuit layer is formed on the storage capacitor layer, and the second integrated circuit layer is electrically connected to the storage capacitor layer.
  • the method before forming the second substrate on the first dielectric layer, the method further includes: forming a first conductive plug in the first dielectric layer, the third A conductive plug electrically connects the first integrated circuit layer and the second substrate.
  • Figure 1 is a schematic structural diagram of a memory provided by an embodiment of the present disclosure
  • Figure 2 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 3 is a schematic structural diagram of a first substrate provided by an embodiment of the present disclosure.
  • Figure 4a is a schematic top view of the second substrate provided by an embodiment of the present disclosure.
  • Figures 4b and 4c are detailed cross-sectional views of the second substrate provided by the embodiment of the present disclosure along the A1-A2 direction and B1-B2 direction of Figure 4a;
  • Figure 5 is a schematic structural diagram of a storage capacitor layer provided by an embodiment of the present disclosure.
  • Figure 6 is a flow chart of a memory preparation method provided by an embodiment of the present disclosure.
  • the peripheral circuit structure and the storage circuit structure are usually formed on different areas of the same substrate.
  • the layout or occupied area of at least one of the peripheral circuit structure or the storage circuit structure changes, the area of the substrate It will passively increase or decrease; when encountering a situation where the substrate area cannot be changed at will, the above changes will also significantly increase the designer's workload.
  • the required substrate area is large, which greatly increases the manufacturing cost, and the memory is large in size and has low array efficiency.
  • An embodiment of the present disclosure provides a memory, including:
  • a plurality of stacked semiconductor structures including:
  • the first substrate includes peripheral circuit structures
  • a first integrated circuit layer is provided on the first substrate, and the first integrated circuit layer is electrically connected to the peripheral circuit structure;
  • a second substrate is provided on the first integrated circuit layer, a first dielectric layer is provided between the first integrated circuit layer and the second substrate, and the second substrate includes a memory circuit structure;
  • the first substrate and the second substrate include semiconductor layers.
  • the memory provided by the embodiment of the present disclosure includes multiple stacked semiconductor structures, which can effectively improve the integration level of the memory; at the same time, the peripheral circuit and the storage circuit structure in the semiconductor structure are respectively located on the first substrate and the second substrate.
  • the longitudinal distribution between the first substrate and the second substrate can significantly reduce the volume of the memory and improve the array efficiency of the memory.
  • a first integrated circuit and a first dielectric layer are sequentially disposed between the first substrate and the second substrate, respectively used to form electrical connections between the peripheral circuit structure and the storage circuit structure and to form electrical connections in areas that do not require electrical connections. Good electrical isolation effect. Therefore, the memory provided by the embodiments of the present disclosure has higher integration level and array efficiency and smaller size than the traditional structure.
  • FIG. 1 is a schematic structural diagram of a memory provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of a first substrate provided by an embodiment of the present disclosure
  • FIG. 4a is a schematic structural diagram of a first substrate provided by an embodiment of the present disclosure.
  • Figures 4b and 4c are detailed cross-sectional views of the second substrate provided by the embodiment of the present disclosure along the A1-A2 direction and B1-B2 direction of Figure 4a;
  • Figure 5 is a detailed cross-sectional view of the second substrate provided by the embodiment of the present disclosure.
  • a schematic diagram of the structure of the storage capacitor layer is provided.
  • the memory 1 includes: a plurality of stacked semiconductor structures 10.
  • the semiconductor structures 10 include:
  • the first substrate 110 includes a peripheral circuit structure P1;
  • a first integrated circuit layer 14 is provided on the first substrate 110, and the first integrated circuit layer 14 is electrically connected to the peripheral circuit structure P1;
  • the second substrate 120 is disposed on the first integrated circuit layer 14.
  • a first dielectric layer 21 is disposed between the first integrated circuit layer 14 and the second substrate 120.
  • the second substrate 120 includes a storage device. Circuit structure C1;
  • the first substrate 110 and the second substrate 120 include semiconductor layers.
  • the first substrate 110 includes a first oxide semiconductor layer L1
  • the second substrate 120 includes a second oxide semiconductor layer L2.
  • the materials of the first oxide semiconductor layer and the second oxide semiconductor layer include indium oxide, tin oxide, In-Zn type oxide, Sn-Zn type oxide, Al-Zn type oxide, In-Ga-based oxides, In-Ga-Zn-based oxides, In-Al-Zn-based oxides, In-Sn-Zn-based oxides, Sn-Ga-Zn-based oxides, Al-Ga-Zn-based oxides At least one of Sn-Al-Zn oxides.
  • the materials of the first oxide semiconductor layer and the second oxide semiconductor layer may also include In-Hf-Zn-based oxides, In-La-Zn-based oxides, In-Ce-Zn Oxides, In-Pr-Zn oxides, In-Nd-Zn oxides, In-Sm-Zn oxides, In-Eu-Zn oxides, In-Gd-Zn oxides, In -Tb-Zn type oxide, In-Dy-Zn type oxide, In-Ho-Zn type oxide, In-Er-Zn type oxide, In-Tm-Zn type oxide, In-Yb-Zn type oxides, In-Lu-Zn oxides; and quaternary metal oxides such as In-Sn-Ga-Zn oxides, In-Hf-Ga-Zn oxides, In-Al-Ga-Zn oxides Materials, In-Sn-Al-Zn oxides, In-Sn-Hf-Zn oxides, In-Sn-Hf-
  • a material containing at least indium (In) or zinc (Zn) may be selected as a material of the first oxide semiconductor layer and the second oxide semiconductor layer.
  • materials containing indium (In) and zinc (Zn) are preferred.
  • a material may be selected that also contains the stabilizer gallium (Ga) element, which can reduce the variation in the electrical characteristics of the finally formed transistor.
  • the materials of the first oxide semiconductor layer and the second oxide semiconductor layer include but are not limited to indium gallium zinc oxide (IGZO), such as a material with a chemical formula of InGaZnO 4 .
  • IGZO indium gallium zinc oxide
  • the thickness range of the indium gallium zinc oxide (IGZO) can be between 10nm and 500nm, such as: 50nm, 100nm, 150nm, 200nm, 300nm, 400nm, etc.
  • the ratio between the elements of indium (In), gallium (Ga), and zinc (Zn) may be 1:1:1 or 2:2:1, etc. But it is not limited thereto, and the ratios between the elements of indium (In), gallium (Ga), and zinc (Zn) can also be other suitable ratios.
  • the first oxide semiconductor layer and the second oxide semiconductor layer are doped materials.
  • the dopant used for doping the semiconductor layer is more than one of boron, nitrogen, phosphorus and arsenic, or more than one of helium, neon, argon, krypton and xenon, or the dopant is hydrogen; but not Limited to this, the dopant can also be used in combination with the above materials according to requirements.
  • the first oxide semiconductor layer and the second oxide semiconductor layer may be formed by sputtering, coating, printing, evaporation, PCVD, PLD, ALD or MBE.
  • the first oxide semiconductor layer and the second oxide semiconductor layer are easier to deposit than silicon materials. Therefore, when the materials of the first substrate and the second substrate include an oxide semiconductor layer At this time, it is very easy to form a memory structure composed of multiple semiconductor structures stacked up. In some embodiments, the number of semiconductor structures ranges from 2 to 500, such as 10, 20, 50, 100, 300, etc.
  • first oxide semiconductor layer and the second oxide semiconductor layer used in the first substrate and the second substrate may be the same or different.
  • materials used for doping the first oxide semiconductor layer and the second oxide semiconductor layer may be the same or different.
  • the thickness of the first oxide semiconductor layer may be greater than the thickness of the second oxide semiconductor layer. Since the thickness of the first oxide semiconductor layer is larger, leakage of the overall device may be reduced. The thickness of the second oxide semiconductor layer is smaller, which can improve the electron mobility of the memory device and improve the performance of the device.
  • the second oxide semiconductor layer may also be provided with an amorphous structure.
  • the second oxide semiconductor layer in the amorphous state can easily obtain a flat surface, thereby reducing the interface disorder of the memory circuit structure manufactured using the second semi-oxide semiconductor layer, thereby further improving the electron migration of the memory device. Rate.
  • a partial lattice structure may also be formed in the second oxide semiconductor layer in the amorphous state, thereby reducing defects in the second oxide semiconductor layer, thereby further improving the performance of the memory device. Electron mobility.
  • the deposition temperature of the second oxide semiconductor layer for example, the deposition temperature is less than 150 degrees Celsius, thereby obtaining the second oxide semiconductor layer with an amorphous structure.
  • an ion implantation method or an ion doping method may also be used to dope the first oxide semiconductor layer and the second oxide semiconductor layer.
  • the doping ions are, for example, boron, nitrogen, phosphorus or arsenic.
  • the conductivity of the first oxide semiconductor layer can be improved. It should be noted that, in order to ensure the carrier mobility of the second oxide semiconductor layer and to improve the conductivity of the first oxide semiconductor layer, the doping concentration in the second oxide semiconductor layer can be less than or equal to The doping concentration in the first oxide semiconductor layer.
  • the doping concentration in the second oxide semiconductor layer is large, the dopant hinders the migration of carriers, thereby reducing the conductivity of the second oxide semiconductor layer.
  • the doping concentration in the first oxide semiconductor layer is, for example, 5 ⁇ 10 19 atmos/cm 3
  • the doping concentration in the second oxide semiconductor layer is, for example, 5 ⁇ 10 18 atmos/cm 3 .
  • the peripheral circuit structure and the storage circuit structure in the semiconductor structure are respectively located on the first substrate and the second substrate.
  • the first substrate and the second substrate are longitudinally distributed. This structure can significantly Reduce the size of the memory and improve the array efficiency of the memory.
  • the semiconductor structure 10 further includes a second dielectric layer 22 located between the first substrate 110 and the first integrated circuit layer 14 .
  • first integrated circuit layer the first conductive plug and the second conductive plug
  • subsequent establishment of electrical connection between the peripheral circuit structure and the storage circuit structure can be facilitated.
  • the first dielectric layer and the second dielectric layer can form a good electrical isolation effect in a region where there is no need to form an electrical connection between the peripheral circuit structure and the storage circuit structure.
  • the materials of the first dielectric layer 21 and the second dielectric layer 22 include but are not limited to oxide layers, nitride layers, metal oxides, spin-on insulating dielectric layers (SOD), etc. or combinations thereof;
  • the materials of the first conductive plug 211 and the second conductive plug 221 include but are not limited to tungsten or titanium nitride.
  • the first substrate 110 further includes a gate layer 113 and a first source/drain layer 111 and a second source/drain layer 112 located on both sides of the gate layer 113 . 113.
  • the first source/drain layer 111 and the second source/drain layer 112 are located on the first oxide semiconductor layer L1; wherein the first oxide semiconductor layer L1 serves as the peripheral circuit structure P1
  • the first source/drain layer 111 and the second source/drain layer 112 are electrically connected to the first integrated circuit layer 14 through the second conductive plug 221 .
  • the gate layer 113, the first source/drain layer 111 and the second source/drain layer 112 belong to the peripheral circuit structure P1.
  • the peripheral circuit structure P1 when the material of the first oxide semiconductor layer is indium gallium zinc oxide (IGZO), the peripheral circuit structure P1 has the advantages of fast signal transmission rate, low off-current, and low power consumption. .
  • IGZO indium gallium zinc oxide
  • the gate layer 113 may include a gate dielectric layer 113 a, a metal layer 113 b and a cap layer 113 c.
  • the material of the gate dielectric layer 113a may be the same as the material of the first dielectric layer 21 and the second dielectric layer 22, which will not be described in detail here;
  • the material used for the metal layer 113b may include but not It is limited to at least one of titanium nitride, tungsten or molybdenum;
  • the material of the cap layer 113c includes but is not limited to silicon nitride and the like.
  • the materials used in the first source/drain layer 111 and the second source/drain layer 112 may include, but are not limited to, indium tin oxide (ITO), molybdenum (Mo), aluminum (Al), titanium/gold (Ti /Au), indium gallium zinc oxide/indium tin oxide (IGZO/ITO) or graphene, etc.; the first integrated circuit layer 14 includes one or more interconnect layers, and the one or more interconnect layers
  • the interconnection layer integrates the peripheral circuit structure P1, and the materials used in the interconnection layer include but are not limited to tungsten, titanium nitride, etc.
  • the second substrate 120 also includes an isolation structure 125, a plurality of word lines 123 extending along the first direction and a plurality of bit lines 124 extending along the second direction; wherein , the isolation structure 125 defines the second oxide semiconductor layer L2 as a plurality of discrete active areas 126, and the plurality of word lines 123 pass through the active areas 126 and the isolation area 125, each Each of the active regions 126 includes a first source/drain region 121 located in the middle and second source/drain regions 122 located on both sides.
  • the bit line 124 is electrically connected to the first source/drain region 121 .
  • the material of the isolation structure 125 includes but is not limited to oxide, nitride, etc.
  • the word line 123 includes a word line insulation layer 123a, an anti-diffusion barrier layer 123b, a metal layer 123c, and a word line capping layer 123d.
  • the materials of the word line insulating layer 123a and the gate dielectric layer 113a may be the same or different.
  • the materials of the word line insulating layer 123a include, but are not limited to, aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ), hafnium oxynitride (HfON), silicon oxide (SiO 2 ), and zirconium oxide (ZrO 2 ) .
  • the material of the anti-diffusion barrier layer 123b includes but is not limited to titanium nitride, etc.; the The material of the metal layer 123c includes, but is not limited to, tungsten, etc.; the material of the word line cover layer 123d includes, but is not limited to, silicon nitride, etc.
  • the bit line 124 includes an anti-diffusion barrier layer 124a, a metal layer 124b, and a bit line capping layer 124c.
  • the material of the anti-diffusion barrier layer 124a includes but is not limited to titanium nitride; the material of the metal layer 124b includes but is not limited to tungsten; the material of the bit line cover layer 124c includes but is not limited to titanium nitride. wait.
  • the second substrate 120 may further include a bit line contact 127, which is used to form an electrical connection between the first source/drain region 121 and the bit line 124;
  • the material of bit line contact 127 includes but is not limited to titanium nitride or tungsten.
  • the semiconductor structure 10 also includes a storage capacitor layer 13 for storing information and a second integrated circuit layer 15 located above the storage capacitor layer 13; the storage capacitor layer 13 is located above the second substrate 120 and is electrically connected to the second source/drain region 122; the second integrated circuit layer 15 is located above the storage capacitor layer 13 and is connected to the storage capacitor layer 13 Electrical connection.
  • the storage capacitor layer 13 includes a lower electrode 131 , a dielectric material 132 and an upper electrode 133 .
  • Materials of the lower electrode 131 and the upper electrode 133 may include one or more conductive materials, such as doped semiconductors, conductive metal nitrides, metals, metal silicides, conductive oxides, or combinations thereof. For example, titanium nitride, tungsten, tantalum nitride, etc.
  • the materials of the lower electrode 131 and the upper electrode 133 may be the same or different.
  • the material of the dielectric material 132 includes, but is not limited to, nitride, oxide, metal oxide or combinations thereof. For example, silicon nitride, silicon oxide, etc.
  • high-K dielectric materials may be used to improve the performance of storage capacitor layer 13.
  • the semiconductor structure 10 further includes a node contact plug 134 for forming an electrical connection between the storage capacitor layer 13 and the second source/drain region 122 ;
  • the material of the node contact plug 134 includes but is not limited to titanium nitride, tungsten, etc.
  • the second integrated circuit layer 15 may have the same composition as the first integrated circuit layer 14, which will not be described again.
  • first source/drain region 121, the second source/drain region 122, the word line 123, and the bit line 124 belong to the memory circuit structure C1.
  • the storage circuit structure C1 When the material of the second oxide semiconductor layer L2 is indium gallium zinc oxide (IGZO), the storage circuit structure C1 has the advantages of fast access speed, low off-current, and low power consumption; the storage capacitor layer 13 has a long data retention time, so a storage capacitor layer with lower capacitance can meet the usage requirements.
  • IGZO indium gallium zinc oxide
  • the second integrated circuit layer 15 is used to form an electrical connection between the peripheral circuit structure P1 and the memory circuit structure C1. Specifically, after the electrical signal in the peripheral circuit structure P1 is transmitted to the first integrated circuit layer 14 through the second conductive plug 221, it is then transmitted to the storage circuit structure C1 through the first conductive plug 211 or directly. The electrical signal transmitted to the second integrated circuit layer 15 can be further transmitted to the memory circuit structure C1, thereby realizing the electrical connection between the peripheral circuit structure P1 and the memory circuit structure C1.
  • the memory 1 further includes an isolation layer 17 located between any two of the semiconductor structures 10 .
  • the material of the isolation layer 17 may include but not Limited to spin-on insulating dielectric layer (SOD), tetraethyl orthosilicate (TEOS), borophosphosilicate glass (BPSG), silicon dioxide (SiO 2 ), etc.
  • the thickness of the isolation layer 17 ranges from 20 nm to 1000 nm, such as 100 nm, 200 nm, 500 nm, 800 nm, etc.
  • the isolation layer 17 is used to form an electrical isolation effect between adjacent semiconductor structures 10 .
  • the memory includes a plurality of stacked semiconductor structures.
  • the stacking method can effectively improve the integration level of the memory.
  • the material of the semiconductor layer in the first substrate 110 can be silicon.
  • silicon can be thicker. , thereby using silicon to form the semiconductor layer, which can support the entire memory structure.
  • the memory 1 further includes at least one connection circuit 16 , the connection circuit 16 is located outside the plurality of semiconductor structures 10 and is used to electrically connect the plurality of semiconductor structures 10 .
  • the stacking method can be used to improve the integration level of the memory, and in each semiconductor structure used to make up the memory, the peripheral circuit and the storage circuit structure are respectively provided on the first substrate and the second substrate,
  • the longitudinal distribution between the first substrate and the second substrate can significantly reduce the volume of the memory and improve the array efficiency of the memory.
  • the memory in the embodiments of the present disclosure has higher integration level, array efficiency and smaller size.
  • An embodiment of the present disclosure also provides a method for preparing a memory. Please see Figure 6 for details. As shown in the figure, the method includes the following steps:
  • Step 610 Form a first substrate, which includes a peripheral circuit structure
  • Step 620 Form a first integrated circuit layer on the first substrate, and the first integrated circuit layer is electrically connected to the peripheral circuit structure;
  • Step 630 Form a first dielectric layer on the first integrated circuit layer
  • Step 640 Form a second substrate on the first dielectric layer, where the second substrate includes a memory circuit structure
  • the first substrate and the second substrate include semiconductor layers.
  • Figures 7 to 14 are process flow diagrams of the preparation process of the memory provided by the embodiment of the present disclosure
  • Figure 4a is a schematic top view of the second substrate provided by the embodiment of the present disclosure
  • Figure 4b and Figure 4c are the embodiments of the present disclosure.
  • the provided second substrate is a detailed cross-sectional view along the A1-A2 direction and the B1-B2 direction of Figure 4a
  • Figure 5 is a schematic structural diagram of the storage capacitor layer provided by an embodiment of the present disclosure.
  • step 610 is performed, as shown in FIGS. 7 , 8 and 9 , to form a first substrate 110 , which includes a peripheral circuit structure P1 .
  • the first substrate 110 includes a first oxide semiconductor layer L1, a gate layer 113, and a first source/drain layer 111 and a second source/drain layer located on both sides of the gate layer 113. 112; Forming the first substrate 110 includes: forming the first oxide semiconductor layer L1, which serves as the channel layer of the peripheral circuit structure P1. Please refer to Figure 7 for details; in The first source/drain layer 111 and the second source/drain layer 112 are formed on the first oxide semiconductor layer L1. Please refer to FIG. 8 for details; on the first source/drain layer 111 and the The gate layer 113 is formed between the second source/drain layers 112. Please refer to FIG. 9 for details.
  • the materials of the first oxide semiconductor layer include indium oxide, tin oxide, In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, In-Ga oxide, In-Ga-Zn type oxide, In-Al-Zn type oxide, In-Sn-Zn type oxide, Sn-Ga-Zn type oxide, Al-Ga-Zn type oxide, Sn-Al-Zn At least one type of oxide.
  • the material of the first oxide semiconductor layer may also include In-Hf-Zn-based oxide, In-La-Zn-based oxide, In-Ce-Zn-based oxide, In-Pr-Zn Oxides, In-Nd-Zn oxides, In-Sm-Zn oxides, In-Eu-Zn oxides, In-Gd-Zn oxides, In-Tb-Zn oxides, In -Dy-Zn type oxide, In-Ho-Zn type oxide, In-Er-Zn type oxide, In-Tm-Zn type oxide, In-Yb-Zn type oxide, In-Lu-Zn type Oxides; and quaternary metal oxides such as In-Sn-Ga-Zn oxides, In-Hf-Ga-Zn oxides, In-Al-Ga-Zn oxides, In-Sn-Al-Zn Oxides, In-Sn-Hf-Zn oxides, In-Hf-Al-Zn
  • a material containing at least indium (In) or zinc (Zn) may be selected.
  • materials containing indium (In) and zinc (Zn) are preferred.
  • a material may be selected that also contains the stabilizer gallium (Ga) element, which can reduce the variation in the electrical characteristics of the finally formed transistor.
  • the material of the first oxide semiconductor layer includes but is not limited to indium gallium zinc oxide (IGZO), such as a material with a chemical formula of InGaZnO 4 .
  • IGZO indium gallium zinc oxide
  • the thickness range of the indium gallium zinc oxide (IGZO) can be between 10nm and 500nm, such as: 50nm, 100nm, 150nm, 200nm, 300nm, 400nm, etc.
  • the ratio between the elements of indium (In), gallium (Ga), and zinc (Zn) can be 1:1:1 or 2:2:1, etc., thereby forming a C-axis orientation.
  • the crystalline oxide semiconductor film layer is beneficial to improving electron mobility. But it is not limited thereto, and the ratios between the elements of indium (In), gallium (Ga), and zinc (Zn) can also be other suitable ratios.
  • the first oxide semiconductor layer is a doped material
  • the dopants used for doping the first oxide semiconductor layer are boron, nitrogen, phosphorus and arsenic. or more than one of helium, neon, argon, krypton, and xenon, or the dopant is hydrogen; but it is not limited to this, the dopant can also be used in combination with the above materials according to needs .
  • the dopant is hydrogen
  • the first oxide semiconductor layer can be bonded with hydrogen, so that part of the hydrogen becomes a donor, thereby generating electrons as carriers, thereby appropriately reducing the hydrogen concentration and suppressing the threshold voltage from decreasing. Negative side drift.
  • the first oxide semiconductor layer may be formed by sputtering, coating, printing, evaporation, PCVD, PLD, ALD or MBE.
  • the gate layer 113 includes a gate dielectric layer 113a, a metal layer 113b and a cap layer 113c. Forming the gate layer 113 includes:
  • the cap layer 113c is formed on the metal layer 113b. Please refer to FIG. 9 for details.
  • the material of the gate dielectric layer 113a may include but is not limited to an oxide layer, a nitride layer, a metal oxide, a spin-coated insulating dielectric layer (SOD), etc. or a combination thereof;
  • the metal layer 113b is made of The material may include but is not limited to at least one of titanium nitride, tungsten or molybdenum;
  • the material of the cap layer 113c may include but is not limited to silicon nitride, etc.;
  • the materials used for the first source/drain layer 111 and the second source/drain layer 112 may include but are not limited to indium tin oxide (ITO), molybdenum (Mo), aluminum (Al), (Ti/Au) , Indium gallium zinc oxide/indium tin oxide (IGZO/ITO) or graphene, etc.
  • ITO indium tin oxide
  • Mo molybdenum
  • Al aluminum
  • Ti/Au titanium oxide
  • IGZO/ITO Indium gallium zinc oxide/indium tin oxide
  • graphene etc.
  • the gate layer, the first source/drain layer and the second source/drain layer may be formed using one or more common thin film deposition processes.
  • the gate layer 113, the first source/drain layer 111 and the second source/drain layer 112 belong to the peripheral circuit structure P1.
  • the peripheral circuit structure P1 when the material of the first oxide semiconductor layer is indium gallium zinc oxide (IGZO), the peripheral circuit structure P1 has the advantages of fast signal transmission rate, low off-current, and low power consumption.
  • IGZO indium gallium zinc oxide
  • step 620 is performed. As shown in FIG. 10 , a first integrated circuit layer 14 is formed on the first substrate 110 . The first integrated circuit layer 14 is electrically connected to the peripheral circuit structure P1 .
  • the first integrated circuit layer 14 includes one or more interconnection layers that integrate the peripheral circuit structure P1, and the interconnection layer adopts Materials include but are not limited to tungsten, titanium nitride, etc.
  • the method further includes: forming a second dielectric layer 22 on the first substrate 110; A second conductive plug 221 is formed inside, and the first source/drain layer 111 and the second source/drain layer 112 are electrically connected to the first integrated circuit layer 14 through the second conductive plug 221.
  • a second dielectric layer 22 on the first substrate 110
  • a second conductive plug 221 is formed inside, and the first source/drain layer 111 and the second source/drain layer 112 are electrically connected to the first integrated circuit layer 14 through the second conductive plug 221.
  • the second conductive plug may be used to form an electrical connection between the peripheral circuit structure and the first integrated circuit layer, and the second dielectric layer may be between the peripheral circuit structure and the first integrated circuit layer.
  • a good electrical isolation effect is achieved in the area where electrical connection is not required between the first integrated circuit layers.
  • the material of the second dielectric layer 22 includes but is not limited to an oxide layer, a nitride layer, a metal oxide, a spin-on insulating dielectric layer (SOD), etc. or a combination thereof; the second conductive plug
  • the materials of 221 include but are not limited to tungsten or titanium nitride.
  • the first integrated circuit layer, the second dielectric layer and the second conductive plug may be formed using one or more thin film deposition processes; the multiple thin film deposition processes include but are not limited to chemical vapor deposition (CVD) process, plasma enhanced chemical vapor deposition (PECVD) process, atomic layer deposition (ALD) process or a combination thereof.
  • CVD chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • ALD atomic layer deposition
  • step 630 is continued. As shown in FIG. 11 , a first dielectric layer 21 is formed on the first integrated circuit layer 14 .
  • the materials and formation processes used for the first dielectric layer 21 may be the same as those used for the second dielectric layer 22 , and will not be described again here.
  • step 640 is performed.
  • a second substrate 120 is formed on the first dielectric layer 21 .
  • the second substrate 120 includes a storage circuit structure C1; wherein, the first substrate 110 And the second substrate 120 includes a semiconductor layer.
  • the method further includes: forming a first conductive plug 211 in the first dielectric layer 21, the first conductive plug 211 electrically connects the first integrated circuit layer 14 and the second substrate 120, as shown in FIG. 11 .
  • the material of the first conductive plug 211 may include but is not limited to tungsten or titanium nitride.
  • the first conductive plug is used to form an electrical connection between the first integrated circuit layer and the subsequently formed storage circuit structure, and the first dielectric layer is used to form an electrical connection in a region where no electrical connection is required. Good electrical isolation effect.
  • the second substrate 120 includes a second oxide semiconductor layer L2, an isolation layer 125, a plurality of word lines 123 extending along the first direction and a plurality of word lines 123 extending along the first direction.
  • forming the second substrate 120 includes: forming a second oxide semiconductor layer L2 and an isolation layer 125, wherein the isolation layer 125 connects the second oxide semiconductor layer Defined as a plurality of discrete active areas 126; a plurality of word lines 123 are formed through the active areas 126 and the isolation area 125, each of the active areas 126 includes a first source located in the middle /drain region 121 and second source/drain regions 122 located on both sides; a plurality of bit lines 124 are formed on the active region 126 and the isolation region 125, and the bit lines 124 are connected to the first Source/drain regions 121 are electrically connected.
  • the material of the isolation structure 125 includes but is not limited to oxide, nitride, etc.
  • the word line 123 includes a word line insulation layer 123a, an anti-diffusion barrier layer 123b, a metal layer 123c, and a word line capping layer 123d.
  • the materials of the word line insulating layer 123a and the gate dielectric layer 113a may be the same or different.
  • the materials of the word line insulating layer 123a include, but are not limited to, aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ), hafnium oxynitride (HfON), silicon oxide (SiO 2 ), and zirconium oxide (ZrO 2 ) .
  • the material of the anti-diffusion barrier layer 123b includes but is not limited to titanium nitride, etc.; the The material of the metal layer 123c includes, but is not limited to, tungsten, etc.; the material of the word line cover layer 123d includes, but is not limited to, silicon nitride, etc.
  • the bit line 124 includes an anti-diffusion barrier layer 124a, a metal layer 124b, and a bit line capping layer 124c.
  • the material of the anti-diffusion barrier layer 124a includes but is not limited to titanium nitride; the material of the metal layer 124b includes but is not limited to tungsten; the material of the bit line cover layer 124c includes but is not limited to titanium nitride. wait.
  • the second substrate 120 may further include a bit line contact 127, which is used to form an electrical connection between the first source/drain region 121 and the bit line 124;
  • the material of bit line contact 127 includes but is not limited to titanium nitride or tungsten.
  • the isolation structure, the word line, and the bit line can be formed using one or more thin film deposition processes; the multiple thin film deposition processes include but are not limited to chemical vapor deposition (CVD). process, plasma enhanced chemical vapor deposition (PECVD) process, atomic layer deposition (ALD) process, or a combination thereof.
  • CVD chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • ALD atomic layer deposition
  • the memory 1 also includes a storage capacitor layer 13 for storing information and a second integrated circuit layer 15 located on the storage capacitor layer 13 ;
  • the method further includes: forming the storage capacitor layer 13 above the second substrate 120; forming the second integrated circuit layer 15 on the storage capacitor layer 13, the second integrated circuit layer 15 It is electrically connected to the storage capacitor layer 13 .
  • the storage capacitor layer 13 includes a lower electrode 131 , a dielectric material 132 and an upper electrode 133 .
  • Materials of the lower electrode 131 and the upper electrode 133 may include one or more conductive materials, such as doped semiconductors, conductive metal nitrides, metals, metal silicides, conductive oxides, or combinations thereof.
  • conductive materials such as doped semiconductors, conductive metal nitrides, metals, metal silicides, conductive oxides, or combinations thereof.
  • the material of the dielectric material 132 includes but is not limited to nitride, oxide, metal oxide or combinations thereof.
  • the memory 1 further includes a node contact plug 134, which is used to form an electrical connection between the storage capacitor layer 13 and the second source/drain region 122;
  • the material of the node contact plug 134 includes but is not limited to titanium nitride, tungsten, etc.
  • the storage capacitor layer 13 , the second integrated circuit layer 15 and the first integrated circuit layer 14 may have the same composition and formation process, and will not be described again here.
  • first source/drain region 121, the second source/drain region 122, the word line 123, and the bit line 124 belong to the memory circuit structure C1.
  • the memory circuit structure C1 when the material of the second oxide semiconductor layer is indium gallium zinc oxide (IGZO), the memory circuit structure C1 has the advantages of fast access speed, low off-current, and low power consumption;
  • the storage capacitor layer has the advantages of reduced refresh speed and extended data retention time, so a storage capacitor layer with a lower capacitance can meet the usage requirements.
  • the second integrated circuit layer 15 is used to form an electrical connection between the peripheral circuit structure P1 and the memory circuit structure C1. Specifically, after the electrical signal in the peripheral circuit structure P1 is transmitted to the first integrated circuit layer 14 through the second conductive plug 221, it is then transmitted to the storage circuit structure C1 through the first conductive plug 211 or directly. The electrical signal transmitted to the second integrated circuit layer 15 can be further transmitted to the memory circuit structure C1, thereby realizing the electrical connection between the peripheral circuit structure P1 and the memory circuit structure C1.
  • oxide semiconductor layers are easy to deposit. Therefore, when the first substrate and the second substrate include a first oxide semiconductor layer and a second oxide semiconductor layer, It is very easy to form a memory structure consisting of multiple semiconductor structures stacked on top of each other. In some embodiments, the number of semiconductor structures included in the memory ranges from 2 to 500, such as 10, 20, 50, 100, 300, etc.
  • the formation process, material and thickness of the first oxide semiconductor layer and the second oxide semiconductor layer used in the first substrate and the second substrate may be the same, or Can be different.
  • the materials used for doping the first oxide semiconductor layer and the second oxide semiconductor layer may be the same or different.
  • the material of the semiconductor layer in the first substrate 110 can be silicon.
  • silicon can be made thicker. The thickness of silicon is used to form the semiconductor layer, which can support the entire memory structure.
  • the memory 1 also includes at least one connection circuit 16, which is located outside a plurality of the semiconductor structures 10 and is used to electrically connect the plurality of semiconductor structures 10. semiconductor structure 10.
  • the memory 1 further includes an isolation layer 17, which is located between any two of the semiconductor structures 10.
  • the material of the isolation layer 17 may include but is not limited to spin-on insulating dielectric layer (SOD). ), tetraethyl orthosilicate (TEOS), borophosphosilicate glass (BPSG), silicon dioxide (SiO 2 ), etc.
  • the thickness of the isolation layer 17 ranges from 20 nm to 1000 nm, such as 100 nm, 200 nm, 500 nm, 800 nm, etc.
  • the memory is formed by stacking a plurality of semiconductor structures, and the isolation layer located between two adjacent semiconductor structures forms effective electrical isolation between the adjacent semiconductor structures.
  • the memory in embodiments of the present disclosure is significantly reduced in size. Therefore, the memory provided by the embodiments of the present disclosure has the advantages of high integration and small size.
  • the peripheral circuit P1 has the advantages of fast signal transmission rate, low cut-off current, and reduced power consumption;
  • the storage The circuit structure C1 has the advantages of fast access speed, low cut-off current, and low power consumption;
  • the storage capacitor layer has the advantages of reduced refresh speed and extended data retention time, so a storage capacitor layer with lower capacitance can meet the needs of use. need.
  • the peripheral circuit and the storage circuit structure are respectively located on the first substrate and the second substrate, and the first substrate and the second substrate are longitudinally distributed. , effectively improving array efficiency and reducing memory size.
  • each semiconductor structure used to form the memory is provided with a first integrated circuit layer, a second integrated circuit layer, a first conductive plug, and a second conductive plug, so that between the peripheral circuit structure and the Electrical connection and data transmission can be achieved between the storage circuit structure and the storage capacitor layer.
  • the first dielectric layer and the second dielectric layer can form a good electrical isolation effect in areas of the semiconductor structure that do not require electrical connection.
  • the method for manufacturing a semiconductor device provided by the embodiments of the present disclosure can be applied to a DRAM structure or other semiconductor devices, and is not subject to excessive limitations here.
  • the embodiments of the semiconductor device preparation method provided by the present disclosure and the embodiments of the semiconductor device belong to the same concept; the technical features in the technical solutions recorded in each embodiment can be combined arbitrarily as long as there is no conflict.
  • the memory includes: a plurality of stacked semiconductor structures, the semiconductor structure includes: a first substrate including a peripheral circuit structure; a first integrated circuit layer provided On the first substrate, the first integrated circuit layer is electrically connected to the peripheral circuit structure; a second substrate is provided on the first integrated circuit layer, the first integrated circuit layer and the second A first dielectric layer is disposed between the substrates, and the second substrate includes a memory circuit structure; wherein the first substrate and the second substrate include a semiconductor layer.
  • the memory provided by the embodiment of the present disclosure includes multiple stacked semiconductor structures, which can effectively improve the integration level of the memory; at the same time, the peripheral circuit and the storage circuit structure in the semiconductor structure are respectively located on the first substrate and the second substrate.
  • the longitudinal distribution between the first substrate and the second substrate can significantly reduce the volume of the memory and improve the array efficiency of the memory.
  • a first integrated circuit and a first dielectric layer are sequentially disposed between the first substrate and the second substrate, respectively used to form electrical connections between the peripheral circuit structure and the storage circuit structure and to form electrical connections in areas that do not require electrical connections. Good electrical isolation effect. Therefore, the memory provided by the embodiments of the present disclosure has higher integration level and array efficiency and smaller size than the traditional structure.

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Abstract

本公开实施例提供了一种存储器及其制备方法，其中，所述存储器包括：多个堆叠设置的半导体结构，所述半导体结构包括：第一基底，包括外围电路结构；第一整合电路层，设置在所述第一基底上，所述第一整合电路层电连接所述外围电路结构；第二基底，设置在所述第一整合电路层上，所述第一整合电路层和所述第二基底之间设有第一介质层，所述第二基底包括存储电路结构；其中，所述第一基底和所述第二基底包括半导体层。本公开实施例提供的存储器与传统结构相比具有较高的集成度和阵列效率，且具有较小的尺寸。

Description

一种存储器及其制备方法
相关申请的交叉引用
本公开基于申请号为202210255720.7、申请日为2022年03月15日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开实施例涉及但不限于一种存储器及其制备方法。
背景技术
在动态随机存储器(Dynamic Random Access Memory，DRAM)中，通常外围电路结构和存储电路结构形成在同一衬底上，所需的衬底面积较大造成制造成本大幅提高。
同时，在上述传统的DRAM结构中，存储器的体积较大、阵列效率较低。
发明内容
本公开实施例提供了一种存储器，所述存储器包括：
多个堆叠设置的半导体结构，所述半导体结构包括：
第一基底，包括外围电路结构；
第一整合电路层，设置在所述第一基底上，所述第一整合电路层电连接所述外围电路结构；
第二基底，设置在所述第一整合电路层上，所述第一整合电路层和所述第二基底之间设有第一介质层，所述第二基底包括存储电路结构；
其中，所述第一基底和所述第二基底包括半导体层。
在本公开的一种可选实施例中，所述第一基底包括第一氧化物半导体层，所述第二基底包括第二氧化物半导体层。
在本公开的一种可选实施例中，所述第一氧化物半导体层的厚度大于所述第二氧化物半导体层的厚度。
在本公开的一种可选实施例中，所述第二氧化物半导体层包括非晶结构。
在本公开的一种可选实施例中，所述半导体结构还包括位于所述第一基底与所述第一整合电路层之间的第二介质层、位于所述第一介质层内的第一导电插塞和位于所述第二介质层内的第二导电插塞；其中，所述第一整合电路层通过所述第二导电插塞与所述外围电路结构电连接，并通过所述第一导电插塞与所述存储电路结构电连接。
在本公开的一种可选实施例中，所述第一基底还包括栅极层以及位于所述栅极层两侧的第一源/漏层和第二源/漏层，所述栅极层、所述第一源/漏层和所述第二源/漏层位于所述第一氧化物半导体层上；其中，所述第一氧化半导体层作为所述外围电路结构的沟道层，所述第一源/漏层和所述第二源/漏层通过所述第二导电插塞与所述第一整合电路层电连接。
在本公开的一种可选实施例中，所述第二基底还包括隔离结构、多条沿第一方向延伸的字线及多条沿第二方向延伸的位线；其中，所述隔离结构将所述第二氧化物半导体层限定为多个分立的有源区，多条所述字线穿过所述有源区及所述隔离区，每个所述有源区包括位于中间的第一源/漏区和位于两侧的第二源/漏区，所述位线与所述第一源/漏区电连接。
在本公开的一种可选实施例中，所述半导体结构还包括用于存储信息的存储电容层及位于所述存储电容层上方的第二整合电路层；所述存储电容层位于所述第二基底的上方，并与所述第二源/漏区电连接；所述第二整合电路层位于所述存储电容层的上方并与所述存储电容层电连接。
在本公开的一种可选实施例中，第二氧化物半导体层内的掺杂浓度可以小于或等于第一氧化物半导体层内的掺杂浓度。
本公开实施例还提供了一种存储器的制备方法，所述方法包括：
形成第一基底，所述第一基底包括外围电路结构；
在所述第一基底上形成第一整合电路层，所述第一整合电路层电连接所述外围电路结构；
在所述第一整合电路层上形成第一介质层；
在所述第一介质层上形成第二基底，所述第二基底包括存储电路结构；
其中，所述第一基底和所述第二基底包括半导体层。
在本公开的一种可选实施例中，所述第一基底包括第一氧化物半导体层、栅极层以及位于所述栅极层两侧的第一源/漏层和第二源/漏层；形成所述第一基底，包括：形成所述第一氧化物半导体层，所述第一氧化半导体层作为所述外围电路结构的沟道层；在所述第一氧化物半导体层上形成所述第一源/漏层和所述第二源/漏层；在所述第一源/漏层和所述第二源/漏层之间形成所述栅极层。
在本公开的一种可选实施例中，在所述第一基底上形成第一整合电路层之前，所述方法还包括：在所述第一基底上形成第二介质层；在所述第二介质层内形成第二导电插塞，所述第一源/漏层和所述第二源/漏层通过所述第二导电插塞与所述第一整合电路层电连接。
在本公开的一种可选实施例中，所述第二基底包括第二氧化物半导体层、隔离层、多条沿第一方向延伸的字线及多条沿第二方向延伸的位线；形成所述第二基底，包括：形成第二氧化物半导体层及隔离层，其中，所述隔离层将所述第二氧化物半导体层限定为多个分立的有源区；形成穿过所述有源区及所述隔离区的多条所述字线，每个所述有源区包括位于中间的第一源/漏区和位于两侧的第二源/漏区；在所述有源区及所述隔离 区上形成多条所述位线，所述位线与所述第一源/漏区电连接。
在本公开的一种可选实施例中，所述存储器还包括用于存储信息的存储电容层及位于所述存储电容层上的第二整合电路层；所述方法还包括：在所述第二基底的上方形成所述存储电容层；在所述存储电容层上形成所述第二整合电路层，所述第二整合电路层与所述存储电容层电连接。
在本公开的一种可选实施例中，在所述第一介质层上形成第二基底之前，所述方法还包括：在所述第一介质层内形成第一导电插塞，所述第一导电插塞电连接所述第一整合电路层及所述第二基底。
附图说明
图1为本公开实施例提供的存储器的构成示意图；
图2为本公开实施例提供的半导体结构的结构示意图；
图3为本公开实施例提供的第一基底的结构示意图；
图4a为本公开实施例提供的第二基底的俯视示意图；
图4b和图4c为本公开实施例提供的第二基底沿图4a的A1-A2方向和B1-B2方向的细节剖视图；
图5为本公开实施例提供的存储电容层的结构示意图；
图6为本公开实施例提供的存储器的制备方法的流程框图；
图7至图14为本公开实施例提供的存储器在制备过程中的工艺流程图。
具体实施方式
下面将参照附图更详细地描述本公开公开的示例性实施方式。虽然附图中显示了本公开的示例性实施方式，然而应当理解，可以以各种形式实现本公开，而不应被这里阐述的具体实施方式所限制。相反，提供这些实施方式是为了能够更透彻地理解本公开，并且能够将本公开公开的范围完整的传达给本领域的技术人员。
在下文的描述中，给出了大量具体的细节以便提供对本公开更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本公开可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本公开发生混淆，对于本领域公知的一些技术特征未进行描述；即，这里不描述实际实施例的全部特征，不详细描述公知的功能和结构。
在附图中，为了清楚，层、区、元件的尺寸以及其相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在……上”、“与……相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在……上”、“与……直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/ 或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本公开教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。而当讨论的第二元件、部件、区、层或部分时，并不表明本公开必然存在第一元件、部件、区、层或部分。
空间关系术语例如“在……下”、“在……下面”、“下面的”、“在……之下”、“在……之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在……下面”和“在……下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
存储器，如DRAM中，外围电路结构和存储电路结构通常形成在同一衬底的不同区域上，当外围电路结构或存储电路结构中至少一个的布局或占用面积发生变化时，所述衬底的面积便会被动增加或减小；当遇到衬底面积不能随意变动的情况时，上述变化还会大幅增加设计人员的工作量。
另外，对外围电路结构和存储电路结构形成在同一衬底上的结构来说，所需的衬底面积较大，使得制造成本大幅提高，且存储器的体积较大、阵列效率较低。
基于此，提出了本公开实施例的以下技术方案：
本公开实施例提供了一种存储器，包括：
多个堆叠设置的半导体结构，所述半导体结构包括：
第一基底，包括外围电路结构；
第一整合电路层，设置在所述第一基底上，所述第一整合电路层电连接所述外围电路结构；
第二基底，设置在所述第一整合电路层上，所述第一整合电路层和所述第二基底之间设有第一介质层，所述第二基底包括存储电路结构；
其中，所述第一基底和所述第二基底包括半导体层。
本公开实施例提供的存储器包含多个堆叠设置的半导体结构，可有效提高存储器的集成度；同时，所述半导体结构中外围电路和存储电路结构分别位于第一基底和第二基底上，所述第一基底和所述第二基底之间呈纵向分布的方式，可显著减小存储器的体积， 提高存储器的阵列效率。另外，在第一基底和第二基底之间还依次设置有第一整合电路和第一介质层，分别用于在外围电路结构和存储电路结构之间形成电连接及在无需电连接的区域形成良好的电隔离效果。因此，本公开实施例提供的存储器与传统结构相比具有较高的集成度和阵列效率，且具有较小的尺寸。
为使本公开的上述目的、特征和优点能够更加明显易懂，下面结合附图对本公开的具体实施方式做详细的说明。在详述本公开实施例时，为便于说明，示意图会不依一般比例作局部放大，而且所述示意图只是示例，其在此不应限制本公开的保护范围。
图1为本公开实施例提供的存储器的构成示意图；图2为本公开实施例提供的半导体结构的结构示意图；图3为本公开实施例提供的第一基底的结构示意图；图4a为本公开实施例提供的第二基底的俯视示意图；图4b和图4c为本公开实施例提供的第二基底沿图4a的A1-A2方向和B1-B2方向的细节剖视图；图5为本公开实施例提供的存储电容层的结构示意图。
下面结合图1、图2、图3、图4a至图4c、图5对本公开实施例提供的存储器结构再作进一步详细的说明。
如图1、图2所示，所述存储器1包括：多个堆叠设置的半导体结构10，所述半导体结构10包括：
第一基底110，包括外围电路结构P1；
第一整合电路层14，设置在所述第一基底110上，所述第一整合电路层14电连接所述外围电路结构P1；
第二基底120，设置在所述第一整合电路层14上，所述第一整合电路层14和所述第二基底120之间设有第一介质层21，所述第二基底120包括存储电路结构C1；
其中，所述第一基底110和所述第二基底120包括半导体层。
在一些实施例中，如图3、图4b所示，所述第一基底110包括第一氧化物半导体层L1，所述第二基底120包括第二氧化物半导体层L2。
具体的，所述第一氧化物半导体层和所述第二氧化物半导体层的材料包括氧化铟、氧化锡、In-Zn类氧化物、Sn-Zn类氧化物、Al-Zn类氧化物、In-Ga类氧化物、In-Ga-Zn类氧化物、In-Al-Zn类氧化物、In-Sn-Zn类氧化物、Sn-Ga-Zn类氧化物、Al-Ga-Zn类氧化物、Sn-Al-Zn类氧化物中的至少一种。
但不限于此，所述第一氧化物半导体层和所述第二氧化物半导体层的材料还可以包括In-Hf-Zn类氧化物、In-La-Zn类氧化物、In-Ce-Zn类氧化物、In-Pr-Zn类氧化物、In-Nd-Zn类氧化物、In-Sm-Zn类氧化物、In-Eu-Zn类氧化物、In-Gd-Zn类氧化物、In-Tb-Zn类氧化物、In-Dy-Zn类氧化物、In-Ho-Zn类氧化物、In-Er-Zn类氧化物、In-Tm-Zn类氧化物、In-Yb-Zn类氧化物、In-Lu-Zn类氧化物；以及四元金属氧化物如In-Sn-Ga-Zn类氧化物、In-Hf-Ga-Zn类氧化物、In-Al-Ga-Zn类氧化物、In-Sn-Al-Zn类氧化物、In-Sn-Hf-Zn类氧化物、In-Hf-Al-Zn类氧化物等。
在一些实施例中，作为所述第一氧化物半导体层和所述第二氧化物半导体层的材料，可选择至少包含铟(In)或锌(Zn)的材料。尤其是优选包含铟(In)及锌(Zn) 的材料。除了上述元素以外，可选择还包含稳定剂镓(Ga)元素的材料，所述稳定剂可以降低最终形成的晶体管的电特性偏差。
可选的，所述第一氧化物半导体层和所述第二氧化物半导体层的材料包括但不限于铟镓锌氧化物(IGZO)，比如化学式为InGaZnO 4的材料。所述铟镓锌氧化物(IGZO)的厚度范围可以为10nm～500nm之间，比如：50nm、100nm、150nm、200nm、300nm、400nm等。
在一些实施例中，所述铟(In)、镓(Ga)、锌(Zn)各元素之间的比例可以为1:1:1或2:2:1等。但不限于此，所述铟(In)、镓(Ga)、锌(Zn)各元素之间的比例还可以为其他适合的比值。
可以理解的，在一些具体的实施例中，所述第一氧化物半导体层和所述第二氧化物半导体层为掺杂材料，对所述第一氧化物半导体层和所述第二氧化物半导体层进行掺杂采用的掺杂剂为硼、氮、磷和砷中的一种以上，或者氦、氖、氩、氪、氙中的一种以上，又或者掺杂剂为氢；但不限于此，所述掺杂剂也可以根据需求将上述材料进行组合使用。
所述第一氧化物半导体层和所述第二氧化物半导体层的形成可以采用溅射法、涂布法、印刷法、蒸镀法、PCVD法、PLD法、ALD法或MBE法等。
所述第一氧化物半导体层和所述第二氧化物半导体层与硅材料相比，具有易于沉积的特点，因此，当所述第一基底和所述第二基底的材料包括氧化物半导体层时，极易形成由多个半导体结构堆叠起来的存储器结构。在一些实施例中，所述半导体结构的数量范围在2至500之间，比如10、20、50、100、300等。
需要说明的是，所述第一基底和所述第二基底所采用的第一氧化物半导体层和第二氧化物半导体层的形成工艺、材料及厚度可以相同，也可以不同。同样的，对第一氧化物半导体层和第二氧化物半导体层进行掺杂所采用的材料可以相同，也可以不同。
在一些实施例中，第一氧化物半导体层的厚度可以大于第二氧化物半导体层的厚度，由于第一氧化物半导体层的厚度较大，由此可以使得整体器件的漏电减小。第二氧化物半导体层的厚度较小，可以提高存储器件的电子迁移率，提供器件的性能。
在一些实施例中，为进一步提高存储器件的电子迁移率，还可以将第二氧化物半导体层设置成非晶结构。非晶状态的第二氧化物半导体层可以较容易的获得平坦的表面，由此可以减少使用该第二半氧化物半导体层制造的存储电路结构的界面散乱，从而可以进一步提高存储器件的电子迁移率。
当然，在一些实施例中，在非晶状态的第二氧化物半导体层内还可以形成部分晶格结构，由此可以降低该第二氧化物半导体层内的缺陷，从而可以进一步提高存储器件的电子迁移率。
在一些实施例中，例如通过降低第二氧化物半导体层的沉积温度，例如沉积温度小于150摄氏度，从而获得非晶结构的第二氧化物半导体层。
在一些实施例中，在形成第一氧化物半导体层和第二氧化物半导体层时，还可以采用离子注入法或离子掺杂法对第一氧化物半导体层和第二氧化物半导体层进行掺杂，掺杂离子例如为硼，氮，磷或砷。当第一氧化物半导体层内包括掺杂离子时，可以提高第 一氧化物半导体层的导电性。需要说明的是，为保证第二氧化物半导体层的载流子迁移率，同时为提高第一氧化物半导体层的导电性，可以使得第二氧化物半导体层内的掺杂浓度可以小于或等于第一氧化物半导体层内的掺杂浓度，如果第二氧化物半导体层内的掺杂浓度较大，掺杂剂阻碍载流子的迁移，由此会降低第二氧化物半导体层的导电性。在一些实施例中，第一氧化物半导体层内的掺杂浓度例如为5×10 19atmos/cm 3，第二氧化物半导体层内的掺杂浓度例如为5×10 18atmos/cm 3。
在该实施例中，半导体结构中外围电路结构和存储电路结构分别位于第一基底和第二基底上，所述第一基底和所述第二基底之间呈纵向分布的方式，该结构可显著减小存储器的体积，提高存储器的阵列效率。
继续参考图2，可以看出，所述半导体结构10还包括位于所述第一基底110与所述第一整合电路层14之间的第二介质层22、位于所述第一介质层21内的第一导电插塞211和位于所述第二介质层22内的第二导电插塞221；其中，所述第一整合电路层14通过所述第二导电插塞221与所述外围电路结构P1电连接，并通过所述第一导电插塞211与所述存储电路结构C1电连接。
可以理解的，通过设置所述第一整合电路层、所述第一导电插塞及所述第二导电插塞，可以方便后续在外围电路结构和存储电路结构之间建立电连接。而所述第一介质层和所述第二介质层可以在所述外围电路结构和存储电路结构之间无需形成电连接的区域内形成良好的电隔离效果。
这里，所述第一介质层21和所述第二介质层22的材料包括但不限于氧化物层、氮化物层、金属氧化物、旋涂绝缘介质层(SOD)等或其组合；所述第一导电插塞211及所述第二导电插塞221的材料包括但不限于钨或氮化钛等。
如图3所示，所述第一基底110还包括栅极层113以及位于所述栅极层113两侧的第一源/漏层111和第二源/漏层112，所述栅极层113、所述第一源/漏层111和所述第二源/漏层112位于所述第一氧化物半导体层L1上；其中，所述第一氧化半导体层L1作为所述外围电路结构P1的沟道层，所述第一源/漏层111和所述第二源/漏层112通过所述第二导电插塞221与所述第一整合电路层14电连接。
可以理解的是，所述栅极层113、所述第一源/漏层111和所述第二源/漏层112属于所述外围电路结构P1。
在本公开实施例中，当所述第一氧化物半导体层的材料为铟镓锌氧化物(IGZO)时，所述外围电路结构P1具有信号传输速率快、截止电流低、功耗低的优点。
继续参考图3，可以看出，所述栅极层113可以包括栅极介质层113a、金属层113b及盖帽层113c。其中，所述栅极介质层113a的材料可以与所述第一介质层21、所述第二介质层22的材料相同，在此不做赘述；所述金属层113b采用的材料可以包括但不限于氮化钛、钨或钼中的至少一种；所述盖帽层113c的材料包括但不限于氮化硅等。
所述第一源/漏层111和所述第二源/漏层112所采用的材料可以包括但不限于氧化铟锡(ITO)、钼(Mo)、铝(Al)、钛/金(Ti/Au)、铟镓锌氧化物/氧化铟锡(IGZO/ITO)或石墨烯等；所述第一整合电路层14包括一层或多层互连层，所述一层或多层互连层将 所述外围电路结构P1进行整合，所述互连层采用的材料包括但不限于钨、氮化钛等。
结合图4a、图4b及图4c可以看出，所述第二基底120还包括隔离结构125、多条沿第一方向延伸的字线123及多条沿第二方向延伸的位线124；其中，所述隔离结构125将所述第二氧化物半导体层L2限定为多个分立的有源区126，多条所述字线123穿过所述有源区126及所述隔离区125，每个所述有源区126包括位于中间的第一源/漏区121和位于两侧的第二源/漏区122，所述位线124与所述第一源/漏区121电连接。
这里，所述隔离结构125的材料包括但不限于氧化物、氮化物等。
在一些实施例中，所述字线123包括字线绝缘层123a、防扩散阻挡层123b、金属层123c、及字线盖层123d。其中，所述字线绝缘层123a与所述栅极介质层113a的材料可以相同，也可以不同。这里，所述字线绝缘层123a的材料包括但不限于氧化铝(Al 2O 3)、氧化铪(HfO 2)、氮氧化铪(HfON)、氧化硅(SiO 2)、氧化锆(ZrO 2)、氧化钛(TiO 2)、铪镧系氧化物(HfLaO)、氧化钽(Ta2O5)及其他有机电介质材料等；所述防扩散阻挡层123b的材料包括但不限于氮化钛等；所述金属层123c的材料包括但不限于钨等；所述字线盖层123d的材料包括但不限于氮化硅等。
所述位线124包括防扩散阻挡层124a、金属层124b、及位线盖层124c。其中，所述防扩散阻挡层124a的材料包括但不限于氮化钛等；所述金属层124b的材料包括但不限于钨等；所述位线盖层124c的材料包括但不限于氮化钛等。
可选的，所述第二基底120还可以包括位线接触127，所述位线接触127用于在所述第一源/漏区121和所述位线124之间形成电连接；所述位线接触127的材料包括但不限于氮化钛或钨等。
继续参考图2及图5，可以看出，所述半导体结构10还包括用于存储信息的存储电容层13及位于所述存储电容层13上方的第二整合电路层15；所述存储电容层13位于所述第二基底120的上方，并与所述第二源/漏区122电连接；所述第二整合电路层15位于所述存储电容层13的上方并与所述存储电容层13电连接。
如图5所示，所述存储电容层13包括下电极131、介电材料132及上电极133。所述下电极131和所述上电极133的材料可以包括一种或多种导电材料，诸如掺杂的半导体，导电金属氮化物，金属，金属硅化物，导电氧化物或其组合。例如，氮化钛、钨、氮化钽等。
可以理解的是，所述下电极131和所述上电极133的材料可以相同也可以不同。所述介电材料132的材料包括但不限于氮化物、氧化物、金属氧化物或其组合。例如，氮化硅、氧化硅等。在某些实施例中，可以使用高K介电材料来提高存储电容层13的性能。
在一些实施例中，所述半导体结构10还包括节点接触插塞134，所述节点接触插塞134用于在所述存储电容层13和所述第二源/漏区122之间形成电连接；所述节点接触插塞134的材料包括但不限于氮化钛、钨等。
这里，所述第二整合电路层15可以与所述第一整合电路层14的组成相同，在此不做赘述。
可以理解的是，所述第一源/漏区121、所述第二源/漏区122、所述字线123、所述位线124属于所述存储电路结构C1。
当所述第二氧化物半导体层L2的材料为铟镓锌氧化物(IGZO)时，所述存储电路结构C1具有存取速度快、截止电流低、功耗低的优点；所述存储电容层13具有较长的数据保持时间，因而具有较低电容量的存储电容层便可满足使用需求。
在实际工艺中，所述第二整合电路层15用于在外围电路结构P1和存储电路结构C1之间形成电连接。具体的，所述外围电路结构P1中的电信号经由所述第二导电插塞221传输至第一整合电路层14后，再经由所述第一导电插塞211传输至存储电路结构C1或直接传输至第二整合电路层15，传输至第二整合电路层15的电信号可进一步传输至存储电路结构C1，从而实现外围电路结构P1和存储电路结构C1之间的电连接。
在一些实施例中，如图1所示，所述存储器1还包括隔离层17，所述隔离层17位于任意两个所述半导体结构10之间，所述隔离层17的材料可以包括但不限于旋涂绝缘介质层(SOD)、正硅酸乙酯(TEOS)、硼磷硅玻璃(BPSG)、二氧化硅(SiO 2)等。在一些实施例中，所述隔离层17的厚度范围在20nm至1000nm之间，比如100nm、200nm、500nm、800nm等。所述隔离层17用于在相邻所述半导体结构10之间形成电隔离效果。
在该实施例中，所述存储器包含多个堆叠设置的半导体结构，通过堆叠的方式可有效提高存储器的集成度。
可以理解的，位于所述存储器1最底层的所述半导体结构10中，所述第一基底110中的所述半导体层的材料可以为硅，在本领域中，硅可以做到较厚的厚度，从而采用硅来形成所述半导体层，可以对整个存储器的结构起到支撑作用。
继续参考图1，可以看出，所述存储器1还包括至少一个连通电路16，所述连通电路16位于多个所述半导体结构10的外侧，用于电连接所述多个半导体结构10。
在本公开实施例中，采用堆叠的方式可提高存储器的集成度，且用于组成所述存储器的每个半导体结构中，外围电路和存储电路结构分别设置在第一基底和第二基底上，所述第一基底和所述第二基底之间呈纵向分布的方式，可显著减小存储器的体积，提高存储器的阵列效率。与传统结构相比，本公开实施例中的存储器具有较高的集成度和阵列效率且具有较小的尺寸。
本公开实施例还提供了一种存储器的制备方法，具体请参见图6。如图所示，所述方法包括了如下步骤：
步骤610：形成第一基底，所述第一基底包括外围电路结构；
步骤620：在所述第一基底上形成第一整合电路层，所述第一整合电路层电连接所述外围电路结构；
步骤630：在所述第一整合电路层上形成第一介质层；
步骤640：在所述第一介质层上形成第二基底，所述第二基底包括存储电路结构；
其中，所述第一基底和所述第二基底包括半导体层。
下面，结合图7至图14、图4a至图4c、图5对本公开实施例提供的存储器的制备 方法再做进一步详细的说明。其中，图7至图14为本公开实施例提供的存储器在制备过程中的工艺流程图；图4a为本公开实施例提供的第二基底的俯视示意图；图4b和图4c为本公开实施例提供的第二基底沿图4a的A1-A2方向和B1-B2方向的细节剖视图；图5为本公开实施例提供的存储电容层的结构示意图。
首先，执行步骤610，如图7、图8和图9所示，形成第一基底110，所述第一基底110包括外围电路结构P1。
在一些实施例中，所述第一基底110包括第一氧化物半导体层L1、栅极层113以及位于所述栅极层113两侧的第一源/漏层111和第二源/漏层112；形成所述第一基底110，包括：形成所述第一氧化物半导体层L1，所述第一氧化半导体层L1作为所述外围电路结构P1的沟道层，具体请参考图7；在所述第一氧化物半导体层L1上形成所述第一源/漏层111和所述第二源/漏层112，具体请参考图8；在所述第一源/漏层111和所述第二源/漏层112之间形成所述栅极层113，具体请参考图9。
在实际工艺中，所述第一氧化物半导体层的材料包括氧化铟、氧化锡、In-Zn类氧化物、Sn-Zn类氧化物、Al-Zn类氧化物、In-Ga类氧化物、In-Ga-Zn类氧化物、In-Al-Zn类氧化物、In-Sn-Zn类氧化物、Sn-Ga-Zn类氧化物、Al-Ga-Zn类氧化物、Sn-Al-Zn类氧化物中的至少一种。
但不限于此，所述第一氧化物半导体层的材料还可以包括In-Hf-Zn类氧化物、In-La-Zn类氧化物、In-Ce-Zn类氧化物、In-Pr-Zn类氧化物、In-Nd-Zn类氧化物、In-Sm-Zn类氧化物、In-Eu-Zn类氧化物、In-Gd-Zn类氧化物、In-Tb-Zn类氧化物、In-Dy-Zn类氧化物、In-Ho-Zn类氧化物、In-Er-Zn类氧化物、In-Tm-Zn类氧化物、In-Yb-Zn类氧化物、In-Lu-Zn类氧化物；以及四元金属氧化物如In-Sn-Ga-Zn类氧化物、In-Hf-Ga-Zn类氧化物、In-Al-Ga-Zn类氧化物、In-Sn-Al-Zn类氧化物、In-Sn-Hf-Zn类氧化物、In-Hf-Al-Zn类氧化物等。
在一些实施例中，作为所述第一氧化物半导体层的材料，可选择至少包含铟(In)或锌(Zn)的材料。尤其是优选包含铟(In)及锌(Zn)的材料。除了上述元素以外，可选择还包含稳定剂镓(Ga)元素的材料，所述稳定剂可以降低最终形成的晶体管的电特性偏差。
可选的，所述第一氧化物半导体层的材料包括但不限于铟镓锌氧化物(IGZO)，比如化学式为InGaZnO 4的材料。所述铟镓锌氧化物(IGZO)的厚度范围可以为10nm～500nm之间，比如：50nm、100nm、150nm、200nm、300nm、400nm等。
在一些实施例中，所述铟(In)、镓(Ga)、锌(Zn)各元素之间的比例可以为1:1:1或2:2:1等，由此可以形成C轴取向结晶氧化物半导体膜层，有利于提高电子迁移率。但不限于此，所述铟(In)、镓(Ga)、锌(Zn)各元素之间的比例还可以为其他适合的比值。
可以理解的，在一些具体的实施例中，所述第一氧化物半导体层为掺杂材料，对所述第一氧化物半导体层进行掺杂采用的掺杂剂为硼、氮、磷和砷中的一种以上，或者氦、氖、氩、氪、氙中的一种以上，又或者掺杂剂为氢；但不限于此，所述掺杂剂也可以根 据需求将上述材料进行组合使用。当掺杂剂为氢时，第一氧化物半导体层可以与氢键合，由此一部分氢成供体，因此产生作为载流子的电子，由此可以适当降低氢浓度，能够抑制阈值电压向负侧漂移。
所述第一氧化物半导体层的形成可以采用溅射法、涂布法、印刷法、蒸镀法、PCVD法、PLD法、ALD法或MBE法等。
在一些实施例中，所述栅极层113包括栅极介质层113a、金属层113b及盖帽层113c，形成所述栅极层113包括：
在所述第一氧化物半导体层L1上形成所述栅极介质层113a；
在所述栅极介质层113a上形成所述金属层113b；
在所述金属层113b上形成所述盖帽层113c，具体请参考图9。
在实际工艺中，所述栅极介质层113a的材料可以包括但不限于氧化物层、氮化物层、金属氧化物、旋涂绝缘介质层(SOD)等或其组合；所述金属层113b采用的材料可以包括但不限于氮化钛、钨或钼中的至少一种；所述盖帽层113c的材料包括但不限于氮化硅等；
所述第一源/漏层111和所述第二源/漏层112所采用的材料可以包括但不限于氧化铟锡(ITO)、钼(Mo)、铝(Al)、(Ti/Au)、铟镓锌氧化物/氧化铟锡(IGZO/ITO)或石墨烯等。
所述栅极层、所述第一源/漏层和所述第二源/漏层可以使用常见的一种或多种薄膜沉积工艺形成。
可以理解的是，所述栅极层113、所述第一源/漏层111和所述第二源/漏层112属于所述外围电路结构P1。
在一些实施例中，当所述第一氧化物半导体层的材料为铟镓锌氧化物(IGZO)时，所述外围电路结构P1具有信号传输速率快、截止电流低、功耗低的优点。
接着，执行步骤620，如图10所示，在所述第一基底110上形成第一整合电路层14，所述第一整合电路层14电连接所述外围电路结构P1。
在一些实施例中，所述第一整合电路层14包括一层或多层互连层，所述一层或多层互连层将所述外围电路结构P1进行整合，所述互连层采用的材料包括但不限于钨、氮化钛等。
可以理解的，在所述第一基底110上形成第一整合电路层14之前，所述方法还包括：在所述第一基底110上形成第二介质层22；在所述第二介质层22内形成第二导电插塞221，所述第一源/漏层111和所述第二源/漏层112通过所述第二导电插塞221与所述第一整合电路层14电连接，具体请参考图10。
在该实施例中，所述第二导电插塞可以用于在所述外围电路结构和所述第一整合电路层之间形成电连接，所述第二介质层可以在所述外围电路结构和所述第一整合电路层之间无需形成电连接的区域内形成良好的电隔离效果。
在实际工艺中，所述第二介质层22的材料包括但不限于氧化物层、氮化物层、金属氧化物、旋涂绝缘介质层(SOD)等或其组合；所述第二导电插塞221的材料包括但 不限于钨或氮化钛等。
所述第一整合电路层、所述第二介质层及所述第二导电插塞的形成可以使用一种或多种薄膜沉积工艺形成；所述多种薄膜沉积工艺包括但不限于化学气相沉积(CVD)工艺、等离子体增强化学气相沉积(PECVD)工艺、原子层沉积(ALD)工艺或其组合。
接下来，继续执行步骤630，如图11所示，在所述第一整合电路层14上形成第一介质层21。
所述第一介质层21采用的材料及形成工艺可以与所述第二介质层22采用的材料及形成工艺相同，在此不做赘述。
最后，执行步骤640，如图11、图12所示，在所述第一介质层21上形成第二基底120，所述第二基底120包括存储电路结构C1；其中，所述第一基底110和所述第二基底120包括半导体层。
可选的，在所述第一介质层21上形成第二基底120之前，所述方法还包括：在所述第一介质层21内形成第一导电插塞211，所述第一导电插塞211电连接所述第一整合电路层14及所述第二基底120，如图11所示。所述第一导电插塞211的材料可以包括但不限于钨或氮化钛等。
所述第一导电插塞用于在所述第一整合电路层和后续的形成的所述存储电路结构之间形成电连接，所述第一介质层用于在无需形成电连接的区域内形成良好的电隔离效果。
在一些实施例中，如图4a、图4b和图4c所示，所述第二基底120包括第二氧化物半导体层L2、隔离层125、多条沿第一方向延伸的字线123及多条沿第二方向延伸的位线124；形成所述第二基底120，包括：形成第二氧化物半导体层L2及隔离层125，其中，所述隔离层125将所述第二氧化物半导体层限定为多个分立的有源区126；形成穿过所述有源区126及所述隔离区125的多条所述字线123，每个所述有源区126包括位于中间的第一源/漏区121和位于两侧的第二源/漏区122；在所述有源区126及所述隔离区125上形成多条所述位线124，所述位线124与所述第一源/漏区121电连接。
这里，所述隔离结构125的材料包括但不限于氧化物、氮化物等。
在一些实施例中，如图4b和图4c所示，所述字线123包括字线绝缘层123a、防扩散阻挡层123b、金属层123c、及字线盖层123d。其中，所述字线绝缘层123a与所述栅极介质层113a的材料可以相同，也可以不同。这里，所述字线绝缘层123a的材料包括但不限于氧化铝(Al 2O 3)、氧化铪(HfO 2),氮氧化铪(HfON)、氧化硅(SiO 2)、氧化锆(ZrO 2)、氧化钛(TiO 2)、铪镧系氧化物(HfLaO)、氧化钽(Ta2O5)及其他有机电介质材料等；所述防扩散阻挡层123b的材料包括但不限于氮化钛等；所述金属层123c的材料包括但不限于钨等；所述字线盖层123d的材料包括但不限于氮化硅等。
继续参考图4b和图4c，所述位线124包括防扩散阻挡层124a、金属层124b、及位线盖层124c。其中，所述防扩散阻挡层124a的材料包括但不限于氮化钛等；所述金属层124b的材料包括但不限于钨等；所述位线盖层124c的材料包括但不限于氮化钛等。
可选的，所述第二基底120还可以包括位线接触127，所述位线接触127用于在所 述第一源/漏区121和所述位线124之间形成电连接；所述位线接触127的材料包括但不限于氮化钛或钨等。
在实际工艺中，所述隔离结构、所述字线、所述位线的形成可以使用一种或多种薄膜沉积工艺形成；所述多种薄膜沉积工艺包括但不限于化学气相沉积(CVD)工艺、等离子体增强化学气相沉积(PECVD)工艺、原子层沉积(ALD)工艺或其组合。
在一些实施例中，如图5及图13所示，可以看出，所述存储器1还包括用于存储信息的存储电容层13及位于所述存储电容层13上的第二整合电路层15；所述方法还包括：在所述第二基底120的上方形成所述存储电容层13；在所述存储电容层13上形成所述第二整合电路层15，所述第二整合电路层15与所述存储电容层13电连接。
所述存储电容层13包括下电极131、介电材料132及上电极133。所述下电极131和所述上电极133的材料可以包括一种或多种导电材料，诸如掺杂的半导体，导电金属氮化物，金属，金属硅化物，导电氧化物或其组合。例如，氮化钛、钨、氮化钽等；所述介电材料132的材料包括但不限于氮化物、氧化物、金属氧化物或其组合。
在一些实施例中，所述存储器1还包括节点接触插塞134，所述节点接触插塞134用于在所述存储电容层13和所述第二源/漏区122之间形成电连接；所述节点接触插塞134的材料包括但不限于氮化钛、钨等。
这里，所述存储电容层13、所述第二整合电路层15与所述第一整合电路层14的组成及形成工艺可以相同，在此不做赘述。
可以理解的，所述第一源/漏区121、所述第二源/漏区122、所述字线123、所述位线124属于所述存储电路结构C1。
可以理解的，当所述第二氧化物半导体层的材料为铟镓锌氧化物(IGZO)时，所述存储电路结构C1具有存取速度快、截止电流低、功耗低的优点；所述存储电容层具有刷新速度降低，数据保持时间延长的优点，因而具有较低电容量的存储电容层便可满足使用需求。
在实际工艺中，所述第二整合电路层15用于在外围电路结构P1和存储电路结构C1之间形成电连接。具体的，所述外围电路结构P1中的电信号经由所述第二导电插塞221传输至第一整合电路层14后，再经由所述第一导电插塞211传输至存储电路结构C1或直接传输至第二整合电路层15，传输至第二整合电路层15的电信号可进一步传输至存储电路结构C1，从而实现外围电路结构P1和存储电路结构C1之间的电连接。
可以理解的，与硅材料相比，氧化物半导体层具有易于沉积的特点，因此，当所述第一基底和所述第二基底包括第一氧化物半导体层和第二氧化物半导体层时，极易形成由多个半导体结构堆叠起来的存储器结构。在一些实施例中，所述存储器中包含的所述半导体结构的数量范围在2至500之间，比如10、20、50、100、300等。
需要说明的是，在本公开实施例中，所述第一基底和所述第二基底所采用的第一氧化物半导体层和第二氧化物半导体层的形成工艺、材料及厚度可以相同，也可以不同。同样的，对第一氧化物半导体层和第二氧化物半导体层进行掺杂所采用的材料可以相同，也可以不同。
在一些实施例中，位于所述存储器1最底层的所述半导体结构10中，所述第一基底110中的所述半导体层的材料可以为硅，在本领域中，硅可以做到较厚的厚度，从而采用硅来形成所述半导体层，可以对整个存储器的结构起到支撑作用。
在实际工艺中，如图14所示，可以看出，所述存储器1还包括至少一个连通电路16，所述连通电路16位于多个所述半导体结构10的外侧，用于电连接所述多个半导体结构10。
可选的，所述存储器1还包括隔离层17，所述隔离层17位于任意两个所述半导体结构10之间，所述隔离层17的材料可以包括但不限于旋涂绝缘介质层(SOD)、正硅酸乙酯(TEOS)、硼磷硅玻璃(BPSG)、二氧化硅(SiO 2)等。在一些实施例中，所述隔离层17的厚度范围在20nm至1000nm之间，比如100nm、200nm、500nm、800nm等。
在本公开实施例中，所述存储器通过将多个半导体结构进行堆叠形成，位于相邻两个半导体结构之间的所述隔离层在相邻所述半导体结构之间形成有效的电隔离。与传统结构相比，本公开实施例中的存储器的体积显著减小。因此，本公开实施例提供的存储器具有集成度高、尺寸小的优点。
可以理解的，当第一基底和第二基底的材料均为铟镓锌氧化物(IGZO)时，所述外围电路P1具有信号传输速率快、截止电流低、降低功耗的优点；所述存储电路结构C1具有存取速度快、截止电流低、功耗低的优点；所述存储电容层具有刷新速度降低、数据保持时间延长的优点，因而具有较低电容量的存储电容层便可满足使用需求。
同时，用于组成所述存储器的每个半导体结构中，外围电路和存储电路结构分别位于第一基底和第二基底上，所述第一基底和所述第二基底之间呈纵向分布的方式，有效的提高了阵列效率，减小存储器的体积。
另外，用于组成所述存储器的每个半导体结构中设置有第一整合电路层、第二整合电路层、第一导电插塞、第二导电插塞，使得在所述外围电路结构及所述存储电路结构、存储电容层之间能够实现电连接及数据传输。同时，第一介质层、第二介质层可在半导体结构中无需电连接的区域形成良好的电隔离效果。
需要说明的是，本公开实施例提供的半导体器件的制备方法可应用于DRAM结构或其他半导体器件中，在此不做过多限定。本公开提供的半导体器件制备方法的实施例与半导体器件的实施例属于同一构思；各实施例所记载的技术方案中各技术特征之间，在不冲突的情况下，可以任意组合。
以上所述，仅为本公开的较佳实施例而已，并非用于限定本公开的保护范围，凡在本公开的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本公开的保护范围之内。
工业实用性
本公开实施例所提供的存储器及其制备方法，其中，所述存储器包括：多个堆叠设置的半导体结构，所述半导体结构包括：第一基底，包括外围电路结构；第一整合电路 层，设置在所述第一基底上，所述第一整合电路层电连接所述外围电路结构；第二基底，设置在所述第一整合电路层上，所述第一整合电路层和所述第二基底之间设有第一介质层，所述第二基底包括存储电路结构；其中，所述第一基底和所述第二基底包括半导体层。本公开实施例提供的存储器包含多个堆叠设置的半导体结构，可有效提高存储器的集成度；同时，所述半导体结构中外围电路和存储电路结构分别位于第一基底和第二基底上，所述第一基底和所述第二基底之间呈纵向分布的方式，可显著减小存储器的体积，提高存储器的阵列效率。另外，在第一基底和第二基底之间还依次设置有第一整合电路和第一介质层，分别用于在外围电路结构和存储电路结构之间形成电连接及在无需电连接的区域形成良好的电隔离效果。因此，本公开实施例提供的存储器与传统结构相比具有较高的集成度和阵列效率，且具有较小的尺寸。

Claims (15)

  1. 一种存储器，包括：
    多个堆叠设置的半导体结构，所述半导体结构包括：
    第一基底，包括外围电路结构；
    第一整合电路层，设置在所述第一基底上，所述第一整合电路层电连接所述外围电路结构；
    第二基底，设置在所述第一整合电路层上，所述第一整合电路层和所述第二基底之间设有第一介质层，所述第二基底包括存储电路结构；
    其中，所述第一基底和所述第二基底包括半导体层。
  2. 根据权利要求1所述的存储器，其中，所述第一基底包括第一氧化物半导体层，所述第二基底包括第二氧化物半导体层。
  3. 根据权利要求2所述的存储器，其中，所述第一氧化物半导体层的厚度大于所述第二氧化半导体层的厚度。
  4. 根据权利要求2所述的存储器，其中，所述第二氧化物半导体层包括非晶结构。
  5. 根据权利要求2所述的存储器，其中，所述半导体结构还包括位于所述第一基底与所述第一整合电路层之间的第二介质层、位于所述第一介质层内的第一导电插塞和位于所述第二介质层内的第二导电插塞；其中，所述第一整合电路层通过所述第二导电插塞与所述外围电路结构电连接，并通过所述第一导电插塞与所述存储电路结构电连接。
  6. 根据权利要求5所述的存储器，其中，所述第一基底还包括栅极层以及位于所述栅极层两侧的第一源/漏层和第二源/漏层，所述栅极层、所述第一源/漏层和所述第二源/漏层位于所述第一氧化物半导体层上；其中，所述第一氧化半导体层作为所述外围电路结构的沟道层，所述第一源/漏层和所述第二源/漏层通过所述第二导电插塞与所述第一整合电路层电连接。
  7. 根据权利要求5所述的存储器，其中，所述第二基底还包括隔离结构、多条沿第一方向延伸的字线及多条沿第二方向延伸的位线；其中，所述隔离结构将所述第二氧化物半导体层限定为多个分立的有源区，多条所述字线穿过所述有源区及所述隔离区，每个所述有源区包括位于中间的第一源/漏区和位于两侧的第二源/漏区，所述位线与所述第一源/漏区电连接。
  8. 根据权利要求7所述的存储器，其中，所述半导体结构还包括用于存储信息的存储电容层及位于所述存储电容层上方的第二整合电路层；所述存储电容层位于所述第二基底的上方，并与所述第二源/漏区电连接；所述第二整合电路层位于所述存储电容层的上方并与所述存储电容层电连接。
  9. 根据权利要求2所述的存储器，其中，所述第二氧化物半导体层内的掺杂浓度小于或等于所述第一氧化物半导体层内的掺杂浓度。
  10. 一种存储器的制备方法，所述方法包括：
    形成第一基底，所述第一基底包括外围电路结构；
    在所述第一基底上形成第一整合电路层，所述第一整合电路层电连接所述外围电路结构；
    在所述第一整合电路层上形成第一介质层；
    在所述第一介质层上形成第二基底，所述第二基底包括存储电路结构；
    其中，所述第一基底和所述第二基底包括半导体层。
  11. 根据权利要求10所述的方法，其中，所述第一基底包括第一氧化物半导体层、栅极层以及位于所述栅极层两侧的第一源/漏层和第二源/漏层；形成所述第一基底，包括：形成所述第一氧化物半导体层，所述第一氧化半导体层作为所述外围电路结构的沟道层；在所述第一氧化物半导体层上形成所述第一源/漏层和所述第二源/漏层；在所述第一源/漏层和所述第二源/漏层之间形成所述栅极层。
  12. 根据权利要求11所述的方法，其中，在所述第一基底上形成第一整合电路层之前，所述方法还包括：在所述第一基底上形成第二介质层；在所述第二介质层内形成第二导电插塞，所述第一源/漏层和所述第二源/漏层通过所述第二导电插塞与所述第一整合电路层电连接。
  13. 根据权利要求10所述的方法，其中，所述第二基底包括第二氧化物半导体层、隔离层、多条沿第一方向延伸的字线及多条沿第二方向延伸的位线；形成所述第二基底，包括：形成第二氧化物半导体层及隔离层，其中，所述隔离层将所述第二氧化物半导体层限定为多个分立的有源区；形成穿过所述有源区及所述隔离区的多条所述字线，每个所述有源区包括位于中间的第一源/漏区和位于两侧的第二源/漏区；在所述有源区及所述隔离区上形成多条所述位线，所述位线与所述第一源/漏区电连接。
  14. 根据权利要求10所述的方法，其中，所述存储器还包括用于存储信息的存储电容层及位于所述存储电容层上的第二整合电路层；所述方法还包括：在所述第二基底的上方形成所述存储电容层；在所述存储电容层上形成所述第二整合电路层，所述第二整合电路层与所述存储电容层电连接。
  15. 根据权利要求10所述的方法，其中，在所述第一介质层上形成第二基底之前，所述方法还包括：在所述第一介质层内形成第一导电插塞，所述第一导电插塞电连接所述第一整合电路层及所述第二基底。
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