WO2023226179A1 - 晶体管及其制备方法、以及存储器 - Google Patents

晶体管及其制备方法、以及存储器 Download PDF

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WO2023226179A1
WO2023226179A1 PCT/CN2022/106460 CN2022106460W WO2023226179A1 WO 2023226179 A1 WO2023226179 A1 WO 2023226179A1 CN 2022106460 W CN2022106460 W CN 2022106460W WO 2023226179 A1 WO2023226179 A1 WO 2023226179A1
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layer
sub
gate
channel layer
active
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PCT/CN2022/106460
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English (en)
French (fr)
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廖君玮
王晓光
肖德元
李宗翰
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长鑫存储技术有限公司
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Priority to US18/151,434 priority Critical patent/US20230389294A1/en
Publication of WO2023226179A1 publication Critical patent/WO2023226179A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line

Definitions

  • the present disclosure relates to, but is not limited to, a transistor, a manufacturing method thereof, and a memory.
  • Transistors are important components in electronic circuits.
  • the transistor uses the gate voltage to control the current flowing through the channel between the source and drain, and is a voltage-controlled switching device.
  • Transistors can be used to form memories, such as dynamic random access memory (DRAM), and together with capacitors form memory cells.
  • DRAM dynamic random access memory
  • the electrical properties of transistors have an important impact on the storage performance of memory cells. Therefore, improving the electrical properties of transistors is an important way to improve the performance of memory cells.
  • a transistor including:
  • a substrate including an active region
  • a gate structure passes through the active area;
  • the gate structure includes a gate electrode and a gate dielectric layer, and the gate dielectric layer covers the sidewalls and bottom of the gate electrode;
  • a channel layer located on a side of the gate dielectric layer relatively away from the gate, where the channel layer includes a metal oxide semiconductor layer;
  • the active area includes a first active layer and a second active layer respectively located on both sides of the gate structure.
  • the first active layer and the second active layer are both connected to the channel layer. contact.
  • the metal oxide semiconductor layer is made of at least one of indium gallium zinc oxide, indium tin oxide, indium tungsten oxide, indium zinc oxide, gallium oxide, and indium oxide.
  • the metal oxide semiconductor layer has a thickness of 0.5 nm to 3 nm.
  • the channel layer includes at least one sub-channel layer group, the sub-channel layer group includes two sub-channel layers stacked in sequence, one of the sub-channel layers of the two sub-channel layers
  • the first layer includes the metal oxide semiconductor layer
  • the other sub-channel layer includes a silicon germanium semiconductor layer or a silicon semiconductor layer.
  • the metal oxide semiconductor layer covers sidewalls of the first active layer and the second active layer relatively close to the gate structure.
  • the first active layer and the second active layer are located on top of the channel layer
  • the gate dielectric layer covers the sidewalls of the first active layer and the second active layer, and the top of the channel layer is not covered by the first active layer and the second active layer. The portion covered by the source layer.
  • the gate includes a first portion and a second portion, the first portion is located on a side of the second portion relatively close to the substrate surface, and the first portion has a first portion along a specified direction. size, the second portion has a second size along the specified direction, the first size is larger than the second size, the specified direction is parallel to the substrate surface and is consistent with an extension of the gate The direction is perpendicular.
  • the gate includes a first sub-gate and a second sub-gate, and the second sub-gate is located on a side of the first sub-gate relatively close to the surface of the substrate, so The first sub-gate is made of metal, and the second sub-gate is made of polysilicon.
  • a memory including:
  • a memory unit configured to store data; the memory unit includes a transistor as described in the first aspect of the present disclosure.
  • the storage unit further includes:
  • a method for manufacturing a transistor including:
  • a substrate is provided; wherein the substrate includes an active region and a trench is formed in the substrate through the active region;
  • a first active layer and a second active layer are formed in the active area; wherein the first active layer and the second active layer are respectively provided on both sides of the trench;
  • a channel layer is formed at the bottom and sidewalls of the trench located in the active area; wherein the channel layer includes a metal oxide semiconductor layer; the channel layer is connected to the first active layer and The second active layer is in contact;
  • a gate dielectric layer and a gate electrode are sequentially formed in the trench; wherein the gate dielectric layer covers the channel layer.
  • the metal oxide semiconductor layer is made of at least one of indium gallium zinc oxide, indium tin oxide, indium tungsten oxide, indium zinc oxide, gallium oxide, and indium oxide.
  • the metal oxide semiconductor layer has a thickness of 0.5 nm to 3 nm.
  • the channel layer includes a first sub-channel layer and a second sub-channel layer stacked in sequence; the trench is formed at the bottom and sidewalls of the trench located in the active area.
  • the steps at the Tao level include:
  • a second sub-channel layer covering the bottom and sidewalls of the first sub-channel layer is formed; wherein the second sub-channel layer includes a metal oxide semiconductor layer.
  • the first active layer and the second active layer are located on top of the first sub-channel layer, and the second sub-channel layer also covers the first active layer
  • the first active layer and the second active layer are located on top of the first sub-channel layer, and the top of the second sub-channel layer and the first sub-channel layer are The top of the channel layer is flush;
  • the step of forming a gate dielectric layer in the trench includes:
  • a gate dielectric layer is formed in the trench; wherein the gate dielectric layer also covers the top of the second sub-channel layer, and the first active layer and the second active layer. side walls.
  • the gate includes a first sub-gate and a second sub-gate, and the second sub-gate is located on a side of the first sub-gate relatively close to the surface of the substrate;
  • the step of forming a gate in the trench includes:
  • the first sub-gate is formed on a side of the gate dielectric layer relatively away from the channel layer; wherein the material of the first sub-gate includes metal;
  • the second sub-gate is formed on the top of the first sub-gate; wherein the material of the second sub-gate includes polysilicon.
  • Figure 1 is a schematic structural diagram of a DRAM memory unit provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of a transistor using a buried word line according to an embodiment of the present disclosure
  • Figure 3 is a top view of a transistor array provided by an embodiment of the present disclosure.
  • Figure 4 is a partial cross-sectional view along line A-A of the transistor array shown in Figure 3;
  • Figure 5 shows transfer characteristic curves of two transistors provided by embodiments of the present disclosure
  • Figure 6 is a schematic cross-sectional view of a transistor provided by an embodiment of the present disclosure.
  • Figure 7 is a schematic cross-sectional view of another transistor provided by an embodiment of the present disclosure.
  • Figure 8 is a schematic cross-sectional view of another transistor provided by an embodiment of the present disclosure.
  • Figure 9 is a schematic cross-sectional view of another transistor provided by an embodiment of the present disclosure.
  • Figure 10 is a schematic cross-sectional view of another transistor provided by an embodiment of the present disclosure.
  • Figure 11 is a schematic cross-sectional view of another transistor provided by an embodiment of the present disclosure.
  • Figure 12 is a schematic cross-sectional view of another transistor provided by an embodiment of the present disclosure.
  • Figure 13 is a schematic cross-sectional view of another transistor provided by an embodiment of the present disclosure.
  • Figure 14 is a schematic flow chart of a method for manufacturing a transistor array provided by an embodiment of the present disclosure
  • 15a to 15e are schematic structural diagrams of the transistor array during the preparation process according to embodiments of the present disclosure.
  • Figure 16 is a schematic cross-sectional view of yet another transistor provided by an embodiment of the present disclosure.
  • orientation or positional relationship indicated by the terms “length”, “width”, “depth”, “upper”, “lower”, “outer”, etc. are based on those shown in the accompanying drawings.
  • the orientation or positional relationship is only for the convenience of describing the present disclosure and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the disclosure.
  • FIG. 1 is a schematic structural diagram of a DRAM memory unit provided by an embodiment of the present disclosure.
  • Each memory cell of DRAM includes a transistor and a capacitor, forming a 1T1C structure.
  • the gate of the transistor is connected to the word line (WL), the drain is connected to the bit line (BL), and the source is connected to the capacitor.
  • the voltage signal on the word line can control the opening or closing of the transistor, and then read the data in the capacitor through the bit line, or write the data into the capacitor through the bit line for storage.
  • the capacitor represents the data "1" or "0” by the amount of stored charge. Usually, a small charge represents a "0", and a large charge represents a "1", and vice versa.
  • FIG. 2 is a schematic structural diagram of a transistor using a buried word line according to an embodiment of the present disclosure.
  • the transistor includes a gate electrode 11 located in a substrate 10 , and a source electrode 12 and a drain electrode 13 located on both sides of the gate electrode 11 in the substrate 10 .
  • the substrate 10 between the source electrode 12 and the drain electrode 13 forms a channel layer 14 .
  • the gate dielectric layer 15 covers the gate electrode 11 to isolate the gate electrode 11 from the source electrode 12 , the drain electrode 13 and the channel layer 14 .
  • the substrate 10 of DRAM usually adopts traditional silicon semiconductor, such as hydrogenated amorphous silicon ⁇ -Si:H, polycrystalline silicon or single crystal silicon. That is, the material of the channel layer 14 is usually silicon semiconductor. Due to the low mobility of carriers in silicon semiconductors, the switching speed of transistors is slow, which in turn results in low read and write rates of memory cells. In addition, the off-current of silicon semiconductors is large. When the transistor is in the off state, the carriers stored in the capacitor are lost at a large rate, which will cause insufficient storage of charge in the capacitor and cause data errors. Therefore, the memory unit must shorten the time between two refreshes. interval, which results in greater power consumption of DRAM.
  • traditional silicon semiconductor such as hydrogenated amorphous silicon ⁇ -Si:H, polycrystalline silicon or single crystal silicon. That is, the material of the channel layer 14 is usually silicon semiconductor. Due to the low mobility of carriers in silicon semiconductors, the switching speed of transistors is slow, which in turn results in low read and write rates of memory cells. In addition, the off
  • FIG. 3 is a top view of a transistor array provided by an embodiment of the present disclosure
  • FIG. 4 is a partial cross-sectional view of the transistor array shown in FIG. 3 along line A-A. As shown in Figures 3 and 4, this transistor includes:
  • substrate 100 includes active region 110;
  • Gate structure 200 the gate structure 200 passes through the active area 110;
  • the gate structure 200 includes a gate electrode 210 and a gate dielectric layer 220, and the gate dielectric layer 220 covers the sidewalls and bottom of the gate electrode 210;
  • the channel layer 300 is located on the side of the gate dielectric layer 220 relatively away from the gate 210.
  • the channel layer 300 includes a metal oxide semiconductor layer;
  • the active region 110 includes a first active layer 111 and a second active layer 112 respectively located on both sides of the gate structure 200 .
  • the first active layer 111 and the second active layer 112 are both in contact with the channel layer 300 .
  • substrate 100 is a semiconductor substrate.
  • the material of the substrate can be silicon, germanium, silicon germanium semiconductor or silicon carbide, etc., or it can be silicon on insulator (SOI) or germanium on insulator (GOI), or it can also be other materials, such as gallium arsenide. etc. III and V group compounds.
  • the substrate 100 can also be implanted with certain doping ions according to design requirements to change the electrical parameters.
  • substrate 100 includes a plurality of active regions 110 and shallow trench isolation structures 120 .
  • a plurality of active areas 110 are arranged in an array, and the shallow trench isolation structure 120 is located between adjacent active areas 110 to electrically isolate the adjacent active areas 110 .
  • each active region 110 may include one or two transistors.
  • each active area 110 includes two transistors arranged in parallel.
  • the second active layers 112 of the two transistors are in contact and can be connected to the same bit line.
  • the first active layer 111 of the first transistor is connected to a capacitor, and the first active layer 111 of the second transistor can be connected to another capacitor.
  • One of the first active layer 111 and the second active layer 112 is a source electrode, and the other is a drain electrode.
  • the first active layer 111 is the source electrode
  • the second active layer 112 is the drain electrode, and vice versa.
  • the first active layer 111 and the second active layer 112 may be formed by injecting doping ions into the substrate 100, and the first active layer 111 and the second active layer 112 may be P-type at the same time.
  • the doped region can also be an N-type doped region at the same time.
  • the doping ions forming the P-type doped region may include boron (B), aluminum (Al), gallium (Ga), etc.
  • the doping ions forming the N-type doped region may include phosphorus (P), arsenic (As) or antimony (Sb).
  • the element types of the doped ions of the first active layer 111 and the second active layer 112 may be the same or different. In some embodiments, the element type of the doping ions of the first active layer 111 and the second active layer 112 is the same.
  • the gate electrode 210 passes through a plurality of active regions 110 arranged side by side, and also passes through the shallow trench isolation structure 120 between adjacent active regions 110 .
  • the plurality of transistors connected to the gate 210 can be controlled to be turned on or off.
  • one active region 110 may allow two gates 210 arranged side by side to pass through, so as to form two transistors in one active region 110 .
  • the first active layer 111 and the second active layer 112 of each transistor are respectively provided on both sides of the gate electrode 210 .
  • the material of the gate 210 may include metal (such as tantalum, titanium, molybdenum, tungsten, platinum, aluminum, hafnium, ruthenium), metal silicide (such as titanium silicide, cobalt silicide, nickel silicide, tantalum silicide), metal nitride (such as Conductive materials such as titanium nitride, tantalum nitride) or doped polysilicon.
  • metal such as tantalum, titanium, molybdenum, tungsten, platinum, aluminum, hafnium, ruthenium
  • metal silicide such as titanium silicide, cobalt silicide, nickel silicide, tantalum silicide
  • metal nitride such as Conductive materials such as titanium nitride, tantalum nitride
  • the material of the gate dielectric layer 220 may include silicon oxide, silicon nitride, or other high-k dielectric materials.
  • the channel layer 300 is located on a side of the gate dielectric layer 220 relatively away from the gate electrode 210 , that is, the channel layer 300 and the gate electrode 210 are isolated by the gate dielectric layer 220 .
  • the channel layer 300 is also in contact with the first active layer 111 and the second active layer 112 .
  • an inversion layer is formed in the channel layer 300 to form a conductive channel, the transistor is turned on, and carriers can pass through the first active layer 111 and the second active layer 112 flow between.
  • the channel layer 300 includes a metal oxide semiconductor layer, that is, the material of the channel layer 300 includes a metal oxide semiconductor.
  • Figure 5 shows the transfer characteristic curves of two transistors provided by embodiments of the present disclosure, in which the abscissa is the gate voltage V G and the ordinate is the base-10 logarithm of the current ID between the source and the drain.
  • the channel layer of transistor M1 is made of hydrogenated amorphous silicon ( ⁇ -Si:H) material
  • the channel layer of transistor M2 is made of amorphous metal oxide semiconductor (AOS) material.
  • the transistor M2 has a larger saturation current (On-current), a smaller off-current (Off-current), and the transistor M2 has a larger switching current ratio.
  • the switch current ratio is the ratio of the current output of the transistor in the on state and the off state.
  • the transfer characteristic curve of the transistor M2 is steeper than that of the transistor M1 , that is, the current of the transistor M2 changes faster from the off state to the on state.
  • the transistor M2 has the above device characteristics because the channel layer of the transistor M2 includes a metal oxide semiconductor layer.
  • the metal and the oxide are connected by ionic bonds, and the conduction band is composed of the s orbital of the metal.
  • the s orbital is spherical and isotropic.
  • the material of the metal oxide semiconductor layer contains more effective holes, which can also improve the mobility of electrons.
  • the carrier mobility of the amorphous metal oxide semiconductor layer is about 20 to 50 times that of hydrogenated amorphous silicon.
  • the transistor M2 using the metal oxide semiconductor layer can have a large saturation current and the current changes from the off state to the on state faster.
  • metal oxide semiconductors have a wide band gap.
  • the band gap value Eg of the metal oxide semiconductor can reach 3.1 eV. In the off state, it is difficult for electrons to be excited from the valence band to the conduction band. Therefore, the metal oxide semiconductor layer has a small off-current.
  • the channel layer of the transistor includes a metal oxide semiconductor layer.
  • the carrier mobility in the metal oxide semiconductor layer is high.
  • a migration layer with higher carrier mobility can be formed in the channel layer, thereby increasing the switching speed of the transistor, thus improving the The read and write operation rate of the storage unit.
  • the saturation current of transistors using metal oxide semiconductor layers is larger, so the volume of the transistor can be reduced, thereby reducing the volume of the memory unit and improving the integration of the memory.
  • the off-current of the transistor using the metal oxide semiconductor layer is small. When the transistor is in the off state, the loss rate of carriers in the capacitor is slow.
  • the stability of the memory unit is good, and when the carriers in the capacitor When the drain rate is slow, the time interval between two refreshes of the storage unit can be extended, thereby reducing the power consumption of the storage unit.
  • the switching current of transistors using metal oxide semiconductor layers is relatively large, and the current changes from the off state to the on state quickly, which can increase the switching speed of the transistor and improve the efficiency of the read and write operations of the memory cell.
  • the electrical performance of the transistor can be improved, thereby improving the storage performance of the memory unit, and improving the storage performance and integration of the memory.
  • the material of the metal oxide semiconductor layer includes indium gallium zinc oxide (InGaZnO, IGZO), indium tin oxide (ITO), indium tungsten oxide (InWO), indium zinc oxide (InZnO), gallium oxide (GaO x ), at least one of indium oxide (InOx).
  • the material of the channel layer 300 includes indium gallium zinc oxide (IGZO).
  • IGZO indium gallium zinc oxide
  • the indium element and the zinc element can improve the mobility of carriers in the channel layer 300.
  • the gallium element can also adjust other parameters of the transistor, such as adjusting the threshold voltage of the transistor, so that the transistor can obtain better performance. Overall performance.
  • the metal oxide semiconductor layer has a thickness of 0.5 nm to 3 nm.
  • controlling the thickness of the metal oxide semiconductor layer between 0.5nm and 3nm can reduce the defect rate of the metal oxide semiconductor layer, improve the quality of the metal oxide semiconductor layer, thereby improving its performance, and thereby improving The long-term reliability of transistors.
  • the channel layer 300 includes a first sub-channel layer 310 and a second sub-channel layer 320 that are stacked in sequence.
  • the second sub-channel layer 320 is located on the first sub-channel layer.
  • the first sub-channel layer 310 includes a silicon semiconductor layer or a silicon germanium semiconductor layer, that is, the material of the first sub-channel layer 310 includes a silicon semiconductor or a silicon germanium semiconductor.
  • the layer 320 includes a metal oxide semiconductor layer, that is, the material of the second sub-channel layer 320 includes a metal oxide semiconductor.
  • the first sub-channel layer 310 may be the substrate 100 located between the first active layer 111 and the second active layer 112 , and the material of the substrate 100 includes silicon semiconductor or silicon germanium semiconductor.
  • the first sub-channel layer 310 may also be a doped silicon semiconductor layer formed by injecting doping ions into the substrate 100 between the first active layer 111 and the second active layer 112 or a doped silicon semiconductor layer. Silicon germanium semiconductor layer. This method of directly forming the first sub-channel layer 310 in the substrate 100 can shorten the preparation cycle.
  • the first sub-channel layer 310 when the first active layer 111 and the second active layer 112 are P-type doped, the first sub-channel layer 310 is N-type doped. When the first active layer 111 and the second active layer 112 are N-type doped, the first sub-channel layer 310 is P-type doped.
  • the positions of the first sub-channel layer 310 and the second sub-channel layer 320 may also be: the first sub-channel layer 310 is located between the second sub-channel layer 320 and the gate dielectric layer 220 between.
  • the first sub-channel layer 310 may be formed by depositing a silicon semiconductor or a silicon germanium semiconductor on the sidewalls and bottom of the second sub-channel layer 320 .
  • the silicon semiconductor may be polycrystalline silicon or amorphous silicon, and polycrystalline silicon includes doped polycrystalline silicon.
  • the two sub-channel layers can further increase the size of the channel layer 300
  • the mobility of carriers is increased, and the saturation current of the channel layer 300 is increased, and the possibility of leakage of the channel layer is reduced, thereby enabling the transistor to have a faster switching speed.
  • the channel layer 300 may include a plurality of sub-channel layer groups, each sub-channel layer group including a first sub-channel layer 310 and a second sub-channel layer 320 .
  • the material of the sub-channel layer 310 includes silicon semiconductor or silicon germanium semiconductor, and the material of the second sub-channel layer 320 includes metal oxide semiconductor.
  • the second sub-channel layer 320 can be stacked on the first sub-channel layer 310 .
  • the first sub-channel layer 310 may be located on the second sub-channel layer 320 .
  • alternating metal oxide semiconductor layers and silicon semiconductor layers or silicon germanium semiconductor layers
  • multiple metal oxide semiconductor layers can be formed to increase the total thickness of the metal oxide semiconductor, thereby further improving the transistor performance.
  • transistors with different performances can also be obtained by designing the position, composition or shape of the channel layer 300, the gate dielectric layer 220 and the gate electrode 210.
  • 7 to 13 are schematic cross-sectional views of various transistors provided by embodiments of the present disclosure. The structure and performance of various transistors provided by embodiments of the present disclosure will be described in detail below with reference to FIG. 4 and FIG. 7 to FIG. 13 .
  • the metal oxide semiconductor layer (second sub-channel layer 320 ) may cover the first active layer 111 and the second active layer 112 relatively close to the sidewalls of the gate structure 200 , the top of the metal oxide semiconductor layer, the top of the first active layer 111 and the top of the second active layer 112 are flush. In this way, the length of the channel can be increased and the mobility of carriers can be improved.
  • the gate dielectric layer 220 may cover the sidewalls and bottom surface of the metal oxide semiconductor layer, and the gate dielectric layer 220 may be flush with the top of the metal oxide semiconductor layer.
  • the gate 210 may include a first part 211 and a second part 212.
  • the first part 211 is located on a side of the second part 212 relatively close to the surface of the substrate 100.
  • the first part 211 has a first size along a specified direction
  • the second portion 212 has a second dimension along the specified direction, the first dimension being smaller than the second dimension.
  • the specified direction is parallel to the surface of the substrate 100 and perpendicular to the extending direction of the gate electrode 210 .
  • the X direction in Figure 4 is the designated direction.
  • the surface of the first part 211 of the gate 210 may be a curved surface, so that the top of the cross section of the gate 210 is ⁇ -shaped, and the cross section of the gate 210 is perpendicular to the surface of the substrate 100 and perpendicular to the extension direction of the gate 210 .
  • setting the first size of the first part 211 of the gate to be smaller than the second size of the second part 212 can reduce the gate-induced drain leakage (GIDL) current of the transistor, that is, reduce the gate-induced drain leakage (GIDL) current of the transistor.
  • the off-current of the transistor increases the time interval between two adjacent refreshes of the memory and improves the performance of the memory.
  • the top of the gate 210 may be lower than the surface of the substrate 100 , and the transistor further includes a protective layer 400 filled in a side of the gate 210 relatively close to the surface of the substrate 100 .
  • the top of the protective layer 400 is flush with the top of the gate dielectric layer 220 .
  • the material of the protective layer 400 may include silicon nitride or silicon oxide.
  • the first active layer 111 and the second active layer 112 are located on top of the channel layer 300;
  • the gate dielectric layer 220 covers the sidewalls of the first active layer 111 and the second active layer 112 and the top portion of the channel layer 300 that is not covered by the first active layer 111 and the second active layer 112 .
  • the channel layer 300 includes a first sub-channel layer 310 (silicon semiconductor layer or silicon germanium semiconductor layer) and a second sub-channel layer 320 (metal oxide semiconductor layer).
  • the tops of the two sub-channel layers 320 are flush, the first active layer 111 and the second active layer 112 are located on the top of the first sub-channel layer 310, and the gate dielectric layer 220 covers the first active layer 111 and the second active layer 112.
  • the channel layer 300 provided in this embodiment can reduce gate-induced drain leakage current, thereby improving memory performance.
  • the first size of the first part 211 of the gate 210 may be larger than the second size of the second part 212 so that the cross-section of the gate 210 is T-shaped, which may increase the cross-section of the conductive layer of the gate 210 , reducing the resistance of the gate 210, thereby increasing the switching speed of the transistor and improving the reading and writing efficiency of the memory.
  • the structure of the transistor can also be shown in FIG. 8 and FIG. 9 , and the structure of the channel layer 300 and the gate dielectric layer 220 of the transistor is the same as that of the transistor shown in FIG. 7 .
  • the gate 210 of the transistor includes a first sub-gate 213 and a second sub-gate 214.
  • the second sub-gate 214 is located on a side of the first sub-gate 213 relatively close to the surface of the substrate 100.
  • the first sub-gate 213 The electrode 213 is made of metal, and the second sub-gate 214 is made of polysilicon.
  • the material of the second sub-gate 214 may also be doped polysilicon.
  • the structure of the first sub-gate 213 may be T-shaped in cross-section (as shown in FIG. 8 ), or may be ⁇ -shaped at the top of the cross-section (as shown in FIG. 9 ).
  • the second sub-gate 214 has a third size along a specified direction (X direction), and the third size is equal to or larger than the first size and the second size of the first sub-gate 213 .
  • the third size of the second sub-gate 214 is equal to the first size of the first part 211 of the first sub-gate 213 and is larger than the second size of the second part 212 .
  • the third size of the second sub-gate 214 is larger than the first size of the first portion 211 and the second size of the second portion 212 of the first sub-gate 213 .
  • the composite gate structure composed of the first sub-gate 213 and the second sub-gate 214 can reduce the gate-induced drain leakage current, thereby improving the performance of the memory.
  • the structure of the transistor may be as shown in FIGS. 10 to 13 .
  • the second sub-channel layer 320 metal oxide semiconductor layer covers the first active layer 111 and the second active layer 112 is relatively close to the gate.
  • the sidewalls of the pole structure 200 and the top of the second sub-channel layer 320 are flush with the tops of the first active layer 111 and the second active layer 112 .
  • the gate dielectric layer 220 covers the bottom surface and part of the sidewalls of the second sub-channel layer 320 , and the top of the gate dielectric layer 220 is lower than the top of the second sub-channel layer 320 .
  • the structure of the second sub-channel layer 320 and the gate dielectric layer 220 provided in this embodiment can reduce the gate-induced drain leakage current, thereby improving the performance of the memory.
  • the structure of the gate electrode 210 may be as shown in FIG. 10 , and the cross-sectional top shape of the gate electrode 210 is ⁇ -shaped, thereby further reducing the gate-induced drain leakage current.
  • the structure of the gate 210 can also be as shown in FIG. 11 , and the cross-sectional shape of the gate 210 is T-shaped, thereby increasing the cross-section of the gate conductive layer, reducing the gate resistance, and increasing the switching speed of the transistor.
  • the structure of the gate 210 may also be as shown in FIG. 12 .
  • the gate 210 includes a first sub-gate 213 and a second sub-gate 214 .
  • the cross-sectional top shape of the first sub-gate 213 is ⁇ -shaped.
  • the structure of the gate 210 may also be as shown in FIG. 13 .
  • the gate 210 includes a first sub-gate 213 and a second sub-gate 214 .
  • the cross-sectional shape of the first sub-gate 213 is T-shaped.
  • the composite gate structure formed by the first sub-gate 213 and the second sub-gate 214 can further reduce the gate-induced drain leakage current.
  • transistors with different performances can be obtained by controlling the positions, compositions, and shapes of the channel layer, the gate dielectric layer, and the gate electrode, thereby obtaining memories with different performances. For example, transistors with faster switching speeds can be obtained, resulting in memory with higher read and write speeds, or transistors with smaller off-current can be obtained, resulting in memories with longer refresh intervals.
  • FIG. 14 is a schematic flow chart of a method of manufacturing a transistor provided by an embodiment of the present disclosure. As shown in Figure 14, the preparation method includes the following steps:
  • S100 Provide a substrate 100; wherein the substrate 100 includes an active region 110, and a trench passing through the active region 110 is formed in the substrate 100;
  • S200 Form the first active layer 111 and the second active layer 112 in the active area 110; wherein the first active layer 111 and the second active layer 112 are respectively provided on both sides of the trench;
  • S300 Form a channel layer 300 at the bottom and sidewalls of the trench located in the active area 110; wherein the channel layer 300 includes a metal oxide semiconductor layer; the channel layer 300 is connected with the first active layer 111 and the second active layer 111.
  • the source layers 112 are in contact;
  • S400 Form the gate dielectric layer 220 and the gate electrode 210 sequentially in the trench; wherein the gate dielectric layer 220 covers the channel layer 300.
  • steps S100 to S400 are not necessarily performed in precise order. On the contrary, various steps can be processed in any order or simultaneously. Additionally, additional steps can be added to these procedures.
  • FIG. 15a to 15e are schematic structural diagrams of the transistor array provided by the embodiment of the present disclosure during the preparation process.
  • the preparation method of the transistor provided by the embodiment of the present disclosure will be introduced below with reference to FIG. 3 and FIG. 15a to 15e. It should be noted that FIG. 15a to FIG. 15e are cross-sectional views of the transistor array along line A-A.
  • step S100 is performed to provide a substrate 100.
  • the substrate 100 includes an active region 110, and a trench 500 passing through the active region 110 is formed in the substrate 100.
  • the material of the substrate 100 may include silicon (Si), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or silicon germanium semiconductor, etc.
  • the substrate 100 includes a plurality of active regions 110 arranged in an array, and shallow trench isolation structures 120 located between adjacent active regions 110 .
  • the trench 500 passes through a plurality of active regions 110 arranged side by side, and also passes through the shallow trench isolation structure 120 between adjacent active regions 110 . Therefore, it can be understood that in FIG. 15a, a trench 500 is also formed in the shallow trench isolation structure 120.
  • the gate 210 and the gate dielectric layer 220 are formed in the trench 500, The first active layer 111 and the second active layer 112 are not formed on both sides of the gate dielectric layer 220 , therefore, no transistor is formed in the shallow trench isolation structure 120 .
  • one active region 110 may allow two trenches 500 arranged side by side to pass through, so as to form two transistors in one active region 110 .
  • the material of the shallow trench isolation structure 120 may include silicon oxide.
  • the depth of the portion of the trench 500 located in the substrate 100 and the portion of the trench 500 located in the shallow trench isolation structure 120 are different because the materials of the substrate 100 and the shallow trench isolation structure 120 are different. Under the etching conditions, the etching rates of the two are different. Therefore, the depth of the portion of the trench 500 located in the substrate 100 is different from the depth of the portion of the trench 500 located in the shallow trench isolation structure 120 .
  • the depth of the portion of the trench 500 located in the substrate 100 may be smaller or greater than the portion of the trench 500 located in the shallow trench isolation structure 120 , depending on the materials and etching conditions of the substrate 100 and the shallow trench isolation structure 120 .
  • an insulating layer 121 and a mask layer 600 are also sequentially stacked on the substrate 100.
  • the insulating layer 121 may be made of the same material as the shallow trench isolation structure 120 , such as silicon oxide.
  • the insulation layer 121 may be formed in the same step as the shallow trench isolation structure 120 .
  • the material of the mask layer 600 may include silicon nitride.
  • the plurality of trenches 500 also penetrate the mask layer 600 and the insulating layer 121 and extend into the substrate 100 or into the shallow trench isolation structure 120 .
  • step S200 is performed to inject first doping ions into the first region and the third region of the active region 110 to form the first active layer 111 of the first transistor and the first active layer of the second transistor.
  • Layer 111 Second doping ions are implanted into the second region of the active region 110 to form the second active layer 112 of the first transistor and the second active layer 112 of the second transistor.
  • the first doping ions may include P-type doping ions (eg, boron, aluminum, or gallium), or N-type doping ions (eg, phosphorus, arsenic, or antimony), and the second doping ions may also include P-type doping ions (such as boron, aluminum or gallium), or N-type doping ions (such as phosphorus, arsenic or antimony).
  • the first doping ions and the second doping ions may both be P-type doping ions or N-type doping ions.
  • the element type of the first doping ion and the element type of the second doping ion may be the same.
  • steps S300 and S400 are performed to form a channel layer 300 at the bottom and sidewalls of the trench 500 in the active area 110 , and a gate dielectric layer 220 and a gate electrode 210 are sequentially formed in the trench 500 .
  • the channel layer 300 may include a first sub-channel layer 310 and a second sub-channel layer 320 stacked in sequence.
  • the material of the first sub-channel layer 310 is doped silicon semiconductor or doped silicon germanium.
  • Semiconductor, the material of the second sub-channel layer 320 is a metal oxide semiconductor.
  • third doping ions are implanted into the substrate 100 between the first active layer 111 and the second active layer 112 to form the first sub-channel layer 310 .
  • the third doping ions may include P-type doping ions (eg, boron, aluminum, or gallium), or N-type doping ions (eg, phosphorus, arsenic, or antimony). It can be understood that when the first active layer 111 and the second active layer 112 are N-type doped, the first sub-channel layer 310 may be P-type doped. When the first active layer 111 and the second active layer 112 are P-type doped, the first sub-channel layer 310 may be N-type doped.
  • step S200 may be performed first to form the first active layer 111 and the second active layer by injecting first doping ions and second doping ions into the active region 110 112. Then perform step S300 to inject third doping ions into the active region 110 to form the first sub-channel layer 310; you may also perform step S300 first, dope to form the first sub-channel layer 310, and then dope.
  • the first active layer 111 and the second active layer 112 are formed. This disclosure is not limited in this regard.
  • step S400 may be executed before steps S200 and S300, may be executed after S200 and S300, or may be executed between S200 and S300, to which the disclosure is not limited.
  • step S200 and step S300 are performed first, and then step S400 is performed, that is, after the first active layer 111, the second active layer 112 and the first sub-channel layer 310 are formed, the gate electrode is formed. 210, which can avoid the impact of ion implantation on the gate 210.
  • a second sub-channel layer 320 covering the sidewalls and bottom of the trench 500 is formed, and the second sub-channel layer 320 includes a metal oxide semiconductor layer.
  • the metal oxide semiconductor layer may include at least one of indium gallium zinc oxide, indium tin oxide, indium tungsten oxide, indium zinc oxide, gallium oxide, and indium oxide.
  • the thickness of the metal oxide semiconductor layer may be 0.5nm to 3nm.
  • the second sub-channel layer 320 since the first sub-channel layer 310 is located in the substrate 100 close to the trench 500, the second sub-channel layer 320 also covers the bottom and sidewalls of the first sub-channel layer 310.
  • only the second sub-channel layer 320 may be provided without the first sub-channel layer 310 .
  • the second sub-channel layer 320 is located in the trench 500 of the active region 110 and is also located in the trench 500 of the shallow trench isolation structure 120, that is, the second sub-channel layer 320 is located in the trench 500 of the active region 110.
  • the channel layer 320 is located on the sidewall and bottom of the entire trench 500, so that the process of setting the second sub-channel layer 320 is relatively simple.
  • the second sub-channel layer 320 may be formed only in the trench 500 in the active region 110 , and the second sub-channel layer 320 is not disposed in the trench 500 in the shallow trench isolation structure 120 .
  • the second sub-channel material layer located in the shallow trench isolation structure 120 can be etched away, leaving only the second sub-channel material layer located at the sidewalls and bottom of the trench 500 in the active area 110 to form a third sub-channel material layer. Two sub-channel layers 320. In this way, interference between adjacent transistors can be reduced.
  • the step of forming the second sub-channel layer 320 covering the sidewalls and the bottom of the trench 500 includes: forming the sidewalls and the bottom of the trench 500 , and forming a second sub-channel layer 320 covering the surface of the mask layer 600 .
  • Sub-channel material layer use chemical mechanical polishing (CMP) to remove the second sub-channel material layer located on the surface of the mask layer 600, leaving only the second sub-channel material layer located on the sidewalls and bottom of the trench 500 to form The second sub-channel layer 320.
  • CMP chemical mechanical polishing
  • a gate dielectric layer 220 covering the sidewalls and bottom of the second sub-channel layer 320 is formed; finally, a gate dielectric layer 220 is formed covering the sidewalls and bottom of the gate dielectric layer 220 and the surface of the mask layer 600 .
  • the gate material layer fills the remaining gaps in the trench 500 .
  • the step of forming the gate dielectric layer 220 covering the sidewalls and the bottom of the second sub-channel layer 320 includes: forming the sidewalls and the bottom of the second sub-channel layer 320 , and covering a mask.
  • the gate material layer includes a third sub-gate material layer and a fourth sub-gate material layer; the step of forming the gate material layer includes: forming a third sub-gate material layer covering the sidewalls and bottom of the gate dielectric layer 220 .
  • the sub-gate material layer forms a sidewall and bottom covering the third sub-gate material layer, and a fourth sub-gate material layer covering the surface of the mask layer 600; wherein the fourth sub-gate material layer fills the trench. The remaining gap within 500.
  • the material of the third sub-gate material layer includes metal nitride, such as titanium nitride, tantalum nitride, tungsten nitride, etc.
  • the fourth sub-gate material layer is made of metal, such as tantalum, titanium, molybdenum, tungsten, platinum, aluminum, hafnium, ruthenium, cobalt, etc.
  • the fourth sub-gate material layer located on the surface of the mask layer 600 is removed.
  • a chemical mechanical polishing process may be used to remove the fourth sub-gate material layer located on the surface of the mask layer 600 , leaving only the fourth sub-gate material layer in the trench 500 .
  • part of the third sub-gate material layer located on the sidewall of the gate dielectric layer 220 is removed by etching, and the remaining third sub-gate material layer forms the third sub-gate 215 .
  • Part of the fourth sub-gate material layer is removed by etching, and the remaining fourth sub-gate material layer forms the fourth sub-gate 216, where the top of the fourth sub-gate 216 can be higher than or flush with the third sub-gate. 215 top.
  • the third sub-gate 215 and the fourth sub-gate 216 constitute the gate 210 in this embodiment.
  • the third sub-gate material layer can be etched first, and then the fourth sub-gate material layer can be etched; the fourth sub-gate material layer can also be etched first, and then the third sub-gate material layer can be etched.
  • the disclosure is not limited.
  • the mask layer 600, as well as the second sub-channel layer 320 and the gate dielectric layer 220 located in the mask layer are removed; a protective layer is formed to fill the remaining gaps in the trench 500 and cover the surface of the insulating layer 121. 400.
  • the protective layer 400 may be made of silicon oxide or silicon nitride.
  • the preparation method includes:
  • etching removes part of the second sub-channel material layer located on the sidewalls of the trench 500, leaving the remaining second sub-channel material layer Form a second sub-channel layer 320, wherein the top of the second sub-channel layer 320 is flush with the top of the first sub-channel layer 310, and both are lower than the surface of the substrate 100;
  • the gate dielectric layer 220 covers the surface of the trench 500 that is not covered by the second sub-channel layer 320 , and covers the top, sidewalls and bottom of the second sub-channel layer 320 .
  • the surface of the trench 500 not covered by the second sub-channel layer 320 includes the sidewalls of the first active layer 111 and the second active layer 112 .
  • step S400 further includes:
  • a first sub-gate 213 is formed on the side of the gate dielectric layer 220 relatively away from the channel layer 300; wherein, the material of the first sub-gate 213 includes metal;
  • a second sub-gate 214 is formed on the top of the first sub-gate 213; the material of the second sub-gate 214 includes polysilicon.
  • a first sub-gate material layer is formed to fill the remaining gaps in the trench 500; part of the first sub-gate material layer is removed by etching, and the remaining first sub-gate material is Form the first sub-gate 213; form a second sub-gate material on the top of the first sub-gate 213 in the trench 500, remove part of the second sub-gate material, and the remaining second sub-gate material forms a second sub-gate Extreme 214.
  • the preparation method further includes:
  • the gate dielectric material layer located on the second sub-channel layer 320 After the gate dielectric material layer located on the second sub-channel layer 320 is formed, part of the gate dielectric material layer located on the sidewall of the second sub-channel layer 320 is removed, and the remaining gate dielectric material layer forms the gate dielectric layer 220 .
  • the gate electrode and protective layer 400 are continued to be formed in the trench 500 .
  • An embodiment of the present disclosure also provides a memory.
  • the memory includes a storage unit configured to store data.
  • the storage unit includes any of the above-mentioned transistors.
  • the memory cell further includes a capacitor coupled to the first active layer 111 or the second active layer 112 of the transistor in the memory cell.
  • the transistor may also be applied to a peripheral circuit of the memory, and the transistor may be coupled to the memory unit and configured to control the operation of the memory unit.
  • Figure 16 is a schematic structural diagram of a transistor applied to a memory cell according to an embodiment of the present disclosure. As shown in Figure 16, the transistor may also include:
  • the deep well region 130 is located on the side of the well region 330 relatively away from the second sub-channel layer 320;
  • the first contact structure 710, the adhesion layer 720, the first barrier layer 730 and the first contact pad 740 are sequentially stacked on the first active layer 111;
  • the second contact structure 810, the second barrier layer 830 and the second contact pad 840 are sequentially stacked on the second active layer 112; and,
  • An isolation structure located on the protective layer 400 includes a first sub-isolation structure 851, a second sub-isolation structure 852 and a third sub-isolation structure 853 that are sequentially stacked along a specified direction (X direction).
  • a region of the well region 330 relatively close to the gate 210 may serve as a first sub-channel layer.
  • the deep well region 130 is used to isolate the transistor from other structures.
  • the doping ions in the deep well region 130 may include P-type doping ions (such as boron, aluminum or gallium), or N-type doping ions (such as phosphorus, arsenic or antimony). ), when the well region 330 is P-type doped, the deep well region 130 is N-type doped, or when the well region 330 is N-type doped, the deep well region 130 is P-type doped.
  • the substrate 100 may include an N-type semiconductor.
  • the material of the first contact structure 710 and the second contact structure 810 may include polysilicon.
  • the material of the adhesion layer 720 may include metal silicide, such as titanium silicide, cobalt silicide, nickel silicide, tantalum silicide, etc.
  • the adhesion layer 720 is used to reduce contact resistance.
  • the material of the first barrier layer 730 and the second barrier layer 830 may include metal nitride, such as titanium nitride, tantalum nitride, tungsten nitride, etc.
  • the first barrier layer 730 and the second barrier layer 830 are used to prevent metal diffusion.
  • the element types of the first barrier layer 730 and the second barrier layer 830 may be the same.
  • the material of the first sub-isolation structure 851, the second sub-isolation structure 852 and the third sub-isolation structure 853 may include silicon oxide or silicon nitride.
  • the first sub-isolation structure 851 and the third sub-isolation structure 853 may be made of the same material.
  • the material of the first contact pad 740 and the second contact pad 840 may include metal, such as tantalum, titanium, molybdenum, tungsten, platinum, aluminum, hafnium, ruthenium, cobalt, etc.
  • the element types of the first contact pad 740 and the second contact pad 840 may be the same.
  • the first contact pad 740 is used to connect the capacitor and the second contact pad 840 is used to connect the bit line.
  • the transistor array provided in this embodiment, together with the capacitor and the bit line, constitutes a memory cell array of a memory, where the memory is a DRAM.

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Abstract

本公开实施例提供了一种晶体管及其制备方法、以及存储器，该晶体管包括：衬底，所述衬底包括有源区；栅极结构，所述栅极结构穿过所述有源区；所述栅极结构包括栅极和栅极介质层，所述栅极介质层覆盖所述栅极的侧壁和底部；沟道层，位于所述栅极介质层相对远离所述栅极的一侧，所述沟道层包括金属氧化物半导体层；所述有源区包括分设于所述栅极结构两侧的第一有源层和第二有源层，所述第一有源层和所述第二有源层均与所述沟道层相接触。

Description

晶体管及其制备方法、以及存储器
相关申请的交叉引用
本公开基于申请号为202210590499.0、申请日为2022年05月26日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及但不限于一种晶体管及其制备方法、以及存储器。
背景技术
晶体管是电子电路中的重要元件。晶体管利用栅极电压来控制源极和漏极间流经沟道的电流，是一种电压控制性开关器件。
晶体管可用于形成存储器，例如可用于动态随机存取存储器(Dynamic random access memory，简称DRAM)中，与电容器共同形成存储单元。晶体管的电学性能对存储单元的存储性能有重要影响，因此，提高晶体管的电学性能是提高存储单元的性能的重要途径。
发明内容
根据本公开的第一个方面，提供了一种晶体管，包括：
衬底，所述衬底包括有源区；
栅极结构，所述栅极结构穿过所述有源区；所述栅极结构包括栅极和栅极介质层，所述栅极介质层覆盖所述栅极的侧壁和底部；
沟道层，位于所述栅极介质层相对远离所述栅极的一侧，所述沟道层包括金属氧化物半导体层；
所述有源区包括分设于所述栅极结构两侧的第一有源层和第二有源层，所述第一有源层和所述第二有源层均与所述沟道层相接触。
在一些实施例中，所述金属氧化物半导体层的材质包括氧化铟镓锌、氧化铟锡、氧化铟钨、氧化铟锌、氧化镓、氧化铟中的至少一种。
在一些实施例中，所述金属氧化物半导体层的厚度为0.5nm至3nm。
在一些实施例中，所述沟道层包括至少一个子沟道层组，所述子沟道层组包括依次层叠的两个子沟道层，所述两个子沟道层其中之一子沟道层包括所述金属氧化物半导体层，另一子沟道层包括硅锗半导体层或硅半导体层。
在一些实施例中，所述金属氧化物半导体层覆盖所述第一有源层和所述第二有源层相对靠近所述栅极结构的侧壁。
在一些实施例中，所述第一有源层和所述第二有源层位于所述沟道层的顶部；
所述栅极介质层，覆盖所述第一有源层和所述第二有源层的侧壁、以及所述沟道层的顶部未被所述第一有源层和所述第二有源层覆盖的部分。
在一些实施例中，所述栅极包括第一部分和第二部分，所述第一部分位于所述第二部分相对靠近所述衬底表面的一侧，所述第一部分具有沿指定方向的第一尺寸，所述第二部分具有沿所述指定方向的第二尺寸，所述第一尺寸大于所述第二尺寸，所述指定方向平行于所述衬底表面，且与所述栅极的延伸方向相垂直。
在一些实施例中，所述栅极包括第一子栅极和第二子栅极，所述第二子栅极位于所述第一子栅极相对靠近所述衬底表面的一侧，所述第一子栅极的材质包括金属，所述第二子栅极的材质包括多晶硅。
根据本公开的第二个方面，提供了一种存储器，包括：
存储单元，所述存储单元配置为存储数据；所述存储单元包括如本公开的第一个方面所述的晶体管。
在一些实施例中，所述存储单元还包括：
电容器，所述电容器与所述存储单元中的所述晶体管的第一有源层或第二有源层耦合。
根据本公开的第三个方面，提供了一种晶体管的制备方法，包括：
提供衬底；其中，所述衬底包括有源区，所述衬底中形成有穿过所述有源区的沟槽；
在所述有源区形成第一有源层和第二有源层；其中，所述第一有源层和所述第二有源层分设于所述沟槽的两侧；
在位于所述有源区的所述沟槽的底部和侧壁形成沟道层；其中，所述沟道层包括金属氧化物半导体层；所述沟道层与所述第一有源层和所述第二有源层相接触；
在所述沟槽内依次形成栅极介质层和栅极；其中，所述栅极介质层覆盖所述沟道层。
在一些实施例中，所述金属氧化物半导体层的材质包括氧化铟镓锌、氧化铟锡、氧化铟钨、氧化铟锌、氧化镓、氧化铟中的至少一种。
在一些实施例中，所述金属氧化物半导体层的厚度为0.5nm至3nm。
在一些实施例中，所述沟道层包括依次层叠的第一子沟道层和第二子沟道层；所述在位于所述有源区的所述沟槽的底部和侧壁形成沟道层的步骤，包括：
向位于所述有源区的所述沟槽的底部和侧壁注入掺杂离子，形成第一子沟道层；
形成覆盖所述第一子沟道层的底部和侧壁的第二子沟道层；其中，所述第二子沟道层包括金属氧化物半导体层。
在一些实施例中，所述第一有源层和所述第二有源层位于所述第一子沟道层的顶部，所述第二子沟道层还覆盖所述第一有源层和所述第二有源层相对靠近所述栅极的侧壁；所述形成覆盖所述第一子沟道层的底部和侧壁的第二子沟道层的步骤，包括：
形成覆盖所述沟槽的底部和侧壁的第二子沟道层；其中，所述第二子沟道 层的顶部与所述第一有源层和所述第二有源层的顶部平齐。
在一些实施例中，所述第一有源层和所述第二有源层位于所述第一子沟道层的顶部，所述第二子沟道层的顶部和所述第一子沟道层的顶部平齐；
所述在所述沟槽内形成栅极介质层的步骤，包括：
在所述沟槽内形成栅极介质层；其中，所述栅极介质层还覆盖所述第二子沟道层的顶部，以及所述第一有源层和所述第二有源层的侧壁。
在一些实施例中，所述栅极包括第一子栅极和第二子栅极，所述第二子栅极位于所述第一子栅极相对靠近所述衬底表面的一侧；
所述在所述沟槽内形成栅极的步骤，包括：
在所述栅极介质层相对远离所述沟道层一侧形成所述第一子栅极；其中，所述第一子栅极的材质包括金属；
在所述第一子栅极的顶部形成所述第二子栅极；其中，所述第二子栅极的材质包括多晶硅。
附图说明
图1为本公开实施例提供的DRAM的存储单元的结构示意图；
图2为本公开实施例提供的采用埋入式字线的晶体管的结构示意图；
图3为本公开实施例提供的晶体管阵列的俯视图；
图4为图3所示的晶体管阵列的沿A-A线的局部剖视图；
图5为本公开实施例提供的两种晶体管的转移特性曲线；
图6为本公开实施例提供的一种晶体管的截面示意图；
图7为本公开实施例提供的又一种晶体管的截面示意图；
图8为本公开实施例提供的又一种晶体管的截面示意图；
图9为本公开实施例提供的又一种晶体管的截面示意图；
图10为本公开实施例提供的又一种晶体管的截面示意图；
图11为本公开实施例提供的又一种晶体管的截面示意图；
图12为本公开实施例提供的又一种晶体管的截面示意图；
图13为本公开实施例提供的又一种晶体管的截面示意图；
图14为本公开实施例提供的晶体管阵列的制备方法的流程示意图；
图15a至图15e为本公开实施例提供的晶体管阵列在制备过程中的结构示意图；
图16为本公开实施例提供的又一种晶体管的截面示意图。
具体实施方式
以下结合说明书附图及具体实施例对本公开的技术方案做详细阐述。
在本公开的描述中，需要理解的是，术语“长度”、“宽度”、“深度”、“上”、“下”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解 为对本公开的限制。
本公开实施例以DRAM的存储单元为例进行描述。图1为本公开实施例提供的DRAM的存储单元的结构示意图。DRAM的每个存储单元包括一个晶体管和一个电容器，构成1T1C结构。晶体管的栅极与字线(WL)相连，漏极与位线(BL)相连，源极与电容器相连。字线上的电压信号能够控制晶体管的打开或关闭，进而通过位线读取在电容器中的数据，或者通过位线将数据写入电容器中进行存储。电容器以存储电荷的多少表示数据“1”或“0”，通常以少电荷代表“0”，多电荷代表“1”，反之亦可。
为提高DRAM的集成度，DRAM存储单元中的晶体管通常采用埋入式字线(Buried Wordline)结构。图2为本公开实施例提供的采用埋入式字线的晶体管的结构示意图。该晶体管包括位于衬底10中的栅极11，以及在衬底10中分设于栅极11两侧的源极12和漏极13。位于源极12和漏极13之间的衬底10形成沟道层14。栅极介质层15覆盖栅极11，以将栅极11与源极12、漏极13和沟道层14相隔离。
DRAM的衬底10通常采用传统的硅半导体，如氢化非晶硅α-Si：H、多晶硅或单晶硅。也即，沟道层14的材质通常为硅半导体。由于硅半导体中载流子的迁移率较低，导致晶体管的开关速度较慢，进而导致存储单元的读写速率较低。此外，硅半导体的截止电流较大，当晶体管处于关态时，电容器中存储的载流子流失速率较大，会导致电容器存储电荷不足而产生数据出错，因此存储单元必须缩短两次刷新的时间间隔，这就导致DRAM的功耗较大。
鉴于此，本公开实施例提供了一种晶体管，该晶体管的沟道层具有较高的迁移率，并且具有较小的截止电流，可提高DRAM的存储性能。图3为本公开实施例提供的晶体管阵列的俯视图，图4为图3所示的晶体管阵列沿A-A线的局部剖视图。如图3和图4所示，该晶体管包括：
衬底100，衬底100包括有源区110；
栅极结构200，栅极结构200穿过有源区110；栅极结构200包括栅极210和栅极介质层220，栅极介质层220覆盖栅极210的侧壁和底部；
沟道层300，位于栅极介质层220相对远离栅极210的一侧，沟道层300包括金属氧化物半导体层；
有源区110包括分设于栅极结构200两侧的第一有源层111和第二有源层112，第一有源层111和第二有源层112均与沟道层300相接触。
在一些实施例中，衬底100是半导体衬底。具体地，衬底的材料可以是硅、锗、硅锗半导体或碳化硅等，也可以是绝缘体上硅(SOI)或者绝缘体上锗(GOI)，或者还可以为其他的材料，例如砷化镓等Ⅲ、Ⅴ族化合物。衬底100还可以根据设计需求注入一定的掺杂离子以改变电学参数。
参见图3，衬底100包括多个有源区110和浅槽隔离结构120。多个有源区110呈阵列排布，浅槽隔离结构120位于相邻有源区110之间，以电隔离相邻有源区110。
示例地，每个有源区110可包括一个或两个晶体管。本实施例中，每个有源区110包括两个并列排布的晶体管，两个晶体管的第二有源层112相接触， 并可与同一位线相连。第一个晶体管的第一有源层111与一个电容器相连，第二个晶体管的第一有源层111可与另外一个电容器相连。
第一有源层111和第二有源层112其中之一为源极，另一为漏极。示例地，第一有源层111为源极，第二有源层112为漏极，反之亦可。
在一些实施例中，第一有源层111和第二有源层112可通过向衬底100中注入掺杂离子形成，第一有源层111和第二有源层112可同时为P型掺杂区，也可同时为N型掺杂区。
形成P型掺杂区的掺杂离子可包括硼(B)、铝(Al)或镓(Ga)等。形成N型掺杂区的掺杂离子可包括磷(P)、砷(As)或锑(Sb)等。第一有源层111和第二有源层112的掺杂离子的元素类型可以相同，也可以不同。在一些实施例中，第一有源层111和第二有源层112的掺杂离子的元素类型相同。
进一步参见图3，栅极210穿过多个并列排布的有源区110，以及还穿过相邻有源区110之间的浅槽隔离结构120。通过控制施加在栅极210上的电压，可控制与该栅极210相连的多个晶体管的开启或关闭。
在一些实施例中，一个有源区110可允许并列排布的两个栅极210穿过，以在一个有源区110形成两个晶体管。每个晶体管的第一有源层111和第二有源层112分设于栅极210的两侧。
栅极210的材料可包括金属(例如钽、钛、钼、钨、铂、铝、铪、钌)、金属硅化物(例如硅化钛、硅化钴、硅化镍、硅化钽)、金属氮化物(例如氮化钛、氮化钽)或者掺杂多晶硅等导电材料。
栅极介质层220的材料可包括氧化硅、氮化硅或其他高k介电材料。
沟道层300位于栅极介质层220相对远离栅极210的一侧，也即沟道层300和栅极210通过栅极介质层220隔离。沟道层300还与第一有源层111和第二有源层112相接触。当向栅极210施加的电压大于该晶体管的阈值电压后，在沟道层300形成反型层构成导电通道，晶体管开启，载流子可在第一有源层111和第二有源层112之间流动。
本公开实施例中，沟道层300包括金属氧化物半导体层，即沟道层300的材质包括金属氧化物半导体。
图5为本公开实施例提供的两种晶体管的转移特性曲线，其中，横坐标为栅极电压V G，纵坐标为源极和漏极之间的电流I D以10为底的对数。晶体管M1的沟道层采用氢化非晶硅(α-Si：H)材料，晶体管M2的沟道层采用非晶态金属氧化物半导体(Amorphous oxide semiconductor，AOS)材料。如图5所示，晶体管M2具有更大的饱和电流(On-current)，更小的截止电流(Off-current)，并且晶体管M2具有更大的开关电流比。开关电流比为晶体管处于开态和关态的电流输出比。
此外，当栅极电压V G大于阈值电压后，晶体管M2的转移特性曲线相较晶体管M1更陡峭，也即，晶体管M2从关态到开态的电流变化更快。
晶体管M2具有上述器件特性，是由于晶体管M2的沟道层包括金属氧化物半导体层。金属氧化物半导体层中，金属与氧化物以离子键相连，导带由金属的s轨道构成，s轨道为球形、各项同性。还由于金属原子外层轨道半径较大， 相邻原子间s轨道发生重叠，为电子传输提供了路径，因此，金属氧化物半导体层具有较高的迁移率。进一步的，金属氧化物半导体层的材质包括较多的有效空穴，也能提高电子的迁移率。示例地，非晶态金属氧化物半导体层的载流子迁移率约是氢化非晶硅的载流子迁移率的20到50倍。
由于金属氧化物半导体层具有高的载流子迁移率，因此，可使采用其的晶体管M2具有大的饱和电流，以及从关态到开态的电流变化更快。
另外，金属氧化物半导体具有宽带隙，示例地，金属氧化物半导体的带隙值Eg可达到3.1eV。在关态下，电子从价带被激发到导带的难度大，因此，金属氧化物半导体层具有较小的截止电流。
本公开实施例中，晶体管的沟道层包括金属氧化物半导体层。第一方面，金属氧化物半导体层中载流子迁移率高，当晶体管处于开态时，能够在沟道层中形成载流子迁移率较高的迁移层，提高晶体管的开关速度，从而提高了存储单元的读写操作速率。第二方面，采用金属氧化物半导体层的晶体管饱和电流较大，因此可减小晶体管的体积，从而减小存储单元的体积，提高存储器的集成度。第三方面，采用金属氧化物半导体层的晶体管截止电流较小，当晶体管处于关态时，电容器中载流子流失速率较慢，因此，存储单元的稳定性好，并且当电容器中载流子流失速率较慢时，可延长存储单元两次刷新的时间间隔，从而降低存储单元的功耗。第四方面，采用金属氧化物半导体层的晶体管的开关电流比较大，从关态到开态的电流变化较快，能够提高晶体管的开关速度，提高存储单元的读写操作效率。总言之，本公开实施例中，当沟道层包括金属氧化物半导体层时，能够提高晶体管的电性能，从而提高存储单元的存储性能，提高存储器的存储性能和集成度。
在一些实施例中，金属氧化物半导体层的材质包括氧化铟镓锌(InGaZnO，IGZO)、氧化铟锡(ITO)、氧化铟钨(InWO)、氧化铟锌(InZnO)、氧化镓(GaO x)、氧化铟(InOx)中的至少一种。
在一些实施例中，沟道层300的材质包括氧化铟镓锌(IGZO)。氧化铟镓锌中，铟元素和锌元素能够提高沟道层300中载流子的迁移率，镓元素还能调整晶体管的其他参数，例如能够调整晶体管的阈值电压，从而使晶体管获得较好的综合性能。
在一些实施例中，金属氧化物半导体层的厚度为0.5nm至3nm。
由于金属氧化物半导体层的成形工艺难度大，金属氧化物半导体层的厚度越大，成形效果越差，缺陷率越高。因此，本实施例中将金属氧化物半导体层的厚度控制在0.5nm至3nm之间，可降低金属氧化物半导体层的缺陷率，提高金属氧化物半导体层的质量，从而提高其性能，进而提高晶体管长期使用的可靠性。
在一些实施例中，如图4所示，沟道层300包括依次层叠的第一子沟道层310和第二子沟道层320，第二子沟道层320位于第一子沟道层310和栅极介质层220之间，第一子沟道层310包括硅半导体层或硅锗半导体层，即第一子沟道层310的材质包括硅半导体或硅锗半导体，第二子沟道层320包括金属氧化物半导体层，即第二子沟道层320的材质包括金属氧化物半导体。
示例地，第一子沟道层310可以是位于第一有源层111和第二有源层112之间的衬底100，衬底100的材料包括硅半导体或硅锗半导体。还示例地，第一子沟道层310也可以是向位于第一有源层111和第二有源层112之间的衬底100中注入掺杂离子形成的掺杂硅半导体层或掺杂硅锗半导体层。这种直接在衬底100中形成第一子沟道层310的方式能够缩短制备周期。
在一些实施例中，当第一有源层111和第二有源层112为P型掺杂时，第一子沟道层310为N型掺杂。当第一有源层111和第二有源层112为N型掺杂时，第一子沟道层310为P型掺杂。
在另外一些实施例中，第一子沟道层310和第二子沟道层320的位置也可以是：第一子沟道层310位于第二子沟道层320和栅极介质层220之间。这种情况下，第一子沟道层310可通过在第二子沟道层320的侧壁和底部沉积硅半导体或硅锗半导体形成。硅半导体可以是多晶硅或非晶硅，多晶硅包括掺杂多晶硅。
总言之，在本实施例中，当晶体管的沟道层300包括金属氧化物半导体层和硅半导体层(或硅锗半导体层时)，两个子沟道层能进一步增大沟道层300内载流子的迁移率、并增大沟道层300的饱和电流，且能降低沟道层漏电的可能性，从而使晶体管具有更快的开关速度。
在一些实施例中，如图6所示，沟道层300可包括多个子沟道层组，每个子沟道层组包括第一子沟道层310和第二子沟道层320，第一子沟道层310的材质包括硅半导体或硅锗半导体，第二子沟道层320的材质包括金属氧化物半导体。
本实施例中，如图6所示，第二子沟道层320可层叠于第一子沟道层310上。在另一些实施例中，也可以是第一子沟道层310位于第二子沟道层320上。
本实施例中，可通过形成交替的金属氧化物半导体层和硅半导体层(或者硅锗半导体层)，可形成多层金属氧化物半导体层，增加金属氧化物半导体的总厚度，从而进一步提高晶体管的性能。
此外，还可通过设计沟道层300、栅极介质层220和栅极210的位置、成分或形状，获得不同性能的晶体管。图7至图13为本公开实施例提供的多种晶体管的截面示意图，下面结合图4、以及图7至图13详述本公开实施例提供的多种晶体管的结构和性能。
在一些实施例中，如图4所示，金属氧化物半导体层(第二子沟道层320)可覆盖第一有源层111和第二有源层112相对靠近栅极结构200的侧壁，金属氧化物半导体层的顶部、第一有源层111的顶部和第二有源层112的顶部平齐。如此，可增加沟道的长度，提高载流子的迁移率。
在一些实施例中，栅极介质层220可覆盖金属氧化物半导体层的侧壁和底面，栅极介质层220和金属氧化物半导体层的顶部平齐。
在一些实施例中，栅极210可包括第一部分211和第二部分212，第一部分211位于第二部分212相对靠近衬底100表面的一侧，第一部分211具有沿指定方向的第一尺寸，第二部分212具有沿该指定方向的第二尺寸，第一尺寸小于第二尺寸。指定方向平行于衬底100表面，且与栅极210的延伸方向相垂直。 图4中的X方向为该指定方向。
栅极210的第一部分211的表面可为弧面，使得栅极210的截面顶部为Ω型，栅极210的截面垂直于衬底100表面，且与栅极210的延伸方向相垂直。
本实施例中，设置栅极的第一部分211的第一尺寸小于第二部分212的第二尺寸，能降低晶体管的栅致漏极泄露(Gate-induced drain leakage，简称GIDL)电流，也即降低晶体管的截止电流，从而增大存储器相邻两次刷新之间的时间间隔，提高存储器的性能。
在一些实施例中，栅极210的顶部可低于衬底100的表面，晶体管还包括保护层400，填充于栅极210相对靠近衬底100表面的一侧。保护层400的顶部与栅极介质层220的顶部平齐。
保护层400的材料可包括氮化硅或氧化硅。
在一些实施例中，如图7所示，第一有源层111和第二有源层112位于沟道层300的顶部；
栅极介质层220，覆盖第一有源层111和第二有源层112的侧壁、以及沟道层300的顶部未被第一有源层111和第二有源层112覆盖的部分。
具体地，沟道层300包括第一子沟道层310(硅半导体层或者硅锗半导体层)和第二子沟道层320(金属氧化物半导体层)，第一子沟道层310和第二子沟道层320的顶部平齐，第一有源层111和第二有源层112位于第一子沟道层310的顶部，栅极介质层220覆盖第一有源层111和第二有源层112侧壁、以及第二子沟道层320的顶部、侧壁和底部。
本实施例中提供的沟道层300能降低栅致漏极泄露电流，从而提高存储器的性能。
在一些实施例中，栅极210的第一部分211的第一尺寸可大于第二部分212的第二尺寸，使得栅极210的截面为T型，这样可以增大栅极210导电层的横截面，降低栅极210电阻，从而提高晶体管的开关速度，提高存储器的读写效率。
在一些实施例中，晶体管的结构还可如图8和图9所示，该晶体管的沟道层300和栅极介质层220的结构同图7所示的晶体管。
此外，该晶体管的栅极210包括第一子栅极213和第二子栅极214，第二子栅极214位于第一子栅极213相对靠近衬底100表面的一侧，第一子栅极213的材质包括金属，第二子栅极214的材质包括多晶硅。
在一些实施例中，第二子栅极214的材质也可以是掺杂多晶硅。
在一些实施例中，第一子栅极213的结构可以是截面为T型(如图8所示)，还可以是截面顶部为Ω型(如图9所示)。
示例地，第二子栅极214沿指定方向(X方向)具有第三尺寸，第三尺寸等于或大于第一子栅极213的第一尺寸和第二尺寸。具体地，图8中，第二子栅极214的第三尺寸等于第一子栅极213的第一部分211的第一尺寸，大于第二部分212的第二尺寸。图9中，第二子栅极214的第三尺寸大于第一子栅极213中第一部分211的第一尺寸和第二部分212的第二尺寸。
本实施例中，使用第一子栅极213和第二子栅极214构成的复合栅结构， 能够降低栅致漏极泄露电流，从而提高存储器的性能。
在一些实施例中，晶体管的结构可如图10至图13所示，第二子沟道层320(金属氧化物半导体层)覆盖第一有源层111和第二有源层112相对靠近栅极结构200的侧壁，第二子沟道层320的顶部和第一有源层111和第二有源层112的顶部平齐。栅极介质层220覆盖第二子沟道层320的底面和部分侧壁，栅极介质层220的顶部低于第二子沟道层320的顶部。
本实施例提供的第二子沟道层320和栅极介质层220的结构，能够降低栅致漏极泄露电流，从而提高存储器的性能。
在一些实施例中，栅极210的结构可以是图10所示的，栅极210的截面顶部形状为Ω型，从而进一步降低栅致漏极泄露电流。
栅极210的结构还可以是图11所示的，栅极210的截面形状为T型，从而增大栅极导电层的横截面，降低栅极电阻，提高晶体管的开关速度。
栅极210的结构还可以是图12所示的，栅极210包括第一子栅极213和第二子栅极214，第一子栅极213的截面顶部形状为Ω型。
栅极210的结构还可以是图13所示的，栅极210包括第一子栅极213和第二子栅极214，第一子栅极213的截面形状为T型。图12和图13中，第一子栅极213和第二子栅极214形成的复合栅结构，能够进一步降低栅致漏极泄露电流。
综上所述，本公开实施例中，可通过调控沟道层、栅极介质层和栅极的位置、成分和形状等，获得不同性能的晶体管，从而获得不同性能的存储器。示例地，可获得开关速度更快的晶体管，从而获得读写速率更高的存储器，或者可获得截止电流更小的晶体管，从而获得刷新时间间隔更长的存储器。
本公开实施例还提供了一种晶体管的制备方法，图14为本公开实施例提供的晶体管的制备方法的流程示意图，如图14所示，该制备方法包括以下步骤：
S100：提供衬底100；其中，衬底100包括有源区110，衬底100中形成有穿过有源区110的沟槽；
S200：在有源区110形成第一有源层111和第二有源层112；其中，第一有源层111和第二有源层112分设于沟槽的两侧；
S300：在位于有源区110的沟槽的底部和侧壁形成沟道层300；其中，沟道层300包括金属氧化物半导体层；沟道层300与第一有源层111和第二有源层112相接触；
S400：在沟槽内依次形成栅极介质层220和栅极210；其中，栅极介质层220覆盖沟道层300。
应当理解，步骤S100至S400所示的操作不一定按照顺序精确的执行，相反，可以按照任意顺序或者同时处理各种步骤。此外，也可将其他操作步骤添加到这些过程中。
图15a至图15e为本公开实施例提供的晶体管阵列在制备过程中的结构示意图，下面结合图3、图15a至图15e介绍本公开实施例提供的晶体管的制备方法。需要说明的是，图15a至图15e为晶体管阵列沿A-A线的剖视图。
参见图3和图15a，执行步骤S100，提供衬底100，衬底100包括有源区 110，衬底100中形成有穿过有源区110的沟槽500。
在一些实施例中，衬底100的材料可包括硅(Si)、锗(Ge)、绝缘体上硅(SOI)、绝缘体上锗(GOI)，或者硅锗半导体等。
衬底100包括呈阵列排布的多个有源区110，以及位于相邻有源区110之间的浅槽隔离结构120。沟槽500穿过多个并列排布的有源区110，以及还穿过相邻有源区110之间的浅槽隔离结构120。因此，可以理解的是，在图15a中，浅槽隔离结构120中也形成有沟槽500，在后续步骤中，该沟槽500内虽然形成了栅极210和栅极介质层220，但是在栅极介质层220两侧并未形成第一有源层111和第二有源层112，因此，浅槽隔离结构120中没有形成晶体管。
在一些实施例中，一个有源区110可允许并列排布的两个沟槽500穿过，以在一个有源区110形成两个晶体管。
在一些实施例中，浅槽隔离结构120的材质可包括氧化硅。
在一些实施例中，沟槽500位于衬底100中的部分和沟槽500位于浅槽隔离结构120中的部分的深度不同，是由于衬底100和浅槽隔离结构120的材质不同，在相同的刻蚀条件下，二者的刻蚀速率不同，因此，沟槽500位于衬底100中的部分，与沟槽位于浅槽隔离结构120中的部分的深度不同。沟槽500位于衬底100中的部分的深度可小于，也可大于沟槽500位于浅槽隔离结构120中的部分，这取决于衬底100和浅槽隔离结构120的材质和刻蚀条件。
在一些实施例中，如图15a所示，衬底100上还依次层叠有绝缘层121和掩膜层600。在一些实施例中，绝缘层121的材质可与浅槽隔离结构120的材质相同，例如为氧化硅。绝缘层121可与浅槽隔离结构120在同一步骤中形成。掩膜层600的材质可包括氮化硅。
本实施例中，多个沟槽500还贯穿掩膜层600和绝缘层121，延伸到衬底100内或者延伸到浅槽隔离结构120中。
参见图15b，执行步骤S200，向有源区110的第一区域和第三区域注入第一掺杂离子，形成第一个晶体管的第一有源层111和第二个晶体管的第一有源层111。向有源区110的第二区域注入第二掺杂离子，形成第一个晶体管的第二有源层112和第二个晶体管的第二有源层112。
在一些实施例中，第一掺杂离子可包括P型掺杂离子(例如硼、铝或镓)，或者N型掺杂离子(例如磷、砷或锑)，第二掺杂离子也可包括P型掺杂离子(例如硼、铝或镓)，或者N型掺杂离子(例如磷、砷或锑)。第一掺杂离子和第二掺杂离子可同为P型掺杂离子，或N型掺杂离子。第一掺杂离子的元素类型和第二掺杂离子的元素类型可相同。
参见图15b，执行步骤S300和步骤S400，在位于有源区110的沟槽500的底部和侧壁形成沟道层300，在沟槽500内依次形成栅极介质层220和栅极210。
在一些实施例中，沟道层300可包括依次层叠的第一子沟道层310和第二子沟道层320，第一子层道层310的材质为掺杂硅半导体或掺杂硅锗半导体，第二子沟道层320的材质为金属氧化物半导体。
首先，向位于第一有源层111和第二有源层112之间的衬底100内注入第三掺杂离子，形成第一子沟道层310。
第三掺杂离子可包括P型掺杂离子(例如硼、铝或镓)，或者N型掺杂离子(例如磷、砷或锑)。可以理解的是，当第一有源层111和第二有源层112为N型掺杂时，第一子沟道层310可为P型掺杂。当第一有源层111和第二有源层112为P型掺杂时，第一子沟道层310可以为N型掺杂。
需要说明的是，在晶体管的制备过程中，可以先执行步骤S200，通过向有源区110注入第一掺杂离子和第二掺杂离子，形成第一有源层111和第二有源层112，再执行步骤S300，向有源区110注入第三掺杂离子，形成第一子沟道层310；也可以先执行步骤S300，掺杂形成第一子沟道层310之后，再掺杂形成第一有源层111和第二有源层112。对此本公开不做限制。
此外，步骤S400可以在步骤S200和S300之前执行，也可以S200和S300之后执行，也可在S200和S300之间执行，对此，本公开不做限制。在一些实施例中，先执行步骤S200和步骤S300，再执行步骤S400，也即在形成第一有源层111、第二有源层112和第一子沟道层310之后，再形成栅极210，这样能够避免离子注入对栅极210的影响。
接着，参见图15b，形成覆盖沟槽500的侧壁和底部的第二子沟道层320，第二子沟道层320包括金属氧化物半导体层。
在一些实施例中，金属氧化物半导体层可包括氧化铟镓锌、氧化铟锡、氧化铟钨、氧化铟锌、氧化镓、氧化铟中的至少一种。金属氧化物半导体层的厚度可为0.5nm至3nm。
在一些实施例中，由于第一子沟道层310位于靠近沟槽500的衬底100内，因此，第二子沟道层320也覆盖第一子沟道层310的底部和侧壁。
需要说明的是，在一些实施例中，也可只设置第二子沟道层320，而不设置第一子沟道层310。
此外，还需要说明的是，本实施例中，第二子沟道层320位于有源区110的沟槽500内，也位于浅槽隔离结构120的沟槽500内，也即第二子沟道层320位于整个沟槽500的侧壁和底部，这样设置第二子沟道层320的工艺较为简单。
在一些实施例中，可以仅在位于有源区110的沟槽500内形成第二子沟道层320，而浅槽隔离结构120中的沟槽500内不设置第二子沟道层320。具体地，可以将位于浅槽隔离结构120中的第二子沟道材料层刻蚀掉，仅保留位于有源区110的沟槽500侧壁和底部的第二子沟道材料层，形成第二子沟道层320。如此，能减少相邻晶体管之间的干扰。
在一些实施例中，形成覆盖沟槽500的侧壁和底部的第二子沟道层320的步骤，包括：形成覆盖沟槽500的侧壁和底部，以及覆盖掩膜层600表面的第二子沟道材料层；采用化学机械研磨(CMP)去除位于掩膜层600表面的第二子沟道材料层，只保留位于沟槽500的侧壁和底部的第二子沟道材料层，形成第二子沟道层320。
继续参见图15b，形成覆盖第二子沟道层320的侧壁和底部的栅极介质层220；最后，形成覆盖栅极介质层220的侧壁和底部，以及覆盖掩膜层600表面的栅极材料层，该栅极材料层填充满沟槽500内剩余的空隙。
在一些实施例中，形成覆盖第二子沟道层320的侧壁和底部的栅极介质层 220的步骤，包括：形成覆盖第二子沟道层320的侧壁和底部，以及覆盖掩膜层600表面的栅极介质材料层；采用化学机械研磨去除位于掩膜层600表面的栅极介质材料层，只保留覆盖第二子沟道层320的侧壁和底部的栅极介质材料层，形成栅极介质层220。
在一些实施例中，栅极材料层包括第三子栅极材料层和第四子栅极材料层；形成栅极材料层的步骤包括：形成覆盖栅极介质层220侧壁和底部的第三子栅极材料层，形成覆盖第三子栅极材料层的侧壁和底部，以及覆盖掩膜层600表面的第四子栅极材料层；其中，第四子栅极材料层填充满沟槽500内剩余的空隙。
在一些实施例中，第三子栅极材料层的材质包括金属氮化物，例如氮化钛、氮化钽、氮化钨等。第四子栅极材料层的材质包括金属，例如钽、钛、钼、钨、铂、铝、铪、钌、钴等。
参见图15c，去除位于掩膜层600表面的第四子栅极材料层。在一些实施例中，可采用化学机械研磨工艺去除位于掩膜层600表面的第四子栅极材料层，仅保留沟槽500内的第四子栅极材料层。
参见图15d，刻蚀去除部分位于栅极介质层220侧壁的第三子栅极材料层，剩余的第三子栅极材料层形成第三子栅极215。
刻蚀去除部分第四子栅极材料层，剩余的第四子栅极材料层形成第四子栅极216，其中，第四子栅极216顶部可高于或平齐于第三子栅极215顶部。第三子栅极215和第四子栅极216构成本实施例中的栅极210。
在一些实施例中，可以先刻蚀第三子栅极材料层，后刻蚀第四子栅极材料层；也可以先刻蚀第四子栅极材料层，后刻蚀第三子栅极材料层。对此，本公开不做限制。
参见图15e，去除掩膜层600，以及位于掩膜层内的第二子沟道层320和栅极介质层220；形成填充沟槽500内剩余的空隙，以及覆盖绝缘层121表面的保护层400。
在一些实施例中，保护层400的材质可包括氧化硅或氮化硅。
此外，在一些实施例中，为获得如图7所示的晶体管，该制备方法包括：
在形成位于沟槽500的侧壁和底部的第二子沟道材料层之后，刻蚀去除部分位于沟槽500的侧壁的第二子沟道材料层，剩余的第二子沟道材料层形成第二子沟道层320，其中，第二子沟道层320的顶部与第一子沟道层310的顶部平齐，且均低于衬底100表面；
在形成栅极介质层220时，该栅极介质层220覆盖沟槽500未被第二子沟道层320覆盖的表面，以及覆盖第二子沟道层320的顶部、侧壁和底部。
本实施例中，沟槽500未被第二子沟道层320覆盖的表面包括第一有源层111和第二有源层112的侧壁。
在一些实施例中，为形成图8所示的晶体管的栅极210，步骤S400还包括：
在栅极介质层220相对远离沟道层300一侧形成第一子栅极213；其中，第一子栅极213的材质包括金属；
在第一子栅极213的顶部形成第二子栅极214；其中，第二子栅极214的材 质包括多晶硅。
具体地，在形成栅极介质层220之后，形成填充沟槽500内剩余的空隙的第一子栅极材料层；刻蚀去除部分第一子栅极材料层，剩余的第一子栅极材料形成第一子栅极213；在沟槽500内第一子栅极213顶部形成第二子栅极材料，去除部分第二子栅极材料，剩余的第二子栅极材料形成第二子栅极214.
在一些实施中，为形成如图10所示的晶体管，该制备方法还包括：
在形成位于第二子沟道层320的栅极介质材料层后，去除部分位于第二子沟道层320侧壁的栅极介质材料层，剩余的栅极介质材料层形成栅极介质层220。
之后，在沟槽500内继续形成栅极和保护层400。
本公开实施例还提供了一种存储器，该存储器包括存储单元，存储单元配置为存储数据，该存储单元包括上述任一种晶体管。
在一些实施例中，存储单元还包括电容器，电容器与存储单元中的晶体管的第一有源层111或第二有源层112耦合。
在一些实施例中，该晶体管还可应用至存储器的外围电路中，该晶体管可耦合至存储单元，配置为控制存储单元的操作。
图16为本公开实施例提供的应用至存储单元的晶体管的结构示意图，如图16所示，该晶体管还可包括：
位于阱区330相对远离第二子沟道层320一侧的深阱区130；
依次层叠于第一有源层111上的第一接触结构710、黏附层720、第一阻挡层730和第一接触焊盘740；
依次层叠于第二有源层112上的第二接触结构810、第二阻挡层830和第二接触焊盘840；以及，
位于保护层400上的隔离结构，该隔离结构包括沿指定方向(X方向)依次层叠的第一子隔离结构851、第二子隔离结构852和第三子隔离结构853。
在一些实施例中，阱区330相对靠近栅极210的区域可作为第一子沟道层。
深阱区130用于将晶体管与其他结构隔离，深阱区130的掺杂离子可包括P型掺杂离子(例如硼、铝或镓)，或者N型掺杂离子(例如磷、砷或锑)，当阱区330为P型掺杂时，深阱区130为N型掺杂，或者阱区330为N型掺杂时，深阱区130为P型掺杂。
衬底100可包括N型半导体。
第一接触结构710和第二接触结构810的材质可包括多晶硅。
黏附层720的材质可包括金属硅化物，例如硅化钛、硅化钴、硅化镍、硅化钽等，黏附层720用于降低接触电阻。
第一阻挡层730和第二阻挡层830的材质可包括金属氮化物，例如氮化钛、氮化钽、氮化钨等，第一阻挡层730和第二阻挡层830用于防止金属扩散。第一阻挡层730和第二阻挡层830的元素类型可相同。
第一子隔离结构851、第二子隔离结构852和第三子隔离结构853的材质可包括氧化硅或氮化硅。其中，第一子隔离结构851和第三子隔离结构853的材质可以相同。
第一接触焊盘740和第二接触焊盘840的材质可包括金属，例如钽、钛、 钼、钨、铂、铝、铪、钌、钴等。第一接触焊盘740和第二接触焊盘840的元素类型可相同。
在一些实施例中，第一接触焊盘740用于连接电容器，第二接触焊盘840用于连接位线。本实施例提供的晶体管阵列，与电容器和位线共同构成存储器的存储单元阵列，其中，存储器为DRAM。
上述实施例仅例示性说明本公开的原理及其功效，而非用于限制本公开。任何熟悉此技术的人士皆可在不违背本公开的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本公开所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本公开的权利要求所涵盖。

Claims (17)

  1. 一种晶体管，包括：
    衬底，所述衬底包括有源区；
    栅极结构，所述栅极结构穿过所述有源区；所述栅极结构包括栅极和栅极介质层，所述栅极介质层覆盖所述栅极的侧壁和底部；
    沟道层，位于所述栅极介质层相对远离所述栅极的一侧，所述沟道层包括金属氧化物半导体层；
    所述有源区包括分设于所述栅极结构两侧的第一有源层和第二有源层，所述第一有源层和所述第二有源层均与所述沟道层相接触。
  2. 根据权利要求1所述的晶体管，其中，所述金属氧化物半导体层的材质包括氧化铟镓锌、氧化铟锡、氧化铟钨、氧化铟锌、氧化镓、氧化铟中的至少一种。
  3. 根据权利要求1所述的晶体管，其中，所述金属氧化物半导体层的厚度为0.5nm至3nm。
  4. 根据权利要求1所述的晶体管，其中，所述沟道层包括至少一个子沟道层组，所述子沟道层组包括依次层叠的两个子沟道层，所述两个子沟道层其中之一子沟道层包括所述金属氧化物半导体层，另一子沟道层包括硅锗半导体层或硅半导体层。
  5. 根据权利要求1所述的晶体管，其中，所述金属氧化物半导体层覆盖所述第一有源层和所述第二有源层相对靠近所述栅极结构的侧壁。
  6. 根据权利要求1所述的晶体管，其中，所述第一有源层和所述第二有源层位于所述沟道层的顶部；
    所述栅极介质层，覆盖所述第一有源层和所述第二有源层的侧壁、以及所述沟道层的顶部未被所述第一有源层和所述第二有源层覆盖的部分。
  7. 根据权利要求1所述的晶体管，其中，所述栅极包括第一部分和第二部分，所述第一部分位于所述第二部分相对靠近所述衬底表面的一侧，所述第一部分具有沿指定方向的第一尺寸，所述第二部分具有沿所述指定方向的第二尺寸，所述第一尺寸大于所述第二尺寸，所述指定方向平行于所述衬底表面，且与所述栅极的延伸方向相垂直。
  8. 根据权利要求1所述的晶体管，其中，所述栅极包括第一子栅极和第二子栅极，所述第二子栅极位于所述第一子栅极相对靠近所述衬底表面的一侧，所述第一子栅极的材质包括金属，所述第二子栅极的材质包括多晶硅。
  9. 一种存储器，包括：存储单元，所述存储单元配置为存储数据；所述存储单元包括如权利要求1至8任一项所述的晶体管。
  10. 根据权利要求9所述的存储器，其中，所述存储单元还包括：
    电容器，所述电容器与所述存储单元中的所述晶体管的第一有源层或第二有源层耦合。
  11. 一种晶体管的制备方法，包括：
    提供衬底；其中，所述衬底包括有源区，所述衬底中形成有穿过所述有源 区的沟槽；
    在所述有源区形成第一有源层和第二有源层；其中，所述第一有源层和所述第二有源层分设于所述沟槽的两侧；
    在位于所述有源区的所述沟槽的底部和侧壁形成沟道层；其中，所述沟道层包括金属氧化物半导体层；所述沟道层与所述第一有源层和所述第二有源层相接触；
    在所述沟槽内依次形成栅极介质层和栅极；其中，所述栅极介质层覆盖所述沟道层。
  12. 根据权利要求11所述的晶体管的制备方法，其中，所述金属氧化物半导体层的材质包括氧化铟镓锌、氧化铟锡、氧化铟钨、氧化铟锌、氧化镓、氧化铟中的至少一种。
  13. 根据权利要求11所述的晶体管的制备方法，其中，所述金属氧化物半导体层的厚度为0.5nm至3nm。
  14. 根据权利要求11所述的晶体管的制备方法，其中，所述沟道层包括依次层叠的第一子沟道层和第二子沟道层；所述在位于所述有源区的所述沟槽的底部和侧壁形成沟道层的步骤，包括：
    向位于所述有源区的所述沟槽的底部和侧壁注入掺杂离子，形成第一子沟道层；
    形成覆盖所述第一子沟道层的底部和侧壁的第二子沟道层；其中，所述第二子沟道层包括金属氧化物半导体层。
  15. 根据权利要求14所述的晶体管的制备方法，其中，所述第一有源层和所述第二有源层位于所述第一子沟道层的顶部，所述第二子沟道层还覆盖所述第一有源层和所述第二有源层相对靠近所述栅极的侧壁；所述形成覆盖所述第一子沟道层的底部和侧壁的第二子沟道层的步骤，包括：
    形成覆盖所述沟槽的底部和侧壁的第二子沟道层；其中，所述第二子沟道层的顶部、所述第一有源层的顶部和所述第二有源层的顶部平齐。
  16. 根据权利要求14所述的晶体管的制备方法，其中，所述第一有源层和所述第二有源层位于所述第一子沟道层的顶部，所述第二子沟道层的顶部和所述第一子沟道层的顶部平齐；
    所述在所述沟槽内形成栅极介质层的步骤，包括：
    在所述沟槽内形成栅极介质层；其中，所述栅极介质层还覆盖所述第二子沟道层的顶部，以及所述第一有源层和所述第二有源层的侧壁。
  17. 根据权利要求11所述的晶体管的制备方法，其中，所述栅极包括第一子栅极和第二子栅极，所述第二子栅极位于所述第一子栅极相对靠近所述衬底表面的一侧；
    所述在所述沟槽内形成栅极的步骤，包括：
    在所述栅极介质层相对远离所述沟道层一侧形成所述第一子栅极；其中，所述第一子栅极的材质包括金属；
    在所述第一子栅极的顶部形成所述第二子栅极；其中，所述第二子栅极的材质包括多晶硅。
PCT/CN2022/106460 2022-05-26 2022-07-19 晶体管及其制备方法、以及存储器 WO2023226179A1 (zh)

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