WO2023167147A1 - 炭化珪素半導体装置 - Google Patents

炭化珪素半導体装置 Download PDF

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Publication number
WO2023167147A1
WO2023167147A1 PCT/JP2023/007114 JP2023007114W WO2023167147A1 WO 2023167147 A1 WO2023167147 A1 WO 2023167147A1 JP 2023007114 W JP2023007114 W JP 2023007114W WO 2023167147 A1 WO2023167147 A1 WO 2023167147A1
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Prior art keywords
region
silicon carbide
contact
dimension
main surface
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English (en)
French (fr)
Japanese (ja)
Inventor
雄 斎藤
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Sumitomo Electric Industries Ltd
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Sumitomo Electric Industries Ltd
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Priority to CN202380019970.3A priority Critical patent/CN118648120A/zh
Priority to JP2024504679A priority patent/JPWO2023167147A1/ja
Priority to DE112023001206.7T priority patent/DE112023001206T5/de
Priority to US18/728,625 priority patent/US20250089292A1/en
Publication of WO2023167147A1 publication Critical patent/WO2023167147A1/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H10D62/107—Buried supplementary regions, e.g. buried guard rings 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H10D62/156—Drain regions of DMOS transistors
    • H10D62/157—Impurity concentrations or distributions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
    • H10D12/038—Manufacture or treatment of IGBTs of vertical IGBTs having a recessed gate, e.g. trench-gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/518—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their lengths or sectional shapes

Definitions

  • the present disclosure relates to silicon carbide semiconductor devices.
  • Patent Document 1 a trench-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) in which an electric field shield region is provided below a gate trench formed on a main surface is disclosed (for example, Patent Document 1, 2).
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • a silicon carbide semiconductor device of the present disclosure includes a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, a source electrode, a gate insulating film, and the silicon carbide substrate. a gate electrode provided on the gate insulating film so as to sandwich the gate insulating film therebetween; and an interlayer insulating film covering the gate electrode, and the silicon carbide substrate has a first conductivity type. a drift region; a body region provided on the drift region and having a second conductivity type different from the first conductivity type; and a contact region provided on the body region and having the second conductivity type, the first main surface having the drift through the source region and the body region.
  • a gate trench defined by a side surface reaching the region and a bottom surface continuous with the side surface and extending in a first direction parallel to the first main surface is provided, and the source electrode extends in the source region and the contact region.
  • the gate insulating film is in contact with the side surface and the bottom surface, and the silicon carbide substrate is provided between the bottom surface and the second main surface, extends in the first direction, and is of the second conductivity type.
  • connection region electrically connecting the contact region and the electric field relaxation region and having the second conductivity type, the electric field relaxation region extending in the first direction a first region having a first dimension in a perpendicular second direction; a second region connected to the first region in the first direction and having a second dimension in the second direction smaller than the first dimension; a contact hole extending in the first direction and partially exposing the source region is formed in the interlayer insulating film, and the contact region is exposed from the contact hole and connected to the source electrode.
  • the gate trench and the electric field relaxation region overlap with an imaginary straight line extending in the first direction, and the connection region includes: The first region and the third region are aligned in the second direction, contacting the electric field relaxation region on the imaginary straight line.
  • FIG. 1 is a perspective cross-sectional view (Part 1) showing the configuration of the silicon carbide semiconductor device according to the embodiment.
  • FIG. 2 is a perspective cross-sectional view (part 2) showing the configuration of the silicon carbide semiconductor device according to the embodiment.
  • FIG. 3 is a diagram showing configurations of an interlayer insulating film and a first main surface in the silicon carbide semiconductor device according to the embodiment.
  • FIG. 4 is a diagram showing the configuration of an electric field relaxation region.
  • FIG. 5 is a cross-sectional view (Part 1) showing the configuration of the silicon carbide semiconductor device according to the embodiment.
  • FIG. 6 is a cross-sectional view (Part 2) showing the configuration of the silicon carbide semiconductor device according to the embodiment.
  • FIG. 7 is a cross-sectional view (Part 3) showing the configuration of the silicon carbide semiconductor device according to the embodiment.
  • FIG. 8 is a cross-sectional view (part 4) showing the configuration of the silicon carbide semiconductor device according to the embodiment.
  • FIG. 9 is a cross-sectional view (No. 5) showing the configuration of the silicon carbide semiconductor device according to the embodiment.
  • FIG. 10 is a cross-sectional view (Part 1) showing the method for manufacturing the silicon carbide semiconductor device according to the embodiment.
  • FIG. 11 is a cross-sectional view (Part 2) showing the method for manufacturing the silicon carbide semiconductor device according to the embodiment.
  • FIG. 12 is a cross-sectional view (Part 3) showing the method for manufacturing the silicon carbide semiconductor device according to the embodiment.
  • FIG. 13 is a cross-sectional view (Part 4) showing the method for manufacturing the silicon carbide semiconductor device according to the embodiment.
  • FIG. 14 is a cross-sectional view (No. 5) showing the method for manufacturing the silicon carbide semiconductor device according to the embodiment.
  • FIG. 15 is a cross-sectional view (No. 6) showing the method for manufacturing the silicon carbide semiconductor device according to the embodiment.
  • FIG. 16 is a cross-sectional view (No. 7) showing the method for manufacturing the silicon carbide semiconductor device according to the embodiment.
  • FIG. 17 is a cross-sectional view (No. 8) showing the method for manufacturing the silicon carbide semiconductor device according to the embodiment.
  • FIG. 18 is a cross-sectional view (part 9) showing the method for manufacturing the silicon carbide semiconductor device according to the embodiment.
  • FIG. 19 is a cross-sectional view (No. 10) showing the method for manufacturing the silicon carbide semiconductor device according to the embodiment.
  • FIG. 20 is a cross-sectional view (No. 11) showing the method for manufacturing the silicon carbide semiconductor device according to the embodiment.
  • FIG. 21 is a cross-sectional view (No. 12) showing the method for manufacturing the silicon carbide semiconductor device according to the embodiment.
  • FIG. 22 is a cross-sectional view (part 13) showing the method for manufacturing the silicon carbide semiconductor device according to the embodiment.
  • FIG. 23 is a cross-sectional view (part 14) showing the method for manufacturing the silicon carbide semiconductor device according to the embodiment.
  • FIG. 24 is a cross-sectional view (No. 15) showing the method for manufacturing the silicon carbide semiconductor device according to the embodiment.
  • FIG. 25 is a cross-sectional view (No. 16) showing the method for manufacturing the silicon carbide semiconductor device according to the embodiment.
  • FIG. 26 is a cross-sectional view (No. 17) showing the method for manufacturing the silicon carbide semiconductor device according to the embodiment.
  • FIG. 27 is a cross-sectional view (No. 18) showing the method for manufacturing the silicon carbide semiconductor device according to the embodiment.
  • FIG. 28 is a cross-sectional view (No. 19) showing the method for manufacturing the silicon carbide semiconductor device according to the embodiment.
  • FIG. 29 is a cross-sectional view (No. 20) showing the method for manufacturing the silicon carbide semiconductor device according to the embodiment.
  • FIG. 30 is a cross-sectional view showing the configuration of a silicon carbide semiconductor device according to the first modification of the embodiment.
  • FIG. 31 is a diagram showing configurations of an interlayer insulating film and a first main surface in a silicon carbide semiconductor device according to a second modification of the embodiment.
  • FIG. 32 is a cross-sectional view showing the configuration of a silicon carbide semiconductor device according to a second modification of the embodiment.
  • FIG. 33 is a diagram showing configurations of an interlayer insulating film and a first main surface in a silicon carbide semiconductor device according to a third modification of the embodiment.
  • FIG. 34 is a cross-sectional view showing the configuration of a silicon carbide semiconductor device according to a third modification of the embodiment.
  • FIG. 35 is a diagram showing configurations of an interlayer insulating film and a first main surface in a silicon carbide semiconductor device according to a fourth modification of the embodiment.
  • FIG. 36 is a cross-sectional view showing the configuration of a silicon carbide semiconductor device according to a fourth modification of the embodiment.
  • An object of the present disclosure is to provide a silicon carbide semiconductor device capable of suppressing drain leakage.
  • a plane including the X1-X2 direction and the Y1-Y2 direction is referred to as the XY plane
  • a plane including the Y1-Y2 direction and the Z1-Z2 direction is referred to as the YZ plane
  • a plane including the Z1-Z2 direction and the X1-X2 direction. is described as the ZX plane.
  • the Z1-Z2 direction is the vertical direction
  • the Z1 side is the upper side
  • the Z2 side is the lower side.
  • the term "planar view” refers to viewing the object from the Z1 side
  • the term "planar shape” refers to the shape of the object viewed from the Z1 side.
  • a silicon carbide semiconductor device includes a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, a source electrode, and a gate insulating film a gate electrode provided on the gate insulating film so as to sandwich the gate insulating film between itself and the silicon carbide substrate; and an interlayer insulating film covering the gate electrode, wherein the silicon carbide substrate comprises a drift region having a first conductivity type; a body region provided on the drift region and having a second conductivity type different from the first conductivity type; and a body region provided on the body region so as to be separated from the drift region.
  • a gate trench defined by a side surface penetrating the region to reach the drift region and a bottom surface continuous with the side surface and extending in a first direction parallel to the first main surface is provided.
  • the silicon carbide substrate is connected to the source region and the contact region, the gate insulating film is in contact with the side surface and the bottom surface, the silicon carbide substrate is provided between the bottom surface and the second main surface, and extends in the first direction.
  • an electric field relaxation region that extends and has the second conductivity type; and a connection region that electrically connects the contact region and the electric field relaxation region and has the second conductivity type, the electric field relaxation region.
  • the connection region is in contact with the electric field relaxation region on the imaginary straight line, and the first region and the third region are aligned in the second direction.
  • the contact region and the electric field relaxation region are electrically connected by the connection region.
  • a contact region is electrically connected to the source electrode. Therefore, the electric field relaxation region is electrically connected to the source electrode.
  • the feedback capacitance can be reduced, carriers can be efficiently supplied from the source electrode to the electric field relaxation region, and the depletion layer extending from the electric field relaxation region toward the drift region during switching operation can be accelerated, thereby reducing switching loss.
  • the gate trench and the electric field relaxation region overlap with the imaginary straight line, and the connection region is in contact with the electric field relaxation region on the imaginary straight line. Therefore, the connection region is less likely to block the current flowing along the portion of the side surface of the gate trench parallel to the first direction. Therefore, a sufficient current can be secured when the device is turned on.
  • the second dimension of the second region is smaller than the first dimension of the first region, and the first region and the third region are aligned in the second direction when viewed from above in a direction perpendicular to the first main surface. . Therefore, the electric field concentration at the position near the second main surface of the contact region at the time of OFF can be alleviated in the vicinity of the first region while securing the region in the vicinity of the second region in which the drain current flows at the time of ON. Therefore, drain leakage caused by electric field concentration can be suppressed.
  • a portion of the first region and a portion of the third region may overlap when viewed in plan from a direction perpendicular to the first main surface.
  • electric field concentration at a position near the second main surface of the contact region is easily alleviated, and drain leakage is easily suppressed.
  • the third region when viewed in plan from a direction perpendicular to the first main surface, the third region has a first side extending in the first direction, and the entire first side is the It may overlap with a part of the first region.
  • the electric field concentration at the position near the second main surface of the contact region can be more easily alleviated, and the drain leakage can be more easily suppressed.
  • a plurality of the gate trenches are provided so as to overlap the imaginary straight line at regular intervals, and the connection region is planarly viewed from a direction perpendicular to the first main surface. may be provided between the gate trenches adjacent to each other in the first direction.
  • the connection region is provided between the gate trenches adjacent to each other in the first direction when viewed in plan from the direction perpendicular to the first main surface, it is easy to secure a large connection region and the electrical resistance in the connection region is low. It's easy to do.
  • the contact region when viewed in plan from a direction perpendicular to the first main surface, the contact region further includes a fourth region provided between the gate trenches adjacent in the first direction. wherein said third region has a third dimension in said first direction and said fourth region has a fourth dimension in said first direction that is less than said third dimension. Since the third dimension is larger than the fourth dimension, it is possible to secure a wide range in which current flows during ON while reducing the contact resistance between the third region and the source electrode.
  • the third dimension may be greater than 1 time and 6 times or less than the fourth dimension.
  • the third dimension is more than 1 time and 6 times or less than the fourth dimension, so that the contact resistance between the third region and the source electrode is reduced while ensuring a wide range in which current flows when the source electrode is turned on.
  • the contact resistance between the region and the source electrode can be kept low.
  • the source regions and the third regions are alternately provided in the first direction, and the third dimension is the length of the source region in the first direction. It may be greater than the fifth dimension. Since the third dimension is larger than the fifth dimension, each of the contact resistance between the third region and the source electrode and the contact resistance between the source region and the source electrode can be kept low.
  • the source region and the third region are alternately provided in the first direction, and the third dimension is the distance between the third dimension and the source region. It may be 0.2 times or more and 0.6 times or less of the sum of the fifth dimension in the first direction.
  • the third dimension is 0.2 times or more and 0.6 times or less the sum of the third dimension and the fifth dimension. Each of the contact resistances in between can be kept low.
  • the fourth region may be exposed from the interlayer insulating film, and the source electrode may also be connected to the fourth region.
  • the source electrode By connecting the source electrode also to the fourth region, the contact resistance between the contact region and the source electrode can be further reduced.
  • the contact region may have the third regions on both sides of the gate trench in the second direction. Since the contact region has the third regions on both sides of the gate trench in the second direction, it is easy to suppress electrical resistance between the source electrode and the electric field relaxation region.
  • the contact region may have the third region only on one side of the gate trench in the second direction. Since the contact region has the third region only on one side of the gate trench in the second direction, the contact hole on the side where the first region is not provided may be narrower than the contact hole on the side where the third region is provided. , it is easy to narrow the cell pitch in the second direction.
  • the first effective concentration of the second conductivity type impurity in the contact region is higher than the second effective concentration of the second conductivity type impurity in the connection region. may be higher. Since the first effective concentration is higher than the second effective concentration, leakage current can be easily suppressed while suppressing the contact resistance between the contact region and the source electrode.
  • the side surface of the gate trench may include a ⁇ 0-33-8 ⁇ plane. Since the side surfaces include the ⁇ 0-33-8 ⁇ plane, good mobility can be obtained on the side surfaces of the gate trench, and channel resistance can be reduced.
  • An embodiment of the present disclosure relates to a so-called vertical MOSFET (silicon carbide semiconductor device).
  • 1 and 2 are perspective cross-sectional views showing the configuration of the silicon carbide semiconductor device according to the embodiment.
  • FIG. 2 shows a see-through part of the internal structure of the silicon carbide semiconductor device.
  • FIG. 3 is a diagram showing configurations of an interlayer insulating film and a first main surface in the silicon carbide semiconductor device according to the embodiment.
  • FIG. 4 is a diagram showing the configuration of an electric field relaxation region.
  • 5 to 9 are cross-sectional views showing the configuration of the silicon carbide semiconductor device according to the embodiment.
  • FIG. 5 corresponds to a cross-sectional view taken along line VV in FIGS. 3 and 4.
  • FIG. 6 corresponds to a cross-sectional view taken along the line VI-VI in FIGS. 3 and 4.
  • FIG. 7 corresponds to a cross-sectional view taken along line VII-VII in FIGS. 3 and 4.
  • FIG. 8 corresponds to a cross-sectional view taken along line VIII-VIII in FIGS. 3 and 4.
  • FIG. 9 corresponds to a cross-sectional view taken along line IX-IX in FIGS. 3 and 4.
  • a MOSFET 100 includes a silicon carbide substrate 10, a gate insulating film 81, a gate electrode 82, an interlayer insulating film 83, a source electrode 60 and a drain electrode 70. , a barrier metal film 84 and a passivation film 85 .
  • Silicon carbide substrate 10 includes a silicon carbide single crystal substrate 50 and a silicon carbide epitaxial layer 40 overlying silicon carbide single crystal substrate 50 .
  • Silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to first main surface 1 .
  • Silicon carbide epitaxial layer 40 forms first main surface 1
  • silicon carbide single-crystal substrate 50 forms second main surface 2 .
  • Silicon carbide single crystal substrate 50 and silicon carbide epitaxial layer 40 are made of hexagonal silicon carbide of polytype 4H, for example.
  • Silicon carbide single crystal substrate 50 contains an n-type impurity such as nitrogen (N) and has n-type (first conductivity type).
  • the first main surface 1 is a plane in which the ⁇ 0001 ⁇ plane or the ⁇ 0001 ⁇ plane is inclined in the off direction by an off angle of 8° or less.
  • the first main surface 1 is the (000-1) plane or a plane in which the (000-1) plane is inclined in the off direction by an off angle of 8° or less.
  • the off direction may be, for example, the ⁇ 11-20> direction or the ⁇ 1-100> direction.
  • the off angle may be, for example, 1° or more, or may be 2° or more.
  • the off angle may be 6° or less, or may be 4° or less.
  • Silicon carbide epitaxial layer 40 mainly has drift region 11 , body region 12 , source region 13 , electric field relaxation region 16 , connection region 17 and contact region 18 .
  • the drift region 11 contains n-type impurities such as nitrogen or phosphorus (P), and has n-type conductivity.
  • the drift region 11 mainly has, for example, a fifth region 11A, a sixth region 11B, and a seventh region 11C.
  • Body region 12 is provided on drift region 11 .
  • Body region 12 contains a p-type impurity such as aluminum (Al) and has p-type (second conductivity type) conductivity.
  • the effective concentration of p-type impurities in body region 12 is 5 ⁇ 10 17 cm ⁇ 3 or higher.
  • a short-channel effect can occur when a depletion layer spreads from the pn junction region into the channel region and the entire channel region becomes a depletion layer.
  • the thickness of the body region 12 may be less than 0.7 ⁇ m, for example.
  • the effective p-type impurity concentration of the body region 12 is, for example, about 1 ⁇ 10 18 cm ⁇ 3 .
  • Source region 13 is provided on body region 12 so as to be separated from drift region 11 by body region 12 .
  • the source region 13 contains n-type impurities such as nitrogen or phosphorus and has n-type conductivity.
  • Source region 13 constitutes first main surface 1 .
  • the effective concentration of n-type impurities in source region 13 may be higher than the effective concentration of p-type impurities in body region 12 .
  • the effective n-type impurity concentration of the source region 13 is, for example, about 1 ⁇ 10 19 cm ⁇ 3 .
  • the contact region 18 contains p-type impurities such as aluminum and has p-type conductivity. Contact region 18 constitutes first main surface 1 .
  • the contact region 18 mainly has, for example, a third region 18A and a fourth region 18B.
  • the effective p-type impurity concentration of the contact region 18 is, for example, higher than the effective p-type impurity concentration of the body region 12 and the effective p-type impurity concentration of the connection region 17 .
  • Contact region 18 penetrates source region 13 and contacts body region 12 .
  • the effective concentration of the p-type impurity in the contact region 18 is, for example, 1 ⁇ 10 18 cm ⁇ 3 or more and 1 ⁇ 10 20 cm ⁇ 3 or less.
  • a gate trench 5 defined by a side surface 3 and a bottom surface 4 is provided on the first main surface 1 .
  • Side surface 3 penetrates source region 13 , body region 12 and drift region 11 to reach electric field relaxation region 16 .
  • the bottom surface 4 is continuous with the side surfaces 3 .
  • Bottom surface 4 is located in electric field relaxation region 16 .
  • the bottom surface 4 is, for example, a plane parallel to the second main surface 2 .
  • An angle ⁇ 1 of the side surface 3 with respect to the plane including the bottom surface 4 is, for example, 45° or more and 65° or less.
  • the angle ⁇ 1 may be, for example, 50° or more.
  • the angle ⁇ 1 may be, for example, 60° or less.
  • Side 3 preferably has a ⁇ 0-33-8 ⁇ plane.
  • the ⁇ 0-33-8 ⁇ plane is a crystal plane that provides excellent mobility.
  • the gate trench 5 extends in the Y1-Y2 direction (first direction) parallel to the first main surface 1 when viewed from above in a direction perpendicular to the first main surface 1. It overlaps with the straight line L1.
  • the gate trench 5 is on the imaginary straight line L1.
  • a plurality of gate trenches 5 are provided at regular intervals on the imaginary straight line L1.
  • a plurality of gate trenches 5 are also provided at regular intervals in the X1-X2 direction (second direction) perpendicular to the Y1-Y2 direction.
  • a plurality of gate trenches 5 may be provided, for example in an array.
  • the electric field relaxation region 16 contains p-type impurities such as Al and has p-type conductivity.
  • the electric field relaxation region 16 is between the bottom surface 4 of the gate trench 5 and the second main surface 2 .
  • the top surface of the electric field relaxation region 16 includes the bottom surface 4 of the gate trench 5, for example.
  • a portion of the upper end surface of the electric field relaxation region 16 faces a portion of the lower end surface of the body region 12 .
  • Electric field relaxation region 16 overlaps imaginary straight line L ⁇ b>1 when viewed from the direction perpendicular to first main surface 1 , similarly to gate trench 5 . When viewed in plan from a direction perpendicular to the first main surface 1, the electric field relaxation region 16 is on the imaginary straight line L1.
  • the electric field relaxation region 16 may be provided in common to the plurality of gate trenches 5 on the imaginary straight line L1. Also, when viewed from the direction perpendicular to the first main surface 1, a plurality of electric field relaxation regions 16 are provided at regular intervals in the X1-X2 direction. A plurality of electric field relaxation regions 16 may be provided in stripes.
  • the effective concentration of the p-type impurity in the electric field relaxation region 16 is, for example, 5 ⁇ 10 17 cm ⁇ 3 or more and 5 ⁇ 10 18 cm ⁇ 3 or less.
  • the fifth region 11A of drift region 11 is sandwiched between body region 12 and electric field relaxation region 16 .
  • the fifth region 11A is in contact with each of the body region 12 and the electric field relaxation region 16. As shown in FIG.
  • the fifth region 11A is located closer to the second main surface 2 than the body region 12 is.
  • the fifth region 11A is located closer to the first main surface 1 than the electric field relaxation region 16 is.
  • the effective n-type impurity concentration of the fifth region 11A is, for example, 5 ⁇ 10 15 cm ⁇ 3 or more and 5 ⁇ 10 16 cm ⁇ 3 or less.
  • the sixth region 11B is located closer to the second main surface 2 than the fifth region 11A.
  • the sixth region 11B is continuous with the fifth region 11A.
  • the sixth region 11B is in contact with the electric field relaxation region 16 in the direction parallel to the second main surface 2 .
  • the sixth region 11B and the electric field relaxation region 16 may be positioned on the same plane parallel to the second main surface 2 .
  • the effective n-type impurity concentration of the sixth region 11B may be higher than the effective n-type impurity concentration of the fifth region 11A.
  • the effective n-type impurity concentration of the sixth region 11B is, for example, 5 ⁇ 10 16 cm ⁇ 3 or more and 5 ⁇ 10 17 cm ⁇ 3 or less.
  • the seventh region 11C is located closer to the second main surface 2 than the sixth region 11B.
  • the seventh region 11C is continuous with the sixth region 11B.
  • the seventh region 11 ⁇ /b>C is in contact with the electric field relaxation region 16 .
  • the seventh region 11C is located closer to the second main surface 2 than the electric field relaxation region 16 is.
  • Seventh region 11 ⁇ /b>C may be sandwiched between sixth region 11 ⁇ /b>B and silicon carbide single-crystal substrate 50 .
  • Seventh region 11 ⁇ /b>C may continue to silicon carbide single-crystal substrate 50 .
  • the effective n-type impurity concentration of the seventh region 11C may be lower than the effective n-type impurity concentration of the sixth region 11B.
  • the effective n-type impurity concentration of the seventh region 11C is, for example, 5 ⁇ 10 15 cm ⁇ 3 or more and 5 ⁇ 10 16 cm ⁇ 3 or less.
  • the gate insulating film 81 is, for example, an oxide film.
  • the gate insulating film 81 is made of a material containing silicon dioxide, for example.
  • Gate insulating film 81 contacts side surface 3 and bottom surface 4 .
  • Gate insulating film 81 is in contact with electric field relaxation region 16 at bottom surface 4 .
  • Gate insulating film 81 is in contact with each of source region 13 , body region 12 and drift region 11 at side surface 3 .
  • Gate insulating film 81 may be in contact with source region 13 on first main surface 1 .
  • the gate electrode 82 is provided on the gate insulating film 81 .
  • the gate electrode 82 is made of, for example, polysilicon (poly-Si) containing conductive impurities.
  • Gate electrode 82 is arranged inside gate trench 5 . A portion of gate electrode 82 may be arranged on first main surface 1 .
  • the interlayer insulating film 83 is provided in contact with the gate electrode 82 and the gate insulating film 81 .
  • the interlayer insulating film 83 is made of a material containing silicon dioxide, for example.
  • Interlayer insulating film 83 electrically insulates gate electrode 82 and source electrode 60 .
  • a portion of the interlayer insulating film 83 may be provided inside the gate trench 5 .
  • the interlayer insulating film 83 overlaps the imaginary straight line L1 when viewed in plan from the direction perpendicular to the first main surface 1, similarly to the gate trench 5 and the electric field relaxation region 16.
  • Interlayer insulating film 83 may be provided in common to a plurality of gate trenches 5 on imaginary straight line L1.
  • Contact holes 90 are formed in the interlayer insulating film 83 and the gate insulating film 81 at regular intervals in the X1-X2 direction when viewed in plan from the direction perpendicular to the first main surface 1 .
  • the contact holes 90 are provided such that the gate trenches 5 are located between the contact holes 90 adjacent in the X1-X2 direction when viewed from above in the direction perpendicular to the first main surface 1 .
  • Contact hole 90 extends in the Y1-Y2 direction. Source region 13 and contact region 18 are exposed from interlayer insulating film 83 and gate insulating film 81 through contact hole 90 .
  • the dimension of the contact hole 90 in the X1-X2 direction may be 1 ⁇ m or less, for example.
  • the third region 18A of the contact region 18 is exposed from the interlayer insulating film 83 through the contact hole 90.
  • the third region 18A may be provided between gate trenches 5 adjacent in the X1-X2 direction. Between two gate trenches 5 adjacent in the X1-X2 direction, the third regions 18A and the source regions 13 may be alternately provided in the Y1-Y2 direction.
  • the third region 18A may be provided near the end of the gate trench 5 in the Y1-Y2 direction, and the source region 13 may be provided near the central portion of the gate trench 5 in the Y1-Y2 direction.
  • the third regions 18A are provided on both sides of the gate trench 5 in the X1-X2 direction.
  • the third region 18A and the source region 13 may be exposed from all the contact holes 90.
  • the third region 18A has a first side 18X extending in the Y1-Y2 direction.
  • the fourth region 18B is provided between the gate trenches 5 adjacent in the Y1-Y2 direction.
  • the fourth region 18B is covered with an interlayer insulating film 83 and a barrier metal film 84. As shown in FIG.
  • the fourth region 18B connects with the third region 18A in the X1-X2 direction.
  • the third regions 18A and the fourth regions 18B are alternately provided in the X1-X2 direction.
  • the third dimension W3 in the Y1-Y2 direction of the third region 18A is greater than the fourth dimension W4 in the Y1-Y2 direction of the fourth region 18B.
  • the connection region 17 contains a p-type impurity such as Al and has a p-type conductivity.
  • the connection region 17 electrically connects the contact region 18 and the electric field relaxation region 16 .
  • the connection region 17 is provided between the gate trenches 5 adjacent to each other in the Y1-Y2 direction when viewed from the direction perpendicular to the first main surface 1 .
  • the connection region 17 contacts the electric field relaxation region 16 on the imaginary straight line L1.
  • the connection region 17 contacts the body region 12 or the contact region 18 .
  • Connection region 17 may contact each of body region 12 and contact region 18 .
  • the connection region 17 is between the field relief region 16 and the contact region 18 .
  • the connection region 17 is located closer to the second main surface 2 than the contact region 18 is.
  • connection region 17 is located closer to the first main surface 1 than the electric field relaxation region 16 is.
  • the connection region 17 may be between the fourth region 18B and the electric field relaxation region 16 and contact each of the fourth region 18B and the electric field relaxation region 16.
  • the connection region 17 is between the fourth region 18B and the electric field relaxation region 16 in the direction perpendicular to the second main surface 2 and is in contact with each of the fourth region 18B and the electric field relaxation region 16, the fourth Series resistance between region 18B and field relaxation region 16 is reduced.
  • the effective p-type impurity concentration of the connection region 17 may be substantially the same as the effective p-type impurity concentration of the electric field relaxation region 16 .
  • the effective concentration of the p-type impurity in the connection region 17 is, for example, 5 ⁇ 10 17 cm ⁇ 3 or more and 5 ⁇ 10 18 cm ⁇ 3 or less.
  • the electric field relaxation region 16 mainly has, for example, a first region 16A and a second region 16B.
  • the first region 16A has a first dimension W1 in the X1-X2 direction and the second region 16B has a second dimension W2 in the X1-X2 direction.
  • the second dimension W2 is smaller than the first dimension W1.
  • the second region 16B connects to the first region 16A in the Y1-Y2 direction.
  • the first regions 16A and the second regions 16B are alternately provided in the Y1-Y2 direction.
  • the central axis of the first region 16A extending in the Y1-Y2 direction and the central axis of the second region 16B extending in the Y1-Y2 direction are continuous.
  • the first region 16A of the electric field relaxation region 16 and the third region 18A of the contact region 18 are arranged in the X1-X2 direction.
  • the first region 16A and part of the third region 18A overlap, more preferably the first side of the third region 18A.
  • the entirety of 18X overlaps a portion of the first region 16A.
  • the gate trench assembly is divided into a plurality of gate trenches 5 by the fourth region 18B and the connection region 17. can be done.
  • the barrier metal film 84 covers the upper and side surfaces of the interlayer insulating film 83 and the side surfaces of the gate insulating film 81 .
  • Barrier metal film 84 is in contact with each of interlayer insulating film 83 and gate insulating film 81 .
  • the barrier metal film 84 is made of a material containing titanium nitride (TiN), for example.
  • the source electrode 60 contacts the first main surface 1 .
  • the source electrode 60 has a contact electrode 61 and a source wiring 62 .
  • the contact electrode 61 is in contact with the source region 13 and the third region 18A of the contact region 18 on the first main surface 1 .
  • the contact electrode 61 is made of a material containing nickel silicide (NiSi), for example.
  • Contact electrode 61 may be made of a material containing titanium (Ti), Al, and Si.
  • the contact electrode 61 is in ohmic contact with the source region 13 and the third region 18A of the contact region 18 .
  • the source wiring 62 covers the top and side surfaces of the barrier metal film 84 and the top surface of the contact electrode 61 .
  • Source wiring 62 is in contact with each of barrier metal film 84 and contact electrode 61 .
  • the source wiring 62 is made of a material containing Al, for example.
  • a passivation film 85 covers the upper surface of the source wiring 62 .
  • the passivation film 85 is in contact with the source wiring 62 .
  • the passivation film 85 is made of a material containing polyimide, for example.
  • the drain electrode 70 is in contact with the second main surface 2 . Drain electrode 70 is in contact with silicon carbide single-crystal substrate 50 at second main surface 2 . Drain electrode 70 is electrically connected to drift region 11 .
  • the drain electrode 70 is made of a material containing NiSi, for example.
  • the drain electrode 70 may be made of a material containing Ti, Al, and Si. Drain electrode 70 is in ohmic contact with silicon carbide single crystal substrate 50 .
  • the upper end surface of the electric field relaxation region 16 may be separated from the bottom surface 4 in the direction perpendicular to the second main surface 2 .
  • bottom surface 4 may be located in drift region 11
  • side surface 3 may extend through source region 13 and body region 12 to drift region 11 .
  • a buffer layer containing an n-type impurity such as nitrogen and having an n-type conductivity may be provided between the silicon carbide single-crystal substrate 50 and the seventh region 11C.
  • the effective n-type impurity concentration of the buffer layer may be higher than the effective n-type impurity concentration of the seventh region 11C.
  • 10 to 29 are cross-sectional views showing the method of manufacturing the MOSFET 100 according to the embodiment.
  • 10 to 21 show variations of the cross section shown in FIG. 22 to 29 show variations of the cross section shown in FIG.
  • Silicon carbide single crystal substrate 50 is prepared by slicing a silicon carbide ingot (not shown) manufactured by, for example, a sublimation method.
  • a buffer layer (not shown) may be formed on silicon carbide single crystal substrate 50 .
  • the buffer layer is formed by chemical vapor deposition (CVD) using, for example, a mixed gas of silane (SiH 4 ) and propane (C 3 H 8 ) as a source gas and hydrogen (H 2 ) as a carrier gas. ) method.
  • CVD chemical vapor deposition
  • SiH 4 silane
  • propane C 3 H 8
  • H 2 hydrogen
  • an n-type impurity such as nitrogen may be introduced into the buffer layer.
  • First epitaxial layer 21 is formed on silicon carbide single crystal substrate 50 by a CVD method using, for example, a mixed gas of silane and propane as a source gas and hydrogen as a carrier gas.
  • an n-type impurity such as nitrogen is introduced into the first epitaxial layer 21 .
  • the first epitaxial layer 21 has n-type conductivity.
  • the effective n-type impurity concentration of the first epitaxial layer 21 may be lower than the effective n-type impurity concentration of the buffer layer.
  • the step of forming the electric field relaxation region 16 is performed.
  • a mask layer (not shown) having openings over the regions where the electric field relaxation regions 16 are to be formed is formed.
  • p-type impurity ions capable of imparting p-type, such as aluminum ions, are implanted into the first epitaxial layer 21 .
  • an electric field relaxation region 16 is formed.
  • the first region 16A is also formed at the same time as the second region 16B (see FIG. 22).
  • a step of forming the sixth region 11B is performed.
  • a mask layer (not shown) having an opening is formed on the region where the sixth region 11B is formed, that is, the region on the side of the electric field relaxation region 16 in the direction parallel to the second main surface 2 .
  • n-type impurity ions capable of imparting n-type, such as nitrogen, are implanted into the first epitaxial layer 21 .
  • the sixth region 11B is formed.
  • a portion of first epitaxial layer 21 closer to silicon carbide single-crystal substrate 50 than electric field relaxation region 16 and a portion closer to silicon carbide single-crystal substrate 50 than sixth region 11B constitute seventh region 11C.
  • the effective n-type impurity concentration of the sixth region 11B is higher than the effective n-type impurity concentration of the seventh region 11C.
  • the step of forming the second epitaxial layer 22 is performed.
  • the second epitaxial layer 22 is formed on the first epitaxial layer 21 by a CVD method using a mixed gas of silane and propane as a source gas and hydrogen as a carrier gas.
  • an n-type impurity such as nitrogen is introduced into the second epitaxial layer 22 .
  • the second epitaxial layer 22 has n-type conductivity.
  • the thickness of the second epitaxial layer 22 is, for example, 0.8 ⁇ m or more and 1.2 ⁇ m or less.
  • the effective n-type impurity concentration of the second epitaxial layer 22 is set lower than the effective n-type impurity concentration of the sixth region 11B.
  • a step of forming body regions 12 is performed.
  • p-type impurity ions capable of imparting p-type, such as aluminum ions are implanted into the entire surface of the second epitaxial layer 22 . Thereby, body region 12 is formed.
  • the step of forming the source region 13 is performed.
  • n-type impurity ions capable of imparting n-type, such as phosphorus are implanted into the entire surface of the second epitaxial layer 22 .
  • a source region 13 is thus formed.
  • connection regions 17 are formed.
  • a mask layer (not shown) having openings over the regions where the connection regions 17 are to be formed is formed.
  • p-type impurity ions capable of imparting p-type, such as aluminum ions are implanted into the source region 13, the body region 12 and the fifth region 11A. Thereby, a connection region 17 in contact with the body region 12 and the electric field relaxation region 16 is formed.
  • a step of forming contact regions 18 is performed.
  • a mask layer (not shown) having openings over regions where contact regions 18 are to be formed is formed.
  • p-type impurity ions capable of imparting p-type, such as aluminum ions are implanted into the connection region 17 . Thereby, a contact region 18 in contact with the body region 12 and the connection region 17 is formed.
  • activation annealing is performed to activate the impurity ions implanted into silicon carbide substrate 10 .
  • the temperature of the activation annealing is preferably 1500°C or higher and 1900°C or lower, for example, about 1700°C.
  • the activation annealing time is, for example, about 30 minutes.
  • the atmosphere for the activation annealing is preferably an inert gas atmosphere such as an Ar atmosphere.
  • a step of forming gate trenches 5 is performed.
  • a mask layer (not shown) having an opening above the position where the gate trench 5 is to be formed is formed on the first main surface 1 composed of the source region 13 and the contact region 18 .
  • a portion of source region 13, a portion of body region 12 and a portion of drift region 11 are etched away.
  • reactive ion etching especially inductively coupled plasma reactive ion etching can be used.
  • inductively coupled plasma reactive ion etching using sulfur hexafluoride (SF 6 ) or a mixed gas of SF 6 and oxygen (O 2 ) as a reactive gas can be used.
  • SF 6 sulfur hexafluoride
  • O 2 oxygen
  • etching in the region where the gate trench 5 is to be formed, a side portion substantially perpendicular to the first main surface 1 and a bottom portion provided continuously with the side portion and substantially parallel to the first main surface 1 are formed.
  • a recess (not shown) having a is formed.
  • a thermal etch is then performed in the recess.
  • Thermal etching can be performed, for example, by heating in an atmosphere containing a reactive gas having at least one type of halogen atom while the mask layer is formed on the first main surface 1 .
  • the at least one halogen atom includes at least one of chlorine (Cl) and fluorine (F) atoms.
  • the atmosphere includes, for example, chlorine (Cl 2 ), boron trichloride (BCl 3 ), SF 6 or carbon tetrafluoride (CF 4 ).
  • a mixed gas of chlorine gas and oxygen gas is used as a reaction gas, and thermal etching is performed at a heat treatment temperature of, for example, 800° C. or higher and 900° C. or lower.
  • the reaction gas may contain a carrier gas in addition to the chlorine gas and the oxygen gas described above.
  • the carrier gas for example, nitrogen gas, argon gas, helium gas, or the like can be used.
  • Gate trenches 5 are formed in first main surface 1 of silicon carbide substrate 10 by the thermal etching described above. Gate trench 5 is defined by side surfaces 3 and a bottom surface 4 . Side surface 3 is composed of source region 13 , body region 12 , and drift region 11 . The bottom surface 4 is composed of an electric field relaxation region 16 . An angle ⁇ 1 between the side surface 3 and the plane including the bottom surface 4 is, for example, 45° or more and 65° or less. The mask layer is then removed from the first major surface 1 .
  • a step of forming a gate insulating film 81 is performed. For example, by thermally oxidizing silicon carbide substrate 10, gate insulating film 81 in contact with source region 13, body region 12, drift region 11, electric field relaxation region 16, and contact region 18 is formed. Specifically, silicon carbide substrate 10 is heated, for example, at a temperature of 1300° C. or more and 1400° C. or less in an atmosphere containing oxygen. As a result, the gate insulating film 81 is formed in contact with the first main surface 1, the side surface 3 and the bottom surface 4. Next, as shown in FIG.
  • heat treatment may be performed on silicon carbide substrate 10 in a nitrogen monoxide (NO) gas atmosphere.
  • NO nitrogen monoxide
  • silicon carbide substrate 10 is held under conditions of, for example, 1100° C. or more and 1400° C. or less for about one hour.
  • nitrogen atoms are introduced into the interface region between gate insulating film 81 and body region 12 .
  • the channel mobility can be improved by suppressing the formation of interface states in the interface region.
  • a gate electrode 82 is formed on the gate insulating film 81 .
  • the gate electrode 82 is formed by, for example, a low pressure CVD (Low Pressure-Chemical Vapor Deposition: LP-CVD) method. Gate electrode 82 is formed to face each of source region 13 , body region 12 and drift region 11 .
  • LP-CVD Low Pressure-Chemical Vapor Deposition
  • interlayer insulating film 83 is formed to cover gate electrode 82 and to be in contact with gate insulating film 81 .
  • the interlayer insulating film 83 is formed by, for example, the CVD method.
  • the interlayer insulating film 83 is made of a material containing silicon dioxide, for example. A portion of interlayer insulating film 83 may be formed inside gate trench 5 .
  • a step of forming the barrier metal film 84, the contact electrode 61 and the drain electrode 70 is performed.
  • the interlayer insulating film 83 and the gate insulating film 81 are etched to form the contact holes 90 in the interlayer insulating film 83 and the gate insulating film 81 .
  • a barrier metal film 84 is formed to cover the top and side surfaces of the interlayer insulating film 83 and the side surfaces of the gate insulating film 81 .
  • the barrier metal film 84 is made of a material containing TiN, for example.
  • the barrier metal film 84 is formed by, for example, film formation by sputtering and reactive ion etching (RIE).
  • a metal film (not shown) for the contact electrode 61 in contact with the source region 13 and the third region 18A is formed on the first main surface 1 .
  • a metal film for the contact electrode 61 is formed by, for example, a sputtering method.
  • the metal film for the contact electrode 61 is made of a material containing Ni, for example.
  • a metal film (not shown) for drain electrode 70 is formed in contact with silicon carbide single crystal substrate 50 on second main surface 2 .
  • a metal film for the drain electrode 70 is formed by, for example, a sputtering method.
  • the metal film for the drain electrode 70 is made of a material containing Ni, for example.
  • the metal film for the contact electrode 61 and the metal film for the drain electrode 70 are held at a temperature of, for example, 900° C. or more and 1100° C. or less for about 5 minutes. As a result, at least part of the metal film for contact electrode 61 and at least part of the metal film for drain electrode 70 react with silicon contained in silicon carbide substrate 10 to be silicided. Thereby, contact electrode 61 in ohmic contact with source region 13 and third region 18A, and drain electrode 70 in ohmic contact with silicon carbide single crystal substrate 50 are formed.
  • Contact electrode 61 may be made of a material containing Ti, Al, and Si.
  • Drain electrode 70 may be made of a material containing Ti, Al, and Si.
  • a step of forming source wiring 62 is performed. Specifically, the source wiring 62 covering the contact electrode 61 and the barrier metal film 84 is formed.
  • the source wiring 62 is formed by, for example, film formation by sputtering and RIE.
  • the source wiring 62 is made of a material containing aluminum, for example.
  • the source electrode 60 having the contact electrode 61 and the source wiring 62 is formed.
  • a step of forming a passivation film 85 is performed. Specifically, a passivation film 85 covering the source wiring 62 is formed.
  • the passivation film 85 is made of a material containing polyimide, for example.
  • the passivation film 85 is formed by, for example, a coating method.
  • the passivation film 85 may be formed by plasma CVD.
  • the contact region 18 and the electric field relaxation region 16 are electrically connected by the connection region 17 .
  • Contact region 18 is electrically connected to source electrode 60 . Therefore, the electric field relaxation region 16 is electrically connected to the source electrode 60.
  • FIG. Therefore, carriers can be supplied from the source electrode 60 to the electric field relaxation region 16, and the feedback capacitance can be reduced. By reducing the feedback capacitance, the switching loss can be reduced and the switching speed can be improved.
  • the gate trench 5 and the electric field relaxation region 16 are on the imaginary straight line L1. That is, the gate trench 5 and the electric field relaxation region 16 overlap the imaginary straight line L1.
  • the connection region 17 is in contact with the electric field relaxation region 16 on the imaginary straight line L1. Therefore, the connection region 17 prevents the drain current flowing along the portion of the side surface 3 parallel to the Y1-Y2 direction, that is, the portion of the side surface 3 which is spaced from the end of the gate trench 5 in the Y1-Y2 direction. hard to hinder. Therefore, a sufficient drain current can be secured when the device is turned on.
  • the second dimension W2 of the second region 16B is smaller than the first dimension W1 of the first region 16A, and when viewed from above in a direction perpendicular to the first main surface 1, the first region 16A extends in the X1-X2 direction. and the third area 18A are arranged. Therefore, the electric field concentration at the second main surface 2 side of the contact region 18 at the time of OFF can be alleviated in the vicinity of the first region 16A while ensuring a region in the vicinity of the second region 16B in which the drain current flows at the time of ON. . Therefore, drain leakage caused by electric field concentration can be suppressed.
  • part of the first region 16A and part of the third region 18A overlap when viewed from the direction perpendicular to the first main surface 1 in plan view.
  • electric field concentration at a position near the second main surface 2 of the contact region 18 is easily alleviated, and drain leakage is easily suppressed.
  • the entire first side 18X of the third region 18A overlaps with a portion of the first region 16A. In this case, the electric field concentration at the position near the second main surface 2 of the contact region 18 can be more easily alleviated, and the drain leakage can be more easily suppressed.
  • a connection region 17 is provided between the gate trenches 5 adjacent to each other in the Y1-Y2 direction when viewed from the direction perpendicular to the first main surface 1 .
  • the connection region 17 may be provided so as to overlap the gate trenches 5 when viewed in plan from the direction perpendicular to the first main surface 1 , the connection regions 17 are better provided between the gate trenches 5 .
  • the volume of the region 17 can be increased, and the electrical resistance in the connection region 17 can be reduced.
  • the gate trench 5 and the fourth region 18B are located in the Y1-Y2 direction.
  • a drain current can also flow in the region between
  • the semiconductor region provided near the upper end of the gate trench 5 is the n-type source region 13 .
  • a p-type contact region 18 may be present near the upper end of the gate trench 5 , but the gate insulating film 81 tends to be thinner over the p-type contact region 18 than over the n-type source region 13 .
  • the electric field tends to concentrate near the upper end of the gate trench 5 . Since the semiconductor region provided in the vicinity of the upper end of the gate trench 5 is the n-type source region 13, it is easy to form a thick gate insulating film 81, and the gate insulating film accompanying the electric field concentration in the vicinity of the upper end of the gate trench 5 is easily formed. Dielectric breakdown of 81 can be suppressed.
  • a third region 18A is provided on both sides of the gate trench 5 in the X1-X2 direction. Therefore, compared to the case where the third region 18A is provided only on one side of the gate trench 5 in the X1-X2 direction, the electrical resistance between the source electrode 60 and the electric field relaxation region 16 can be suppressed.
  • connection region 17 is between the fourth region 18B and the electric field relaxation region 16 in the direction perpendicular to the second main surface 2 and is in contact with each of the fourth region 18B and the electric field relaxation region 16. Series resistance between the 4 region 18B and the electric field relaxation region 16 can be reduced.
  • the first effective concentration of p-type impurities in the contact region 18 is preferably higher than the second effective concentration of p-type impurities in the connection region 17 .
  • the high first effective concentration can suppress the contact resistance between the contact region 18 and the contact electrode 61 . If the second effective concentration is as high as the first effective concentration, a leak current may easily flow due to the introduction of crystal defects.
  • the third dimension W3 in the Y1-Y2 direction of the third region 18A is preferably larger than the fourth dimension W4 in the Y1-Y2 direction of the fourth region 18B. Since the contact electrode 61 is ohmic-connected to the third region 18A, the contact resistance between the third region 18A and the contact electrode 61 can be reduced as the third dimension W3 increases. On the other hand, the fourth region 18B is provided between the gate trenches 5 adjacent in the Y1-Y2 direction. It may become difficult to obtain a sufficient drain current. Since the third dimension W3 is larger than the fourth dimension W4, it is possible to reduce the contact resistance between the third region 18A and the source electrode 60 while ensuring a wide range in which the drain current flows during the ON state. Therefore, the third dimension W3 is preferably larger than the fourth dimension W4.
  • the third dimension W3 is preferably more than 1 time and 6 times or less than the fourth dimension W4. If the third dimension W3 is more than six times the fourth dimension W4, the area where the contact electrode 61 makes an ohmic contact with the source region 13 inside the contact hole 90 becomes small, and the contact between the source region 13 and the contact electrode 61 becomes small. Resistance may increase. When the third dimension W3 is more than 1 time and 6 times or less than the fourth dimension W4, the contact resistance between the third region 18A and the source electrode 60 is reduced, and the range in which the drain current flows when ON is widened. In addition, the contact resistance between the source region 13 and the source electrode 60 can be kept low. Therefore, it is more preferable that the third dimension W3 is two to five times the fourth dimension W4.
  • the third dimension W3 is preferably larger than the fifth dimension W5 of the source region 13 in the Y1-Y2 direction.
  • p-type impurities are more difficult to activate than n-type impurities. Since the third dimension W3 is larger than the fifth dimension W5, each of the contact resistance between the third region 18A and the contact electrode 61 and the contact resistance between the source region 13 and the contact electrode 61 can be kept low. .
  • the third dimension W3 is preferably 0.2 to 0.6 times the sum Wch of the third dimension W3 and the fifth dimension W5. If the third dimension W3 is less than 0.2 times the sum Wch, the contact resistance between the third region 18A and the contact electrode 61 may become too high. If the third dimension W3 is larger than 0.6 times the sum Wch, the contact resistance between the source region 13 and the contact electrode 61 may become too high. When the third dimension W3 is 0.2 to 0.6 times the sum Wch, the contact resistance between the third region 18A and the contact electrode 61 and the contact resistance between the source region 13 and the contact electrode 61 are reduced. Each of the resistances can be kept low. More preferably, the third dimension W3 is 0.3 to 0.6 times the sum Wch.
  • FIG. 30 is a cross-sectional view showing the configuration of a MOSFET (silicon carbide semiconductor device) according to the first modification of the embodiment.
  • FIG. 30 shows a cross section similar to the cross section along line VV in FIG.
  • the gate trench 5 is a vertical trench. That is, the angle ⁇ 1 of the side surface 3 with respect to the plane including the bottom surface 4 may be 90°. Other configurations are the same as in the embodiment.
  • FIG. 31 is a diagram showing configurations of an interlayer insulating film and a first main surface in a silicon carbide semiconductor device according to a second modification of the embodiment.
  • FIG. 32 is a cross-sectional view showing the configuration of a silicon carbide semiconductor device according to a second modification of the embodiment.
  • FIG. 32 corresponds to a cross-sectional view taken along line XXXII-XXXII in FIG.
  • the third region 18A is provided only on one side of the gate trench 5 in the X1-X2 direction.
  • a contact hole 91 and a contact hole 92 are formed in the interlayer insulating film 83 .
  • Contact holes 91 and contact holes 92 are alternately arranged in the X1-X2 direction.
  • Third region 18A may be provided in a portion of first main surface 1 exposed to contact hole 91 and not provided in a portion of first main surface 1 exposed to contact hole 92 .
  • the third region 18A and the source region 13 may be exposed through the contact hole 91 . Only source region 13 may be exposed from contact hole 92 .
  • the contact electrode 61 is in ohmic contact with each of the source region 13 and the third region 18A. Inside the contact hole 92 , the contact electrode 61 is in ohmic contact with the source region 13 .
  • Other configurations are the same as in the embodiment.
  • the second modification it is possible to reduce the feedback capacitance, reduce the switching loss by reducing the feedback capacitance, and improve the switching speed. Sufficient drain current can also be ensured by the second modification. According to the second modification, it is also possible to suppress dielectric breakdown of the gate insulating film 81 due to electric field concentration in the vicinity of the upper end of the gate trench 5 . The second modification can also reduce the series resistance between the fourth region 18B and the electric field relaxation region 16 .
  • FIG. 33 is a diagram showing configurations of an interlayer insulating film and a first main surface in a silicon carbide semiconductor device according to a third modification of the embodiment.
  • FIG. 34 is a cross-sectional view showing the configuration of a silicon carbide semiconductor device according to a third modification of the embodiment.
  • FIG. 34 corresponds to a cross-sectional view taken along line XXXIV-XXXIV in FIG.
  • the contact region 18 is composed of the third region 18A and the contact region 18 does not include the fourth region 18B.
  • the connection region 17 may constitute the first main surface 1 between the gate trenches 5 adjacent in the Y1-Y2 direction and below the interlayer insulating film 83 and the barrier metal film 84 .
  • the connection region 17 may contact the gate insulating film 81 and the barrier metal film 84 .
  • Other configurations are the same as in the embodiment.
  • the third modification it is possible to reduce the feedback capacitance, reduce the switching loss by reducing the feedback capacitance, and improve the switching speed. Sufficient drain current can also be ensured by the third modification. According to the third modification, it is also possible to suppress dielectric breakdown of the gate insulating film 81 due to electric field concentration in the vicinity of the upper end of the gate trench 5 . Also according to the third modification, the electric resistance between the source electrode 60 and the electric field relaxation region 16 is reduced compared to the case where the third region 18A is provided only on one side of the gate trench 5 in the X1-X2 direction. can.
  • FIG. 35 is a diagram showing configurations of an interlayer insulating film and a first main surface in a silicon carbide semiconductor device according to a fourth modification of the embodiment.
  • FIG. 36 is a cross-sectional view showing the configuration of a silicon carbide semiconductor device according to a fourth modification of the embodiment.
  • FIG. 36 corresponds to a cross-sectional view taken along line XXXVI-XXXVI in FIG.
  • a plurality of gate trenches 5 arranged on the imaginary straight line L1 in the embodiment are connected to each other to form a gate trench 5A.
  • the fourth region 18B and the connection region 17 are provided on both sides of the gate trench 5A in the X1-X2 direction.
  • the fourth region 18B and the connection region 17 may be in contact with the side surface 3.
  • Other configurations are the same as in the embodiment.
  • the feedback capacitance can be reduced, the switching loss can be reduced by reducing the feedback capacitance, and the switching speed can be improved.
  • a sufficient drain current can also be ensured by the fourth modification.
  • the electric resistance between the source electrode 60 and the electric field relaxation region 16 is also reduced compared to the case where the third region 18A is provided only on one side of the gate trench 5 in the X1-X2 direction. can.
  • the series resistance between the fourth region 18B and the electric field relaxation region 16 can be reduced also by the fourth modification.
  • the contact hole may be formed to reach the fourth region, the fourth region may be exposed from the interlayer insulating film, and the source electrode may also be connected to the fourth region. In this case, contact resistance between the contact region and the source electrode can be further reduced.
  • the n-type is the first conductivity type and the p-type is the second conductivity type. good.
  • a MOSFET is used as an example of a silicon carbide semiconductor device, but the silicon carbide semiconductor device may be, for example, an insulated gate bipolar transistor (IGBT).
  • IGBT insulated gate bipolar transistor
  • the effective concentration of p-type impurities and the effective concentration of n-type impurities in each of the above impurity regions can be determined, for example, by a scanning capacitance microscope (SCM) method or a secondary ion mass spectrometry (SIMS) method. It can be measured by, for example.
  • SCM scanning capacitance microscope
  • SIMS secondary ion mass spectrometry
  • the position of the interface between the p-type region and the n-type region can be specified by, for example, the SCM method or the SIMS method.
  • the distribution of the effective concentration of majority carriers in the current diffusion region can be identified, for example, based on the thickness distribution of the depletion layer generated by the pn junction between the current diffusion region and the body region without measuring the effective concentration.
  • the thickness of the depletion layer can be specified by, for example, the SCM method or the SIMS method.

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  • Electrodes Of Semiconductors (AREA)
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DE112023001206.7T DE112023001206T5 (de) 2022-03-04 2023-02-27 Siliziumkarbid-Halbleitervorrichtung
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Publication number Priority date Publication date Assignee Title
WO2018088063A1 (ja) * 2016-11-11 2018-05-17 住友電気工業株式会社 炭化珪素半導体装置
JP2019087647A (ja) * 2017-11-07 2019-06-06 富士電機株式会社 絶縁ゲート型半導体装置及びその製造方法
WO2021124800A1 (ja) * 2019-12-20 2021-06-24 住友電気工業株式会社 炭化珪素半導体装置

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Publication number Priority date Publication date Assignee Title
WO2018088063A1 (ja) * 2016-11-11 2018-05-17 住友電気工業株式会社 炭化珪素半導体装置
JP2019087647A (ja) * 2017-11-07 2019-06-06 富士電機株式会社 絶縁ゲート型半導体装置及びその製造方法
WO2021124800A1 (ja) * 2019-12-20 2021-06-24 住友電気工業株式会社 炭化珪素半導体装置

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