WO2023164973A1 - 阵列基板及显示面板 - Google Patents

阵列基板及显示面板 Download PDF

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Publication number
WO2023164973A1
WO2023164973A1 PCT/CN2022/080808 CN2022080808W WO2023164973A1 WO 2023164973 A1 WO2023164973 A1 WO 2023164973A1 CN 2022080808 W CN2022080808 W CN 2022080808W WO 2023164973 A1 WO2023164973 A1 WO 2023164973A1
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Prior art keywords
layer
reduction potential
array substrate
host material
barrier layer
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PCT/CN2022/080808
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English (en)
French (fr)
Inventor
孙建强
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广州华星光电半导体显示技术有限公司
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Priority to US17/754,249 priority Critical patent/US20240053646A1/en
Publication of WO2023164973A1 publication Critical patent/WO2023164973A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting

Definitions

  • the present application relates to the field of display technology, and in particular to an array substrate and a display panel.
  • the second metal layer in the thin film transistor usually includes a first barrier layer, a conductive layer and a second barrier layer that are sequentially stacked along the direction close to the substrate, because the first barrier layer and the conductive layer
  • the reduction potential is very close, causing the lateral etching of the first barrier layer and the conductive layer to proceed almost simultaneously, resulting in a relatively large taper angle (cone angle) of the second metal layer, almost 90°, and accompanied by a long tip (tip), causing the passivation layer covering the second metal layer to be too thin at the climbing point and appear indented, thus causing the overlapping fracture of the pixel electrode layer disposed on the passivation layer.
  • the embodiment of the present application provides an array substrate and a display panel to solve the problem that the taper angle of the second metal layer of the existing array substrate and display panel is too large, and it is accompanied by a long tip, which causes the first passivation layer to be too high at the climbing point. Thin and sunken, resulting in the technical problem of overlapping fracture of the pixel electrode layer.
  • the application provides an array substrate, including:
  • the thin film transistor array layer is arranged on one side of the base substrate, and the thin film transistor array layer includes a first metal layer, a gate insulating layer, a semiconductor layer and a second metal layer;
  • the second metal layer includes a first barrier layer, a conductive layer, and a second barrier layer that are sequentially stacked along the direction close to the base substrate, the material of the second barrier layer is molybdenum-titanium alloy, and the first barrier layer
  • the reduction potential of a barrier layer is lower than the reduction potential of the conductive layer, and the absolute value of the difference between the reduction potential of the first barrier layer and the reduction potential of the conductive layer ranges from 0.15 to 0.59.
  • the absolute value of the difference between the reduction potential of the first barrier layer and the reduction potential of the conductive layer is greater than the reduction potential of the second barrier layer and the reduction potential of the conductive layer The absolute value of the difference between .
  • the first barrier layer includes a first host material and a first auxiliary material, and the reduction potential of the first auxiliary material is lower than the reduction potential of the first host material.
  • the absolute value of the difference between the reduction potential of the first auxiliary material and the reduction potential of the first host material is greater than the reduction potential of the first host material and the reduction potential of the conductive layer.
  • the absolute value of the difference between the reduction potentials; the reduction potential of the first host material is positive, and the reduction potential of the first auxiliary material is negative.
  • the application provides an array substrate, including:
  • the thin film transistor array layer is arranged on one side of the base substrate, and the thin film transistor array layer includes a first metal layer, a gate insulating layer, a semiconductor layer and a second metal layer;
  • the second metal layer includes a first barrier layer, a conductive layer, and a second barrier layer that are sequentially stacked along the direction close to the substrate, and the reduction potential of the first barrier layer is lower than that of the conductive layer. potential.
  • the absolute value of the difference between the reduction potential of the first barrier layer and the reduction potential of the conductive layer ranges from 0.15 to 0.59.
  • the absolute value of the difference between the reduction potential of the first barrier layer and the reduction potential of the conductive layer is greater than the reduction potential of the second barrier layer and the reduction potential of the conductive layer The absolute value of the difference between .
  • the first barrier layer includes a first host material and a first auxiliary material, and the reduction potential of the first auxiliary material is lower than the reduction potential of the first host material.
  • the absolute value of the difference between the reduction potential of the first auxiliary material and the reduction potential of the first host material is greater than the reduction potential of the first host material and the reduction potential of the conductive layer.
  • the absolute value of the difference between the reduction potentials; the reduction potential of the first host material is positive, and the reduction potential of the first auxiliary material is negative.
  • the conductive layer is made of copper
  • the first main body material is molybdenum-titanium alloy
  • the first auxiliary material is any one of nickel, magnesium, aluminum and zinc.
  • the mass ratio of the molybdenum is greater than 50%, and the mass ratio of the first auxiliary material is greater than 0 and less than or equal to 49%.
  • the conductive layer includes a second host material and a second auxiliary material, and the reduction potential of the second auxiliary material is greater than that of the second host material.
  • the absolute value of the difference between the reduction potential of the second auxiliary material and the reduction potential of the second host material is greater than the reduction potential of the first barrier layer and the reduction potential of the second host material.
  • the absolute value of the difference between the reduction potentials of the materials; the reduction potential of the second host material is positive, and the reduction potential of the second auxiliary material is positive.
  • the material of the first barrier layer is molybdenum-titanium alloy
  • the second host material is copper
  • the second auxiliary material is any one of silver, gold, platinum and mercury.
  • the material of the second barrier layer is molybdenum-titanium alloy.
  • the conductive layer includes a second host material and a second auxiliary material, and the reduction potential of the second auxiliary material is greater than that of the second host material; and, the second auxiliary material
  • the absolute value of the difference between the reduction potential of the material and the reduction potential of the second host material is greater than the absolute value of the difference between the reduction potential of the first host material and the reduction potential of the second host material.
  • the first metal layer, the gate insulating layer, the semiconductor layer, and the second metal layer are sequentially stacked along a direction away from the base substrate; or, the semiconductor layer, the gate insulating layer, the first metal layer and the second metal layer are sequentially stacked along a direction away from the base substrate.
  • the array substrate further includes:
  • the pixel electrode layer is disposed on the side of the first passivation layer away from the base substrate, and the pixel electrode layer is electrically connected to the second metal layer through the first via hole penetrating through the first passivation layer. connect.
  • the array substrate further includes:
  • a second passivation layer disposed on a side of the organic planarization layer away from the base substrate;
  • the pixel electrode layer is located on a side of the second passivation layer away from the base substrate, and the first via hole penetrates through the second passivation layer, the organic planar layer and the first passivation layer. passivation layer.
  • the present application provides a display panel, including an opposite substrate, a liquid crystal layer, and the above-mentioned array substrate, the opposite substrate and the array substrate are arranged at intervals, and the liquid crystal layer is arranged between the opposite substrate and the array substrate between;
  • the array substrate includes:
  • the thin film transistor array layer is arranged on one side of the base substrate, and the thin film transistor array layer includes a first metal layer, a gate insulating layer, a semiconductor layer and a second metal layer;
  • the second metal layer includes a first barrier layer, a conductive layer, and a second barrier layer that are sequentially stacked along the direction close to the substrate, and the reduction potential of the first barrier layer is lower than that of the conductive layer. potential.
  • the second metal layer includes a stacked second barrier layer, a conductive layer and a first barrier layer, and by setting the reduction potential of the first barrier layer to be less than
  • the reduction potential of the conductive layer makes the first barrier layer easier to be etched in galvanic corrosion than the conductive layer, which is beneficial to reduce the taper angle of the second metal layer, simultaneously improves the long tip, and effectively improves the first passivation
  • the coverage of the layer reduces the occurrence of overlapping fractures of the pixel electrode layer caused by the sinking of the first passivation layer at the climbing point when it is too thin; in addition, it enhances the electrical properties and reliability of the thin film transistor device and reduces the The risk of electrostatic discharge explosion is eliminated.
  • FIG. 1 is a schematic cross-sectional structure diagram of an array substrate in the prior art
  • Fig. 2 is a schematic cross-sectional structure diagram of an array substrate provided by an embodiment of the present application
  • 3A is a schematic cross-sectional structure diagram of the first thin film transistor array layer in the array substrate provided by the embodiment of the present application;
  • Fig. 3B is a schematic cross-sectional structure diagram of the second thin film transistor array layer in the array substrate provided by the embodiment of the present application;
  • FIG. 4 is a schematic diagram of a first cross-sectional structure of a second metal layer provided in an embodiment of the present application
  • FIG. 5 is a schematic diagram of a second cross-sectional structure of a second metal layer provided in an embodiment of the present application.
  • FIG. 6 is a schematic diagram of a third cross-sectional structure of a second metal layer provided in an embodiment of the present application.
  • FIG. 7 is a schematic cross-sectional structure diagram of another array substrate provided by an embodiment of the present application.
  • FIG. 8 is a flow chart of a method for manufacturing an array substrate provided in an embodiment of the present application.
  • Base substrate 20. Thin film transistor array layer; 201. First metal layer; 202. Gate insulating layer; 203. Semiconductor layer; 204. Second metal layer; 205. Source-drain insulating layer; 30.
  • FIG. 1 is a schematic cross-sectional structure diagram of an array substrate in the prior art.
  • the thin film transistor includes a base substrate 10 and a thin film transistor array layer 20.
  • the thin film transistor array layer 20 includes a first metal layer 201, a gate An insulating layer 202, a semiconductor layer (not shown in the figure) and a second metal layer 204, the side of the second metal layer 204 away from the base substrate 10 is provided with a first passivation layer 30, the first A pixel electrode layer 40 is disposed on a side of the passivation layer 30 away from the base substrate 10 .
  • the second metal layer 204 is generally composed of three metal layers: first barrier layer 2041 / conductive layer 2042 / second barrier layer 2043 .
  • FIG. 3B is a schematic cross-sectional structural schematic view of the second type of thin film transistor array layer in the array substrate provided by the embodiment of the present application.
  • the array substrate includes a base substrate 10 and a thin film transistor array layer 20.
  • the thin film transistor array layer 20 is arranged on one side of the base substrate 10.
  • the thin film transistor array layer 20 includes a plurality of thin film transistors.
  • the transistor array layer 20 includes a first metal layer 201 , a gate insulating layer 202 , a semiconductor layer 203 and a second metal layer 204 .
  • the thin film transistor may be a bottom gate thin film transistor, specifically, the first metal layer 201, the gate insulating layer 202, the semiconductor layer 203 and the second metal layer 204 stacked in sequence along a direction away from the base substrate 10 .
  • the thin film transistor may also be a top-gate thin film transistor.
  • the thin film transistor array layer 20 further includes a source-drain insulating layer 205, and the source-drain insulating layer 205 covers the first metal layer 201 and the gate insulating layer.
  • Layer 202, the source-drain insulating layer 205 includes a source and a drain, the source is electrically connected to the semiconductor layer 203 through a via hole penetrating through the source-drain insulating layer 205, and the drain is electrically connected to the semiconductor layer 203 through a hole penetrating through the source-drain insulating layer 205.
  • Another via hole of the source-drain insulating layer 205 is electrically connected to the semiconductor layer 203 .
  • the array substrate further includes a first passivation layer 30 and a pixel electrode layer 40 , and the first passivation layer 30 covers the second metal layer 204 .
  • the pixel electrode layer 40 is disposed on the side of the first passivation layer 30 away from the base substrate 10 , and the pixel electrode layer 40 passes through the first via hole 301 penetrating through the first passivation layer 30 and The second metal layer 204 is electrically connected.
  • the second metal layer 204 adopts a three-layer metal structure.
  • the second metal layer 204 includes a stacked second barrier layer 2043, a conductive layer 2042, and a first barrier layer 2041. It can be understood that the present application In the embodiment, by setting the reduction potential of the first barrier layer 2041 to be lower than the reduction potential of the conductive layer 2042, since the contact between two metals or alloys is in a conductive state, Janifan corrosion will occur, that is, the potential is lower than that of the conductive layer 2042.
  • Negative metals are corroded at an accelerated rate, and metals with higher potentials are protected from corrosion, so that the first barrier layer 2041 is more likely to be etched in galvanic corrosion than the conductive layer 2042, and the first barrier layer Layer 2041 is consumed preferentially.
  • the taper angle of the second metal layer 204 in the embodiment of the present application is significantly reduced, and the long tip is improved.
  • the coverage of the first passivation layer 30 is better, which avoids the indentation caused by the first passivation layer 30 being too thin at the climbing point. A situation where the pixel electrode layer 40 is lapped and broken occurs.
  • the first passivation layer 30 has better coverage and can effectively block water vapor and ions in the outside air from entering the thin film transistor array layer 20, which enhances the electrical properties and reliability of thin film transistor devices, and reduces static electricity. Risk of explosion injury.
  • the reduction potential of the first barrier layer 2041 is the same as that of the conductive layer 2042
  • the absolute value of the difference between the reduction potentials ranged from 0.15 to 0.59.
  • the absolute value of the difference between the reduction potential of the first barrier layer 2041 and the reduction potential of the conductive layer 2042 is greater than the difference between the reduction potential of the second barrier layer 2043 and the reduction potential of the conductive layer 2042
  • the absolute value of the difference makes the reduction potential of the first barrier layer 2041 much smaller than the reduction potential of the conductive layer 2042, which is conducive to further reducing the reduction of the taper angle of the second metal layer 204, so that the long tip is further improved .
  • the taper angle of the second metal layer 204 is less than 60 degrees, compared with the taper angle of the second metal layer 204 in the prior art greater than 80 degrees, the taper angle can be greatly reduced , so that it meets the requirements.
  • the base substrate 10 is made of a rigid substrate or any suitable insulating material with flexibility, and may be transparent, translucent or opaque; optionally, the base substrate 10 may be glass substrate.
  • the first metal layer 201 is disposed on one side of the base substrate 10, and the first metal layer 201 includes a gate, and the gate may include gold (Au), silver (Ag), copper (Cu), Single or multiple layers of nickel (Ni), platinum (Pt), palladium (Pd), aluminum (Al), molybdenum (Mo), or chromium (Cr), or alloys such as aluminum (Al):neodymium (Nd), molybdenum (Mo): An alloy of tungsten (W) alloy.
  • the gate insulating layer 202 covers the first metal layer 201 and the base substrate 10, and the gate insulating layer 202 may be formed of an insulating inorganic layer such as silicon oxide or silicon nitride, or may be formed of An insulating organic layer is formed.
  • the semiconductor layer 203 is disposed on the side of the gate insulating layer 202 away from the base substrate 10, and the material of the semiconductor layer 203 includes indium gallium zinc oxide (indium gallium zinc oxide, IGZO).
  • the second metal layer 204 is disposed on the side of the semiconductor layer 203 away from the base substrate 10, the second metal layer 204 includes a source electrode and a drain electrode, and the pixel electrode layer 40 passes through the first
  • the via hole 301 is electrically connected to the drain; the first passivation layer 30 may be formed of an inorganic layer such as silicon oxide or silicon nitride, or an organic layer.
  • the electrolytic solution used in the galvanic corrosion process may be a cupric acid solution.
  • other types of electrolytic solutions may also be used, which is not limited in this application.
  • the reduction potential of the first barrier layer 2041 in the prior art is close to the reduction potential of the conductive layer 2042, and the material of the first barrier layer 2041 and the second barrier layer 2043 is the same, That is, the reduction potential of the first barrier layer 2041 is the same as that of the second barrier layer, that is, the reduction potentials of the first barrier layer 2041 and the second barrier layer 2043 are both the same as the conductive
  • the reduction potential of layer 2042 is close.
  • this application needs to realize that the reduction potential of the first barrier layer 2041 is lower than the reduction potential of the conductive layer 2042, and the reduction potential of the first barrier layer 2041 and the reduction potential of the first barrier layer 2041 should be increased as much as possible.
  • FIG. 4 is a schematic diagram of a first cross-sectional structure of the second metal layer provided by the embodiment of the present application.
  • this embodiment achieves the above purpose by lowering the reduction potential of the first barrier layer 2041 while keeping the reduction potential of the conductive layer 2042 unchanged.
  • the first barrier The layer 2041 includes a first host material and a first auxiliary material, and the reduction potential of the first auxiliary material is lower than that of the first host material.
  • the first host material is the material used in the first barrier layer 2041 in the prior art
  • the first auxiliary material is a newly added material in the first host material
  • the first auxiliary material only serves to adjust the overall reduction potential of the first barrier layer 2041 , and does not have much influence on the properties and functions of the first barrier layer 2041 .
  • the first auxiliary material by adding the first auxiliary material in the first host material, since the reduction potential of the first auxiliary material is lower than that of the first host material, the first auxiliary material The overall reduction potential of a blocking layer 2041 is reduced. Since the reduction potential of the first host material is close to the reduction potential of the conductive layer 2042, the adjusted reduction potential of the first barrier layer 2041 is much lower than the reduction potential of the conductive layer 2042.
  • the first barrier layer 2041 is easier to be etched in galvanic corrosion, which is beneficial to reduce the taper angle of the second metal layer 204, simultaneously improves the long tip, and effectively improves the
  • the coverage of the first passivation layer 30 reduces the occurrence of overlapping fractures of the pixel electrode layer 40 caused by the first passivation layer 30 being too thin at the slope and causing indentation; in addition, it enhances the The electrical properties and reliability of thin film transistor devices reduce the risk of electrostatic discharge explosions.
  • the absolute value of the difference between the reduction potential of the first auxiliary material and the reduction potential of the first host material is greater than that between the reduction potential of the first host material and the reduction potential of the conductive layer 2042
  • the absolute value of the difference in this embodiment, the reduction potential of the first host material is positive, the reduction potential of the first auxiliary material is negative, and the first auxiliary material with a negative reduction potential is added to the first host material , can greatly reduce the reduction potential of the first barrier layer 2041 .
  • the material of the conductive layer 2042 is copper
  • the first main body material is a molybdenum-titanium alloy
  • the first auxiliary material is any one of nickel, magnesium, aluminum and zinc; optionally, the The first auxiliary material is nickel.
  • the reduction potential of molybdenum-titanium alloy is 0.29 E0/V
  • that of copper is 0.34 E0/V
  • the reduction potential of nickel is -0.25 E0/V
  • the mass ratio of the molybdenum is greater than 50%, and the mass ratio range of the first auxiliary material is greater than 0 and less than or equal to 49%; optionally, in this implementation In the example, the mass ratio of molybdenum, titanium and nickel is 61%:13%:26%.
  • the material of the second barrier layer 2043 is the same as that of the first main body.
  • the material of the second barrier layer 2043 is molybdenum-titanium alloy, and the molybdenum-titanium alloy in the molybdenum-titanium alloy
  • the mass ratio to titanium is 50%:50%.
  • FIG. 5 is a schematic diagram of a second cross-sectional structure of the second metal layer provided by the embodiment of the present application.
  • the difference from the previous embodiment is that in this embodiment, the reduction potential of the conductive layer 2042 is increased while the reduction potential of the first barrier layer 2041 remains unchanged.
  • the conductive layer 2042 includes a second host material and a second auxiliary material, and the reduction potential of the second auxiliary material is greater than that of the second host material.
  • the second host material is the material used in the conductive layer 2042 in the prior art
  • the second auxiliary material is a newly added material in the second host material
  • the second The auxiliary material only plays the role of adjusting the overall reduction potential of the conductive layer 2042 , and does not have much influence on the properties and functions of the conductive layer 2042 .
  • the conductive layer 2042 by adding the first auxiliary material in the second host material, since the reduction potential of the second auxiliary material is greater than that of the second host material, the conductive layer The overall reduction potential of 2042 increases. And because the reduction potential of the second host material is close to the reduction potential of the first barrier layer 2041, the reduction potential of the first barrier layer 2041 after adjustment is much lower than the reduction potential of the conductive layer 2042, Therefore, compared with the conductive layer 2042, the first barrier layer 2041 is easier to be etched in the galvanic corrosion, which is beneficial to reduce the taper angle of the second metal layer 204, simultaneously improves the long tip, and effectively improves the The coverage of the first passivation layer 30 reduces the occurrence of overlapping fractures of the pixel electrode layer 40 caused by the first passivation layer 30 being too thin at the slope and causing indentation; in addition, The electrical properties and reliability of thin film transistor devices are enhanced, and the risk of electrostatic discharge explosion is reduced.
  • the absolute value of the difference between the reduction potential of the second auxiliary material and the reduction potential of the second host material is greater than the reduction potential of the first barrier layer 2041 and the reduction potential of the second host material
  • the reduction potential of the second host material is positive
  • the reduction potential of the first auxiliary material is positive
  • the reduction potential of the first auxiliary material is much greater than that of the second host material. potential.
  • the material of the first barrier layer 2041 is molybdenum-titanium alloy
  • the second main body material is copper
  • the second auxiliary material is any one of silver, gold, platinum and mercury; optionally,
  • the second auxiliary material is silver.
  • the reduction potential of molybdenum-titanium alloy is 0.29 E0/V
  • the reduction potential of copper is 0.34 E0/V
  • the reduction potential of silver is 1.987 E0/V
  • FIG. 6 is a schematic diagram of a third cross-sectional structure of the second metal layer provided by the embodiment of the present application.
  • the difference from the above two embodiments is that this embodiment combines the above two implementation methods, by reducing the reduction potential of the first barrier layer 2041, and at the same time increasing the conductive layer 2042
  • the first barrier layer 2041 includes a first host material and a first auxiliary material, and the reduction potential of the first auxiliary material is lower than the reduction potential of the first host material , and, the absolute value of the difference between the reduction potential of the first auxiliary material and the reduction potential of the first host material is greater than that between the reduction potential of the first host material and the reduction potential of the conductive layer 2042
  • the absolute value of the difference; the conductive layer 2042 includes a second host material and a second auxiliary material, the reduction potential of the second auxiliary material is greater than the reduction potential of the second host material, and the second auxiliary material
  • the first auxiliary material is added to the first host material, and the second auxiliary material is added to the second host material at the same time, since the reduction potential of the first auxiliary material is lower than that of the The reduction potential of the first host material, the reduction potential of the second auxiliary material is greater than the reduction potential of the second host material, so that the reduction potential of the first barrier layer 2041 decreases, and the reduction potential of the conductive layer 2042 increases and because the reduction potentials of the first host material and the second host material are close, the difference between the reduction potential of the first barrier layer 2041 and the reduction potential of the conductive layer 2042 can be further increased , so that the first barrier layer 2041 is more likely to be etched in galvanic corrosion than the conductive layer 2042, and the taper angle of the second metal layer 204 is further reduced, reducing the first The passivation layer 30 is too thin at the climbing point, which causes the pixel electrode layer 40 to be lapped and broken; in addition, the electrical properties and reliability of the thin film transistor device are enhanced, and the electrostatic discharge
  • the material of the conductive layer 2042 is copper
  • the first main body material is a molybdenum-titanium alloy
  • the first auxiliary material is any one of nickel, magnesium, aluminum and zinc
  • the The first auxiliary material is nickel
  • the first main body material is molybdenum-titanium alloy
  • the second main body material is copper
  • the second auxiliary material is any one of silver, gold, platinum and mercury
  • the second auxiliary material is silver.
  • FIG. 7 is a schematic cross-sectional structure diagram of another array substrate provided by an embodiment of the present application.
  • the first passivation layer 30 in the embodiment of the present application can also adopt an external structure, that is, the first passivation layer 30 is provided with a second via hole 302, and the second via hole 302 is close to the first passivation layer.
  • the second metal layer 204 is disposed and has a certain distance from the second metal layer 204 . Because the taper angle of the second metal layer 204 in the prior art is too large, the slope of the formed second via hole 302 is relatively steep.
  • the pixel electrode layer 40 is formed in the second via hole 302
  • the taper angle of the second metal layer 204 is relatively small, so that the slope of the formed second via hole 302 is relatively flat, so that the pixel electrode can be lowered.
  • the layer 40 is at the risk of climbing and disconnection at the second via hole 302 .
  • the array substrate further includes an organic planar layer 50 and a second passivation layer 60, the organic planar layer 50 is disposed on a side of the first passivation layer 30 away from the base substrate 10; the The second passivation layer 60 is disposed on the side of the organic planar layer 50 away from the base substrate 10; the pixel electrode layer 40 is located on the side of the second passivation layer 60 away from the base substrate 10 , the first via hole 301 penetrates through the second passivation layer 60 , the organic planar layer 50 and the first passivation layer 30 .
  • the material of the organic planar layer 50 may be organosiloxane resin, and the material of the second passivation layer 60 may be the same as that of the first passivation layer 30 .
  • the embodiment of the present application also provides a display panel, the display panel includes an opposite substrate, a liquid crystal layer, and the array substrate in the above embodiment, the opposite substrate is arranged at a distance from the array substrate, and the liquid crystal layer is arranged between the opposite substrate and the array substrate.
  • FIG. 8 is a flowchart of a method for manufacturing an array substrate provided in an embodiment of the present application.
  • the embodiment of the present application also provides a method for preparing an array substrate, including the following steps:
  • Step S10 providing a base substrate 10
  • Step S20 forming a thin film transistor array layer 20 on one side of the base substrate 10, the thin film transistor array layer 20 including a first metal layer 201, a gate insulating layer 202, a semiconductor layer 203 and a second metal layer 204;
  • Step S30 forming a first passivation layer 30 covering the second metal layer 204;
  • Step S40 forming a first via hole 301 penetrating through the first passivation layer 30;
  • Step S50 forming a pixel electrode layer 40 on the side of the first passivation layer 30 away from the base substrate 10, the pixel electrode layer 40 passes through the first via hole 301 and the second metal layer 204 electrical connection.
  • the thin film transistor array layer 20 includes a plurality of thin film transistors, and the thin film transistors are bottom-gate thin film transistors as an example for illustration and description, and the step S20 includes:
  • Step S201 forming the first metal layer 201 on the base substrate 10;
  • Step S202 forming a gate insulating layer 202 covering the first metal layer 201;
  • Step S203 forming the semiconductor layer 203 on the gate insulating layer 202.
  • Step S204 forming the second metal layer 204 on the semiconductor layer 203 .
  • step S204 includes:
  • Step S2041 sequentially coating the second barrier layer material, the conductive layer material and the first barrier layer material on the semiconductor layer 203;
  • Step S2042 Exposing, developing and etching the second barrier layer material, the conductive layer material and the first barrier layer material to form the second metal layer 204 .
  • the first barrier layer material includes a first host material and a first auxiliary material
  • the conductive layer material is copper
  • the second barrier layer material Molybdenum-titanium alloy
  • the first main body material is molybdenum-titanium alloy
  • the first auxiliary material is any one of nickel, magnesium, aluminum and zinc; optionally, the first auxiliary material is nickel.
  • the conductive layer material includes a second main body material and a second auxiliary material, both the first barrier layer material and the second barrier layer material are molybdenum-titanium alloys, and the second main body
  • the material is copper
  • the second auxiliary material is any one of silver, gold, platinum and mercury; optionally, the second auxiliary material is silver.
  • the first barrier layer material includes a first host material and a first auxiliary material
  • the conductive layer material includes a second host material and a second auxiliary material
  • the first host material and the The materials of the second barrier layer are all molybdenum-titanium alloys
  • the first auxiliary material is any one of nickel, magnesium, aluminum and zinc; optionally, the first auxiliary material is nickel; the second auxiliary material
  • the material is any one of silver, gold, platinum and mercury; optionally, the second auxiliary material is silver.
  • a wet etching method may be used, and the etching solution may be copper acid solution.
  • the second metal layer includes a stacked second barrier layer, a conductive layer and a first barrier layer, and by setting the reduction potential of the first barrier layer to be lower than that of the conductive
  • the reduction potential of the layer makes the first barrier layer easier to be etched in galvanic corrosion than the conductive layer, which is beneficial to reduce the taper angle of the second metal layer, simultaneously improves the long tip, and effectively improves the first passivation layer.
  • the coverage of the first passivation layer reduces the occurrence of overlapping fractures of the pixel electrode layer caused by the sinking of the first passivation layer at the climbing point; in addition, it enhances the electrical properties and reliability of the thin film transistor device, and reduces the Risk of injury from electrostatic discharge.

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Abstract

本申请公开了一种阵列基板及显示面板，阵列基板包括衬底基板、第一金属层、栅极绝缘层、半导体层和第二金属层；第二金属层包括第一阻挡层、导电层和第二阻挡层，本申请通过将第一阻挡层的还原电位小于导电层的还原电位，使得第一阻挡层相较于导电层在电偶腐蚀中更易被刻蚀，有利于降低第二金属层的taper角，改善了长tip。

Description

阵列基板及显示面板 技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板及显示面板。
 背景技术
对于TFT（Thin Film Transistor，薄膜晶体管）阵列基板，薄膜晶体管中的第二金属层通常包括沿靠近衬底基板方向依次层叠设置的第一阻挡层、导电层和第二阻挡层，由于第一阻挡层和导电层的还原电位非常接近，导致第一阻挡层与导电层的侧向刻蚀几乎是同时进行的，从而导致第二金属层的taper角（锥角）较大，几乎成90°，并且伴有长tip（尖端），造成覆盖在第二金属层上的钝化层在爬坡处过薄而出现内陷，从而导致设置于钝化层上的像素电极层搭接断裂。
 技术问题
本申请实施例提供一种阵列基板及显示面板，以解决现有的阵列基板及显示面板的第二金属层taper角过大，并且伴有长tip，造成第一钝化层在爬坡处过薄而出现内陷，从而导致像素电极层搭接断裂的技术问题。
 技术解决方案
为解决上述问题，本申请提供的技术方案如下：
本申请提供一种阵列基板，包括：
衬底基板；以及
薄膜晶体管阵列层，设置于所述衬底基板一侧，所述薄膜晶体管阵列层包括第一金属层、栅极绝缘层、半导体层和第二金属层；
其中，所述第二金属层包括沿靠近所述衬底基板方向依次层叠设置的第一阻挡层、导电层和第二阻挡层，所述第二阻挡层的材料为钼钛合金，所述第一阻挡层的还原电位小于所述导电层的还原电位，所述第一阻挡层的还原电位与所述导电层的还原电位之间的差值绝对值的范围为0.15~0.59。
根据本申请提供的阵列基板，所述第一阻挡层的还原电位与所述导电层的还原电位之间的差值绝对值大于所述第二阻挡层的还原电位与所述导电层的还原电位之间的差值绝对值。
根据本申请提供的阵列基板，所述第一阻挡层包括第一主体材料和第一辅助材料，所述第一辅助材料的还原电位小于所述第一主体材料的还原电位。
根据本申请提供的阵列基板，所述第一辅助材料的还原电位与所述第一主体材料的还原电位之间的差值绝对值大于所述第一主体材料的还原电位与所述导电层的还原电位之间的差值绝对值；所述第一主体材料的还原电位为正，所述第一辅助材料的还原电位为负。
本申请提供一种阵列基板，包括：
衬底基板；以及
薄膜晶体管阵列层，设置于所述衬底基板一侧，所述薄膜晶体管阵列层包括第一金属层、栅极绝缘层、半导体层和第二金属层；
其中，所述第二金属层包括沿靠近所述衬底基板方向依次层叠设置的第一阻挡层、导电层和第二阻挡层，所述第一阻挡层的还原电位小于所述导电层的还原电位。
根据本申请提供的阵列基板，所述第一阻挡层的还原电位与所述导电层的还原电位之间的差值绝对值的范围为0.15~0.59。
根据本申请提供的阵列基板，所述第一阻挡层的还原电位与所述导电层的还原电位之间的差值绝对值大于所述第二阻挡层的还原电位与所述导电层的还原电位之间的差值绝对值。
根据本申请提供的阵列基板，所述第一阻挡层包括第一主体材料和第一辅助材料，所述第一辅助材料的还原电位小于所述第一主体材料的还原电位。
根据本申请提供的阵列基板，所述第一辅助材料的还原电位与所述第一主体材料的还原电位之间的差值绝对值大于所述第一主体材料的还原电位与所述导电层的还原电位之间的差值绝对值；所述第一主体材料的还原电位为正，所述第一辅助材料的还原电位为负。
根据本申请提供的阵列基板，所述导电层的材料为铜，所述第一主体材料为钼钛合金，所述第一辅助材料为镍、镁、铝和锌中的任意一种。
根据本申请提供的阵列基板，在所述第一阻挡层中，所述钼的质量比大于50%，所述第一辅助材料的质量比范围为大于0且小于或等于49%。
根据本申请提供的阵列基板，所述导电层包括第二主体材料和第二辅助材料，所述第二辅助材料的还原电位大于所述第二主体材料的还原电位。
根据本申请提供的阵列基板，所述第二辅助材料的还原电位与所述第二主体材料的还原电位之间的差值绝对值大于所述第一阻挡层的还原电位与所述第二主体材料的还原电位之间的差值绝对值；所述第二主体材料的还原电位为正，所述第二辅助材料的还原电位为正。
根据本申请提供的阵列基板，所述第一阻挡层的材料为钼钛合金，所述第二主体材料为铜，所述第二辅助材料为银、金、铂和汞中的任意一种。
根据本申请提供的阵列基板，所述第二阻挡层的材料为钼钛合金。
根据本申请提供的阵列基板，所述导电层包括第二主体材料和第二辅助材料，所述第二辅助材料的还原电位大于所述第二主体材料的还原电位；且，所述第二辅助材料的还原电位与所述第二主体材料的还原电位之间的差值绝对值大于所述第一主体材料的还原电位与所述第二主体材料的还原电位之间的差值绝对值。
根据本申请提供的阵列基板，所述第一金属层、所述栅极绝缘层、所述半导体层和所述第二金属层沿远离所述衬底基板方向依次层叠设置；或者，所述半导体层、所述栅极绝缘层、所述第一金属层和所述第二金属层沿远离所述衬底基板方向依次层叠设置。
根据本申请提供的阵列基板，所述阵列基板还包括：
第一钝化层，覆盖所述第二金属层；以及
像素电极层，设置于所述第一钝化层远离所述衬底基板的一侧，所述像素电极层通过贯穿所述第一钝化层的第一过孔与所述第二金属层电连接。
根据本申请提供的阵列基板，所述阵列基板还包括：
有机平坦层，设置于所述第一钝化层远离所述衬底基板的一侧；以及
第二钝化层，设置于所述有机平坦层远离所述衬底基板的一侧；
其中，所述像素电极层位于所述第二钝化层远离所述衬底基板的一侧，所述第一过孔贯穿所述第二钝化层、所述有机平坦层和所述第一钝化层。
本申请提供一种显示面板，包括对置基板、液晶层和上述阵列基板，所述对置基板与所述阵列基板相对间隔设置，所述液晶层设置于所述对置基板与所述阵列基板之间；
所述阵列基板包括：
衬底基板；以及
薄膜晶体管阵列层，设置于所述衬底基板一侧，所述薄膜晶体管阵列层包括第一金属层、栅极绝缘层、半导体层和第二金属层；
其中，所述第二金属层包括沿靠近所述衬底基板方向依次层叠设置的第一阻挡层、导电层和第二阻挡层，所述第一阻挡层的还原电位小于所述导电层的还原电位。
 有益效果
本发明的有益效果为：本申请提供的阵列基板及显示面板，第二金属层包括层叠设置的第二阻挡层、导电层和第一阻挡层，通过将第一阻挡层的还原电位设置为小于导电层的还原电位，使得第一阻挡层相较于导电层在电偶腐蚀中更易被刻蚀，有利于降低第二金属层的taper角，同步改善了长tip，有效提高了第一钝化层的覆盖性，减少了第一钝化层在爬坡处过薄而出现内陷而导致的像素电极层搭接断裂的情况发生；此外，增强了薄膜晶体管器件的电性及信赖性，降低了静电释放炸伤风险。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是现有技术中的阵列基板的截面结构示意图；
图2是本申请实施例提供的一种阵列基板的截面结构示意图；
图3A是本申请实施例提供的阵列基板中的第一种薄膜晶体管阵列层的截面结构示意图；
图3B是本申请实施例提供的阵列基板中的第二种薄膜晶体管阵列层的截面结构示意图；
图4是本申请实施例提供的第二金属层的第一种截面结构示意图；
图5是本申请实施例提供的第二金属层的第二种截面结构示意图；
图6是本申请实施例提供的第二金属层的第三种截面结构示意图；
图7是本申请实施例提供的另一种阵列基板的截面结构示意图；
图8是本申请实施例提供的一种阵列基板的制备方法的流程图。
附图标记说明：
1a、尖端；1b、断裂位置；
10、衬底基板；20、薄膜晶体管阵列层；201、第一金属层；202、栅极绝缘层；203、半导体层；204、第二金属层；205、源漏极绝缘层；30、第一钝化层；40、像素电极层；50、有机平坦层；60、第二钝化层；
2041、第一阻挡层；2042、导电层；2043、第二阻挡层；
301、第一过孔；302、第二过孔。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。此外，应当理解的是，此处所描述的具体实施方式仅用于说明和解释本申请，并不用于限制本申请。在本申请中，在未作相反说明的情况下，使用的方位词如“上”和“下”通常是指装置实际使用或工作状态下的上和下，具体为附图中的图面方向；而“内”和“外”则是针对装置的轮廓而言的。
请参阅图1，图1为现有技术中的阵列基板的截面结构示意图，薄膜晶体管包括衬底基板10和薄膜晶体管阵列层20，所述薄膜晶体管阵列层20包括第一金属层201、栅极绝缘层202、半导体层（图中未示出）和第二金属层204，所述第二金属层204上远离所述衬底基板10的一侧设置有第一钝化层30，所述第一钝化层30远离所述衬底基板10的一侧设置有像素电极层40。所述第二金属层204通常由第一阻挡层2041/导电层2042/第二阻挡层2043三层金属组成。
需要说明的是，在电解质溶液中，当两种金属或者合金接触处于导通状态时，电位较负的金属腐蚀被加速腐蚀，电位较正的金属被保护不易被腐蚀，由于所述第一阻挡层2041和所述导电层2042之间的还原电位非常接近，所述第一阻挡层2041和所述导电层2042的侧向刻蚀几乎是同时进行的，导致所述第二金属层204的taper角（锥角）较大，几乎成90°，并且伴有长tip（尖端）1a，造成所述第一钝化层30在爬坡处过薄而出现内陷，从而导致所述像素电极层40搭接断裂，如图1中的断裂位置1b。
有鉴于此，本申请实施例提供一种阵列基板，请参阅图2和图3A~图3B，图2是本申请实施例提供的一种阵列基板的截面结构示意图，图3A是本申请实施例提供的阵列基板中的薄膜晶体管阵列层的截面结构示意图，图3B是本申请实施例提供的阵列基板中的第二种薄膜晶体管阵列层的截面结构示意图。
所述阵列基板包括衬底基板10和薄膜晶体管阵列层20，所述薄膜晶体管阵列层20设置于所述衬底基板10一侧，所述薄膜晶体管阵列层20包括多个薄膜晶体管，所述薄膜晶体管阵列层20包括第一金属层201、栅极绝缘层202、半导体层203和第二金属层204。如图3A所示，所述薄膜晶体管可以为底栅型薄膜晶体管，具体的，所述第一金属层201、所述栅极绝缘层202、所述半导体层203和所述第二金属层204沿远离所述衬底基板10方向依次层叠设置。如图3B所示，所述薄膜晶体管也可以为顶栅型薄膜晶体管，具体的，所述半导体层203、所述栅极绝缘层202、所述第一金属层201和第二金属层204沿远离所述衬底基板10方向依次层叠设置，所述薄膜晶体管阵列层20还包括源漏极绝缘层205，所述源漏极绝缘层205覆盖所述第一金属层201和所述栅极绝缘层202，所述源漏极绝缘层205包括源极和漏极，所述源极通过贯穿所述源漏极绝缘层205的过孔与所述半导体层203电连接，所述漏极通过贯穿所述源漏极绝缘层205的另一过孔与所述半导体层203电连接。
进一步的，所述阵列基板还包括第一钝化层30和像素电极层40，所述第一钝化层30覆盖所述第二金属层204。所述像素电极层40设置于所述第一钝化层30远离所述衬底基板10的一侧，所述像素电极层40通过贯穿所述第一钝化层30的第一过孔301与所述第二金属层204电连接。
所述第二金属层204采用三层金属结构，具体的，所述第二金属层204包括层叠设置的第二阻挡层2043、导电层2042和第一阻挡层2041，可以理解的是，本申请实施例通过将所述第一阻挡层2041的还原电位设置为小于所述导电层2042的还原电位，由于当两种金属或者合金接触处于导通状态时会产生贾尼凡腐蚀，即，电位较负的金属被加速腐蚀，电位较正的金属被保护而不易被腐蚀，使得所述第一阻挡层2041相较于所述导电层2042在电偶腐蚀中更易被刻蚀，所述第一阻挡层2041被优先消耗。相较于现有技术，本申请实施例中的所述第二金属层204的taper角明显降低，且长tip得到改善。在后续制备所述第一钝化层30时，所述第一钝化层30覆盖较佳，避免了所述第一钝化层30在爬坡处过薄而出现内陷而导致的所述像素电极层40搭接断裂的情况发生。与此同时，所述第一钝化层30覆盖性较好能够有效阻隔外界空气中的水汽及离子进入所述薄膜晶体管阵列层20，增强了薄膜晶体管器件的电性及信赖性，降低了静电释放炸伤风险。
具体的，为了保证所述第一阻挡层2041相较于所述导电层2042被刻蚀的更快，在本申请实施例中，所述第一阻挡层2041的还原电位与所述导电层2042的还原电位之间的差值绝对值的范围为0.15~0.59。
进一步的，所述第一阻挡层2041的还原电位与所述导电层2042的还原电位之间的差值绝对值大于所述第二阻挡层2043的还原电位与导电层2042的还原电位之间的差值绝对值，使得所述第一阻挡层2041的还原电位远远小于所述导电层2042的还原电位，有利于进一步降低所述第二金属层204的taper角降低，使得长tip得到进一步改善。
在本申请实施例中，所述第二金属层204的taper角小于60度，相较于现有技术中的所述第二金属层204的taper角大于80度，能够实现taper角大幅度降低，使其满足要求。
具体的，所述衬底基板10由硬质基板或具有柔性的任意合适的绝缘材料制成，可以是透明的、半透明的或不透明的；可选的，所述衬底基板10可以为玻璃基板。所述第一金属层201设置于所述衬底基板10一侧，所述第一金属层201包括栅极，所述栅极可包括金(Au)、银(Ag)、铜(Cu)、镍(Ni)、铂(Pt)、钯(Pd)、铝(Al)、钼(Mo)或铬(Cr)的单层或多层，或者诸如铝(Al):钕(Nd)合金、钼(Mo):钨(W)合金的合金。所述栅极绝缘层202覆于所述第一金属层201和所述衬底基板10上，所述栅极绝缘层202可以由氧化硅或氮化硅等的绝缘无机层形成，也可以由绝缘有机层形成。所述半导体层203设置于所述栅极绝缘层202远离所述衬底基板10的一侧，所述半导体层203的材料包括铟镓锌氧化物（indium gallium zinc oxide，IGZO）。所述第二金属层204设置于所述半导体层203远离所述衬底基板10的一侧，所述第二金属层204包括源极和漏极，所述像素电极层40通过所述第一过孔301与所述漏极电连接；所述第一钝化层30可以由氧化硅或氮化硅等无机层形成，也可由有机层形成。
可选的，在本申请实施例中，电偶腐蚀过程中采用的电解质溶液可以为铜酸溶液，当然的，也可选用其它类型的电解质溶液，本申请对此不作任何限定。
需要说明的是，现有技术中的所述第一阻挡层2041的还原电位与所述导电层2042的还原电位接近，所述第一阻挡层2041与所述第二阻挡层2043的材料相同，即，所述第一阻挡层2041的还原电位与所述第二阻挡的还原电位相同，也就是说，所述第一阻挡层2041和所述第二阻挡层2043的还原电位均与所述导电层2042的还原电位接近。
为了解决本申请存在的技术问题，本申请需要实现所述第一阻挡层2041的还原电位小于所述导电层2042的还原电位，且需尽量增大所述第一阻挡层2041的还原电位与所述导电层2042的还原电位之间的差值绝对值。
有鉴于此，本申请提出多种类型的实施例来达到上述目的，具体将一一阐述如下：
请参阅图4，图4是本申请实施例提供的第二金属层的第一种截面结构示意图。在一种实施例中，本实施例通过降低所述第一阻挡层2041的还原电位，而所述导电层2042的还原电位保持不变的方式来达到上述目的，具体的，所述第一阻挡层2041包括第一主体材料和第一辅助材料，所述第一辅助材料的还原电位小于所述第一主体材料的还原电位。
需要说明的是，所述第一主体材料即为现有技术中的所述第一阻挡层2041所采用的材料，所述第一辅助材料为在所述第一主体材料内新添加的材料，所述第一辅助材料仅起到调节所述第一阻挡层2041的整体还原电位的作用，对所述第一阻挡层2041的性质和作用并无太多影响。
可以理解的是，本实施例通过在所述第一主体材料内添加所述第一辅助材料，由于所述第一辅助材料的还原电位小于所述第一主体材料的还原电位，使得所述第一阻挡层2041的整体还原电位降低。又由于所述第一主体材料的还原电位和所述导电层2042的还原电位接近，则调整之后的所述第一阻挡层2041的还原电位远远小于所述导电层2042的还原电位，故，所述第一阻挡层2041相较于所述导电层2042在电偶腐蚀中更易被刻蚀，有利于降低所述第二金属层204的taper角，同步改善了长tip，有效提高了所述第一钝化层30的覆盖性，减少了所述第一钝化层30在爬坡处过薄而出现内陷而导致的所述像素电极层40搭接断裂的情况发生；此外，增强了薄膜晶体管器件的电性及信赖性，降低了静电释放炸伤风险。
进一步的，所述第一辅助材料的还原电位与所述第一主体材料的还原电位之间的差值绝对值大于所述第一主体材料的还原电位与所述导电层2042的还原电位之间的差值绝对值。在本实施例中，所述第一主体材料的还原电位为正，所述第一辅助材料的还原电位为负，在所述第一主体材料内添加还原电位为负的所述第一辅助材料，能够大幅度降低所述第一阻挡层2041的还原电位。
具体的，所述导电层2042的材料为铜，所述第一主体材料为钼钛合金，所述第一辅助材料为镍、镁、铝和锌中的任意一种；可选的，所述第一辅助材料为镍。一般的，钼钛合金的还原电位为0.29 E0/V，铜的还原电位为0.34 E0/V，镍的还原电位为-0.25 E0/V，由此可见，在添加金属元素镍之后，所述第一阻挡层2041的还原电位得到大幅度降低。
进一步的，在所述第一阻挡层2041中，所述钼的质量比大于50%，所述第一辅助材料的质量比范围为大于0且小于或等于49%；可选的，在本实施例中，钼、钛、镍的质量比为61%：13%：26%。
具体的，所述第二阻挡层2043的材料与所述第一主体材料相同，在本申请实施例中，所述第二阻挡层2043的材料为钼钛合金，所述钼钛合金中的钼与钛的质量比为50%：50%。
请参阅图5，图5是本申请实施例提供的第二金属层的第二种截面结构示意图。在另一种实施例中，与上一实施例的不同之处在于，本实施例通过增大所述导电层2042的还原电位，而所述第一阻挡层2041的还原电位保持不变的方式来达到上述目的，具体的，所述导电层2042包括第二主体材料和第二辅助材料，所述第二辅助材料的还原电位大于所述第二主体材料的还原电位。
同样的，所述第二主体材料即为现有技术中的所述导电层2042所采用的材料，所述第二辅助材料为在所述第二主体材料内新添加的材料，所述第二辅助材料仅起到调节所述导电层2042的整体还原电位的作用，对所述导电层2042的性质和作用并无太多影响。
同理的，本实施例通过在所述第二主体材料内添加所述第一辅助材料，由于所述第二辅助材料的还原电位大于所述第二主体材料的还原电位，使得所述导电层2042的整体还原电位增大。又由于所述第二主体材料的还原电位和所述第一阻挡层2041的还原电位接近，则调整之后的所述第一阻挡层2041的还原电位远远小于所述导电层2042的还原电位，故，所述第一阻挡层2041相较于所述导电层2042在电偶腐蚀中更易被刻蚀，有利于降低所述第二金属层204的taper角，同步改善了长tip，有效提高了所述第一钝化层30的覆盖性，减少了所述第一钝化层30在爬坡处过薄而出现内陷而导致的所述像素电极层40搭接断裂的情况发生；此外，增强了薄膜晶体管器件的电性及信赖性，降低了静电释放炸伤风险。
进一步的，所述第二辅助材料的还原电位与所述第二主体材料的还原电位之间的差值绝对值大于所述第一阻挡层2041的还原电位与所述第二主体材料的还原电位之间的差值绝对值。在本实施例中，所述第二主体材料的还原电位为正，所述第一辅助材料的还原电位为正，所述第一辅助材料的还原电位远远大于所述第二主体材料的还原电位。
具体的，所述第一阻挡层2041的材料为钼钛合金，所述第二主体材料为铜，所述第二辅助材料为银、金、铂和汞中的任意一种；可选的，所述第二辅助材料为银。一般的，钼钛合金的还原电位为0.29 E0/V，铜的还原电位为0.34 E0/V，银的还原电位为1.987 E0/V，由此可见，在添加金属元素银之后，所述导电层2042的还原电位得到大幅度提升。
请参阅图6，图6是本申请实施例提供的第二金属层的第三种截面结构示意图。在又一种实施例中，与上述两实施例的不同之处在于，本实施例结合上述两种实施方式，通过降低所述第一阻挡层2041的还原电位，同时增大所述导电层2042的还原电位的方式来达到上述目的，具体的，所述第一阻挡层2041包括第一主体材料和第一辅助材料，所述第一辅助材料的还原电位小于所述第一主体材料的还原电位，且，所述第一辅助材料的还原电位与所述第一主体材料的还原电位之间的差值绝对值大于所述第一主体材料的还原电位与所述导电层2042的还原电位之间的差值绝对值；所述导电层2042包括第二主体材料和第二辅助材料，所述第二辅助材料的还原电位大于所述第二主体材料的还原电位，且，所述第二辅助材料的还原电位与所述第二主体材料的还原电位之间的差值绝对值大于所述第一主体材料的还原电位与所述第二主体材料的还原电位之间的差值绝对值。
同理的，在所述第一主体材料中添加所述第一辅助材料，同时在所述第二主体材料中添加所述第二辅助材料，由于所述第一辅助材料的还原电位小于所述第一主体材料的还原电位，所述第二辅助材料的还原电位大于所述第二主体材料的还原电位，使得所述第一阻挡层2041的还原电位降低，所述导电层2042的还原电位增大；又由于所述第一主体材料和所述第二主体材料的还原电位接近，因此，所述第一阻挡层2041还原电位与所述导电层2042的还原电位之间的差值可以进一步增大，从而进一步使得所述第一阻挡层2041相较于所述导电层2042在电偶腐蚀中更易被刻蚀，所述第二金属层204的taper角得到进一步降低，减少了所述第一钝化层30在爬坡处过薄而出现内陷而导致的所述像素电极层40搭接断裂的情况发生；此外，增强了所述薄膜晶体管器件的电性及信赖性，降低了静电释放炸伤风险。
具体的，所述导电层2042的材料为铜，所述第一主体材料为钼钛合金，所述第一辅助材料为镍、镁、铝和锌中的任意一种；可选的，所述第一辅助材料为镍；所述第一主体材料为钼钛合金，所述第二主体材料为铜，所述第二辅助材料为银、金、铂和汞中的任意一种；可选的，所述第二辅助材料为银。
请参阅图7，图7是本申请实施例提供的另一种阵列基板的截面结构示意图。本申请实施例中的所述第一钝化层30还可采用外挂式结构，即，所述第一钝化层30设置有第二过孔302，所述第二过孔302靠近所述第二金属层204设置且与所述第二金属层204之间存在一定距离。由于现有技术中的所述第二金属层204的taper角过大，导致形成的所述第二过孔302的坡度较为陡峭，因此，所述像素电极层40在所述第二过孔302处易发生爬坡断线；而本申请实施例中的所述第二金属层204的taper角较小，使得形成的所述第二过孔302的坡度较为平坦，从而能够降低所述像素电极层40在所述第二过孔302处发生爬坡断线的情况发生的风险。
进一步的，所述阵列基板还包括有机平坦层50和第二钝化层60，所述有机平坦层50设置于所述第一钝化层30远离所述衬底基板10的一侧；所述第二钝化层60设置于所述有机平坦层50远离所述衬底基板10的一侧；所述像素电极层40位于所述第二钝化层60远离所述衬底基板10的一侧，所述第一过孔301贯穿所述第二钝化层60、所述有机平坦层50和所述第一钝化层30。
具体的，所述有机平坦层50的材料可以为有机硅氧烷树脂，所述第二钝化层60的材料可以与所述第一钝化层30的材料相同。
本申请实施例还提供一种显示面板，所述显示面板包括对置基板、液晶层和上述实施例中的阵列基板，所述对置基板与所述阵列基板相对间隔设置，所述液晶层设置于所述对置基板与所述阵列基板之间。
请参阅图8，图8是本申请实施例提供的一种阵列基板的制备方法的流程图。本申请实施例还提供一种阵列基板的制备方法，包括以下步骤：
步骤S10：提供一衬底基板10；
步骤S20：在所述衬底基板10一侧形成薄膜晶体管阵列层20，所述薄膜晶体管阵列层20包括第一金属层201、栅极绝缘层202、半导体层203和第二金属层204；
步骤S30：形成覆于所述第二金属层204上的第一钝化层30；
步骤S40：形成贯穿所述第一钝化层30的第一过孔301；以及
步骤S50：在所述第一钝化层30远离所述衬底基板10的一侧形成像素电极层40，所述像素电极层40通过所述第一过孔301与所述第二金属层204电连接。
具体的，所述薄膜晶体管阵列层20包括多个薄膜晶体管，以所述薄膜晶体管为底栅型薄膜晶体管为例进行阐述说明，所述步骤S20包括：
步骤S201：在所述衬底基板10上形成所述第一金属层201；
步骤S202：形成覆于所述第一金属层201上的栅极绝缘层202；
步骤S203：在所述栅极绝缘层202上形成所述半导体层203；以及
步骤S204：在所述半导体层203上形成所述第二金属层204。
进一步的，所述步骤S204包括：
步骤S2041：在所述半导体层203上依次涂布第二阻挡层材料、导电层材料和第一阻挡层材料；以及
步骤S2042：对所述第二阻挡层材料、所述导电层材料和所述第一阻挡层材料进行曝光显影刻蚀，以形成所述第二金属层204。
具体的，在所述步骤S2041中，在一种实施例中，所述第一阻挡层材料包括第一主体材料和第一辅助材料，所述导电层材料为铜，所述第二阻挡层材料为钼钛合金，所述第一主体材料为钼钛合金，所述第一辅助材料为镍、镁、铝和锌中的任意一种；可选的，所述第一辅助材料为镍。
在另一种实施例中，所述导电层材料包括第二主体材料和第二辅助材料，所述第一阻挡层材料和所述第二阻挡层材料均为钼钛合金，所述第二主体材料为铜，所述第二辅助材料为银、金、铂和汞中的任意一种；可选的，所述第二辅助材料为银。
在又一种实施例中，所述第一阻挡层材料包括第一主体材料和第一辅助材料，所述导电层材料包括第二主体材料和第二辅助材料，所述第一主体材料和所述第二阻挡层材料均为钼钛合金，所述第一辅助材料为镍、镁、铝和锌中的任意一种；可选的，所述第一辅助材料为镍；所述第二辅助材料为银、金、铂和汞中的任意一种；可选的，所述第二辅助材料为银。
具体的，在所述步骤S2042中，可采用湿法刻蚀方法，刻蚀液可选用铜酸溶液。
有益效果为：本申请实施例提供的阵列基板及显示面板，第二金属层包括层叠设置的第二阻挡层、导电层和第一阻挡层，通过将第一阻挡层的还原电位设置为小于导电层的还原电位，使得第一阻挡层相较于导电层在电偶腐蚀中更易被刻蚀，有利于降低第二金属层的taper角，同步改善了长tip，有效提高了第一钝化层的覆盖性，减少了第一钝化层在爬坡处过薄而出现内陷而导致的像素电极层搭接断裂的情况发生；此外，增强了薄膜晶体管器件的电性及信赖性，降低了静电释放炸伤风险。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种阵列基板，包括：
    衬底基板；以及
    薄膜晶体管阵列层，设置于所述衬底基板一侧，所述薄膜晶体管阵列层包括第一金属层、栅极绝缘层、半导体层和第二金属层；
    其中，所述第二金属层包括沿靠近所述衬底基板方向依次层叠设置的第一阻挡层、导电层和第二阻挡层，所述第二阻挡层的材料为钼钛合金，所述第一阻挡层的还原电位小于所述导电层的还原电位，所述第一阻挡层的还原电位与所述导电层的还原电位之间的差值绝对值的范围为0.15~0.59。
  2. 根据权利要求1所述的阵列基板，其中，所述第一阻挡层的还原电位与所述导电层的还原电位之间的差值绝对值大于所述第二阻挡层的还原电位与所述导电层的还原电位之间的差值绝对值。
  3. 根据权利要求2所述的阵列基板，其中，所述第一阻挡层包括第一主体材料和第一辅助材料，所述第一辅助材料的还原电位小于所述第一主体材料的还原电位。
  4. 根据权利要求3所述的阵列基板，其中，所述第一辅助材料的还原电位与所述第一主体材料的还原电位之间的差值绝对值大于所述第一主体材料的还原电位与所述导电层的还原电位之间的差值绝对值；所述第一主体材料的还原电位为正，所述第一辅助材料的还原电位为负。
  5. 一种阵列基板，包括：
    衬底基板；以及
    薄膜晶体管阵列层，设置于所述衬底基板一侧，所述薄膜晶体管阵列层包括第一金属层、栅极绝缘层、半导体层和第二金属层；
    其中，所述第二金属层包括沿靠近所述衬底基板方向依次层叠设置的第一阻挡层、导电层和第二阻挡层，所述第一阻挡层的还原电位小于所述导电层的还原电位。
  6. 根据权利要求5所述的阵列基板，其中，所述第一阻挡层的还原电位与所述导电层的还原电位之间的差值绝对值的范围为0.15~0.59。
  7. 根据权利要求6所述的阵列基板，其中，所述第一阻挡层的还原电位与所述导电层的还原电位之间的差值绝对值大于所述第二阻挡层的还原电位与所述导电层的还原电位之间的差值绝对值。
  8. 根据权利要求7所述的阵列基板，其中，所述第一阻挡层包括第一主体材料和第一辅助材料，所述第一辅助材料的还原电位小于所述第一主体材料的还原电位。
  9. 根据权利要求8所述的阵列基板，其中，所述第一辅助材料的还原电位与所述第一主体材料的还原电位之间的差值绝对值大于所述第一主体材料的还原电位与所述导电层的还原电位之间的差值绝对值；所述第一主体材料的还原电位为正，所述第一辅助材料的还原电位为负。
  10. 根据权利要求9所述的阵列基板，其中，所述导电层的材料为铜，所述第一主体材料为钼钛合金，所述第一辅助材料为镍、镁、铝和锌中的任意一种。
  11. 根据权利要求10所述的阵列基板，其中，在所述第一阻挡层中，所述钼的质量比大于50%，所述第一辅助材料的质量比范围为大于0且小于或等于49%。
  12. 根据权利要求11所述的阵列基板，其中，所述导电层包括第二主体材料和第二辅助材料，所述第二辅助材料的还原电位大于所述第二主体材料的还原电位。
  13. 根据权利要求12所述的阵列基板，其中，所述第二辅助材料的还原电位与所述第二主体材料的还原电位之间的差值绝对值大于所述第一阻挡层的还原电位与所述第二主体材料的还原电位之间的差值绝对值；所述第二主体材料的还原电位为正，所述第二辅助材料的还原电位为正。
  14. 根据权利要求13所述的阵列基板，其中，所述第一阻挡层的材料为钼钛合金，所述第二主体材料为铜，所述第二辅助材料为银、金、铂和汞中的任意一种。
  15. 根据权利要求5所述的阵列基板，其中，所述第二阻挡层的材料为钼钛合金。
  16. 根据权利要求6所述的阵列基板，其中，所述导电层包括第二主体材料和第二辅助材料，所述第二辅助材料的还原电位大于所述第二主体材料的还原电位；且，所述第二辅助材料的还原电位与所述第二主体材料的还原电位之间的差值绝对值大于所述第一主体材料的还原电位与所述第二主体材料的还原电位之间的差值绝对值。
  17. 根据权利要求5所述的阵列基板，其中，所述第一金属层、所述栅极绝缘层、所述半导体层和所述第二金属层沿远离所述衬底基板方向依次层叠设置；或者，所述半导体层、所述栅极绝缘层、所述第一金属层和所述第二金属层沿远离所述衬底基板方向依次层叠设置。
  18. 根据权利要求5所述的阵列基板，其中，所述阵列基板还包括：
    第一钝化层，覆盖所述第二金属层；以及
    像素电极层，设置于所述第一钝化层远离所述衬底基板的一侧，所述像素电极层通过贯穿所述第一钝化层的第一过孔与所述第二金属层电连接。
  19. 根据权利要求18所述的阵列基板，其中，所述阵列基板还包括：
    有机平坦层，设置于所述第一钝化层远离所述衬底基板的一侧；以及
    第二钝化层，设置于所述有机平坦层远离所述衬底基板的一侧；
    其中，所述像素电极层位于所述第二钝化层远离所述衬底基板的一侧，所述第一过孔贯穿所述第二钝化层、所述有机平坦层和所述第一钝化层。
  20. 一种显示面板，包括对置基板、液晶层和如上述阵列基板，所述对置基板与所述阵列基板相对间隔设置，所述液晶层设置于所述对置基板与所述阵列基板之间；
    所述阵列基板包括：
    衬底基板；以及
    薄膜晶体管阵列层，设置于所述衬底基板一侧，所述薄膜晶体管阵列层包括第一金属层、栅极绝缘层、半导体层和第二金属层；
    其中，所述第二金属层包括沿靠近所述衬底基板方向依次层叠设置的第一阻挡层、导电层和第二阻挡层，所述第一阻挡层的还原电位小于所述导电层的还原电位。
PCT/CN2022/080808 2022-03-04 2022-03-15 阵列基板及显示面板 WO2023164973A1 (zh)

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CN101771072A (zh) * 2010-02-23 2010-07-07 友达光电股份有限公司 主动元件阵列基板及其制作方法
CN113745341A (zh) * 2021-07-30 2021-12-03 惠科股份有限公司 薄膜晶体管及其制备方法、阵列基板和显示面板

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CN1697575A (zh) * 2004-05-11 2005-11-16 三星Sdi株式会社 有机发光显示装置及其制造方法
CN101771072A (zh) * 2010-02-23 2010-07-07 友达光电股份有限公司 主动元件阵列基板及其制作方法
CN113745341A (zh) * 2021-07-30 2021-12-03 惠科股份有限公司 薄膜晶体管及其制备方法、阵列基板和显示面板

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