WO2023159667A1 - 增强相邻存储单元之间漏电的方法及漏电检测方法、装置 - Google Patents

增强相邻存储单元之间漏电的方法及漏电检测方法、装置 Download PDF

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WO2023159667A1
WO2023159667A1 PCT/CN2022/079034 CN2022079034W WO2023159667A1 WO 2023159667 A1 WO2023159667 A1 WO 2023159667A1 CN 2022079034 W CN2022079034 W CN 2022079034W WO 2023159667 A1 WO2023159667 A1 WO 2023159667A1
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storage unit
level storage
low
level
voltage
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PCT/CN2022/079034
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English (en)
French (fr)
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刘欢欢
王伟洲
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长鑫存储技术有限公司
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Priority to US17/809,551 priority Critical patent/US20230267987A1/en
Publication of WO2023159667A1 publication Critical patent/WO2023159667A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/1204—Bit line control

Definitions

  • the present disclosure relates to the technical field of semiconductors, and in particular to a method for enhancing leakage between adjacent memory cells, a method and a device for detecting leakage.
  • Dynamic Random Access Memory is a semiconductor storage device commonly used in computers, consisting of many repeated storage units. Each memory cell usually includes a capacitor and a transistor. The gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor. The voltage signal on the word line can control the opening or closing of the transistor, and then through the bit line Read the data information stored in the capacitor, or write the data information into the capacitor through the bit line for storage.
  • the embodiments of the present disclosure provide a method for enhancing leakage between adjacent memory cells, a method and a device for detecting leakage in order to solve at least one problem in the prior art.
  • an embodiment of the present disclosure provides a method for enhancing leakage between adjacent memory cells, the method comprising:
  • the column stripe test pattern is that the low-level memory cells and the high-level memory cells are arranged in columns, and there are N between two adjacent columns of low-level memory cells.
  • Column high level memory cells N ⁇ 2;
  • Voltage regulation is performed on the low-level storage unit and the high-level storage unit to increase the potential difference between the low-level storage unit and the high-level storage unit.
  • performing voltage regulation on the high-level storage unit includes:
  • the high voltage VARY corresponding to the high level storage unit is connected to the high voltage VDD, so that the level of the high level storage unit is increased.
  • the method also includes:
  • performing voltage regulation on the low-level storage unit and the high-level storage unit further includes:
  • the plate voltage VPLT corresponding to the low-level storage unit and the high-level storage unit is adjusted in the first step until the plate voltage VPLT drops to a target voltage.
  • the method also includes:
  • the gate voltage VKK of the low-level storage unit and the high-level storage unit is step-down regulated.
  • the method also includes:
  • the bit line precharge voltage VBLP of the low-level storage unit and the high-level storage unit is step-down regulated.
  • the low-level storage unit is a storage unit whose write logic is 0; the high-level storage unit is a storage unit whose write logic is 1.
  • an embodiment of the present disclosure provides a leakage detection method based on any one of the methods described in the first aspect, the method comprising:
  • the method also includes:
  • the voltages corresponding to the low-level storage unit and the high-level storage unit are restored.
  • an embodiment of the present disclosure provides a device for enhancing leakage between adjacent storage cells, the device comprising:
  • the write unit is configured to perform a write operation on the storage array to form a column stripe test pattern;
  • the column stripe test pattern is that low-level storage units and high-level storage units are arranged in columns, and two adjacent columns are low-level There are N columns of high-level memory cells between the memory cells, N ⁇ 2;
  • a voltage adjusting unit configured to adjust the voltage of the low-level storage unit and the high-level storage unit to increase the potential difference between the low-level storage unit and the high-level storage unit.
  • the voltage adjusting unit is specifically configured to connect the high-level voltage VARY corresponding to the high-level storage unit to the high-voltage voltage VDD, so as to increase the potential of the high-level storage unit.
  • the device also includes:
  • the refresh unit is configured to perform multiple refresh operations on the high-level storage unit.
  • the voltage adjustment unit is further configured to, after each refresh operation, set the corresponding poles of the low-level storage unit and the high-level storage unit The plate voltage VPLT is adjusted until the plate voltage VPLT drops to the target voltage.
  • the device also includes:
  • the first regulating unit is configured to step-down regulate the gate voltage VKK of the low-level storage unit and the high-level storage unit.
  • the device also includes:
  • the second adjustment unit is configured to step down and adjust the bit line precharge voltage VBLP of the low-level storage unit and the high-level storage unit.
  • the low-level storage unit is a storage unit whose write logic is 0; the high-level storage unit is a storage unit whose write logic is 1.
  • an embodiment of the present disclosure provides a leakage detection device including the device described in any one of the third aspect, and the device includes:
  • a read unit configured to perform a read operation on the low-level storage unit to read read data in the low-level storage unit
  • a processing unit configured to acquire a leakage detection result of the low-level storage unit based on the read data.
  • the device also includes:
  • the restoring unit is configured to restore voltages corresponding to the low-level storage unit and the high-level storage unit after obtaining the leakage detection result of the low-level storage unit.
  • an embodiment of the present disclosure provides a semiconductor memory, including the device described in any one of the third aspect and the device described in any one of the fourth aspect.
  • the semiconductor memory is a dynamic random access memory (DRAM).
  • DRAM dynamic random access memory
  • a method for enhancing leakage between adjacent memory cells in which the low-level memory cells and high-level memory cells arranged in columns are written into, There are N columns of high-level memory cells between two adjacent columns of low-level memory cells.
  • the present disclosure adjusts the voltage of the low-level storage unit and the high-level storage unit to increase the potential difference between the low-level storage unit and the high-level storage unit, so that the potential leakage defect between the storage units can be enhanced, and further Potential leakage defects between adjacent memory cells can be detected when leakage detection is performed.
  • FIG. 1 is a schematic flowchart of a method for enhancing leakage between adjacent memory cells provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of forming a column stripe test pattern in an embodiment of the present disclosure
  • FIG. 3A is a first schematic diagram of leakage between adjacent memory cells provided by an embodiment of the present disclosure.
  • FIG. 3B is a second schematic diagram of leakage between adjacent memory cells provided by an embodiment of the present disclosure.
  • FIG. 3C is a third schematic diagram of leakage between adjacent memory cells provided by an embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of a leakage path under normal conditions provided by an embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram of an implementation flow of a leakage detection method provided by an embodiment of the present disclosure
  • FIG. 6 is a schematic flow diagram of an implementation flow of a leakage detection method provided in a specific example of the present disclosure
  • FIG. 7 is a schematic structural diagram of a device for enhancing leakage between adjacent memory cells provided by an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of a leakage detection device provided by an embodiment of the present disclosure.
  • spatially relative terms such as “below”, “under”, “under”, “under”, “on”, “above”, etc. are used herein Descriptive convenience may be used to describe the relationship of one element or feature to other elements or features shown in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as “below” or “beneath” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary terms “below” and “beneath” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
  • the potential leakage defect between adjacent memory cells refers to the leakage defect formed between adjacent memory cells due to the influence of process deviation, environment, equipment and other factors during the memory production process; It is difficult to detect during the detection stage of the memory. Only in later use, it will appear due to cyclic reading and writing, and cause data reading errors.
  • FIG. 1 is a schematic flow diagram of a method for enhancing leakage between adjacent storage cells provided by an embodiment of the present disclosure. As shown in FIG. 1 , The method comprises the steps of:
  • Step 110 Perform a write operation on the memory array to form a column stripe test pattern;
  • the column stripe test pattern is that low-level memory cells and high-level memory cells are arranged in columns, and between two adjacent columns of low-level memory cells There are N columns of high-level memory cells between them, N ⁇ 2;
  • Step 120 Perform voltage regulation on the low-level storage unit and the high-level storage unit to increase the potential difference between the low-level storage unit and the high-level storage unit.
  • FIG. 2 is a schematic diagram of forming a column stripe test pattern in an embodiment of the disclosure.
  • a write operation is performed on the storage array to form a column stripe test pattern.
  • the specific process is: corresponding to WL0 Write logic 0 in the storage unit, write logic 1 in the storage unit corresponding to WL1, WL2, WL3; write logic 0 in the storage unit corresponding to WL4, write logic 0 in the storage unit corresponding to WL5, WL6, WL7 1; ... and so on, until all columns in the storage array are written.
  • low-level memory cells are low-level memory cells, and the memory cells corresponding to WL1, WL2, WL3, WL5, WL6, WL7,... are high-level memory cells.
  • the low-level memory cells and the high-level memory cells are arranged in columns, and there are three columns of high-level memory cells between two adjacent columns of low-level memory cells.
  • the test pattern is any combination of writing logic "1" or "0" in one-to-one correspondence with each storage unit of the storage array, for example, "1" can be written to each storage unit of the storage array by column Or “0" (that is, the column stripe test pattern), or write "1” or “0” (that is, the row stripe test pattern) to each memory cell of the memory array by row.
  • a write operation can also be performed on the memory array to form a row stripe test pattern. The specific process is: write logic 0 in BL0, and then write logic 1 in BL1, BL2, and BL3; Write logic 0 in BL4, write logic 1 in BL5, BL6, BL7; ...
  • BL0, BL4, BL8... are low-level memory cells
  • BL1, BL2, BL3, BL5, BL6, BL7,... are high-level memory cells.
  • the low-level storage cells and the high-level storage cells are arranged in rows, and there are three rows of high-level storage cells between two adjacent rows of low-level storage cells.
  • the high-level voltage VARY corresponding to the high-level storage unit is connected to the high-voltage voltage VDD, so as to increase the level of the high-level storage unit.
  • the high voltage VARY is a voltage signal when the write logic is “1”. That is, in the embodiment of the present disclosure, the high voltage VARY is applied to WL1, WL2, WL3, WL5, WL6, WL7, .
  • the level of the high-level storage unit is increased by connecting the high-level voltage VARY to the high-voltage voltage VDD, so that the voltage between the low-level storage unit and the high-level storage unit The potential difference intensifies.
  • the high voltage VDD is 1.4V.
  • multiple refresh operations are performed on the high-level storage unit.
  • the low-level storage unit is used as the detection target, and multiple refresh operations are performed on the high-level storage unit, thereby intensifying the leakage between the low-level storage unit and the high-level storage unit, resulting in potential leakage defects memory cells can be detected.
  • the plate voltage VPLT corresponding to the low-level storage unit and the high-level storage unit is adjusted in the first step until the plate Voltage VPLT drops to the target voltage.
  • the first step length may be 0.1, 0.15 or 0.2.
  • the plate voltage VPLT corresponding to the low-level storage unit and the high-level storage unit may also be adjusted with a variable step size until the plate voltage VPLT drops to a target voltage.
  • the step size during the first adjustment may be 0.1
  • the step size during the second adjustment may be 0.2.
  • the plate voltage VPLT corresponding to the low-level memory unit and the high-level memory unit may also be adjusted so that the plate voltage VPLT is lowered.
  • the plate voltage VPLT corresponding to the low-level storage unit and the high-level storage unit is adjusted from 0.5V to 0.3V.
  • the target voltage of the plate voltage VPLT may be 0.1V.
  • the initial voltage of the plate voltage VPLT may be 0.5V.
  • the bit line precharge voltage VBLP can be further adjusted down.
  • the bit line precharge voltage VBLP is adjusted from 0.5V to 0.45V, so that the potential leakage defects of low-level memory cells can be detected more easily.
  • FIG. 3A is a first schematic diagram of leakage between adjacent memory cells provided by an embodiment of the present disclosure
  • FIG. 3B is a second schematic diagram of leakage between adjacent memory cells provided by an embodiment of the present disclosure.
  • Fig. 3A shows the leakage situation of the memory cell voltage regulation without the method of enhancing the leakage between adjacent memory cells provided by the present disclosure
  • Fig. 3B shows the enhanced phase leakage provided by the present disclosure.
  • the method of leakage between adjacent memory cells regulates the voltage leakage of the memory cells.
  • the low-level voltage Vss corresponding to the low-level storage unit is 0V
  • the plate voltage VPLT corresponding to the low-level storage unit is 0.5V
  • the high-level voltage VARY corresponding to the high-level storage unit is 1V.
  • the plate voltage VPLT corresponding to the memory cell is 0.5V.
  • the plate voltage VPLT corresponding to the low-level storage unit and the high-level storage unit is adjusted to 0.3V, so that the low-level voltage Vss corresponding to the low-level storage unit will become -0.2V
  • the The high-level voltage VARY corresponding to the high-level storage unit is adjusted to 1.4V. In this way, compared with FIG.
  • the potential difference between the low-level storage unit and the high-level storage unit changes from 1V to 1.6V. Therefore, through the method for enhancing the leakage between adjacent memory cells provided by the present disclosure, the leakage between low-level memory cells and high-level memory cells can be aggravated to a large extent, so that there are memory cells with potential leakage defects be detected.
  • FIG. 3C is a third schematic diagram of leakage between adjacent memory cells provided by an embodiment of the present disclosure.
  • the plate voltage VPLT corresponding to the level storage unit and the high-level storage unit is adjusted to 0.1V, so that the low-level voltage Vss corresponding to the low-level storage unit will be changed to -0.4V, so that, compared with Figure 3A, the The potential difference between the low-level storage unit and the high-level storage unit changes from 1V to 1.8V.
  • the leakage between the low-level storage unit and the high-level storage unit is further exacerbated, so that the storage unit with a potential leakage defect can be detected more easily and faster.
  • step-down regulation is performed on the gate voltage VKK of the low-level storage unit and the high-level storage unit. For example, adjust the gate voltage VKK from -0.2V to -0.5V to suppress leakage under normal conditions.
  • FIG. 4 is a schematic diagram of a leakage path under normal conditions provided by an embodiment of the present disclosure. As shown in FIG. 4 , there are three kinds of leakage conditions under normal conditions. The first type is the leakage current under the reverse bias of the PN junction, corresponding to the leakage path X ; The second type is the leakage current in the cut-off state of the MOS transistor, which corresponds to the leakage path Y; the third type is the leakage current caused by the strong potential difference between the memory cell and the word line, which corresponds to the leakage path Z.
  • the first type is the leakage current under the reverse bias of the PN junction, corresponding to the leakage path X .
  • the second type is the leakage current in the cut-off state of the MOS transistor, which corresponds to the leakage path Y;
  • the third type is the leakage current caused by the strong potential difference between the memory cell and the word line, which corresponds to the leakage path Z.
  • the gate voltage VKK is stepped down to suppress the second and the second Three leakage situations.
  • the gate voltage VKK is the gate voltage in the off state of the MOS transistor.
  • the low-level memory cell is used as the detection target, thereby avoiding the reverse bias of the PN junction, thereby avoiding the first leakage situation. In this way, the electric leakage under normal conditions can be greatly reduced, so that the targeted detection of electric leakage under abnormal conditions can be strengthened. Moreover, it can also avoid the situation that a normal memory cell is detected to have a leakage defect due to leakage under normal conditions.
  • FIG. 5 is a schematic flow diagram of an implementation flow of a leakage detection method provided by an embodiment of the present disclosure. As shown in FIG. 5, the method includes the following steps:
  • Step 510 performing a read operation on the low-level storage unit to read the read data in the low-level storage unit
  • Step 520 based on the read data, obtain a leakage detection result of the low-level storage unit.
  • a read operation is performed on the low-level storage unit in a low-temperature environment to read the Read data in the low-level storage unit.
  • the temperature range of the low temperature environment is -40°C to -10°C. Leakage detection in a low temperature environment can effectively suppress the leakage under the three normal conditions shown in Figure 4. Thereby, targeted detection of electric leakage under abnormal conditions can be strengthened.
  • the test temperature of DDR4 may be -10°C
  • the test temperature of LPDDR4 may be -33°C.
  • the low-level storage unit is used as the detection target, and after the leakage detection result of the low-level storage unit is obtained, the voltage corresponding to the low-level storage unit and the high-level storage unit is checked. recovery.
  • the specific process of restoring the voltages corresponding to the low-level storage unit and the high-level storage unit is: The voltage VPLT, the high-level voltage VARY corresponding to the high-level storage unit, and the gate voltages VKK of the low-level storage unit and the high-level storage unit recover to initial voltages.
  • the write operation is performed on the memory array to form a column stripe test pattern.
  • the specific process is: write logic 0 in the storage unit corresponding to WL0/WL4/..., write logic 0 in the memory unit corresponding to WL1/WL5/..., WL2/WL6 Write logic 1 to memory cells corresponding to /... and WL3/WL7/....
  • WL0, WL1, WL2 and WL3 constitute a repeating unit, and the number of WLs in the repeating unit is 4.
  • the memory cells corresponding to WL0/WL4/... are low-level memory cells
  • the memory cells corresponding to WL1/WL5/..., WL2/WL6/... and WL3/WL7/... are high-level memory cells.
  • the voltage adjustment of the low-level storage unit and the high-level storage unit is performed, the specific process is: the gate voltage of the low-level storage unit and the high-level storage unit VKK is adjusted from -0.2V to -0.5V, the plate voltage VPLT corresponding to the low-level storage unit and the high-level storage unit is adjusted from 0.5V to 0.3V, and the bit line precharge voltage VBLP is adjusted from 0.5V to 0.5V. V is adjusted to 0.45V and the high voltage VARY corresponding to the high level storage unit is adjusted to a high voltage VDD.
  • the first refresh operation is performed on the high-level memory cells WL1/WL5/ . . . , WL2/WL6/ . . . and WL3/WL7/ .
  • the plate voltage VPLT is further step-down adjusted with 0.2 as the first step until the plate voltage VPLT drops to the target voltage 0.1V.
  • the plate voltage VPLT has been adjusted to the target voltage of 0.1V, so after the subsequent refreshing operation, there is no need to further step-down adjust the plate voltage VPLT.
  • the low-level memory cells are refreshed in a low temperature environment.
  • WL0/WL4/... perform a read operation to read the read data in the low-level storage unit WL0/WL4/..., and obtain the leakage detection result of the low-level storage unit based on the read data .
  • the low-level storage unit is used as the detection target, and multiple refresh operations are performed on the high-level storage unit, thereby intensifying the leakage between the low-level storage unit and the high-level storage unit, resulting in potential leakage defects memory cells can be detected.
  • the low-level storage unit WL0/WL4/... is used as the detection target, and after the leakage detection is performed, the voltage corresponding to the low-level storage unit and the high-level storage unit is restored.
  • the high voltage VARY corresponding to the flat memory cell is restored from VDD to 1V.
  • the storage unit corresponding to WL1/WL5/... can be used as the detection target, write logic 0 in the storage unit corresponding to WL1/WL5/..., write logic 0 in the storage unit corresponding to WL0/WL4/..., WL2/WL6/... and WL3/WL7/ ...write a logic 1 to the corresponding memory cell.
  • the memory cells corresponding to WL1/WL5/... are low-level memory cells, and the memory cells corresponding to WL0/WL4/..., WL2/WL6/... and WL3/WL7/... are high-level memory cells.
  • the storage unit corresponding to WL3/WL7/... is used as the detection target for leakage detection, and logic 0 is written in the storage unit corresponding to WL3/WL7/..., and in WL0/WL4/..., Write a logic 1 in the memory cells corresponding to WL1/WL5/... and WL2/WL6/....
  • the detected memory cells cover the entire storage array. In other words, after four rounds of leakage detection, the detection of the entire storage array is realized.
  • the number of WL in the repeating unit can be adjusted according to the actual detection requirements, so that the number of detection rounds can be adjusted based on the number of WL in the repeating unit, and the detection time can be controlled based on the number of detection rounds.
  • the embodiments of the present disclosure also provide a leakage detection method, which makes it easier and faster to detect storage cells with potential leakage defects when performing leakage detection on low-level memory cells. Therefore, the technical solution of the present disclosure reduces to a certain extent the problems of potential defects between adjacent storage units appearing due to cyclic reading and writing during the use of the memory, and causes data reading errors, etc., ensuring the memory quality.
  • the embodiment of the present disclosure provides a device for enhancing leakage between adjacent storage cells.
  • a schematic structural diagram of a device for leakage between cells, as shown in FIG. 7 , the device 700 for enhancing leakage between adjacent memory cells includes:
  • the write unit 710 is configured to perform a write operation on the storage array to form a column stripe test pattern;
  • the column stripe test pattern is that low-level memory cells and high-level memory cells are arranged in columns, and two adjacent columns of low-power There are N columns of high-level memory cells between flat memory cells, N ⁇ 2;
  • the voltage adjusting unit 720 is configured to adjust the voltage of the low-level storage unit and the high-level storage unit, so as to increase the potential difference between the low-level storage unit and the high-level storage unit.
  • the voltage adjusting unit 720 is specifically configured to connect the high-level voltage VARY corresponding to the high-level storage unit to the high-voltage voltage VDD, so as to increase the potential of the high-level storage unit.
  • the device also includes:
  • the refresh unit 730 is configured to perform multiple refresh operations on the high-level storage unit.
  • the voltage adjustment unit 720 is further configured to adjust the plate voltage VPLT corresponding to the low-level storage unit and the high-level storage unit with a first step after each refresh operation. Adjust until the plate voltage VPLT drops to the target voltage.
  • the device also includes:
  • the first regulating unit 740 is configured to step-down regulate the gate voltage VKK of the low-level storage unit and the high-level storage unit.
  • the device also includes:
  • the second regulating unit 750 is configured to step-down regulate the bit line precharge voltage VBLP of the low-level storage unit and the high-level storage unit.
  • the low-level storage unit is a storage unit whose write logic is 0; the high-level storage unit is a storage unit whose write logic is 1.
  • FIG. 8 is a schematic structural diagram of a leakage detection device provided by an embodiment of the disclosure. As shown in FIG. 8 , the leakage detection device 800 includes:
  • the reading unit 810 is configured to perform a reading operation on the low-level storage unit in a low-temperature environment, so as to read the read data in the low-level storage unit;
  • the processing unit 820 is configured to acquire a leakage detection result of the low-level storage unit based on the read data.
  • the device also includes:
  • the restoring unit 830 is configured to restore voltages corresponding to the low-level storage unit and the high-level storage unit after obtaining the leakage detection result of the low-level storage unit.
  • An embodiment of the present disclosure further provides a semiconductor memory, including the above-mentioned device for enhancing leakage between adjacent memory cells and the above-mentioned leakage detection device.
  • the semiconductor memory referred to in the present disclosure includes but is not limited to dynamic random access memory DRAM, etc., and the semiconductor memory can use the device for enhancing leakage between adjacent memory cells of the present disclosure to increase the low-level memory cells and the high-level memory cells.
  • the potential difference between the storage cells can enhance the potential leakage defect between the adjacent storage cells, and then the potential leakage defect between the adjacent storage cells can be detected when the leakage detection device of the present disclosure is used for leakage detection.
  • the semiconductor memory is a dynamic random access memory DRAM chip, and the memory of the dynamic random access memory DRAM chip conforms to the DDR2 memory specification.
  • the semiconductor memory is a dynamic random access memory DRAM chip, and the memory of the dynamic random access memory DRAM chip conforms to the DDR3 memory specification.
  • the semiconductor memory is a dynamic random access memory DRAM chip, and the memory of the dynamic random access memory DRAM chip conforms to the DDR4 memory specification.
  • the semiconductor memory is a dynamic random access memory DRAM chip, and the memory of the dynamic random access memory DRAM chip conforms to the DDR5 memory specification.
  • the present disclosure adjusts the voltage of the low-level storage unit and the high-level storage unit to increase the potential difference between the low-level storage unit and the high-level storage unit, so that the potential leakage defect between the storage units can be enhanced, and further Potential leakage defects between adjacent memory cells can be detected when leakage detection is performed.

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Abstract

一种增强相邻存储单元之间漏电的方法及漏电检测方法、装置，该增强相邻存储单元之间漏电的方法包括：对存储阵列进行写入操作，形成列条纹测试图形；该列条纹测试图形为低电平存储单元和高电平存储单元按列排布，相邻两列低电平存储单元之间有N列高电平存储单元，N≥2（110）；对该低电平存储单元和该高电平存储单元进行电压调节，以增加该低电平存储单元和该高电平存储单元之间的电势差（120）。

Description

增强相邻存储单元之间漏电的方法及漏电检测方法、装置
相关申请的交叉引用
本公开基于申请号为202210172926.3、申请日为2022年02月24日、发明名称为“增强相邻存储单元之间漏电的方法及漏电检测方法、装置”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体技术领域，尤其涉及一种增强相邻存储单元之间漏电的方法及漏电检测方法、装置。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，DRAM)是计算机中常用的半导体存储器件，由许多重复的存储单元组成。每个存储单元通常包括电容器和晶体管，晶体管的栅极与字线相连、漏极与位线相连、源极与电容器相连，字线上的电压信号能够控制晶体管的打开或关闭，进而通过位线读取存储在电容器中的数据信息，或者通过位线将数据信息写入到电容器中进行存储。
随着DRAM的制程工艺越来越先进、存储密度越来越高，DRAM制程工艺中也出现了越来越多的问题，比如：副产物掉落引发的短路、位线漏电流、电容的倒塌、金属线的断裂，关键尺寸不合格造成的结构问题等，这些制程工艺中出现的问题需要在良率测试过程中筛选出来，但是现有的良率测试方法无法准确的检测出存在潜在漏电缺陷的存储单元，导致产品良率较低。
如何在良率测试过程中准确的检测出存在潜在漏电缺陷的存储单元， 是本领域技术人员亟须解决的问题。
发明内容
有鉴于此，本公开实施例为解决现有技术中存在的至少一个问题而提供一种增强相邻存储单元之间漏电的方法及漏电检测方法、装置。
为达到上述目的，本公开实施例的技术方案是这样实现的：
第一方面，本公开实施例提供一种增强相邻存储单元之间漏电的方法，所述方法包括：
对存储阵列进行写入操作，形成列条纹测试图形；所述列条纹测试图形为低电平存储单元和高电平存储单元按列排布，相邻两列低电平存储单元之间有N列高电平存储单元，N≥2；
对所述低电平存储单元和所述高电平存储单元进行电压调节，以增加所述低电平存储单元和所述高电平存储单元之间的电势差。
在一种可选的实施方式中，对所述高电平存储单元进行电压调节，包括：
将所述高电平存储单元对应的高位电压VARY连接至高压电压VDD，以使所述高电平存储单元的电平升高。
在一种可选的实施方式中，所述方法还包括：
对所述高电平存储单元进行多次刷新操作。
在一种可选的实施方式中，对所述低电平存储单元和所述高电平存储单元进行电压调节，还包括：
在每次刷新操作后，以第一步长，对所述低电平存储单元和所述高电平存储单元对应的极板电压VPLT进行调节，直至所述极板电压VPLT下降至目标电压。
在一种可选的实施方式中，所述方法还包括：
对所述低电平存储单元和所述高电平存储单元的栅极电压VKK进行 降压调节。
在一种可选的实施方式中，所述方法还包括：
对所述低电平存储单元和所述高电平存储单元的位线预充电压VBLP进行降压调节。
在一种可选的实施方式中，所述低电平存储单元为写入逻辑为0的存储单元；所述高电平存储单元为写入逻辑为1的存储单元。
第二方面，本公开实施例提供一种基于第一方面任一项所述方法的漏电检测方法，所述方法包括：
对所述低电平存储单元进行读取操作，以读取所述低电平存储单元内的读取数据；
基于所述读取数据，获取所述低电平存储单元的漏电检测结果。
在一种可选的实施方式中，所述方法还包括：
得到所述低电平存储单元的漏电检测结果后，对所述低电平存储单元和所述高电平存储单元对应的电压进行复原。
第三方面，本公开实施例提供一种增强相邻存储单元之间漏电的装置，所述装置包括：
写入单元，配置为对存储阵列进行写入操作，形成列条纹测试图形；所述列条纹测试图形为低电平存储单元和高电平存储单元按列排布，相邻两列低电平存储单元之间有N列高电平存储单元，N≥2；
电压调节单元，配置为对所述低电平存储单元和所述高电平存储单元进行电压调节，以增加所述低电平存储单元和所述高电平存储单元之间的电势差。
在一种可选的实施方式中，电压调节单元，具体配置为将所述高电平存储单元对应的高位电压VARY连接至高压电压VDD，以使所述高电平存储单元的电势升高。
在一种可选的实施方式中，所述装置还包括：
刷新单元，配置为对所述高电平存储单元进行多次刷新操作。
在一种可选的实施方式中，所述电压调节单元还配置为在每次刷新操作后，以第一步长，对所述低电平存储单元和所述高电平存储单元对应的极板电压VPLT进行调节，直至所述极板电压VPLT下降至目标电压。
在一种可选的实施方式中，所述装置还包括：
第一调节单元，配置为对所述低电平存储单元和所述高电平存储单元的栅极电压VKK进行降压调节。
在一种可选的实施方式中，所述装置还包括：
第二调节单元，配置为对所述低电平存储单元和所述高电平存储单元的位线预充电压VBLP进行降压调节。
在一种可选的实施方式中，所述低电平存储单元为写入逻辑为0的存储单元；所述高电平存储单元为写入逻辑为1的存储单元。
第四方面，本公开实施例提供一种包括第三方面任一项所述装置的漏电检测装置，所述装置包括：
读取单元，配置为对所述低电平存储单元进行读取操作，以读取所述低电平存储单元内的读取数据；
处理单元，配置为基于所述读取数据，获取所述低电平存储单元的漏电检测结果。
在一种可选的实施方式中，所述装置还包括：
复原单元，配置为在得到所述低电平存储单元的漏电检测结果后，对所述低电平存储单元和所述高电平存储单元对应的电压进行复原。
第五方面，本公开实施例提供一种半导体存储器，包括如第三方面任一项所述装置及如第四方面任一项所述装置。
在一种可选的实施方式中，所述半导体存储器为动态随机存取存储器DRAM。
在本公开所提供的技术方案中，提供了一种增强相邻存储单元之间漏 电的方法，该方法中对按列排布的低电平存储单元和高电平存储单元进行写入操作，其中相邻两列低电平存储单元之间有N列高电平存储单元。本公开通过对低电平存储单元和高电平存储单元进行电压调节，以增加低电平存储单元和高电平存储单元之间的电势差，从而可以增强存储单元之间潜在的漏电缺陷，进而在进行漏电检测的时候能够检测出相邻存储单元之间潜在的漏电缺陷。
附图说明
在附图中，除非另外规定，否则贯穿多个附图相同的附图标记表示相同或相似的部件或元素。这些附图不一定是按照比例绘制的。应该理解，这些附图仅描绘了根据本公开的一些实施方式，而不应将其视为是对本公开范围的限制。
图1为本公开实施例提供的一种增强相邻存储单元之间漏电的方法的实现流程示意图；
图2为本公开实施例中形成列条纹测试图形的示意图；
图3A为本公开实施例提供的相邻存储单元之间漏电的示意图一；
图3B为本公开实施例提供的相邻存储单元之间漏电的示意图二；
图3C为本公开实施例提供的相邻存储单元之间漏电的示意图三；
图4为本公开实施例提供的正常情况下的漏电路径的示意图；
图5为本公开实施例提供的一种漏电检测方法的实现流程示意图；
图6为本公开一具体示例提供的一种漏电检测方法的实现流程示意图；
图7为本公开实施例提供的一种增强相邻存储单元之间漏电的装置的结构示意图；
图8为本公开实施例提供的一种漏电检测装置的结构示意图。
具体实施方式
下面将参照附图更详细地描述本公开公开的示例性实施方式。虽然附图中显示了本公开的示例性实施方式，然而应当理解，可以以各种形式实现本公开，而不应被这里阐述的具体实施方式所限制。相反，提供这些实施方式是为了能够更透彻地理解本公开，并且能够将本公开的范围完整的传达给本领域的技术人员。
在下文的描述中，给出了大量具体的细节以便提供对本公开更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本公开可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本公开发生混淆，对于本领域公知的一些技术特征未进行描述；即，这里不描述实际实施例的全部特征，不详细描述公知的功能和结构。
在附图中，为了清楚，层、区、元件的尺寸以及其相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，空间关系术语例如“在……下”、“在……下面”、“下面的”、“在……之下”、“在……之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在……下面”和“在……下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或 “包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
半导体存储技术的发展，存储器的生产工艺也越来越成熟，半导体存储器也朝着更小尺度和更大集成的方向发展。半导体生产过程中，因生产工艺的高要求和高精度，往往会存在一定数量的缺陷产品。对于缺陷产品，有些缺陷暴漏较明显，能够在检测时检测出来进而进行修复或丢弃；但对于有些缺陷，在检测时往往不能检测出来，只有在以后的反复擦除与写入中才会显露出来。对于相邻存储单元之间的缺陷，其中一种是比较明显的缺陷在检测的时候能够快速、准确的检测出来；其中一种是潜在漏电缺陷。相邻存储单元之间的潜在漏电缺陷是指在存储器生产工艺流程中，因工艺的偏差、环境、设备等因素的影响，在相邻存储单元之间形成的漏电缺陷；对于此类缺陷在在对存储器进行检测阶段很难检测出来，只有在以后的使用中，因循环的读取和写入呈现出来，并造成数据读取错误等。
基于此，如何能够及时检测出相邻存储单元之间的潜在漏电缺陷成为了亟待解决的问题。
为此，提出了本公开以下实施方式。本公开实施例提供一种增强相邻存储单元之间漏电的方法，图1为本公开实施例提供的一种增强相邻存储单元之间漏电的方法的实现流程示意图，如图1所示，所述方法包括如下步骤：
步骤110：对存储阵列进行写入操作，形成列条纹测试图形；所述列条纹测试图形为低电平存储单元和高电平存储单元按列排布，相邻两列低电平存储单元之间有N列高电平存储单元，N≥2；
步骤120：对所述低电平存储单元和所述高电平存储单元进行电压调节，以增加所述低电平存储单元和所述高电平存储单元之间的电势差。
需要说明的是，本公开实施例中以N＝3为例进行说明。
图2为本公开实施例中形成列条纹测试图形的示意图，如图2所示，在本公开实施例中，对存储阵列进行写入操作，形成列条纹测试图形，具体过程为：在WL0对应的存储单元中写入逻辑0，在WL1，WL2，WL3对应的存储单元中写入逻辑1；在WL4对应的存储单元中写入逻辑0，在WL5，WL6，WL7对应的存储单元写入逻辑1；……以此类推，直至存储阵列中所有列均进行写入操作。这里，WL0、WL4、WL8……对应的存储单元即为低电平存储单元，WL1，WL2，WL3、WL5，WL6，WL7、……对应的存储单元即为高电平存储单元。低电平存储单元和高电平存储单元按列排布，相邻两列低电平存储单元之间有3列高电平存储单元。
在一些实施例中，测试图形为与存储阵列的各存储单元一一对应写入逻辑为“1”或“0”的任意组合，例如可以对存储阵列的各存储单元按列写入“1”或“0”(即列条纹测试图形)，或者对存储阵列的各存储单元按行写入“1”或“0”(即行条纹测试图形)。例如，本公开另一些实施例中也可以对存储阵列进行写入操作，形成行条纹测试图形，具体过程为：在BL0中写入逻辑0，然后在BL1，BL2，BL3写入逻辑1；在BL4中写入逻辑0，在BL5，BL6，BL7写入逻辑1；……以此类推，直至存储阵列中所有行均进行写入操作。这里，BL0、BL4、BL8……即为低电平存储单元，BL1，BL2，BL3、BL5，BL6，BL7、……即为高电平存储单元。低电平存储单元和高电平存储单元按行排布，相邻两行低电平存储单元之间有3行高电平存储单元。
在本公开实施例中，将所述高电平存储单元对应的高位电压VARY连接至高压电压VDD，以使所述高电平存储单元的电平升高。这里，高位电压VARY为写入逻辑为“1”时的电压信号。即本公开实施例中对WL1，WL2，WL3、WL5，WL6，WL7、……施加高位电压VARY，以在WL1，WL2，WL3、WL5，WL6，WL7、……中写入逻辑1。本公开实施例中通 过将高位电压VARY连接至高压电压VDD，使所述高电平存储单元的电平升高，从而使得所述低电平存储单元和所述高电平存储单元之间的电势差加剧。
在本公开一具体实施方式中，高压电压VDD为1.4V。
在本公开实施例中，对所述高电平存储单元进行多次刷新操作。本公开实施例中以低电平存储单元为检测目标，对高电平存储单元进行多次刷新操作，从而加剧低电平存储单元和高电平存储单元之间的漏电，使得存在潜在漏电缺陷的存储单元得以被检测出来。
在本公开实施例中，在每次刷新操作后，以第一步长，对所述低电平存储单元和所述高电平存储单元对应的极板电压VPLT进行调节，直至所述极板电压VPLT下降至目标电压。这里，所述第一步长可以为0.1、0.15或0.2。本公开实施例中通过分步减小极板电压VPLT，避免出现因极板电压VPLT骤变过大而导致的存储单元电势异常。
在一些实施例中，还可以以变化步长对所述低电平存储单元和所述高电平存储单元对应的极板电压VPLT进行调节，直至所述极板电压VPLT下降至目标电压。例如，第一次调节时的步长可以为0.1，第二次调节的步长可以为0.2。
在一些实施例中，在对存储阵列进行写入操作后，也可以对所述低电平存储单元和所述高电平存储单元对应的极板电压VPLT进行调节，以使所述极板电压VPLT降低。例如，在对存储阵列进行写入操作后，将所述低电平存储单元和所述高电平存储单元对应的极板电压VPLT从0.5V调节为0.3V。
在本公开一具体实施方式中，所述极板电压VPLT的目标电压可以为0.1V。而所述极板电压VPLT的初始电压可以为0.5V。
在本公开实施例中，还可以进一步将位线预充电压VBLP进行降压调节。例如，将位线预充电压VBLP从0.5V调节为0.45V，以使得低电平存 储单元的潜在的漏电缺陷更容易被检测出来。
图3A为本公开实施例提供的相邻存储单元之间漏电的示意图一，图3B为本公开实施例提供的相邻存储单元之间漏电的示意图二。需要说明的是，图3A所示的为未通过本公开提供的增强相邻存储单元之间漏电的方法对存储单元进行电压调节的漏电情况，图3B所示的为通过本公开提供的增强相邻存储单元之间漏电的方法对存储单元进行电压调节的漏电情况。如图3A所示，低电平存储单元对应的低位电压Vss为0V，低电平存储单元对应的极板电压VPLT为0.5V，高电平存储单元对应的高位电压VARY为1V，高电平存储单元对应的极板电压VPLT为0.5V。如图3B所示，将低电平存储单元和高电平存储单元对应的极板电压VPLT调整为0.3V，从而低电平存储单元对应的低位电压Vss将随之变为-0.2V，将高电平存储单元对应的高位电压VARY调整为1.4V，如此，相较于图3A，使得低电平存储单元和高电平存储单元之间的电势差由1V变为1.6V。由此，通过本公开提供的增强相邻存储单元之间漏电的方法，可以在很大程度上加剧低电平存储单元和高电平存储单元之间的漏电，使得存在潜在漏电缺陷的存储单元得以被检测出来。
图3C为本公开实施例提供的相邻存储单元之间漏电的示意图三，如图3C所示，在图3B的基础上，在对所述高电平存储单元进行刷新操作后，进一步将低电平存储单元和高电平存储单元对应的极板电压VPLT调整为0.1V，从而低电平存储单元对应的低位电压Vss将随之变为-0.4V，如此，相较于图3A，使得低电平存储单元和高电平存储单元之间的电势差由1V变为1.8V。进一步加剧了低电平存储单元和高电平存储单元之间的漏电，使得存在潜在漏电缺陷的存储单元更容易且更快被检测出来。
在本公开实施例中，对所述低电平存储单元和所述高电平存储单元的栅极电压VKK进行降压调节。例如，将栅极电压VKK从-0.2V调节为-0.5V，以抑制正常情况下的漏电。
图4为本公开实施例提供的正常情况下的漏电路径的示意图，如图4所示，正常情况下存在3种漏电情况，第一种为PN结反偏下的漏电电流，对应漏电路径X；第二种为MOS晶体管截止状态下的漏电电流，对应漏电路径Y；第三种为存储单元到字线之间存在的强电势差引起的漏电电流，对应漏电路径Z。由于相邻存储单元之间存在的这些正常情况下的漏电会影响非正常情况下的漏电检测，基于此，本公开实施例中通过对栅极电压VKK进行降压调节来抑制第二种和第三种漏电情况。这里，栅极电压VKK为MOS晶体管截止状态下的栅极电压。且进一步地，本公开实施例中以低电平存储单元为检测目标，从而可以避免出现PN结反偏的情况，从而避免出现第一种漏电情况。如此，可以极大程度减小正常情况下的漏电，从而可以加强对非正常情况下的漏电的针对性检测。并且还可以避免出现因正常情况下的漏电而导致的正常的存储单元被检测出存在漏电缺陷的情况。
本公开实施例提供一种基于上述增强相邻存储单元之间漏电的方法的漏电检测方法，即本公开实施例提供的漏电检测方法是在增强相邻存储单元之间漏电的方法的基础上进行的。图5为本公开实施例提供的一种漏电检测方法的实现流程示意图，如图5所示，所述方法包括如下步骤：
步骤510，对所述低电平存储单元进行读取操作，以读取所述低电平存储单元内的读取数据；
步骤520，基于所述读取数据，获取所述低电平存储单元的漏电检测结果。
在本公开实施例中，在对所述低电平存储单元和所述高电平存储单元进行电压调节后，在低温环境下对所述低电平存储单元进行读取操作，以读取所述低电平存储单元内的读取数据。这里，所述低温环境的温度范围为-40℃至-10℃。在低温环境下进行漏电检测，可以有效抑制图4所示的三种正常情况下的漏电。从而可以加强对非正常情况下的漏电的针对性检测。在一具体示例中，DDR4测试温度可以为-10℃，LPDDR4的测试温度可以 为-33℃。
本公开实施例中以低电平存储单元为检测目标，在得到所述低电平存储单元的漏电检测结果后，对所述低电平存储单元和所述高电平存储单元对应的电压进行复原。需要说明的是，对所述低电平存储单元和所述高电平存储单元对应的电压进行复原具体过程为，将所述低电平存储单元和所述高电平存储单元对应的极板电压VPLT、所述高电平存储单元对应的高位电压VARY和所述低电平存储单元和所述高电平存储单元的栅极电压VKK恢复至初始电压。
图6为本公开一具体示例提供的一种漏电检测方法的实现流程示意图，需要说明的是，图6以N＝3为例进行说明。如图6所示，对存储阵列进行写入操作，形成列条纹测试图形，具体过程为：在WL0/WL4/…对应的存储单元中写入逻辑0，在WL1/WL5/…、WL2/WL6/…和WL3/WL7/…对应的存储单元中写入逻辑1。对于WL来说，WL0、WL1、WL2和WL3四个为一重复单元，该重复单元中WL的数量为4。WL0/WL4/…对应的存储单元为低电平存储单元，WL1/WL5/…、WL2/WL6/…和WL3/WL7/…对应的存储单元为高电平存储单元。
如图6所示，对所述低电平存储单元和所述高电平存储单元进行电压调节，具体过程为：将所述低电平存储单元和所述高电平存储单元的栅极电压VKK从-0.2V调节为-0.5V、将所述低电平存储单元和所述高电平存储单元对应的极板电压VPLT从0.5V调节为0.3V、将位线预充电压VBLP从0.5V调节为0.45V以及将所述高电平存储单元对应的高位电压VARY调节为高压电压VDD。
如图6所示，对所述高电平存储单元WL1/WL5/…、WL2/WL6/…和WL3/WL7/…进行第一次刷新操作。
如图6所示，在第一次刷新操作后，以0.2为第一步长，对极板电压VPLT进行再次降压调节，直至所述极板电压VPLT下降至目标电压0.1V。 而在此次降压调节后，极板电压VPLT已经调节为目标电压0.1V，因而在后续的刷新操作后，无需再对极板电压VPLT进行降压调节。
如图6所示，对所述高电平存储单元WL1/WL5/…、WL2/WL6/…和WL3/WL7/…进行多次刷新操作后，在低温环境下对所述低电平存储单元WL0/WL4/…进行读取操作，以读取所述低电平存储单元WL0/WL4/…内的读取数据，基于所述读取数据，获取所述低电平存储单元的漏电检测结果。本公开实施例中以低电平存储单元为检测目标，对高电平存储单元进行多次刷新操作，从而加剧低电平存储单元和高电平存储单元之间的漏电，使得存在潜在漏电缺陷的存储单元得以被检测出来。
如图6所示，以低电平存储单元WL0/WL4/…为检测目标，进行漏电检测后，对所述低电平存储单元和所述高电平存储单元对应的电压进行复原，具体过程为：将栅极电压VKK从-0.5V复原为-0.2V、将极板电压VPLT从复原0.1V为0.5V、将位线预充电压VBLP从0.45V复原为0.5V以及将所述高电平存储单元对应的高位电压VARY从VDD复原为1V。
由于此时已检测的存储单元并未涵盖整个存储阵列，因而需要进行检测目标的切换，以对未检测的存储单元进行检测。此时可以将WL1/WL5/…对应的存储单元作为检测目标，在WL1/WL5/…对应的存储单元中写入逻辑0，在WL0/WL4/…、WL2/WL6/…和WL3/WL7/…对应的存储单元中写入逻辑1。这里，WL1/WL5/…对应的存储单元为低电平存储单元，WL0/WL4/…、WL2/WL6/…和WL3/WL7/…对应的存储单元为高电平存储单元。对所述低电平存储单元和所述高电平存储单元进行电压调节，以增加所述低电平存储单元和所述高电平存储单元之间的电势差；再对所述低电平存储单元WL1/WL5/…进行读取操作，以读取所述低电平存储单元WL1/WL5/…内的读取数据；基于所述读取数据，获取所述低电平存储单元WL1/WL5/…的漏电检测结果。
以低电平存储单元WL1/WL5/…为检测目标，进行漏电检测后。再将 WL2/WL6/…对应的存储单元作为检测目标进行漏电检测，在WL2/WL6/…对应的存储单元中写入逻辑0，在WL0/WL4/…、WL1/WL5/…和WL3/WL7/…对应的存储单元中写入逻辑1。WL2/WL6/…检测完成后，再将WL3/WL7/…对应的存储单元作为检测目标进行漏电检测，在WL3/WL7/…对应的存储单元中写入逻辑0，在WL0/WL4/…、WL1/WL5/…和WL2/WL6/…对应的存储单元中写入逻辑1。如此，经过4轮漏电检测，已检测的存储单元就涵盖了整个存储阵列，换言之，经过4轮漏电检测，即实现了整个存储阵列的检测。
需要说明的是，在实际应用时，可以根据实际检测需求而调整重复单元中WL的数量，从而基于重复单元中WL的数量来调整检测的轮数，基于检测的轮数即可控制检测时间。
进而本公开实施例还提供了一种漏电检测方法，在对低电平存储单元进行漏电检测时，使得存在潜在漏电缺陷的存储单元更容易且更快被检测出来。因此，本公开技术方案在一定程度上减少了存储器在使用过程中，相邻存储单元之间潜在缺陷因循环的读取和写入呈现出来，并造成数据读取错误等问题，保证了存储器的质量。
基于前述增强相邻存储单元之间漏电的方法相同的技术构思，本公开实施例提供一种增强相邻存储单元之间漏电的装置，图7为本公开实施例提供的一种增强相邻存储单元之间漏电的装置的结构示意图，如图7所示，所述增强相邻存储单元之间漏电的装置700包括：
写入单元710，配置为对存储阵列进行写入操作，形成列条纹测试图形；所述列条纹测试图形为低电平存储单元和高电平存储单元按列排布，相邻两列低电平存储单元之间有N列高电平存储单元，N≥2；
电压调节单元720，配置为对所述低电平存储单元和所述高电平存储单元进行电压调节，以增加所述低电平存储单元和所述高电平存储单元之间的电势差。
在一些实施例中，电压调节单元720，具体配置为将所述高电平存储单元对应的高位电压VARY连接至高压电压VDD，以使所述高电平存储单元的电势升高。
在一些实施例中，所述装置还包括：
刷新单元730，配置为对所述高电平存储单元进行多次刷新操作。
在一些实施例中，所述电压调节单元720还配置为在每次刷新操作后，以第一步长，对所述低电平存储单元和所述高电平存储单元对应的极板电压VPLT进行调节，直至所述极板电压VPLT下降至目标电压。
在一些实施例中，所述装置还包括：
第一调节单元740，配置为对所述低电平存储单元和所述高电平存储单元的栅极电压VKK进行降压调节。
在一些实施例中，所述装置还包括：
第二调节单元750，配置为对所述低电平存储单元和所述高电平存储单元的位线预充电压VBLP进行降压调节。
在一些实施例中，所述低电平存储单元为写入逻辑为0的存储单元；所述高电平存储单元为写入逻辑为1的存储单元。
基于前述漏电检测方法相同的技术构思，本公开实施例提供一种漏电检测装置，图8为本公开实施例提供的一种漏电检测装置的结构示意图，如图8所示，所述漏电检测装置800包括：
读取单元810，配置为在低温环境下对所述低电平存储单元进行读取操作，以读取所述低电平存储单元内的读取数据；
处理单元820，配置为基于所述读取数据，获取所述低电平存储单元的漏电检测结果。
在一些实施例中，所述装置还包括：
复原单元830，配置为在得到所述低电平存储单元的漏电检测结果后，对所述低电平存储单元和所述高电平存储单元对应的电压进行复原。
本公开实施例还提供一种半导体存储器，包括上述增强相邻存储单元之间漏电的装置及上述漏电检测装置。本公开所指半导体存储器包括但不限于动态随机存取存储器DRAM等，半导体存储器可以采用本公开的增强相邻存储单元之间漏电的装置来增加所述低电平存储单元和所述高电平存储单元之间的电势差，从而可以增强相邻存储单元之间潜在的漏电缺陷，进而在采用本公开的漏电检测装置进行漏电检测的时候能够检测出相邻存储单元之间潜在的漏电缺陷。
在一些实施例中，所述半导体存储器为动态随机存取存储器DRAM芯片，所述动态随机存取存储器DRAM芯片的内存符合DDR2内存规格。
在一些实施例中，所述半导体存储器为动态随机存取存储器DRAM芯片，所述动态随机存取存储器DRAM芯片的内存符合DDR3内存规格。
在一些实施例中，所述半导体存储器为动态随机存取存储器DRAM芯片，所述动态随机存取存储器DRAM芯片的内存符合DDR4内存规格。
在一些实施例中，所述半导体存储器为动态随机存取存储器DRAM芯片，所述动态随机存取存储器DRAM芯片的内存符合DDR5内存规格。
本公开所提供的几个方法实施例中所揭露的方法，在不冲突的情况下可以任意组合，得到新的方法实施例。
本公开所提供的几个装置实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的装置实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。
工业实用性
本公开通过对低电平存储单元和高电平存储单元进行电压调节，以增 加低电平存储单元和高电平存储单元之间的电势差，从而可以增强存储单元之间潜在的漏电缺陷，进而在进行漏电检测的时候能够检测出相邻存储单元之间潜在的漏电缺陷。

Claims (20)

  1. 一种增强相邻存储单元之间漏电的方法，所述方法包括：
    对存储阵列进行写入操作，形成列条纹测试图形；所述列条纹测试图形为低电平存储单元和高电平存储单元按列排布，相邻两列低电平存储单元之间有N列高电平存储单元，N≥2；
    对所述低电平存储单元和所述高电平存储单元进行电压调节，以增加所述低电平存储单元和所述高电平存储单元之间的电势差。
  2. 根据权利要求1所述的方法，其中，对所述高电平存储单元进行电压调节，包括：
    将所述高电平存储单元对应的高位电压VARY连接至高压电压VDD，以使所述高电平存储单元的电平升高。
  3. 根据权利要求1所述的方法，其中，所述方法还包括：
    对所述高电平存储单元进行多次刷新操作。
  4. 根据权利要求3所述的方法，其中，对所述低电平存储单元和所述高电平存储单元进行电压调节，还包括：
    在每次刷新操作后，以第一步长，对所述低电平存储单元和所述高电平存储单元对应的极板电压VPLT进行调节，直至所述极板电压VPLT下降至目标电压。
  5. 根据权利要求1所述的方法，其中，所述方法还包括：
    对所述低电平存储单元和所述高电平存储单元的栅极电压VKK进行降压调节。
  6. 根据权利要求1所述的方法，其中，所述方法还包括：
    对所述低电平存储单元和所述高电平存储单元的位线预充电压VBLP进行降压调节。
  7. 根据权利要求1所述的方法，其中，所述低电平存储单元为写入逻 辑为0的存储单元；所述高电平存储单元为写入逻辑为1的存储单元。
  8. 一种基于权利要求1至7任一项所述方法的漏电检测方法，所述方法包括：
    对所述低电平存储单元进行读取操作，以读取所述低电平存储单元内的读取数据；
    基于所述读取数据，获取所述低电平存储单元的漏电检测结果。
  9. 根据权利要求8所述的方法，其中，所述方法还包括：
    得到所述低电平存储单元的漏电检测结果后，对所述低电平存储单元和所述高电平存储单元对应的电压进行复原。
  10. 一种增强相邻存储单元之间漏电的装置，所述装置包括：
    写入单元，配置为对存储阵列进行写入操作，形成列条纹测试图形；所述列条纹测试图形为低电平存储单元和高电平存储单元按列排布，相邻两列低电平存储单元之间有N列高电平存储单元，N≥2；
    电压调节单元，配置为对所述低电平存储单元和所述高电平存储单元进行电压调节，以增加所述低电平存储单元和所述高电平存储单元之间的电势差。
  11. 根据权利要求10所述的装置，其中，电压调节单元，具体配置为将所述高电平存储单元对应的高位电压VARY连接至高压电压VDD，以使所述高电平存储单元的电势升高。
  12. 根据权利要求10所述的装置，其中，所述装置还包括：
    刷新单元，配置为对所述高电平存储单元进行多次刷新操作。
  13. 根据权利要求12所述的装置，其中，所述电压调节单元还配置为在每次刷新操作后，以第一步长，对所述低电平存储单元和所述高电平存储单元对应的极板电压VPLT进行调节，直至所述极板电压VPLT下降至目标电压。
  14. 根据权利要求10所述的装置，其中，所述装置还包括：
    第一调节单元，配置为对所述低电平存储单元和所述高电平存储单元的栅极电压VKK进行降压调节。
  15. 根据权利要求10所述的装置，其中，所述装置还包括：
    第二调节单元，配置为对所述低电平存储单元和所述高电平存储单元的位线预充电压VBLP进行降压调节。
  16. 根据权利要求10所述的装置，其中，所述低电平存储单元为写入逻辑为0的存储单元；所述高电平存储单元为写入逻辑为1的存储单元。
  17. 一种包括权利要求10至16任一项所述装置的漏电检测装置，所述装置包括：
    读取单元，配置为对所述低电平存储单元进行读取操作，以读取所述低电平存储单元内的读取数据；
    处理单元，配置为基于所述读取数据，获取所述低电平存储单元的漏电检测结果。
  18. 根据权利要求17所述的装置，其中，所述装置还包括：
    复原单元，配置为在得到所述低电平存储单元的漏电检测结果后，对所述低电平存储单元和所述高电平存储单元对应的电压进行复原。
  19. 一种半导体存储器，包括如权利要求10至16任一项所述装置及如权利要求17至18任一项所述装置。
  20. 根据权利要求19所述的半导体存储器，其中，所述半导体存储器为动态随机存取存储器DRAM。
PCT/CN2022/079034 2022-02-24 2022-03-03 增强相邻存储单元之间漏电的方法及漏电检测方法、装置 WO2023159667A1 (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02235300A (ja) * 1989-03-09 1990-09-18 Fujitsu Ltd 半導体記憶装置の試験方法
US5428574A (en) * 1988-12-05 1995-06-27 Motorola, Inc. Static RAM with test features
US20030012067A1 (en) * 2001-07-11 2003-01-16 International Business Machines Corporation Method and apparatus for identifying SRAM cells having weak pull-up PFETs
CN104425036A (zh) * 2013-08-26 2015-03-18 北京兆易创新科技股份有限公司 增强存储阵列位线缺陷漏电的方法
CN106601287A (zh) * 2015-10-15 2017-04-26 中芯国际集成电路制造(上海)有限公司 静态随机存取存储器单元、静态随机存取存储器及电子装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5428574A (en) * 1988-12-05 1995-06-27 Motorola, Inc. Static RAM with test features
JPH02235300A (ja) * 1989-03-09 1990-09-18 Fujitsu Ltd 半導体記憶装置の試験方法
US20030012067A1 (en) * 2001-07-11 2003-01-16 International Business Machines Corporation Method and apparatus for identifying SRAM cells having weak pull-up PFETs
CN104425036A (zh) * 2013-08-26 2015-03-18 北京兆易创新科技股份有限公司 增强存储阵列位线缺陷漏电的方法
CN106601287A (zh) * 2015-10-15 2017-04-26 中芯国际集成电路制造(上海)有限公司 静态随机存取存储器单元、静态随机存取存储器及电子装置

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