WO2023159439A1 - 显示面板及其制作方法、显示装置 - Google Patents

显示面板及其制作方法、显示装置 Download PDF

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Publication number
WO2023159439A1
WO2023159439A1 PCT/CN2022/077756 CN2022077756W WO2023159439A1 WO 2023159439 A1 WO2023159439 A1 WO 2023159439A1 CN 2022077756 W CN2022077756 W CN 2022077756W WO 2023159439 A1 WO2023159439 A1 WO 2023159439A1
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Prior art keywords
base substrate
conductive
reflective
layer
display panel
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PCT/CN2022/077756
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English (en)
French (fr)
Inventor
赵德江
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京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280000260.1A priority Critical patent/CN116965172A/zh
Priority to PCT/CN2022/077756 priority patent/WO2023159439A1/zh
Publication of WO2023159439A1 publication Critical patent/WO2023159439A1/zh

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  • the present disclosure relates to the field of display technology, and in particular, to a display panel, a manufacturing method thereof, and a display device.
  • OLEDs organic light-emitting devices
  • solution-casting methods The fabrication methods of organic functional thin film layers of organic light-emitting devices (OLEDs, organic light-emitting diodes) are divided into vacuum thermal deposition and solution-casting methods.
  • the solution film-forming method is subdivided into methods such as spin coating, ink-jet printing, and screen printing.
  • the inkjet printing method uses a solvent to melt the OLED organic material, and then directly prints the material on the surface of the substrate to form a light-emitting functional layer.
  • the formed luminescent functional layer will affect the quality of the film formation due to the coffee ring effect, etc., and cause uneven luminescence.
  • the purpose of the present disclosure is to provide a display panel that enhances the luminous intensity corresponding to the middle region of the light emitting device, thereby relatively reducing the influence of the edge region on the display quality. .
  • a display panel including a base substrate and a light emitting structure provided on one side of the base substrate, the light emitting structure comprising:
  • a pixel defining structure is provided on one side of the base substrate, and the pixel defining structure defines a plurality of pixel regions arranged in an array;
  • the reflective layer disposed on one side of the base substrate, the reflective layer includes a plurality of reflective portions distributed at intervals, and the reflective portions are located in the pixel area;
  • the first conductive layer is arranged on the side of the reflective layer away from the base substrate, and the first conductive layer includes a plurality of first conductive parts distributed at intervals;
  • the hole injection layer is arranged on the side of the first conductive layer away from the base substrate, the hole injection layer includes a first sub-section and a second sub-section, and the middle part of the pixel area is , the second sub-section is located at the edge portion of the pixel region, and the distance between the middle portion of the pixel region and the pixel defining structure is not less than the distance between the edge portion of the pixel region and the pixel defining structure distance;; in a direction perpendicular to the base substrate, the size of at least a partial area of the second sub-section is larger than the size of the first sub-section;
  • the reflective part corresponds to the first conductive part one by one, and the orthographic projections of the first conductive part and the reflective part on the base substrate at least partially overlap;
  • the orthographic projection of the first subsection on the base substrate overlaps the orthographic projection of the reflection part on the base substrate, and the second The orthographic projection of the sub-section on the base substrate does not overlap with the orthographic projection of the reflective portion on the base substrate; or the orthographic projection of the first sub-section on the base substrate does not overlap with the The orthographic projection of the first conductive portion on the base substrate overlaps, and the orthographic projection of the second sub-portion on the base substrate overlaps with the orthographic projection of the first conductive portion on the base substrate. Projections do not overlap.
  • a first conductive portion is disposed between a side of the first conductive portion close to the pixel defining structure and a side of the corresponding pixel defining structure close to the first conductive portion.
  • the first pitch is 1-3 ⁇ m
  • the second pitch is 1-3 ⁇ m.
  • the light emitting structure further includes:
  • the second conductive layer is arranged between the base substrate and the reflective layer, and the second conductive layer includes a plurality of second conductive parts distributed at intervals;
  • the orthographic projection of the pixel area on the substrate is located within the orthographic projection of the second conductive portion on the substrate;
  • the reflective portion and the second conductive portion correspond to each other in a direction perpendicular to the base substrate, and the orthographic projections of the second conductive portion and the reflective portion on the base substrate are at least partially overlap.
  • the pixel defining structure in a direction perpendicular to the base substrate, has a bottom end close to the base substrate, a top end far away from the base substrate, and a In the middle between the bottom end and the top end, the bottom end of the pixel defining structure defines a plurality of openings, and the middle or top of the pixel defining structure defines a plurality of light outlets, and the openings correspond to expose all the second conductive part;
  • the orthographic projection of the light outlet on the base substrate is located within the orthographic projection of the opening on the base substrate;
  • Orthographic projections of the light outlet, the reflective portion and the first conductive portion on the base substrate at least partially overlap.
  • the pixel defining structure along the direction away from the base substrate, includes a first part and a second part connected in sequence, and the first part is on the base substrate
  • the orthographic projection of is located within the orthographic projection of the second part on the base substrate, and the area of the orthographic projection of the first part on the base substrate is smaller than that of the second part on the base substrate The area of the orthographic projection.
  • the overlapping area of the orthographic projection of the first conductive part and the reflective part on the base substrate and the second part on the base substrate do not overlap;
  • At least a partial area of the orthographic projection of the first distance or the second distance on the base substrate is located within the orthographic projection of the second portion on the base substrate.
  • the height of the first portion is not less than the sum of the thicknesses of the reflective portion and the first conductive portion.
  • the side of the cross-section of the second portion away from the base substrate is convex toward the direction away from the base substrate. out of the arc.
  • a section of the pixel defining structure in a direction perpendicular to the base substrate, is mushroom-shaped.
  • the reflection part has a first surface close to the base substrate, a second surface away from the base substrate, and a the sidewall between the surfaces, the first conductive part is in contact with the sidewall of the reflective part and the second surface.
  • the light emitting structure further includes:
  • a first insulating layer disposed between the reflective layer and the first conductive layer, the first insulating layer includes a plurality of first insulating parts distributed at intervals, and the first insulating parts are located in the pixel area
  • the orthographic projection of the reflective portion on the base substrate is located within the orthographic projection of the first insulating portion on the base substrate.
  • the first insulating portion is in contact with the side wall of the reflection portion and a side surface away from the base substrate, and the first insulating portion is in contact with the second An area where the conductive part is exposed by the reflective part.
  • the light emitting structure further includes:
  • the second insulating layer is arranged on the side of the second conductive layer away from the base substrate, the second insulating layer includes a plurality of second insulating parts distributed at intervals, and the second insulating parts are located at the pixel area, the second insulating portion contacts the area where the second conductive portion is exposed by the reflective portion, and the second insulating portion contacts the first conductive portion and the side wall of the reflective portion, and contacts the At least a part of the surface of the first conductive portion away from the base substrate.
  • the second conductive layer has a thickness of 8-18 nm
  • the reflective layer has a thickness of 60-150 nm
  • the first conductive layer has a thickness of 8-18 nm
  • the pixel-defining structure In a direction perpendicular to the base substrate, the pixel-defining structure has a height of 1.2-2 ⁇ m.
  • the display panel further includes:
  • planarization layer disposed on a side of the light-emitting structure close to the base substrate
  • the first conductive portion is connected to the pixel circuit through a via hole in the planarization layer, and the orthographic projection of the via hole on the base substrate is at least at least the same as the orthographic projection of the pixel defining structure on the base substrate partially overlapped.
  • the first insulating part includes:
  • the third subsection is located on a side of the reflection section away from the base substrate;
  • the fourth subsection is in contact with the second conductive section
  • the fifth subsection is connected between the third subsection and the fourth subsection, the extending direction of the fifth subsection has an included angle with the base substrate, and the included angle is an acute angle .
  • the display panel further includes:
  • planarization layer disposed on a side of the light-emitting structure close to the base substrate
  • An orthographic projection of the first conductive portion on the base substrate at least partially overlaps an orthographic projection of the pixel defining structure on the base substrate;
  • At least a partial area of the first conductive portion is in contact with the planarization layer.
  • the display panel further includes:
  • a first insulating layer located between the reflective layer and the second conductive layer, the first insulating layer includes a plurality of first insulating parts distributed at intervals, and the first insulating parts at least partially cover the first insulating part The part of the second conductive part exposed by the reflective part.
  • a method for manufacturing a display panel including:
  • forming a light-emitting structure on one side of the base substrate includes:
  • a reflective layer is formed on one side of the base substrate, the reflective layer includes a plurality of reflective portions distributed at intervals;
  • first conductive layer on a side of the reflective layer away from the base substrate, the first conductive layer including a plurality of first conductive portions distributed at intervals;
  • a pixel defining structure is formed on one side of the base substrate, the pixel defining structure defines a plurality of pixel areas arranged in an array, and the reflection part is located in the pixel area;
  • a hole injection layer is formed on the side of the first conductive layer away from the base substrate, the hole injection layer includes a first sub-section and a second sub-section, and the first sub-section is located in the pixel area
  • the middle part, the second sub-part is located at the edge part of the pixel area, the distance between the middle part of the pixel area and the pixel defining structure is not less than the edge part of the pixel area and the pixel defining the distance between the structures; in a direction perpendicular to the base substrate, the size of at least a partial area of the second subsection is larger than the size of the first subsection;
  • the reflective part and the first conductive part correspond to each other in a direction perpendicular to the base substrate, and the orthographic projection of the first conductive part and the reflective part on the base substrate at least partially overlap;
  • a first distance is set between one side of the conductive part.
  • forming the pixel defining structure on one side of the base substrate includes:
  • An embedded layer is formed on the side of the first conductive layer away from the base substrate, the embedded layer includes a plurality of embedded parts distributed at intervals, and the embedded parts cover the first conductive part and are far away from the the surface of the base substrate, and the embedded part covers at least the side walls of the first conductive part and the reflective part;
  • the pixel defining structure covering at least part of the top surface of the embedded part and the sidewall of the embedded part;
  • the side of the embedded portion away from the reflective portion and the side of the reflective portion close to the embedded portion The distance between one side is equal to the first distance.
  • a display device including the display panel as described in the first aspect.
  • the pixel defining structure defines a plurality of pixel regions
  • the reflective part is located in the pixel region defined by the pixel defining structure
  • the reflective part or the first conductive part is parallel to the pixel defining structure in a direction parallel to the substrate.
  • the overlapping region of the reflective part and the first conductive part is correspondingly located in the middle region of the second conductive part, and this structure is conducive to enhancing the luminous intensity corresponding to the middle region, thereby relatively reducing the influence of the edge region on the display quality .
  • FIG. 1 is a schematic structural diagram of a display panel in an exemplary embodiment of the present disclosure
  • Fig. 2 is a schematic structural diagram of a display panel in another exemplary embodiment of the present disclosure.
  • Fig. 3 is a schematic structural diagram of a display panel in another exemplary embodiment of the present disclosure.
  • Fig. 4 is a schematic structural diagram of a display panel in another exemplary embodiment of the present disclosure.
  • Fig. 5 is a schematic structural diagram of a display panel in another exemplary embodiment of the present disclosure.
  • Fig. 6 is a schematic structural diagram of a display panel in another exemplary embodiment of the present disclosure.
  • Fig. 7 is a schematic structural diagram of a display panel in another exemplary embodiment of the present disclosure.
  • Fig. 8 is a schematic structural diagram of a display panel in another exemplary embodiment of the present disclosure.
  • Fig. 9 is a schematic structural diagram of a display panel in another exemplary embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of a driving circuit layer structure of a display panel in an exemplary embodiment of the present disclosure.
  • Fig. 11 is a schematic diagram of the formation structure of step S241 in an exemplary embodiment of the present disclosure.
  • Fig. 12 is a schematic diagram of the formation structure of step S242 in an exemplary embodiment of the present disclosure.
  • Fig. 13 is a schematic diagram of the formation structure of step S243 in an exemplary embodiment of the present disclosure.
  • Fig. 14 is an SEM image of the middle part of the pixel area of the display panel in Fig. 3;
  • Fig. 15 is an SEM image of a pixel-defining structure in an exemplary embodiment of the present disclosure
  • Figure 16 is a SEM image of the display panel in Figure 2;
  • FIG. 17 is an SEM image of the portion of the display panel in FIG. 3 that is close to the pixel-defining structure
  • Fig. 18 is a cross-sectional SEM diagram of a connection between a light emitting device and a pixel circuit in an exemplary embodiment of the present disclosure
  • Fig. 19 is a top-view SEM image of an anode connection via hole of a light emitting device in an exemplary embodiment of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided in order to give a thorough understanding of embodiments of the present disclosure.
  • a structure When a structure is "on" another structure, it may mean that a structure is integrally formed on another structure, or that a structure is “directly” placed on another structure, or that a structure is “indirectly” placed on another structure through another structure. other structures.
  • inkjet printing technology is applied to the production and preparation of OLED display panels due to its advantages of high production efficiency and low material cost.
  • Inkjet printing technology is to drop inkjet droplets into the pixel area, and then perform drying treatment to solidify the inkjet droplets to form a light-emitting functional layer.
  • the present disclosure provides a display panel, including a base substrate 1 and a light emitting structure 3 disposed on one side of the base substrate 1 .
  • the light emitting structure 3 includes a pixel defining structure 38 , a reflective layer 32 , a first conductive layer 33 and a hole injection layer 361 .
  • the pixel defining structure 38 is arranged on one side of the base substrate 1, and the pixel defining structure 38 defines a plurality of pixel areas arranged in an array;
  • the reflective layer 32 is arranged on one side of the base substrate 1, and the reflective layer 32 includes a plurality of intervals Distributed reflective portions 321 , the reflective portions 321 are located in the pixel area;
  • the first conductive layer 33 is disposed on the side of the reflective layer 32 away from the base substrate 1 , and the first conductive layer 33 includes a plurality of first conductive portions 331 distributed at intervals.
  • the hole injection layer 361 is disposed on the side of the first conductive layer 33 away from the base substrate 1, the hole injection layer 361 includes a first sub-section 3611 and a second sub-section 3612, and the first sub-section 3611 is located in the middle part of the pixel area , the second sub-section 3612 is located at the edge portion of the pixel region, the distance between the middle portion of the pixel region and the pixel defining structure 38 is not less than the distance between the edge portion of the pixel region and the pixel defining structure 38; 1, the size of at least a partial area of the second sub-section 362 is greater than that of the first sub-section 361 .
  • the reflective part 321 corresponds to the first conductive part 331 one by one, and the orthographic projections of the first conductive part 331 and the reflective part 321 on the base substrate 1 at least partially overlap; in a direction parallel to the base substrate 1, the reflective A first distance L1 is provided between a side of the portion 321 close to the pixel defining structure 38 and a side of the corresponding pixel defining structure 38 close to the reflecting portion 321 .
  • the pixel defining structure 38 defines a plurality of pixel regions, the reflecting part 321 is located in the pixel region defined by the pixel defining structure 38, and the reflecting part 321 or the first conductive part 331 is parallel to the base substrate 1 There is a distance from the pixel defining structure 38 in the direction. That is, the overlapping area of the reflective portion 321 and the first conductive portion 331 corresponds to the middle area of the light emitting structure, and this structure is conducive to enhancing the luminous intensity corresponding to the middle area, so as to relatively reduce the influence of the edge area on the display quality.
  • the reflective portion 321 or the first conductive portion 331 there is a distance between the reflective portion 321 or the first conductive portion 331 and the pixel defining structure 38 . Edge regions of the formed reflective portion 321 or the first conductive portion 331 may be stepped. This structural design helps to improve the thickness and flatness at the edge of the film layer when other film layers are subsequently formed by inkjet printing, thereby helping to improve the impact of the coffee ring effect on display quality in the related art.
  • an embodiment of the present disclosure provides a display panel, which can be an OLED (Organic Light-Emitting Diode, organic light-emitting diode) display panel or a QLED (Quantum Dot Light Emitting Diodes, quantum dot light-emitting diode) display panel.
  • the display panel includes a base substrate 1 and a light emitting structure 3 disposed on one side of the base substrate 1 , the light emitting structure 3 includes a pixel defining structure 38 , a reflective layer 32 and a first conductive layer 33 .
  • the base substrate 1 may be a base substrate of inorganic material, or a base substrate of organic material.
  • the material of the base substrate 1 can be glass materials such as soda-lime glass, quartz glass, sapphire glass, or can be stainless steel, aluminum, nickel, etc. metallic material.
  • the material of the base substrate 1 can be polymethyl methacrylate (Polymethyl methacrylate, PMMA), polyvinyl alcohol (Polyvinyl alcohol, PVA), polyvinyl phenol (Polyvinyl phenol, PVP), polyethersulfone (Polyether sulfone, PES), polyimide, polyamide, polyacetal, polycarbonate (Polycarbonate, PC), polyethylene terephthalate (Polyethylene terephthalate, PET), Polyethylene naphthalate (PEN) or a combination thereof.
  • the base substrate 1 may also be a flexible base substrate 1 , for example, in one embodiment of the present disclosure, the material of the base substrate 1 may be polyimide (PI).
  • the base substrate 1 can also be a composite of multi-layer materials.
  • the base substrate 1 can include a bottom film layer (Bottom Film), a pressure-sensitive adhesive layer, A first polyimide layer and a second polyimide layer.
  • the light emitting structure 3 is disposed on one side of the base substrate 1 , and the light emitting structure 3 can be used to form a light emitting device to complete picture display.
  • the light emitting structure 3 includes a pixel defining structure 38 , a reflective layer 32 and a first conductive layer 33 .
  • the pixel defining structure 38 is disposed on one side of the base substrate 1 , and the pixel defining structure 38 defines a plurality of pixel regions arranged in an array.
  • the shape of the orthographic projection of the pixel area on the substrate 1 may be a polygon, a smooth curved closed figure or other figures, which is not limited in this disclosure.
  • the reflective layer 32 is disposed on one side of the base substrate 1 , and the reflective layer 32 includes a plurality of reflective portions 321 distributed at intervals, and the reflective portions 321 are located in the pixel area.
  • the material of the reflective layer 32 may include conductive materials, such as conductive metal materials or alloy materials. In an embodiment, the material of the reflective layer 32 may include metal materials such as silver and aluminum.
  • the first conductive layer 33 is disposed on a side of the reflective layer 32 away from the base substrate 1 .
  • the first conductive layer 33 includes a plurality of first conductive portions 331 distributed at intervals.
  • the first conductive portion 331 corresponds to the reflective portion 321 in a one-to-one correspondence in a direction perpendicular to the base substrate 1 , that is, in a one-to-one correspondence in the Y direction.
  • Orthographic projections of the first conductive portion 331 and the reflective portion 321 on the base substrate 1 are at least partially overlapped.
  • the orthographic projection of the reflective portion 321 on the base substrate 1 may be located within the orthographic projection of the first conductive portion 331 on the base substrate 1 , or be different from the orthographic projection of the first conductive portion 331 on the base substrate 1 fully overlapped.
  • completely overlapping means that the shapes, sizes and positions are substantially the same.
  • the reflection portion 321 has a first surface close to the base substrate 1 and a second surface far away from the base substrate 1 , and is located between the first surface and the second surface.
  • the first conductive portion 331 contacts the second surface and the sidewall of the reflective portion 321 , and the first conductive portion 331 extends to the bottom end of the pixel defining structure 38 , that is, an end close to the base substrate 1 .
  • the orthographic projection of the reflection part 321 on the base substrate 1 may be located within the orthographic projection of the first conductive part 331 on the base substrate 1 .
  • the first conductive layer 33 can be made of a transparent conductive material, such as ITO (indium tin oxide), IZO (indium zinc oxide) and the like.
  • the first conductive layer 33 may have a single-layer or multi-layer structure. In one embodiment, the first conductive layer 33 has a single-layer structure and is made of ITO material.
  • the reflective portion 321 is located in the pixel area, and the reflective portion 321 and the first conductive portion 331 at least partially overlap. This structure helps to improve the reflectivity of the light emitted by the light-emitting device through the reflective portion 321, and enhance the light emission. Luminous intensity of the device.
  • the light emitting structure 3 further includes a second conductive layer 31 .
  • the second conductive layer 31 is disposed between the base substrate 1 and the reflective layer 32 , and the second conductive layer 31 includes a plurality of second conductive portions 311 distributed at intervals. A plurality of second conductive portions 311 are arranged in an array.
  • the second conductive layer 31 can be made of a transparent conductive material, such as ITO (indium tin oxide), IZO (indium zinc oxide) and the like.
  • the orthographic projection of the second conductive portion 311 on the base substrate 1 may be a circle, an ellipse, a regular polygon, or an irregular curved side or a polygon, which is not limited in this disclosure.
  • the second conductive layer 31 may be a single-layer or multi-layer structure. In one embodiment, the second conductive layer 31 is a single-layer structure made of ITO material.
  • the first conductive portion 331 may not extend to the bottom of the pixel defining structure 38 , and may only contact the first portion of the reflective portion 321 away from the base substrate 1 .
  • the two surfaces, and the corner of the second surface and the sidewall of the reflective portion 321 are shown in FIG. 16 .
  • the first conductive portion 331 may include a sub-conductive portion 3311 in contact with the second surface of the reflective portion 321 and a sub-conductive portion 3311 in contact with the second surface of the reflective portion 321 .
  • the non-contact sub-conductive portion 3312 has an included angle between the extending direction of the sub-conductive portion 3312 and the second conductive portion 311 , and the included angle is an acute angle.
  • the pixel defining structure 38 is disposed on one side of the base substrate 1 , and the pixel defining structure 38 defines a plurality of pixel regions arranged in an array. Each pixel region exposes each second conductive portion 311 in a one-to-one correspondence.
  • the orthographic projection of the pixel area on the base substrate 1 is located within the orthographic projection of the second conductive portion 311 on the base substrate 1 . That is, the range of the pixel area is located within the boundary of its corresponding second conductive portion 311 .
  • the reflective portion 321 corresponds to the second conductive portion 311 in a one-to-one correspondence in a direction perpendicular to the base substrate 1 , that is, in a one-to-one correspondence in the Y direction. Orthographic projections of the second conductive portion 311 and the reflective portion 321 on the base substrate 1 overlap at least partially.
  • the orthographic projection of the reflective portion 321 on the base substrate 1 is located within the orthographic projection of the second conductive portion 311 on the base substrate 1, and the area of the orthographic projection of the reflective portion 321 is smaller than that of the second conductive portion 311 is the area exposed by the pixel area.
  • the reflective portion 321 or the first conductive portion 331 is close to the side of the pixel defining structure 38 and the corresponding pixel defining structure 38 is close to the reflective portion.
  • a distance is provided between the portion 321 or one side of the first conductive portion 331 .
  • the side of the reflective portion 321 close to the pixel defining structure 38 and the corresponding pixel defining structure 38 close to the reflective portion 321 A first distance L1 is set between one side of the .
  • the display panel further includes the second conductive portion 311 , no reflective portion 321 is disposed above the area of the second conductive portion 311 corresponding to the first distance L1 .
  • the size of the first distance L1 can be set according to the actual situation.
  • the size of the first distance L1 may be 1-3 ⁇ m, specifically 1.1 ⁇ m, 1.2 ⁇ m, 1.3 ⁇ m, 1.4 ⁇ m, 1.5 ⁇ m, 1.7 ⁇ m, 1.9 ⁇ m, 2 ⁇ m, 2.1 ⁇ m, 2.2 ⁇ m, 2.3 ⁇ m, 2.4 ⁇ m, 2.5 ⁇ m, 2.7 ⁇ m, 2.9 ⁇ m, or 3 ⁇ m, etc., but not limited thereto.
  • the orthographic projection of the first conductive portion 331 on the base substrate 1 is located within the orthographic projection of the second conductive portion 311 on the base substrate 1, and the area of the orthographic projection of the first conductive portion 331 is smaller than The area of the second conductive portion 311 exposed by the pixel region.
  • a second distance L2 is provided between a side of the first conductive portion 331 close to the pixel defining structure 38 and a side of the corresponding pixel defining structure 38 close to the first conductive portion 331 .
  • no first conductive portion 331 is disposed above the area of the second conductive portion 311 corresponding to the second distance L2 .
  • the size of the second interval can be set according to actual conditions.
  • the size of the second pitch can be 1-3 ⁇ m, specifically 1.1 ⁇ m, 1.2 ⁇ m, 1.3 ⁇ m, 1.4 ⁇ m, 1.5 ⁇ m, 1.7 ⁇ m, 1.9 ⁇ m, 2 ⁇ m, 2.1 ⁇ m, 2.2 ⁇ m , 2.3 ⁇ m, 2.4 ⁇ m, 2.5 ⁇ m, 2.7 ⁇ m, 2.9 ⁇ m or 3 ⁇ m, etc., but not limited thereto.
  • the first distance L1 is equal to the sum of the second distance L2 and the thickness of the first conductive portion 331 .
  • the second conductive layer 31 , the reflective layer 32 and the first conductive layer 33 are all film layers with a certain thickness.
  • the thickness of the reflective layer 32 is not less than the thickness of the second conductive layer 31 and the first conductive layer 33 .
  • the thickness of the second conductive layer 31 is 8-18nm, specifically 8nm, 10nm, 12nm, 13nm, 15nm, 16nm, 17nm or 18nm, but not limited thereto.
  • the reflective layer 32 has a thickness of 60-150nm, specifically 60nm, 65nm, 70nm, 75nm, 80nm, 85nm, 90nm, 95nm, 100nm, 105nm, 115nm, 120nm, 125nm, 130nm, 135nm, 140nm, 145nm or 150nm, but Not limited to this.
  • the thickness of the first conductive layer 33 is 8-18nm, specifically 8nm, 10nm, 12nm, 13nm, 15nm, 16nm, 17nm or 18nm, but not limited thereto.
  • the light emitting structure 3 includes a plurality of light emitting devices, and each light emitting device is located in a pixel area.
  • the light emitting device may be OLED or QLED or the like.
  • the first conductive part 331 and the reflective part 321 can be used as the anode of the light emitting device; in other embodiments, the second conductive part 311, the reflective part 321 and the first conductive part 331 can be used as the anode of the light emitting device . In some other embodiments, the first conductive part 331 can be used as an anode of the light emitting device.
  • the light emitting structure 3 further includes a light emitting functional layer 36 and a third conductive layer 37 .
  • the light-emitting functional layer 36 is disposed on the side of the first conductive layer 33 away from the base substrate 1 .
  • the light-emitting functional layer 36 may be formed by an inkjet printing method.
  • the light-emitting functional layer 36 is a multi-layer structure. Along the direction away from the substrate 1, the light-emitting functional layer 36 includes a hole injection layer 361, a hole transport layer 362, a light-emitting material layer 363, and an electron transport layer 364.
  • the luminescent material layer 363 may be an organic luminescent material layer or a quantum dot luminescent material layer.
  • the light-emitting functional layer 36 includes a plurality of light-emitting functional parts, and the light-emitting functional parts are located in each pixel area in a one-to-one correspondence.
  • the thickness of the light-emitting functional layer 36 may be 200-500 nm, and the specific thickness may be set according to actual conditions.
  • the light-emitting functional layer 36 may further include an electron injection layer disposed on a side of the electron transport layer 364 away from the base substrate 1 .
  • the hole injection layer 361 is disposed on a side of the first conductive layer 33 away from the base substrate 1 , and the hole injection layer 361 includes a first subsection 3611 and a second subsection 3612 .
  • the first sub-section 3611 is located in the middle part of the pixel area
  • the second sub-section 3612 is located in the edge part of the pixel area
  • the middle part of the pixel area is in contact with the pixel defining structure 38
  • the distance between them is not smaller than the distance between the edge portion of the pixel region and the pixel defining structure 38 .
  • the orthographic projection of the first sub-part 3611 on the base substrate 1 overlaps with the orthographic projection of the reflection part 321 on the base substrate 1, and the second The orthographic projection of the sub-section 362 on the base substrate 1 does not overlap with the orthographic projection of the reflection portion 321 on the base substrate 1, or as shown in FIG. 5 , the orthographic projection of the first sub-section 3611 on the base substrate 1 It overlaps with the orthographic projection of the first conductive portion 331 on the base substrate 1 , and the orthographic projection of the second sub-portion 3612 on the base substrate 1 does not overlap with the orthographic projection of the first conductive portion 331 on the base substrate 1 .
  • the size of at least a partial area of the second subsection 3612 is larger than that of the first subsection 3611 .
  • the third conductive layer 37 is disposed on a side of the light emitting functional layer 36 away from the base substrate 1 .
  • the third conductive layer 37 may serve as a cathode of the light emitting device.
  • the third conductive layer 37 may be a single-layer or multi-layer structure, and its material may include one or more of conductive metals, metal oxides and alloys.
  • the third conductive layer 37 is a continuous conductive layer covering the light-emitting functional layer 36 and the pixel-defining structure 38 of each light-emitting device, that is, the third conductive layer 37 is on the base substrate
  • the orthographic projection of 1 covers the respective pixel area and the orthographic projection of the pixel-defining structure 38 on the base substrate 1 .
  • the third conductive layer 37 is recessed into the pixel area at the place corresponding to the pixel area, that is, the third conductive layer 37 is recessed in the direction close to the base substrate 1 at the place corresponding to the pixel area.
  • the display quality of the display panel in addition to improving the luminous intensity of the middle region through the above-mentioned embodiments and relatively reducing the influence of the edge region on the display quality, the display quality of the display panel can be further improved in other ways.
  • the reflection part 321 and the first conductive part 331 serve as the anode of the light emitting device.
  • the second conductive part 311 , the reflective part 321 and the first conductive part 331 serve as the anode of the light emitting device.
  • the first conductive portion 331 is in contact with the side wall of the reflective portion 321 and the surface of the side away from the base substrate 1 . That is, the first conductive portion 331 wraps the reflective portion 321 .
  • the reflective part 321 is usually a film layer with a certain thickness made of metal material. The edge rigidity of the film layer is relatively high, which may cause damage to the film layer formed later, such as scratching and breaking.
  • the first conductive portion 331 wraps the reflective portion 321 to help prevent breakage when forming subsequent film layers.
  • the first conductive portion 331 can further extend to the bottom of the pixel defining structure 38 , and the first conductive portion 331 and the reflective portion 321 are in contact with each other to form an anode of the light emitting device.
  • the first conductive portion 331 may or may not extend to the bottom of the pixel defining structure 38 , which is not limited in this disclosure.
  • the first conductive part 331 , the reflective part 321 and the second conductive part 311 are in contact with each other to form an anode of the light emitting device.
  • the specific shape of the pixel defining structure 38 can be improved to limit the emission of light at the edge of the light emitting device in the pixel area.
  • the above purpose can be achieved by changing the size of the pixel defining structure 38 in a direction parallel to the base substrate 1 .
  • the pixel defining structure 38 has a bottom end close to the base substrate 1 , a top end far away from the base substrate 1 , and a middle portion between the bottom end and the top end.
  • the bottom end of the pixel defining structure 38 defines a plurality of openings 01 .
  • the opening 01 exposes a partial area of the second conductive portion 311 .
  • the middle or top of the pixel defining structure 38 defines a plurality of light outlets 02.
  • the range of the light outlet 02 is smaller than the range of the opening 01 , that is, the orthographic projection of the light outlet 02 on the base substrate 1 is within the orthographic projection of the opening 01 on the base substrate 1 .
  • the orthographic projections of the light outlet 02 , the reflective portion 321 , and the first conductive portion 331 on the base substrate 1 are at least partially overlapped.
  • the overlapping area of the orthographic projection of the reflective portion 321 and the first conductive portion 331 on the base substrate 1 completely overlaps the orthographic projection of the light outlet 02 on the base substrate 1 .
  • the orthographic projection of the light outlet 02 on the base substrate 1 is located within the orthographic projection of the reflective portion 321 and the first conductive portion 331 on the base substrate 1 .
  • the pixel defining structure 38 can block the light that may be emitted from the area corresponding to the edge position of the second conductive portion 311 , so as to prevent this part of the area from affecting the microcavity effect.
  • the specific pattern of the pixel defining structure 38 can be set according to actual needs.
  • the pixel defining structure 38 along the direction away from the base substrate 1, the pixel defining structure 38 includes a first portion 381 and a second portion 382 connected in sequence, and the orthographic projection of the first portion 381 on the base substrate 1 is located at the second portion 382 is within the orthographic projection on the base substrate 1 , and the area of the orthographic projection of the first portion 381 on the base substrate 1 is smaller than the area of the orthographic projection of the second portion 382 on the base substrate 1 .
  • the second portion 382 of the pixel defining structure 38 defines the range of the light outlet 02
  • the end of the first portion 381 close to the base substrate 1 defines the range of the opening 01 .
  • the overlapping area of the orthographic projection of the first conductive portion 331 and the reflective portion 321 on the base substrate 1 does not overlap with the orthographic projection of the second portion 382 on the base substrate 1; and the first distance L1 or the second distance L2 At least a part of the orthographic projection on the base substrate 1 is located within the orthographic projection of the second portion 382 on the base substrate 1 . That is, the second portion 382 of the pixel defining structure 38 is used to block the light that may be emitted from the region corresponding to the edge position of the second conductive portion 311 .
  • the height of the first portion 381 is not less than the sum of the thicknesses of the reflective portion 321 and the first conductive portion 331 . That is, in a direction perpendicular to the base substrate 1 , the formed reflective portion 321 and the first conductive portion 331 are roughly located on a side of the second portion 382 close to the base substrate 1 . Further, the height of the first portion 381 is greater than the sum of the thicknesses of the reflective portion 321 and the first conductive portion 331 .
  • the cross section of the first portion 381 in a direction perpendicular to the base substrate 1 , is roughly rectangular, and of course it can also be trapezoidal or irregular polygonal.
  • the side of the cross-section of the second portion 382 away from the base substrate 1 is an arc protruding toward the direction away from the base substrate 1. This curved design helps to avoid breakage of subsequent film layers, such as the cathode layer.
  • the section of the pixel defining structure 38 is mushroom-shaped. In the present disclosure, the mushroom shape is roughly an open umbrella-shaped structure, the bottom is roughly cylindrical, and the top is roughly hemispherical. In practical applications, the specific shape of the pixel defining structure 38 may be shown in FIG. 15 , which is a scanning electron microscope (SEM) image of the actual pixel defining structure 38 .
  • SEM scanning electron microscope
  • the height of the pixel defining structure 38 is 1.2-2 ⁇ m. Specifically, it may be 1.2 ⁇ m, 1.3 ⁇ m, 1.4 ⁇ m, 1.5 ⁇ m, 1.6 ⁇ m, 1.7 ⁇ m, 1.8 ⁇ m, 1.9 ⁇ m or 2 ⁇ m, but not limited thereto.
  • the first conductive portion 331 may serve as an anode of the light emitting device.
  • the display panel further includes a first insulating layer 34 .
  • the first insulating layer 34 is disposed between the reflective layer 32 and the first conductive layer 33 , and the first insulating layer 34 includes a plurality of first insulating portions 341 distributed at intervals.
  • the first conductive part 331, the first insulating part 341, the reflective part 321 and the second conductive part 311 correspond to each other in a direction perpendicular to the base substrate 1, and each first insulating part 341 is located in each pixel area in a one-to-one correspondence. .
  • the first insulating portion 341 is located in the pixel area, and the orthographic projection of the reflective portion 321 on the base substrate 1 is located within the orthographic projection of the first insulating portion 341 on the base substrate 1 .
  • the thickness of the first insulating layer 34 is 30-100nm, specifically 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm, 65nm, 70nm, 75nm, 80nm, 85nm, 90nm, 95nm or 100nm, but not limited thereto.
  • the material of the first insulating layer 34 includes inorganic materials, such as silicon nitride or silicon dioxide.
  • the first insulating portion 341 contacts the side wall of the reflective portion 321 and the side surface away from the base substrate 1 , and the first The insulating part 341 contacts the area of the second conductive part 311 exposed by the reflective part 321 . That is, the first insulating part 341 insulates and isolates the second conductive part 311, the reflective part 321 and the first conductive part 331, so that the first conductive part 331 is used as the anode of the light emitting device.
  • the orthographic projection of the first conductive portion 331 on the base substrate 1 may completely overlap the orthographic projection of the reflective portion 321 on the base substrate 1 , that is, in a direction parallel to the base substrate 1 ,
  • the width of the first conductive portion 331 is substantially equal to the width of the reflective portion 321 .
  • the first insulating portion 341 contacts the surface of the reflective portion 321 away from the base substrate 1 .
  • the first insulating portion 341 does not contact the area of the second conductive portion 311 exposed by the reflective portion 321 , but only contacts the surface of the reflective portion 321 away from the base substrate 1 .
  • the orthographic projections of the first conductive portion 331 , the first insulating portion 341 , and the reflective portion 321 on the base substrate 1 completely overlap each other. That is, the shapes, sizes and positions of the orthographic projections of the first conductive part 331 , the first insulating part 341 and the reflective part 321 on the base substrate 1 are substantially the same.
  • the display panel further includes a second insulating layer 35, which is disposed on the side of the second conductive layer 31 away from the base substrate 1.
  • the second insulating layer 35 includes a plurality of second insulating portions 351 distributed at intervals.
  • the second insulating portion 351 is located in the pixel region, the second insulating portion 351 contacts the area of the second conductive portion 311 exposed by the reflective portion 321 , and the second insulating portion 351 contacts the first conductive portion 331 , the first insulating portion 341 and the reflective portion 321 and contact at least part of the surface of the first conductive portion 331 away from the base substrate 1 , so as to prevent the reflection portion 321 from being oxidized.
  • the area of the second conductive part 311 exposed by the reflective part 321 is covered by the second insulating part 351, and the reflective part 321 is covered by the first insulating part 341, so that the first conductive part 331 can be used as the anode of the light emitting device .
  • the thickness of the second insulating layer 35 is 10-20nm, specifically 10nm, 11nm, 12nm, 13nm, 14nm, 15nm, 16nm, 17nm, 18nm, 19nm or 20nm, but not limited thereto.
  • the material of the second insulating layer 35 includes inorganic materials, such as silicon nitride or silicon dioxide.
  • the shape and size of the second insulating portion 351 can be set according to the first distance L1 or the second distance L2 .
  • the size of the second insulating portion 351 in a direction parallel to the base substrate 1 , is substantially equal to the first distance L1 . That is, in the X direction, the width of the second insulating portion 351 is approximately equal to the first distance L1.
  • the height of the second insulating portion 351 is approximately the sum of the thicknesses of the first conductive portion 331 , the first insulating portion 341 and the reflective portion 321 .
  • the second insulating portion 351 may cover a part of the sidewall of the pixel defining structure 38 close to the reflective portion 321 or the first conductive portion 331 .
  • the shape of the second insulating portion 351 is a groove shape.
  • the display panel when the display panel further includes the second insulating layer 35, the display panel may not include the first insulating layer 34.
  • the first conductive part 331, the reflective part 321 and part of the second insulating layer The second conductive part 311 can be used as an anode of the light emitting device.
  • the present disclosure can also limit the light emission in the edge region of the light emitting device by adjusting the positional relationship of each film layer and the like.
  • the first insulating layer 34 is located between the reflective layer 32 and the second conductive layer 31, and the first insulating layer 34 includes a plurality of first insulating portions 341 distributed at intervals.
  • the first insulating part 341 contacts the part of the second conductive part 311 exposed by the reflective part 321 .
  • the first conductive part 331 and the reflective part 321 can serve as an anode of the light emitting device.
  • the specific shape of the pixel defining structure 38 is not particularly limited, and it can adopt a columnar, inverted trapezoidal and other structures commonly used in the field.
  • the cross section of the pixel defining structure 38 is a cylindrical shape with a circular arc at the top.
  • the shape of the pixel defining structure 38 may also adopt the mushroom-shaped pixel defining structure 38 in the foregoing embodiments, which is not specifically limited in the present disclosure.
  • the edge regions of the second conductive portion 311 , the reflective portion 321 and the first conductive portion 331 of the light emitting device have a stepped shape.
  • This structural design helps to improve the thickness and smoothness at the edge of the film layer when the luminescent functional layer 36 is formed by inkjet printing, as shown in FIG. 14 .
  • FIG. 14 may correspond to the embodiment shown in FIG. 3 or FIG. 4 .
  • FIG. 14 is an SEM image of various film layers formed at the edge of the light emitting device, that is, on the side close to the pixel defining structure. It can be seen from the figure that at the edge position A, the thickness of each formed film layer is normal, and the flatness is good, such as the hole injection layer 361, the hole transport layer 362, the light emitting material layer 363 and the electron transport layer 364 wait. Therefore, it is helpful to improve the influence on the display quality caused by the coffee ring effect in the related art.
  • the formed first insulating portion 341 includes a third sub-portion 3411 , a fourth sub-portion 3412 and a fifth sub-portion 3413 .
  • the third sub-section 3411 is located on the side of the reflective portion 321 away from the base substrate 1; the fourth sub-section 3412 is in contact with the second conductive portion 311; the fifth sub-section 3413 is connected to the third sub-section 3411 and the fourth sub-section 3412, the extending direction of the fifth sub-portion 3413 has an included angle ⁇ with the base substrate 1, and the included angle ⁇ is an acute angle.
  • FIG. 14 only shows the SEM image of the film layer structure of the middle part of the pixel region as shown in the embodiment shown in ⁇ 3 or FIG.
  • the first conductive portion 331 is not provided near the pixel defining structure 38 , that is, there is a distance between the first conductive portion 331 and the pixel defining structure 38 .
  • the display panel further includes a driving circuit layer 2 disposed between the base substrate 1 and the light emitting structure 3 .
  • the driving circuit layer 2 includes a driving circuit, and the driving circuit includes a pixel circuit, and the pixel circuit is used to drive the light emitting device 30 of the display panel to emit light.
  • the pixel circuit may be a 7T1C, 7T2C, 6T1C or 6T2C pixel circuit, and its structure is not specifically limited here.
  • nTmC indicates that a pixel circuit includes n transistors (indicated by the letter "T") and m capacitors (indicated by the letter "C").
  • the pixel circuits are connected to the light emitting devices 30 in a one-to-one correspondence to drive the light emitting devices 30 to emit light.
  • the driving circuit layer 2 may be composed of a multi-layer film structure. Taking the transistor in the driving circuit as an example of a top-gate thin film transistor, the driving circuit layer 2 includes an active layer 21, a first gate insulating layer 22, a first gate metal layer 23, a second gate insulating layer 24, a second gate metal Layer 25, interlayer dielectric layer 26 and source drain layer 27.
  • the active layer 21 is arranged on one side of the base substrate 1; the first gate insulating layer 22 is arranged on the side of the active layer 21 away from the base substrate 1, and the first gate insulating layer 22 covers the active layer 21;
  • the metal layer 23 is disposed on the side of the first gate insulating layer 22 away from the substrate 1, the first gate metal layer 23 is used to form the first plate of the capacitor C and the gate of the transistor T;
  • the second gate insulating layer 24 is disposed On the side of the first gate metal layer 23 away from the base substrate 1, the second gate insulating layer 24 covers the first gate metal layer 23;
  • the second gate metal layer 25 is disposed on the side of the first gate insulating layer 22 away from the base substrate 1
  • One side, and is arranged opposite to the first plate, the second gate metal layer 25 is used to form the second plate of the capacitor C;
  • the interlayer dielectric layer 26 is arranged on the second gate metal layer 25 away from the base substrate 1 side, the interlayer dielectric layer 26 covers the second gate metal layer
  • the driving circuit layer 2 further includes a buffer layer BFL disposed between the active layer 21 and the base substrate 1 .
  • the display panel further includes a planarization layer PLN.
  • the planarization layer PLN is disposed on the side of the light emitting structure 3 close to the substrate 1 , and the anode 301 of the light emitting device 30 can be connected to the pixel circuit through the via holes in the planarization layer PLN to drive the light emitting device 30 to emit light.
  • the light-emitting device 30 can pass any one of the first conductive part 331, the reflective part 321 and the second conductive part 311 It is connected with the source/drain of the transistor in the pixel circuit through the via hole.
  • the actual connection method can be referred to as shown in FIG. 18.
  • the light emitting device is connected to the source/source of the transistor in the pixel circuit through the via hole 5 through any one of the first conductive part 331, the reflective part 321 and the second conductive part 311. drain connection.
  • the first conductive part 331 When the first conductive part 331 is used as the anode 301 of the light emitting device 30, the first conductive part 331 can be connected to the source/drain of the transistor in the pixel circuit through the via hole.
  • the first conductive part 331 and the reflective part 321 are used as the anode 301 of the light emitting device 30, the first conductive part 331 or the reflective part 321 can be connected to the source/drain of the transistor in the pixel circuit through the via hole.
  • the first conductive part 331 is connected to the pixel circuit through the via hole 5 in the planarization layer PLN, and the orthographic projection of the via hole 5 on the base substrate 1 is the same as
  • the orthographic projections of the pixel-defining structures 38 on the base substrate 1 overlap at least partially.
  • the orthographic projection of the via hole on the base substrate 1 It can also at least partially overlap with the orthographic projection of the pixel defining structure 38 on the base substrate 1 .
  • disposing the via hole in the planarization layer PLN at the position of the pixel defining structure 38 helps to improve the aperture ratio of the display panel to a certain extent.
  • the microscope only turns on the top light and does not turn on the bottom light, and the reflection part 321 reflects light, so the brightness is relatively high.
  • Some regions of the pixel defining structure 38 correspond to light-shielding structures, while some regions do not have light-shielding structures. Therefore, it presents different brightness in different regions.
  • the regions with light-shielding structures are dark in color, while those without Areas are brightly colored.
  • the present disclosure also provides a method for manufacturing a display panel, including:
  • Step S100 providing a base substrate 1;
  • Step S200 forming a light emitting structure 3 on one side of the base substrate 1;
  • step S200 includes:
  • Step S210 forming a reflective layer 32 on one side of the base substrate 1, the reflective layer 32 includes a plurality of reflective portions 321 distributed at intervals;
  • Step S220 forming a first conductive layer 33 on the side of the reflective layer 32 away from the base substrate 1, the first conductive layer 33 includes a plurality of first conductive portions 331 distributed at intervals;
  • Step S230 forming a pixel defining structure 38 on one side of the base substrate 1, the pixel defining structure 38 defines a plurality of pixel areas arranged in an array, and the reflective part 321 is located in the pixel area;
  • Step S240 forming a hole injection layer 361 on the side of the first conductive layer 33 away from the base substrate 1, the hole injection layer 361 includes a first sub-section 3611 and a second sub-section 3612, and the first sub-section 3611 is located in the pixel area
  • the middle part, the second sub-part 3612 is located at the edge part of the pixel area, the distance between the middle part of the pixel area and the pixel defining structure 38 is not less than the distance between the edge part of the pixel area and the pixel defining structure 38;
  • the size of at least part of the second subsection 3612 is larger than the size of the first subsection 3611;
  • the reflective portion 321 corresponds to the first conductive portion 331 one-to-one, and the orthographic projections of the first conductive portion 331 and the reflective portion 321 on the base substrate 1 at least partially overlap;
  • step S240 includes:
  • an embedded layer 4 is formed on the side of the first conductive layer 33 away from the base substrate 1.
  • the embedded layer 4 includes a plurality of embedded portions 41 distributed at intervals.
  • the embedded portion 41 covers the first conductive layer 41.
  • a conductive portion 331 is away from the surface of the base substrate 1 , and the embedded portion 41 covers at least the sidewalls of the first conductive portion 331 and the reflective portion 321 .
  • the material of the embedded layer 4 may include metal material.
  • the distance between the side of the embedded portion 41 away from the reflective portion 321 and the side of the reflective portion 321 close to the embedded portion 41 is equal to the first distance L1; In the direction of the base substrate 1 , the distance between the side of the embedded portion 41 away from the first conductive portion 331 and the side of the first conductive portion 331 close to the embedded portion 41 is equal to the second distance L2 .
  • the first distance L1 may be the sum of the second distance L2 and the thickness of the first conductive layer 33 .
  • step S242 as shown in FIG. 12 , a pixel defining structure 38 is formed, and the pixel defining structure 38 covers at least part of the top surface of the embedded part 41 and the sidewall of the embedded part 41 ;
  • Step S243 as shown in FIG. 13 , removing the embedded layer 4 .
  • Embodiments of the present disclosure also provide a display device, including a display panel.
  • the display panel may be the display panel in any of the above embodiments.
  • the display device of the present disclosure may be electronic equipment such as a mobile phone, a tablet computer, and a television, which will not be listed here.

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Abstract

本公开提供了一种显示面板及其制作方法、显示装置，属于显示技术领域。该显示面板包括衬底基板(1)和发光结构(3)，发光结构(3)包括像素限定结构(38)、反射层(32)和第一导电层(33)。反射层(32)包括多个间隔分布的反射部(321)；第一导电层(33)包括多个间隔分布的第一导电部(331)。在平行于衬底基板(1)方向上，反射部(321)或第一导电部(331)靠近像素限定结构(38)的一侧与对应的像素限定结构(38)靠近该反射部(321)或该第一导电部(331)的一侧之间设置有间距。

Description

显示面板及其制作方法、显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板及其制作方法、显示装置。
背景技术
有机发光器件(OLED，organic l ight-emitting diode)的有机功能薄膜层的制作方法分为真空热蒸镀(vacuum thermal deposition)与溶液成膜法(solution-castingmethod)。溶液成膜法又细分为旋涂法(spin coating)、喷墨打印(ink-jet printing)、丝网印刷(screen printing)等方法。
喷墨打印法是使用溶剂将OLED有机材料融化，然后将材料直接喷印在衬底基板表面形成发光功能层。然而，受到打印技术自身特性的约束，形成的发光功能层会由于咖啡环效应等，影响成膜质量，并导致发光不均匀。
所述背景技术部分公开的上述信息仅用于加强对本公开的背景的理解，因此它可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于提供一种显示面板，增强发光器件中间区域对应的发光强度，从而在相对程度上降低边缘区域对显示质量的影响。。
为实现上述发明目的，本公开采用如下技术方案：
根据本公开的第一个方面，提供一种显示面板，包括衬底基板和设于所述衬底基板一侧的发光结构，所述发光结构包括：
像素限定结构，设于所述衬底基板的一侧，所述像素限定结构界定出多个阵列排列的像素区域；
反射层，设于所述衬底基板的一侧，所述反射层包括多个间隔分布的反射部，所述反射部位于所述像素区域内；
第一导电层，设于所述反射层远离所述衬底基板的一侧，所述第一 导电层包括多个间隔分布的第一导电部；
空穴注入层，设于所述第一导电层远离所述衬底基板的一侧，所述空穴注入层包括第一子部和第二子部，所述位于所述像素区域的中间部分，所述第二子部位于所述像素区域的边缘部分，所述像素区域的中间部分与所述像素限定结构之间的距离不小于所述像素区域的边缘部分与所述像素限定结构之间的距离；；在垂直于所述衬底基板的方向上，所述第二子部的至少部分区域的尺寸大于所述第一子部的尺寸；
其中，所述反射部和所述第一导电部一一对应，且所述第一导电部、所述反射部在所述衬底基板上的正投影至少部分交叠；
在平行于所述衬底基板方向上，所述反射部或所述第一导电部靠近所述像素限定结构的一侧与对应的所述像素限定结构靠近该所述反射部或该所述第一导电部的一侧之间设置有间距。
在本公开的一种示例性实施例中，所述第一子部在所述衬底基板上的正投影与所述反射部在所述衬底基板上的正投影交叠，所述第二子部在所述衬底基板上的正投影与所述反射部在所述衬底基板上的正投影不交叠；或所述第一子部在所述衬底基板上的正投影与所述第一导电部在所述衬底基板上的正投影交叠，所述第二子部在所述衬底基板上的正投影与所述第一导电部在所述衬底基板上的正投影不交叠。
在本公开的一种示例性实施例中，在平行于所述衬底基板方向上，所述反射部靠近所述像素限定结构的一侧与对应的所述像素限定结构靠近该所述反射部的一侧之间设置有第一间距，
在平行于所述衬底基板方向上，所述第一导电部靠近所述像素限定结构的一侧与对应的所述像素限定结构靠近该所述第一导电部的一侧之间设置有第二间距；
所述第一间距为1-3μm，所述第二间距为1-3μm。
在本公开的一种示例性实施例中，所述发光结构还包括：
第二导电层，设于所述衬底基板和所述反射层之间，所述第二导电层包括多个间隔分布的第二导电部；
所述像素区域在所述基板上的正投影位于所述第二导电部在所述基板上的正投影之内；
所述反射部和所述第二导电部在垂直于所述衬底基板的方向上一一对应，且所述第二导电部、所述反射部在所述衬底基板上的正投影至少部分交叠。
在本公开的一种示例性实施例中，在垂直于所述衬底基板的方向上，所述像素限定结构具有靠近所述衬底基板的底端、远离所述衬底基板的顶端以及位于所述底端和顶端之间的中部，所述像素限定结构的底端界定出多个开口，所述像素限定结构的中部或顶端界定出多个出光口，所述开口一一对应暴露出所述第二导电部；
所述出光口在所述衬底基板上的正投影位于所述开口在所述衬底基板上的正投影之内；
所述出光口、所述反射部和所述第一导电部在所述衬底基板上的正投影至少部分交叠。
在本公开的一种示例性实施例中，沿远离所述衬底基板方向，所述像素限定结构包括依次连接的第一部和第二部，所述第一部在所述衬底基板上的正投影位于所述第二部在所述衬底基板上的正投影之内，且所述第一部在衬底基板上的正投影的面积小于所述第二部在衬底基板上的正投影的面积。
在本公开的一种示例性实施例中，所述第一导电部、所述反射部在所述衬底基板上的正投影的交叠区域与所述第二部在所述衬底基板上的正投影不交叠；
所述第一间距或所述第二间距在所述衬底基板上的正投影至少部分区域位于所述第二部在所述衬底基板上的正投影之内。
在本公开的一种示例性实施例中，在垂直于所述衬底基板的方向上，所述第一部的高度不小于所述反射部和所述第一导电部的厚度之和。
在本公开的一种示例性实施例中，在垂直于所述衬底基板的方向上，所述第二部的截面的远离所述衬底基板的一边为朝远离所述衬底基板方向凸出的弧形。
在本公开的一种示例性实施例中，在垂直于所述衬底基板的方向上，所述像素限定结构的截面为蘑菇形。
在本公开的一种示例性实施例中，所述反射部具有靠近所述衬底基 板第一表面、远离所述衬底基板的第二表面、以及位于所述第一表面和所述第二表面之间的侧壁，所述第一导电部接触所述反射部的所述侧壁和所述第二表面。
在本公开的一种示例性实施例中，所述发光结构还包括：
第一绝缘层，设于所述反射层和所述第一导电层之间，所述第一绝缘层包括多个间隔分布的第一绝缘部，所述第一绝缘部位于所述像素区域内，所述反射部在所述衬底基板上的正投影位于所述第一绝缘部在所述衬底基板上的正投影之内。
在本公开的一种示例性实施例中，所述第一绝缘部接触所述反射部的侧壁和远离所述衬底基板的一侧表面，且所述第一绝缘部接触所述第二导电部被所述反射部暴露的区域。
在本公开的一种示例性实施例中，所述发光结构还包括：
第二绝缘层，设于所述第二导电层远离所述衬底基板的一侧，所述第二绝缘层包括多个间隔分布的第二绝缘部，所述第二绝缘部位于所述像素区域，所述第二绝缘部接触所述第二导电部被所述反射部暴露的区域，且所述第二绝缘部接触所述第一导电部和所述反射部的侧壁，并接触所述第一导电部的远离所述衬底基板的至少部分表面。
在本公开的一种示例性实施例中，所述第二导电层的厚度为8-18nm，所述反射层的厚度为60-150nm，所述第一导电层的厚度为8-18nm；
在垂直于所述衬底基板的方向上，所述像素限定结构的高度为1.2-2μm。
在本公开的一种示例性实施例中，所述显示面板还包括：
平坦化层，设于所述发光结构靠近所述衬底基板的一侧；
所述第一导电部通过所述平坦化层中的过孔与像素电路连接，所述过孔在衬底基板上的正投影与所述像素限定结构在所述衬底基板上的正投影至少部分交叠。
在本公开的一种示例性实施例中，所述第一绝缘部包括：
第三子部，位于所述反射部远离所述衬底基板的一侧；
第四子部，与所述第二导电部接触；
第五子部，连接于所述第三子部和所述第四子部之间，所述第五子 部的延伸方向与所述衬底基板之间具有夹角，所述夹角为锐角。
在本公开的一种示例性实施例中，所述显示面板还包括：
平坦化层，设于所述发光结构靠近所述衬底基板的一侧；
所述第一导电部在所述衬底基板上的正投影与所述像素限定结构在所述衬底基板上的正投影至少部分交叠；
所述第一导电部至少部分区域与所述平坦化层接触。
在本公开的一种示例性实施例中，所述显示面板还包括：
第一绝缘层，位于所述反射层和所述第二导电层之间，所述第一绝缘层包括多个间隔分布的第一绝缘部，且所述第一绝缘部至少部分覆盖所述第二导电部被所述反射部暴露的部分。
根据本公开第二个方面，提供一种显示面板的制作方法，包括：
提供衬底基板；
于所述衬底基板一侧形成发光结构；
其中，于所述衬底基板一侧形成发光结构包括：
于所述衬底基板的一侧形成反射层，所述反射层包括多个间隔分布的反射部；
于所述反射层远离所述衬底基板的一侧形成第一导电层，所述第一导电层包括多个间隔分布的第一导电部；
于所述衬底基板的一侧形成像素限定结构，所述像素限定结构界定出多个阵列排列的像素区域，所述反射部位于所述像素区域内；
于所述第一导电层远离所述衬底基板的一侧形成空穴注入层，所述空穴注入层包括第一子部和第二子部，所述第一子部位于所述像素区域的中间部分，所述第二子部位于所述像素区域的边缘部分，所述像素区域的中间部分与所述像素限定结构之间的距离不小于所述像素区域的边缘部分与所述像素限定结构之间的距离；在垂直于所述衬底基板的方向上，所述第二子部的至少部分区域的尺寸大于所述第一子部的尺寸；
其中，所述反射部和所述第一导电部在垂直于所述衬底基板的方向上一一对应，且所述第一导电部、所述反射部在所述衬底基板上的正投影至少部分交叠；
在平行于所述衬底基板方向上，所述反射部或所述第一导电部靠近 所述像素限定结构的一侧与对应的所述像素限定结构靠近该所述反射部或该所述第一导电部的一侧之间设置有第一间距。
在本公开的一种示例性实施例中，于所述衬底基板的一侧形成像素限定结构包括：
于所述第一导电层远离所述衬底基板的一侧形成预埋层，所述预埋层包括多个间隔分布的预埋部，所述预埋部覆盖所述第一导电部远离所述衬底基板的表面，且所述预埋部至少覆盖所述第一导电部和所述反射部的侧壁；
形成所述像素限定结构，所述像素限定结构至少覆盖所述预埋部部分顶表面以及所述预埋部的侧壁；
去除所述预埋层。
在本公开的一种示例性实施例中，在平行于所述衬底基板的方向上，所述预埋部远离所述反射部的一侧与所述反射部靠近该所述预埋部的一侧之间的距离与所述第一间距相等。
根据本公开第三个方面，提供一种显示装置，包括如第一方面所述的显示面板。
本公开提供的显示面板，像素限定结构界定出多个像素区域，反射部位于像素限定结构界定出的像素区域内，且反射部或第一导电部在平行于衬底基板方向上与像素限定结构之间具有间距。也即，反射部和第一导电部的交叠区域对应位于第二导电部的中间区域，该结构有利于增强此中间区域对应的发光强度，从而在相对程度上降低边缘区域对显示质量的影响。
附图说明
通过参照附图详细描述其示例实施方式，本公开的上述和其它特征及优点将变得更加明显。
图1是本公开示例性实施例中显示面板结构示意图；
图2是本公开另一示例性实施例中显示面板结构示意图；
图3是本公开又一示例性实施例中显示面板结构示意图；
图4是本公开又一示例性实施例中显示面板结构示意图；
图5是本公开又一示例性实施例中显示面板结构示意图；
图6是本公开又一示例性实施例中显示面板结构示意图；
图7是本公开又一示例性实施例中显示面板结构示意图；
图8是本公开又一示例性实施例中显示面板结构示意图；
图9是本公开又一示例性实施例中显示面板结构示意图；
图10是本公开示例性实施例中显示面板的驱动电路层结构示意图；
图11是本公开示例性实施例中步骤S241形成结构示意图；
图12是本公开示例性实施例中步骤S242形成结构示意图；
图13是本公开示例性实施例中步骤S243形成结构示意图；
图14是图3中显示面板像素区域中间部分SEM图；
图15是本公开一示例性实施例中像素限定结构SEM图；
图16是图2中显示面板SEM图；
图17是图3中显示面板靠近像素限定结构部分SEM图；
图18是本公开示例性实施例中发光器件与像素电路连接截面SEM图；
图19是本公开示例性实施例中发光器件阳极连接过孔俯视SEM图。
图中主要元件附图标记说明如下：
1-衬底基板；2-驱动电路层；21-有源层；22-第一栅绝缘层；23-第一栅金属层；24-第二栅绝缘层；25-第二栅金属层；26-层间介质层；27-源漏层；PLN-平坦化层；BFL-缓冲层；3-发光结构；31-第二导电层；311-第二导电部；32-反射层；321-反射部；33-第一导电层；331-第一导电部；34-第一绝缘层；341-第一绝缘部；3411-第三子部；3412-第四子部；3413-第五子部；35-第二绝缘层；351-第二绝缘部；36-发光功能层；361-空穴注入层；3611-第一子部；3612-第二子部；362-空穴传输层；363-发光材料层；364-电子传输层；37-第三导电层；38-像素限定结构；381-第一部；382-第二部；01-开口；02-出光口；30-发光器件；301-阳极；4-预埋层；41-预埋部；5-过孔。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够 以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施例使得本公开将更加全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施例中。在下面的描述中，提供许多具体细节从而给出对本公开的实施例的充分理解。
在图中，为了清晰，可能夸大了区域和层的厚度。在图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施例中。在下面的描述中，提供许多具体细节从而给出对本公开的实施例的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而没有所述特定细节中的一个或更多，或者可以采用其它的方法、组元、材料等。在其它情况下，不详细示出或描述公知结构、材料或者操作以避免模糊本公开的主要技术创意。
当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“所述”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。用语“第一”和“第二”等仅作为标记使用，不是对其对象的数量限制。
相关技术中，喷墨打印技术由于生产效率高、材料成本底低等优点被应用于OLED显示面板的生产制备。喷墨打印技术是将喷墨液滴滴入像素区域内，然后进行烘干处理，使喷墨液滴发生固化从而形成发光功能层。然而，这种方式虽然制作简便，但在喷墨液滴的烘干过程中，由于边缘位置的蒸发速率大于中间位置的蒸发速率，致使喷墨液滴内部产生一个外向的毛细流动，将悬浮的粒子携带至边缘位置，在边缘位置沉积成环，导致边缘位置的厚度大于中间位置的厚度，出现咖啡环效应，从而干扰干扰微腔效应，使色度发生偏移，影响OLED显示面板的显示质量。
如图1至图9所示，本公开提供一种显示面板，包括衬底基板1和 设于衬底基板1一侧的发光结构3。发光结构3包括像素限定结构38、反射层32、第一导电层33和空穴注入层361。其中，像素限定结构38设于衬底基板1的一侧，像素限定结构38界定出多个阵列排列的像素区域；反射层32设于衬底基板1的一侧，反射层32包括多个间隔分布的反射部321，反射部321位于像素区域内；第一导电层33设于反射层32远离衬底基板1的一侧，第一导电层33包括多个间隔分布的第一导电部331。空穴注入层361设于第一导电层33远离衬底基板1的一侧，空穴注入层361包括第一子部3611和第二子部3612，第一子部3611位于像素区域的中间部分，第二子部3612位于像素区域的边缘部分，像素区域的中间部分与像素限定结构38之间的距离不小于像素区域的边缘部分与像素限定结构38之间的距离；在垂直于衬底基板1的方向上，第二子部362的至少部分区域的尺寸大于第一子部361的尺寸。其中，反射部321和第一导电部331一一对应，且第一导电部331、反射部321在衬底基板1上的正投影至少部分交叠；在平行于衬底基板1方向上，反射部321靠近像素限定结构38的一侧与对应的像素限定结构38靠近该反射部321的一侧之间设置有第一间距L1。
本公开提供的显示面板，像素限定结构38界定出多个像素区域，反射部321位于像素限定结构38界定出的像素区域内，且反射部321或第一导电部331在平行于衬底基板1方向上与像素限定结构38之间具有间距。也即，反射部321和第一导电部331的交叠区域对应发光结构的中间区域，该结构有利于增强此中间区域对应的发光强度，从而在相对程度上降低边缘区域对显示质量的影响。
此外，本公开中由于反射部321或第一导电部331与像素限定结构38之间具有间距，因此。形成的反射部321或第一导电部331的边缘区域处可呈台阶形态。该种结构设计有助于后续通过喷墨打印法形成其他膜层时，改善膜层边缘位置处的厚度及平整性，从而有助于改善相关技术中由于咖啡环效应对显示质量造成的影响。
下面结合附图对本公开实施方式提供的显示面板的各部件进行详细说明：
如图1至图9所示，本公开实施方式提供了一种显示面板，该显示 面板可以是OLED(Organic Light-Emitting Diode，有机发光二极管)显示面板或QLED(Quantum Dot Light Emitting Diodes，量子点发光二极管)显示面板。该显示面板包括衬底基板1和设于衬底基板1一侧的发光结构3，发光结构3包括像素限定结构38、反射层32和第一导电层33。
衬底基板1可以为无机材料的衬底基板，也可以为有机材料的衬底基板。举例而言，在本公开的一种实施方式中，衬底基板1的材料可以为钠钙玻璃(soda-lime glass)、石英玻璃、蓝宝石玻璃等玻璃材料，或者可以为不锈钢、铝、镍等金属材料。在本公开的另一种实施方式中，衬底基板1的材料可以为聚甲基丙烯酸甲酯(Polymethyl methacrylate，PMMA)、聚乙烯醇(Polyvinyl alcohol，PVA)、聚乙烯基苯酚(Polyvinyl phenol，PVP)、聚醚砜(Polyether sulfone，PES)、聚酰亚胺、聚酰胺、聚缩醛、聚碳酸酯(Poly carbonate，PC)、聚对苯二甲酸乙二酯(Polyethylene terephthalate，PET)、聚萘二甲酸乙二酯(Polyethylene naphthalate，PEN)或其组合。衬底基板1也可以为柔性衬底基板1，举例而言，在本公开的一种实施方式中，衬底基板1的材料可以为聚酰亚胺(polyimide，PI)。衬底基板1还可以为多层材料的复合，举例而言，在本公开的一种实施方式中，衬底基板1可以包括依次层叠设置的底膜层(Bottom Film)、压敏胶层、第一聚酰亚胺层和第二聚酰亚胺层。
如图1所示，发光结构3设于衬底基板1的一侧，发光结构3可用于形成发光器件，以完成画面显示。发光结构3包括像素限定结构38、反射层32和第一导电层33。
像素限定结构38设衬底基板1的一侧，像素限定结构38界定出多个阵列排列的像素区域。像素区域在衬底基板1上的正投影的形状可以是多边形、光滑的曲线闭合图形或其他图形，具体本公开不做限定。
反射层32设于衬底基板1的一侧，反射层32包括多个间隔分布的反射部321，反射部321位于像素区域内。反射层32的材料可以包括导电材料，如导电金属材料或合金材料等。在一实施例中，反射层32的材料可以包含银、铝等金属材料。
第一导电层33设于反射层32远离衬底基板1的一侧。第一导电层 33包括多个间隔分布的第一导电部331。第一导电部331与反射部321在垂直于衬底基板1方向上一一对应，即在Y方向上一一对应。第一导电部331、反射部321在衬底基板1上的正投影至少部分交叠。具体地，反射部321在衬底基板1上的正投影可位于第一导电部331在衬底基板1上的正投影之内，或与第一导电部331在衬底基板1上的正投影完全交叠。在本公开中，完全交叠是指形状、大小及位置大致相同。举例而言，如图1所示，在一些实施例中，反射部321具有靠近衬底基板1的第一表面和远离衬底基板1的第二表面，以及位于第一表面和第二表面之间的侧壁，第一导电部331接触反射部321的第二表面和侧壁，且第一导电部331的延伸至像素限定结构38的底端，即靠近衬底基板1的一端。在这类实施例中，反射部321在衬底基板1上的正投影可位于第一导电部331在衬底基板1上的正投影之内。
第一导电层33可由透明导电材料构成，如ITO(氧化铟锡)、IZO(氧化铟锌)等。第一导电层33可以单层或多层结构，在一实施例中，第一导电层33为单层结构，由ITO材料构成。
本公开中，反射部321位于像素区域内，且反射部321和第一导电部331至少部分交叠，该结构通过反射部321有助于提高对发光器件所发出的光的反射率，提升发光器件的发光强度。
如图2所示，在本公开另一些实施例中，发光结构3还包括第二导电层31。第二导电层31设于衬底基板1和反射层32之间，第二导电层31包括多个间隔分布的第二导电部311。多个第二导电部311阵列排列。第二导电层31可由透明导电材料构成，如ITO(氧化铟锡)、IZO(氧化铟锌)等。第二导电部311在衬底基板1上的正投影可以是圆形、椭圆形、正多边形或不规则曲边形或多边形等，具体本公开不做限定。第二导电层31可以是单层或多层结构，在一实施例中，第二导电层31为单层结构，由ITO材料构成。
在此需说明的是，当发光结构还包括第二导电层31时，第一导电部331可不延伸至像素限定结构38的底端，其可以只接触反射部321的远离衬底基板1的第二表面，以及反射部321的第二表面与侧壁的转角处。如图16所示，在实际工艺中，当形成第一导电层33时，第一导电部331 可包括与反射部321的第二表面接触的子导电部3311和与反射部321的第二表面不接触的子导电部3312，子导电部3312的延伸方向与第二导电部311之间具有夹角，且该夹角为锐角。
像素限定结构38设衬底基板1的一侧，像素限定结构38界定出多个阵列排列的像素区域。各个像素区域一一对应地暴露出各第二导电部311。像素区域在衬底基板1上的正投影位于第二导电部311在衬底基板1上的正投影之内。即像素区域的范围位于其对应的第二导电部311的边界以内。
反射部321与第二导电部311在垂直于衬底基板1方向上一一对应，即在Y方向上一一对应。第二导电部311、反射部321在衬底基板1上的正投影至少部分交叠。
在一些实施例中，反射部321在衬底基板1上的正投影位于第二导电部311在衬底基板1上的正投影之内，且反射部321的正投影的面积小于第二导电部311被像素区域所暴露的面积。
本公开中，如图1、图2所示，在平行于衬底基板1方向上，反射部321或第一导电部331靠近像素限定结构38的一侧与对应的像素限定结构38靠近该反射部321或该第一导电部331的一侧之间设置有间距。具体地，反射部321与像素限定结构38之间设有间距，或第一导电部331与像素限定结构38之间设有间距。
如图1、图2所示，在本公开一些实施例中，在平行于衬底基板1方向上，反射部321靠近像素限定结构38的一侧与对应的像素限定结构38靠近该反射部321的一侧之间设置有第一间距L1。如图2所示，当显示面板还包括第二导电部311时，第一间距L1对应的第二导电部311的区域上方未设置有反射部321。
继续如图1、图2所示，在X方向上，第一间距L1的大小可根据实际情况进行设定。如，在一些实施例中，第一间距L1的大小可以是1-3μm，具体可以是1.1μm、1.2μm、1.3μm、1.4μm、1.5μm、1.7μm、1.9μm、2μm、2.1μm、2.2μm、2.3μm、2.4μm、2.5μm、2.7μm、2.9μm或3μm等，但不限于此。
在一些实施例中，第一导电部331在衬底基板1上的正投影位于第 二导电部311在衬底基板1上的正投影之内，且第一导电部331的正投影的面积小于第二导电部311被像素区域所暴露的面积。在平行于衬底基板1方向上，第一导电部331靠近像素限定结构38的一侧与对应的像素限定结构38靠近该第一导电部331的一侧之间设置有第二间距L2。如图2所示，当显示面板还包括第二导电部311时，第二间距L2对应的第二导电部311的区域上方未设置有第一导电部331。
如图1、图2所示，在X方向上，第二间距L2对应的第二导电部311的区域上方未设置有第一导电部331。第二间距的大小可根据实际情况进行设定。如，在一些实施例中，第二间距的大小可以是1-3μm，具体可以是1.1μm、1.2μm、1.3μm、1.4μm、1.5μm、1.7μm、1.9μm、2μm、2.1μm、2.2μm、2.3μm、2.4μm、2.5μm、2.7μm、2.9μm或3μm等，但不限于此。在一些实施例中，第一间距L1等于第二间距L2与第一导电部331的厚度之和。
本公开中，第二导电层31、反射层32和第一导电层33均是具有一定厚度的膜层。其中，反射层32的厚度不小于第二导电层31和第一导电层33的厚度。在一实施例中，第二导电层31的厚度为8-18nm，具体可以是8nm、10nm、12nm、13nm、15nm、16nm、17nm或18nm，但不限于此。反射层32的厚度为60-150nm，具体可以是60nm、65nm、70nm、75nm、80nm、85nm、90nm、95nm、100nm、105nm、115nm、120nm、125nm、130nm、135nm、140nm、145nm或150nm，但不限于此。第一导电层33的厚度为为8-18nm，具体可以是8nm、10nm、12nm、13nm、15nm、16nm、17nm或18nm，但不限于此。
本公开中，发光结构3包含多个发光器件，每个发光器件位于像素区域内。发光器件可以是OLED或QLED等。
在一些实施例中，第一导电部331和反射部321可作为发光器件的阳极；在另一些实施例中，第二导电部311、反射部321和第一导电部331可作为发光器件的阳极、在又一些实施例中，第一导电部331可作为发光器件的阳极。
如图1至图9所示，在本公开一些实施例中，发光结构3还包括发光功能层36和第三导电层37。发光功能层36设于第一导电层33远离 衬底基板1的一侧。在本公开中，可采用喷墨打印法形成发光功能层36。发光功能层36为多层结构，沿远离衬底基板1方向上，发光功能层36包括空穴注入层361、空穴传输层362、发光材料层363、电子传输层364，可通过使空穴和电子在发光材料层363复合成激子，由激子辐射光子，从而产生可见光，具体发光原理在此不再详述。发光材料层363可以是有机发光材料层或量子点发光材料层。发光功能层36包括多个发光功能部，发光功能部一一对应地位于各个像素区域内。发光功能层36的厚度可以为200-500nm，具体厚度可根据实际情况进行设定。在一些实施例中，发光功能层36还可以包括电子注入层，设于电子传输层364远离衬底基板1的一侧。
在本公开一些实施例中，空穴注入层361设于第一导电层33远离衬底基板1的一侧，空穴注入层361包括第一子部3611和第二子部3612。如图1至图4，图5、图6至图9，第一子部3611位于像素区域的中间部分，第二子部3612位于像素区域的边缘部分，像素区域的中间部分与像素限定结构38之间的距离不小于像素区域的边缘部分与像素限定结构38之间的距离。具体地，如图1至图4，图6至图9所示，第一子部3611在衬底基板1上的正投影与反射部321在衬底基板1上的正投影交叠，第二子部362在衬底基板1上的正投影与反射部321在衬底基板1上的正投影不交叠，或如图5所示，第一子部3611在衬底基板1上的正投影与第一导电部331在衬底基板1上的正投影交叠，第二子部3612在衬底基板1上的正投影与第一导电部331在衬底基板1上的正投影不交叠。在垂直于衬底基板1的方向上，第二子部3612的至少部分区域的尺寸大于第一子部3611的尺寸。
第三导电层37设于发光功能层36远离衬底基板1的一侧。第三导电层37可作为发光器件的阴极。第三导电层37可以是单层或多层结构，其材料可包括导电的金属、金属氧化物以及合金中的一种或多种。
各发光器件可共用同一阴极，具体而言，第三导电层37为覆盖各发光器件的发光功能层36和像素限定结构38的连续导电层，也就是说，第三导电层37在衬底基板1的正投影覆盖各个像素区域以及像素限定结构38在衬底基板1上的正投影。同时，第三导电层37在对应于像素区 域的地方凹陷至像素区域内，即在像素区域对应的地方向靠近衬底基板1的方向凹陷。
本公开中，除通过上述实施例改善中间区域的发光强度，在相对程度上降低边缘区域对显示质量的影响外，还可以通过其他方式进一步改善显示面板的显示质量。
下面将结合不同的实施例，详细说明进一步的改善显示面板显示质量的方法。
如图1所示，在本公开一些实施例中，反射部321和第一导电部331作为发光器件的阳极。或如图2所示，在本公开一些实施例中，第二导电部311、反射部321和第一导电部331作为发光器件的阳极。
如图1、图2所示，第一导电部331接触反射部321的侧壁和远离衬底基板1的一侧表面。即第一导电部331将反射部321予以包裹。在实际应用中，反射部321通常是由金属材料制成的具有一定厚度的膜层，该膜层的边缘刚性较高，有可能对之后形成的膜层等造成损伤，如划伤断裂。本实施例中，第一导电部331将反射部321予以包裹，有助于防止形成后续膜层时发生断裂。
在图1中，第一导电部331可进一步延伸至像素限定结构38的底端，第一导电部331和反射部321相互接触形成发光器件的阳极。在图2中，第一导电部331可延伸或不延伸至像素限定结构38的底端，具体本公开不做限定。当第一导电部331未延伸至像素限定结构38的底端时，第一导电部331与像素限定结构38之间具有第二间距L2。在图2中，第一导电部331、反射部321和第二导电部311相互接触形成发光器件的阳极。
在这些实施例中，可通过改善像素限定结构38的具体形状，以限制位于像素区域内发光器件边缘部分光的出射。具体可通过改变像素限定结构38在平行于衬底基板1方向上的尺寸来实现上述目的。举例而言，在垂直于衬底基板1方向上，像素限定结构38具有靠近衬底基板1的底端、远离衬底基板1的顶端以及位于底端和顶端之间的中部。像素限定结构38的底端界定多个开口01。在图2中，当显示面板还包括第二导电部311时，开口01暴露第二导电部311的部分区域。像素限定结构 38的中部或顶端界定出多个出光口02。出光口02的范围小于开口01的范围，即出光口02在衬底基板1上的正投影位于开口01在衬底基板1上的正投影之内。
进一步地，出光口02、反射部321、第一导电部331在衬底基板1上的正投影至少部分交叠。较佳地，反射部321和第一导电部331在衬底基板1上的正投影的交叠区域与出光口02在衬底基板1上的正投影完全交叠。或，出光口02在衬底基板1上的正投影的位于反射部321和第一导电部331在衬底基板1上的正投影之内。如此，像素限定结构38可将第二导电部311的边缘位置对应区域可能发出的光予以阻挡，从而避免该部分区域对微腔效应造成影响。
继续如图1或图2所示，像素限定结构38的具体图形可根据实际需求进行设定。在一具体实施例中，沿远离衬底基板1方向，像素限定结构38包括依次连接的第一部381和第二部382，第一部381在衬底基板1上的正投影位于第二部382在衬底基板1上的正投影之内，且第一部381在衬底基板1上的正投影的面积小于第二部382在衬底基板1上的正投影的面积。在这些实施例中，像素限定结构38中的第二部382界定出出光口02的范围，第一部381靠近衬底基板1的一端界定出开口01的范围。
第一导电部331、反射部321在衬底基板1上的正投影的交叠区域与第二部382在衬底基板1上的正投影不交叠；且第一间距L1或第二间距L2在衬底基板1上的正投影至少部分区域位于第二部382在衬底基板1上的正投影之内。即利用像素限定结构38的第二部382将第二导电部311的边缘位置对应区域可能发出的光予以阻挡。
在垂直于衬底基板1的方向上，第一部381的高度不小于反射部321和第一导电部331的厚度之和。即，在垂直于衬底基板1方向上，形成的反射部321和第一导电部331大致位于第二部382的靠近衬底基板1的一侧。进一步地，第一部381的高度大于反射部321和第一导电部331的厚度之和。
在一实施例中，在垂直于衬底基板1的方向上，第一部381的截面大致呈长方形，当然也可以是梯形或不规则的多边形等。在垂直于衬底 基板1的方向上，第二部382的截面的远离衬底基板1的一边为朝远离衬底基板1方向凸出的弧形。该弧形设计有助于避免后续膜层，如阴极层的断裂。进一步地，在垂直于衬底基板1的方向上，像素限定结构38的截面为蘑菇形。在本公开中，蘑菇形即大致为撑开的伞状结构，底部大致为柱形，顶部大致为近似的半球形结构。在实际应用中，像素限定结构38的具体形状可如图15所示，图15为实际像素限定结构38的扫描电子显微镜(scanning electron microscope，SEM)图。
在一实施例中，在垂直于衬底基板1的方向上，像素限定结构38的高度为1.2-2μm。具体可以是1.2μm、1.3μm、1.4μm、1.5μm、1.6μm、1.7μm、1.8μm、1.9μm或2μm，但不限于此。
如图3至图7所示，在本公开另一些实施例中，第一导电部331可作为发光器件的阳极。在这些实施例中，第一导电部331与像素限定结构38之间具有间距，只有第一导电部331所对应的区域可以发光，而其他边缘区域不发光，以此来改善边缘区域对显示画面质量的影响。
具体在一些实施例中，显示面板还包括第一绝缘层34。
如图3至图7所示，在一实施例中，第一绝缘层34设于反射层32和第一导电层33之间，第一绝缘层34包括多个间隔分布的第一绝缘部341。第一导电部331、第一绝缘部341、反射部321与第二导电部311在垂直于衬底基板1方向上一一对应，且各个第一绝缘部341一一对应地位于各像素区域内。
第一绝缘部341位于像素区域内，反射部321在衬底基板1上的正投影位于第一绝缘部341在衬底基板1上的正投影之内。第一绝缘层34的厚度为30-100nm，具体可以为30nm、35nm、40nm、45nm、50nm、55nm、60nm、65nm、70nm、75nm、80nm、85nm、90nm、95nm或100nm，但不限于此。第一绝缘层34的材料包括无机材料，如氮化硅或二氧化硅等。
如图3和图4所示，当反射部321与像素限定结构38之间具有间距时，第一绝缘部341接触反射部321的侧壁和远离衬底基板1的一侧表面，且第一绝缘部341接触第二导电部311被反射部321暴露的区域。即第一绝缘部341将第二导电部311、反射部321与第一导电部331绝 缘隔离，从而将第一导电部331作为发光器件的阳极。在该实施例中，第一导电部331在衬底基板1上的正投影可与反射部321在衬底基板1上的正投影完全交叠，即在平行于衬底基板1的方向上，第一导电部331的宽度与反射部321的宽度大致相等。如图5所示，当反射部321与像素限定结构38之间不设有间距时，第一绝缘部341接触反射部321远离衬底基板1的一侧表面。
如图6和图7所示，在另一实施例中，第一绝缘部341未接触第二导电部311被反射部321暴露的区域，仅接触反射部321远离衬底基板1的一侧表面。在该实施例中，第一导电部331、第一绝缘部341、反射部321在衬底基板1上的正投影完全交叠。即，第一导电部331、第一绝缘部341和反射部321在衬底基板1上的正投影的形状、大小和位置大致相同。
在该实施例中，显示面板还包括第二绝缘层35，设于第二导电层31远离衬底基板1的一侧，第二绝缘层35包括多个间隔分布的第二绝缘部351，第二绝缘部351位于像素区域内，第二绝缘部351接触第二导电部311被反射部321暴露的区域，且第二绝缘部351接触第一导电部331、第一绝缘部341和反射部321的侧壁，并接触第一导电部331的远离衬底基板1的至少部分表面，以防止反射部321氧化等。在该实施例中，第二导电部311被反射部321暴露的区域被第二绝缘部351覆盖，反射部321被第一绝缘部341覆盖，从而可将第一导电部331作为发光器件的阳极。
第二绝缘层35的厚度为10-20nm，具体可以为10nm、11nm、12nm、13nm、14nm、15nm、16nm、17nm、18nm、19nm或20nm，但不限于此。第二绝缘层35的材料包括无机材料，如氮化硅或二氧化硅等。
第二绝缘部351的形状和大小可根据第一间距L1或第二间距L2等进行设定。在一实施例中，在平行于衬底基板1方向上，第二绝缘部351的尺寸与第一间距L1大致相等。也即，在X方向上，第二绝缘部351的宽度与第一间距L1大致相等。在垂直于衬底基板1的方向上，第二绝缘部351的高度大致为第一导电部331、第一绝缘部341和反射部321的厚度之和。在一实施例中，第二绝缘部351可覆盖像素限定结构38 靠近反射部321或第一导电部331的部分侧壁。在垂直于衬底基板1的方向上，第二绝缘部351的形状为凹槽形。
在此需说明的是，如图8所示，当显示面板还包括第二绝缘层35时，显示面板可不包括第一绝缘层34，此时，第一导电部331、反射部321和部分第二导电部311可作为发光器件的阳极。
此外，本公开也可通过调整各个膜层的位置关系等，来限制发光器件边缘区域的发光情况。如图9所示，在本公开另一些实施例中，第一绝缘层34位于反射层32和第二导电层31之间，第一绝缘层34包括多个间隔分布的第一绝缘部341，第一绝缘部341接触第二导电部311被反射部321暴露的部分。在该实施例中，第一导电部331和反射部321可作为发光器件的阳极。
当显示面板包含有绝缘层时，如第一绝缘层34或第二绝缘层35，像素限定结构38的具体形状不做特殊限定，其可采用本领域常用的柱形、倒梯形等结构。如图3和图6所示，在垂直于衬底基板1平面的方向上，像素限定结构38的截面为顶端呈圆弧的柱形。当然，如图4和图7等所示，像素限定结构38的形状也可以采用前述实施例中截面为蘑菇形的像素限定结构38，具体本公开不做限定。
本公开上述实施例中，由于反射部321和第一导电部331的设置，使得发光器件的第二导电部311、反射部321和第一导电部331的边缘区域处呈台阶形状。该种结构设计有助于后续通过喷墨打印法形成发光功能层36时，改善膜层边缘位置处的厚度及平整性，具体如图14所示。图14可对应于图3或图4所示的实施例。
图14中为发光器件边缘位置处，即靠近像素限定结构的一侧，形成各个膜层的SEM图。从图中可以看出，在边缘位置A处，形成的各个膜层的厚度正常，且平整性较好，如空穴注入层361、空穴传输层362、发光材料层363和电子传输层364等。从而有助于改善相关技术中由于咖啡环效应对显示质量造成的影响。
继续如图14所示，在实际工艺中，形成的第一绝缘部341包括第三子部3411、第四子部3412和第五子部3413。其中，第三子部3411位于反射部321远离衬底基板1的一侧；第四子部3412与第二导电部311接 触；第五子部3413连接于第三子部3411和第四子部3412之间，第五子部3413的延伸方向与衬底基板1之间具有夹角β，夹角β为锐角。
在此需说明的是，图14仅示出如士3或图4所示实施例的像素区域中间部分的膜层结构SEM图，针对边缘区域的SEM图可参照图17所示，在图17中，靠近像素限定结构38位置处不设有第一导电部331，即第一导电部331与像素限定结构38之间具有间距。
如图1至图9、和图10所示，在本公开一些实施例中，显示面板还包括驱动电路层2，设于衬底基板1和发光结构3之间。驱动电路层2包括驱动电路，驱动电路包括像素电路，像素电路用于驱动显示面板的发光器件30发光。像素电路可以是7T1C、7T2C、6T1C或6T2C等像素电路，在此不对其结构做特殊限定。其中，nTmC表示一个像素电路包括n个晶体管(用字母“T”表示)和m个电容(用字母“C”表示)。像素电路与发光器件30一一对应连接，以驱动发光器件30发光。
如图10所示，在本公开一些实施例中，驱动电路层2可由多层膜结构构成。以驱动电路中的晶体管为顶栅型薄膜晶体管为例，驱动电路层2包括有源层21、第一栅绝缘层22、第一栅金属层23、第二栅绝缘层24、第二栅金属层25、层间介质层26和源漏层27。
有源层21设于衬底基板1的一侧；第一栅绝缘层22设于有源层21远离衬底基板1的一侧，第一栅绝缘层22覆盖有源层21；第一栅金属层23设于第一栅绝缘层22远离衬底基板1的一侧，第一栅金属层23用于形成电容C的第一极板和晶体管T的栅极；第二栅绝缘层24设于第一栅金属层23远离衬底基板1的一侧，第二栅绝缘层24覆盖第一栅金属层23；第二栅金属层25设于第一栅绝缘层22远离衬底基板1的一侧，且与第一极板正对设置，第二栅金属层25用于形成电容C的第二极板；层间介质层26设于第二栅金属层25远离衬底基板1的一侧，层间介质层26覆盖第二栅金属层25；源漏层27设于层间介质层26远离衬底基板1的一侧，源漏层27用于形成晶体管的源极27S和漏极27D，源极27S和漏极27D连接于有源层21。
在本公开一些实施例中，驱动电路层2还包括缓冲层BFL，设于有源层21和衬底基板1之间。
如图1、图10、图18和图19所示，在一些实施例中，显示面板还包括平坦化层PLN。平坦化层PLN设于发光结构3靠近衬底基板1的一侧，发光器件30的阳极301可通过平坦化层PLN中的过孔与像素电路连接，以驱动发光器件30发光。
当第二导电部311、反射部321和第一导电部331作为发光器件30的阳极301时，发光器件30可通过第一导电部331、反射部321和第二导电部311中的任一者通过过孔与像素电路中晶体管的源/漏极连接。实际连接方式可参照图18所示，在图18中，发光器件通过第一导电部331、反射部321和第二导电部311中的任一者通过过孔5与像素电路中晶体管的源/漏极连接。
当第一导电部331作为发光器件30的阳极301时，第一导电部331可通过过孔与像素电路中晶体管的源/漏极连接。当第一导电部331、反射部321作为发光器件30的阳极301时，第一导电部331或反射部321可通过过孔与像素电路中晶体管的源/漏极连接。
如图1和图19所示，在本公开一些实施例中，第一导电部331通过平坦化层PLN中的过孔5与像素电路连接，过孔5在衬底基板1上的正投影与像素限定结构38在衬底基板1上的正投影至少部分交叠。当然，在其他实施例中，当发光器件30的阳极301通过第二导电部311，并通过平坦化层PLN中的过孔与像素电路连接时，该过孔在衬底基板1上的正投影与像素限定结构38在衬底基板1上的正投影也可至少部分交叠。在这些实施例中，将平坦化层PLN中的过孔设置在像素限定结构38位置处，在一定程度上有助于提升显示面板的开口率等。
在此需说明的是，获得图19中所示的SEM图时，显微镜只开顶光，未开底光，反射部321反光因此亮度较高。而像素限定结构38的部分区域对应有挡光结构，而部分区域未有挡光结构，因此，其在不同区域呈现出不同的亮度，有挡光结构的区域为暗色，而没有挡光结构的区域为亮色。
如图1所示，本公开还提供一种显示面板的制作方法，包括：
步骤S100，提供衬底基板1；
步骤S200，于衬底基板1一侧形成发光结构3；
其中，步骤S200包括：
步骤S210，于衬底基板1的一侧形成反射层32，反射层32包括多个间隔分布的反射部321；
步骤S220，于反射层32远离衬底基板1的一侧形成第一导电层33，第一导电层33包括多个间隔分布的第一导电部331；
步骤S230，于衬底基板1的一侧形成像素限定结构38，像素限定结构38界定出多个阵列排列的像素区域，反射部321位于像素区域内；
步骤S240，于第一导电层33远离衬底基板1的一侧形成空穴注入层361，空穴注入层361包括第一子部3611和第二子部3612，第一子部3611位于像素区域的中间部分，第二子部3612位于像素区域的边缘部分，像素区域的中间部分与像素限定结构38之间的距离不小于像素区域的边缘部分与像素限定结构38之间的距离；在垂直于衬底基板1的方向上，第二子部3612的至少部分区域的尺寸大于第一子部3611的尺寸；
其中，反射部321和第一导电部331一一对应，且第一导电部331、反射部321在衬底基板1上的正投影至少部分交叠；
在平行于衬底基板1方向上，反射部321或第一导电部331靠近像素限定结构38的一侧与对应的像素限定结构38靠近该反射部321或该第一导电部331的一侧之间设置有间距。
如图11至图13所示，在一些实施例中，步骤S240包括：
步骤S241，如图11所示，于第一导电层33远离衬底基板1的一侧形成预埋层4，预埋层4包括多个间隔分布的预埋部41，预埋部41覆盖第一导电部331远离衬底基板1的表面，且预埋部41至少覆盖第一导电部331和反射部321的侧壁。预埋层4的材料可包括金属材料。在平行于衬底基板1的方向上，预埋部41远离反射部321的一侧与反射部321靠近该预埋部41的一侧之间的距离与第一间距L1相等；在平行于衬底基板1的方向上，预埋部41远离第一导电部331的一侧与第一导电部331靠近该预埋部41的一侧之间的距离与第二间距L2相等。第一间距L1可以为第二间距L2与第一导电层33的厚度之和。
步骤S242，如图12所示，形成像素限定结构38，像素限定结构38至少覆盖预埋部41部分顶表面以及预埋部41的侧壁；
步骤S243，如图13所示，去除预埋层4。
本公开实施方式还提供一种显示装置，包括显示面板，该显示面板可为上述任意实施方式的显示面板，其具体结构和有益效果可参考上文中显示面板的实施方式，在此不再赘述。本公开的显示装置可以是手机、平板电脑、电视等电子设备，在此不再一一列举。
需要说明的是，尽管在附图中以特定顺序描述了本公开中方法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步骤，或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行，以及/或者将一个步骤分解为多个步骤执行等，均应视为本公开的一部分。
应可理解的是，本公开不将其应用限制到本说明书提出的部件的详细结构和布置方式。本公开能够具有其他实施方式，并且能够以多种方式实现并且执行。前述变形形式和修改形式落在本公开的范围内。应可理解的是，本说明书公开和限定的本公开延伸到文中和/或附图中提到或明显的两个或两个以上单独特征的所有可替代组合。所有这些不同的组合构成本公开的多个可替代方面。本说明书的实施方式说明了已知用于实现本公开的最佳方式，并且将使本领域技术人员能够利用本公开。

Claims (23)

  1. 一种显示面板，包括衬底基板和设于所述衬底基板一侧的发光结构，所述发光结构包括：
    像素限定结构，设于所述衬底基板的一侧，所述像素限定结构界定出多个阵列排列的像素区域；
    反射层，设于所述衬底基板的一侧，所述反射层包括多个间隔分布的反射部，所述反射部位于所述像素区域内；
    第一导电层，设于所述反射层远离所述衬底基板的一侧，所述第一导电层包括多个间隔分布的第一导电部；
    空穴注入层，设于所述第一导电层远离所述衬底基板的一侧，所述空穴注入层包括第一子部和第二子部，所述第一子部位于所述像素区域的中间部分，所述第二子部位于所述像素区域的边缘部分，所述像素区域的中间部分与所述像素限定结构之间的距离不小于所述像素区域的边缘部分与所述像素限定结构之间的距离；在垂直于所述衬底基板的方向上，所述第二子部的至少部分区域的尺寸大于所述第一子部的尺寸；
    其中，所述反射部和所述第一导电部一一对应，且所述第一导电部、所述反射部在所述衬底基板上的正投影至少部分交叠；
    在平行于所述衬底基板方向上，所述反射部或所述第一导电部靠近所述像素限定结构的一侧与对应的所述像素限定结构靠近该所述反射部或该所述第一导电部的一侧之间设置有间距。
  2. 根据权利要求1所述的显示面板，其中，所述第一子部在所述衬底基板上的正投影与所述反射部在所述衬底基板上的正投影交叠，所述第二子部在所述衬底基板上的正投影与所述反射部在所述衬底基板上的正投影不交叠；或所述第一子部在所述衬底基板上的正投影与所述第一导电部在所述衬底基板上的正投影交叠，所述第二子部在所述衬底基板上的正投影与所述第一导电部在所述衬底基板上的正投影不交叠。
  3. 根据权利要求1所述的显示面板，其中，在平行于所述衬底基板方向上，所述反射部靠近所述像素限定结构的一侧与对应的所述像素限定结构靠近该所述反射部的一侧之间设置有第一间距，
    在平行于所述衬底基板方向上，所述第一导电部靠近所述像素限定 结构的一侧与对应的所述像素限定结构靠近该所述第一导电部的一侧之间设置有第二间距；
    所述第一间距为1-3μm，所述第二间距为1-3μm。
  4. 根据权利要求1所述的显示面板，其中，所述发光结构还包括：
    第二导电层，设于所述衬底基板和所述反射层之间，所述第二导电层包括多个间隔分布的第二导电部；
    所述像素区域在所述基板上的正投影位于所述第二导电部在所述基板上的正投影之内；
    所述反射部和所述第二导电部在垂直于所述衬底基板的方向上一一对应，且所述第二导电部、所述反射部在所述衬底基板上的正投影至少部分交叠。
  5. 根据权利要求4所述的显示面板，其中，在垂直于所述衬底基板的方向上，所述像素限定结构具有靠近所述衬底基板的底端、远离所述衬底基板的顶端以及位于所述底端和顶端之间的中部，所述像素限定结构的底端界定出多个开口，所述像素限定结构的中部或顶端界定出多个出光口，所述开口一一对应暴露出所述第二导电部；
    所述出光口在所述衬底基板上的正投影位于所述开口在所述衬底基板上的正投影之内；
    所述出光口、所述反射部和所述第一导电部在所述衬底基板上的正投影至少部分交叠。
  6. 根据权利要求3所述的显示面板，其中，沿远离所述衬底基板方向，所述像素限定结构包括依次连接的第一部和第二部，所述第一部在所述衬底基板上的正投影位于所述第二部在所述衬底基板上的正投影之内，且所述第一部在衬底基板上的正投影的面积小于所述第二部在衬底基板上的正投影的面积。
  7. 根据权利要求6所述的显示面板，其中，所述第一导电部、所述反射部在所述衬底基板上的正投影的交叠区域与所述第二部在所述衬底基板上的正投影不交叠；
    所述第一间距或所述第二间距在所述衬底基板上的正投影至少部分区域位于所述第二部在所述衬底基板上的正投影之内。
  8. 根据权利要求6所述的显示面板，其中，在垂直于所述衬底基板的方向上，所述第一部的高度不小于所述反射部和所述第一导电部的厚度之和。
  9. 根据权利要求6所述的显示面板，其中，在垂直于所述衬底基板的方向上，所述第二部的截面的远离所述衬底基板的一边为朝远离所述衬底基板方向凸出的弧形。
  10. 根据权利要求6所述的显示面板，其中，在垂直于所述衬底基板的方向上，所述像素限定结构的截面为蘑菇形。
  11. 根据权利要求1所述的显示面板，其中，所述反射部具有靠近所述衬底基板第一表面、远离所述衬底基板的第二表面、以及位于所述第一表面和所述第二表面之间的侧壁，所述第一导电部接触所述反射部的所述侧壁和所述第二表面。
  12. 根据权利要求4所述的显示面板，其中，所述发光结构还包括：
    第一绝缘层，设于所述反射层和所述第一导电层之间，所述第一绝缘层包括多个间隔分布的第一绝缘部，所述第一绝缘部位于所述像素区域内，所述反射部在所述衬底基板上的正投影位于所述第一绝缘部在所述衬底基板上的正投影之内。
  13. 根据权利要求12所述的显示面板，其中，所述第一绝缘部接触所述反射部的侧壁和远离所述衬底基板的一侧表面，且所述第一绝缘部接触所述第二导电部被所述反射部暴露的区域。
  14. 根据权利要求4所述的显示面板，其中，所述发光结构还包括：
    第二绝缘层，设于所述第二导电层远离所述衬底基板的一侧，所述第二绝缘层包括多个间隔分布的第二绝缘部，所述第二绝缘部位于所述像素区域，所述第二绝缘部接触所述第二导电部被所述反射部暴露的区域，且所述第二绝缘部接触所述第一导电部和所述反射部的侧壁，并接触所述第一导电部的远离所述衬底基板的至少部分表面。
  15. 根据权利要求4所述的显示面板，其中，所述第二导电层的厚度为8-18nm，所述反射层的厚度为60-150nm，所述第一导电层的厚度为8-18nm；
    在垂直于所述衬底基板的方向上，所述像素限定结构的高度为1.2-2 μm。
  16. 根据权利要求4所述的显示面板，其中，所述显示面板还包括：
    平坦化层，设于所述发光结构靠近所述衬底基板的一侧；
    所述第一导电部通过所述平坦化层中的过孔与像素电路连接，所述过孔在衬底基板上的正投影与所述像素限定结构在所述衬底基板上的正投影至少部分交叠。
  17. 根据权利要求12所述的显示面板，其中，所述第一绝缘部包括：
    第三子部，位于所述反射部远离所述衬底基板的一侧；
    第四子部，与所述第二导电部接触；
    第五子部，连接于所述第三子部和所述第四子部之间，所述第五子部的延伸方向与所述衬底基板之间具有夹角，所述夹角为锐角。
  18. 根据权利要求1所述的显示面板，其中，所述显示面板还包括：
    平坦化层，设于所述发光结构靠近所述衬底基板的一侧；
    所述第一导电部在所述衬底基板上的正投影与所述像素限定结构在所述衬底基板上的正投影至少部分交叠；
    所述第一导电部至少部分区域与所述平坦化层接触。
  19. 根据权利要求4所述的显示面板，其中，所述显示面板还包括：
    第一绝缘层，位于所述反射层和所述第一导电层之间，所述第一绝缘层包括多个间隔分布的第一绝缘部，且所述第一绝缘部至少部分覆盖所述第二导电部被所述反射部暴露的部分。
  20. 一种显示面板的制作方法，包括：
    提供衬底基板；
    于所述衬底基板一侧形成发光结构；
    其中，于所述衬底基板一侧形成发光结构包括：
    于所述衬底基板的一侧形成反射层，所述反射层包括多个间隔分布的反射部；
    于所述反射层远离所述衬底基板的一侧形成第一导电层，所述第一导电层包括多个间隔分布的第一导电部；
    于所述衬底基板的一侧形成像素限定结构，所述像素限定结构界定出多个阵列排列的像素区域，所述反射部位于所述像素区域内；
    于所述第一导电层远离所述衬底基板的一侧形成空穴注入层，所述空穴注入层包括第一子部和第二子部，所述第一子部位于所述像素区域的中间部分，所述第二子部位于所述像素区域的边缘部分，所述像素区域的中间部分与所述像素限定结构之间的距离不小于所述像素区域的边缘部分与所述像素限定结构之间的距离；在垂直于所述衬底基板的方向上，所述第二子部的至少部分区域的尺寸大于所述第一子部的尺寸；
    其中，所述反射部和所述第一导电部一一对应，且所述第一导电部、所述反射部在所述衬底基板上的正投影至少部分交叠；
    在平行于所述衬底基板方向上，所述反射部或所述第一导电部靠近所述像素限定结构的一侧与对应的所述像素限定结构靠近该所述反射部或该所述第一导电部的一侧之间设置有第一间距。
  21. 根据权利要求20所述的显示面板的制作方法，其中，于所述衬底基板的一侧形成像素限定结构包括：
    于所述第一导电层远离所述衬底基板的一侧形成预埋层，所述预埋层包括多个间隔分布的预埋部，所述预埋部覆盖所述第一导电部远离所述衬底基板的表面，且所述预埋部至少覆盖所述第一导电部和所述反射部的侧壁；
    形成所述像素限定结构，所述像素限定结构至少覆盖所述预埋部部分顶表面以及所述预埋部的侧壁；
    去除所述预埋层。
  22. 根据权利要求21所述的显示面板的制作方法，其中，在平行于所述衬底基板的方向上，所述预埋部远离所述反射部的一侧与所述反射部靠近该所述预埋部的一侧之间的距离与所述第一间距相等。
  23. 一种显示装置，包括如权利要求1-19任一项所述的显示面板。
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CN117202726A (zh) * 2023-09-13 2023-12-08 绵阳惠科光电科技有限公司 显示面板及其制备方法

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CN107579098A (zh) * 2017-08-21 2018-01-12 上海天马微电子有限公司 一种阵列基板及显示装置
CN109950298A (zh) * 2019-04-17 2019-06-28 京东方科技集团股份有限公司 一种显示基板及其制备方法、显示装置

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CN107579098A (zh) * 2017-08-21 2018-01-12 上海天马微电子有限公司 一种阵列基板及显示装置
CN109950298A (zh) * 2019-04-17 2019-06-28 京东方科技集团股份有限公司 一种显示基板及其制备方法、显示装置

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Publication number Priority date Publication date Assignee Title
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