WO2023155249A1 - 驱动基板及其制作方法、显示面板 - Google Patents

驱动基板及其制作方法、显示面板 Download PDF

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Publication number
WO2023155249A1
WO2023155249A1 PCT/CN2022/079165 CN2022079165W WO2023155249A1 WO 2023155249 A1 WO2023155249 A1 WO 2023155249A1 CN 2022079165 W CN2022079165 W CN 2022079165W WO 2023155249 A1 WO2023155249 A1 WO 2023155249A1
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Prior art keywords
layer
gate
via hole
light
source
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PCT/CN2022/079165
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English (en)
French (fr)
Inventor
刘方梅
曹蔚然
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深圳市华星光电半导体显示技术有限公司
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Priority to US17/753,685 priority Critical patent/US20240088300A1/en
Publication of WO2023155249A1 publication Critical patent/WO2023155249A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs

Definitions

  • Embodiments of the present application provide a driving substrate, a manufacturing method thereof, and a display panel, which are used to reduce the size of the driving substrate, thereby realizing a narrow frame design.
  • An embodiment of the present application provides a drive substrate, including a display area and a non-display area, the non-display area is located on at least one side of the display area, and the drive substrate includes:
  • the first thin film transistor structure is arranged on the substrate and corresponds to the non-display area, and the first thin film transistor structure includes a first light shielding layer, a first active layer, a first gate, and a first source An electrode and a first drain, the first light-shielding layer is multiplexed as a second gate, and the first light-shielding layer is electrically connected to the first gate;
  • a buffer layer located on a side of the first light-shielding layer away from the substrate
  • an interlayer dielectric layer located on a side of the first gate away from the gate insulating layer, the interlayer dielectric layer including a second via hole and a third via hole;
  • the second via hole and the third via hole penetrate through the interlayer dielectric layer, and the first source and the first drain pass through the second via hole and the third via respectively.
  • the hole is electrically connected to the first active layer;
  • the passivation layer is located on a side of the interlayer dielectric layer away from the first gate.
  • the driving substrate further includes:
  • a buffer layer located on a side of the first light-shielding layer away from the substrate
  • a gate insulating layer located on a side of the first active layer away from the buffer layer;
  • an interlayer dielectric layer located on a side of the first gate away from the gate insulating layer, and the interlayer dielectric layer includes a first via hole, a second via hole, a third via hole and a fourth via hole;
  • first via hole, the second via hole and the third via hole penetrate the interlayer dielectric layer
  • the fourth via hole penetrates the interlayer dielectric layer and the buffer layer, so The first source and the first drain are electrically connected to the first active layer through the second via hole and the third via hole respectively;
  • connection electrode includes a first connection electrode, a second connection electrode and a connection part, the first connection electrode and the second connection electrode are connected through the connection part, and the connection part is located between the layers On the dielectric layer, the first connection electrode is disposed in the first via hole, and the second connection electrode is disposed in the fourth via hole;
  • the passivation layer is located on a side of the interlayer dielectric layer away from the first gate, and covers the first source, the first drain and the connection electrode.
  • connection electrode and the first source electrode are arranged in the same layer.
  • the driving substrate further includes:
  • the third thin film transistor structure is located on the substrate and corresponds to the display area, and the third thin film transistor structure includes a third active layer, a fourth gate, a third source and a third drain.
  • the first light-shielding layer and the second light-shielding layer are arranged in the same layer;
  • the first active layer, the second active layer and the third active layer are arranged in the same layer;
  • the first source, the first drain, the second source, the second drain, the third source and the third drain are arranged in the same layer.
  • the driving substrate further includes:
  • the fourth thin film transistor structure is located on the substrate and corresponds to the display area, and the fourth thin film transistor structure includes a fourth active layer, a fifth gate, a fourth source and a fourth drain; wherein
  • the fourth active layer and the third active layer are arranged in the same layer;
  • the fifth gate and the fourth gate are arranged in the same layer;
  • the orthographic projection of the first light-shielding layer on the substrate covers the orthographic projection of the first active layer on the substrate.
  • the first active layer is an amorphous silicon active layer or a metal oxide active layer
  • the second active layer and the third active layer are metal oxide active layer
  • an embodiment of the present application further provides a display panel, the display panel includes a driving substrate and a light-emitting functional layer, the light-emitting functional layer is disposed on the driving substrate and located in the display area, and the driving substrate include:
  • the first thin film transistor structure is arranged on the substrate and corresponds to the non-display area, and the first thin film transistor structure includes a first light shielding layer, a first active layer, a first gate, and a first source An electrode and a first drain, the first light-shielding layer is multiplexed as a second gate, and the first light-shielding layer is electrically connected to the first gate;
  • the second thin film transistor structure is located on the substrate and corresponds to the display area, and the second thin film transistor structure includes a second light shielding layer, a second active layer, a third gate, a second source and a second light shielding layer.
  • the second drain is electrically connected to the second light shielding layer and the second source.
  • the driving substrate further includes:
  • a buffer layer located on a side of the first light-shielding layer away from the substrate
  • a gate insulating layer located on a side of the first active layer away from the buffer layer, and covering the first active layer, the gate insulating layer includes a first via hole, and the first via hole penetrates the gate insulating layer and the buffer layer;
  • connecting electrodes the connecting electrodes being arranged in the first via holes
  • an interlayer dielectric layer located on a side of the first gate away from the gate insulating layer, the interlayer dielectric layer including a second via hole and a third via hole;
  • the second via hole and the third via hole penetrate through the interlayer dielectric layer, and the first source and the first drain pass through the second via hole and the third via respectively.
  • the hole is electrically connected to the first active layer;
  • the passivation layer is located on a side of the interlayer dielectric layer away from the first gate.
  • the driving substrate further includes:
  • a buffer layer located on a side of the first light-shielding layer away from the substrate
  • first via hole, the second via hole and the third via hole penetrate the interlayer dielectric layer
  • the fourth via hole penetrates the interlayer dielectric layer and the buffer layer, so The first source and the first drain are electrically connected to the first active layer through the second via hole and the third via hole respectively;
  • connection electrode includes a first connection electrode, a second connection electrode and a connection part, the first connection electrode and the second connection electrode are connected through the connection part, and the connection part is located between the layers On the dielectric layer, the first connection electrode is disposed in the first via hole, and the second connection electrode is disposed in the fourth via hole;
  • the passivation layer is located on a side of the interlayer dielectric layer away from the first gate, and covers the first source, the first drain and the connection electrode.
  • connection electrode and the first source electrode are arranged in the same layer.
  • the driving substrate further includes:
  • the third thin film transistor structure is located on the substrate and corresponds to the display area, and the third thin film transistor structure includes a third active layer, a fourth gate, a third source and a third drain.
  • the first active layer, the second active layer and the third active layer are arranged in the same layer;
  • the first source, the first drain, the second source, the second drain, the third source and the third drain are arranged in the same layer.
  • the driving substrate further includes:
  • the fourth thin film transistor structure is located on the substrate and corresponds to the display area, and the fourth thin film transistor structure includes a fourth active layer, a fifth gate, a fourth source and a fourth drain; wherein
  • the fourth active layer and the third active layer are arranged in the same layer;
  • the fifth gate and the fourth gate are arranged in the same layer;
  • the fourth source, the fourth drain and the third source and the third drain are arranged in the same layer.
  • the embodiment of the present application also provides a method for manufacturing a driving substrate, and the method for manufacturing the driving substrate includes the following steps:
  • a first thin film transistor structure and a second thin film transistor structure are formed on the substrate, and the first thin film transistor structure includes a first light shielding layer, a first active layer, a first gate, a first source and a first Drain, the first light-shielding layer is multiplexed as a second gate, the first light-shielding layer is electrically connected to the first gate, the second thin film transistor structure includes a second light-shielding layer, and the second active layer, a third gate, a second source and a second drain, and the second light-shielding layer is electrically connected to the second source.
  • the step of forming the first thin film transistor structure and the second thin film transistor structure on the substrate further includes:
  • first metal layer on the gate insulating layer, and patterning the first metal layer to form the first gate, the third gate and a connecting electrode, the connecting electrode being disposed on In the first via hole, the first gate and the first light-shielding layer are electrically connected through the connecting electrode;
  • a second metal layer is formed on the interlayer dielectric layer, and the second metal layer is patterned to form the first source, the first drain, the second source, the The second drain electrode and the auxiliary electrode, the first source electrode and the first drain electrode are electrically connected to the first active layer through the second via hole and the third via hole respectively, and the auxiliary electrode an electrode is disposed in the first contact hole, and the second source and the second drain are electrically connected to the second active layer through the second contact hole and the third contact hole respectively;
  • a passivation layer is formed on the interlayer dielectric layer.
  • the step of forming the first thin film transistor structure and the second thin film transistor structure on the substrate further includes:
  • An interlayer dielectric layer is formed on the first gate, and the interlayer dielectric layer is processed by a yellow light process to form a first via hole, a second via hole, a third via hole, and a fourth via hole , a first contact hole, a second contact hole and a third contact hole;
  • connection electrode includes a first connection electrode, a second connection electrode and a connection part, and the first connection electrode and the second connection electrode are connected through the connection part , the first connection electrode is disposed in the first via hole, the second connection electrode is disposed in the fourth via hole, the first source and the first drain pass through the
  • the second via hole is electrically connected to the third via hole; the auxiliary electrode is disposed in the first contact hole, and the second source and the second drain pass through the second contact hole and the second drain respectively.
  • the third contact hole is electrically connected to the active layer;
  • the second thin film transistor structure is located on the substrate and corresponds to the display area.
  • the second TFT structure includes a second light shielding layer, a second active layer, a third gate, a second source and a second drain.
  • the second light shielding layer is electrically connected to the second source.
  • FIG. 1 is a schematic plan view of a driving substrate provided in an embodiment of the present application
  • FIG. 2 is a schematic diagram of the first structure of the driving substrate provided by the embodiment of the present application.
  • FIG. 3 is a schematic diagram of the second structure of the drive substrate provided by the embodiment of the present application.
  • FIG. 4 is a flowchart of steps of a method for manufacturing a driving substrate provided in an embodiment of the present application
  • FIG. 6 is a second schematic diagram of the manufacturing method of the driving substrate provided in the embodiment of the present application.
  • first and second are used for descriptive purposes only, and cannot be interpreted as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features.
  • a feature defined as “first” or “second” may explicitly or implicitly include one or more of said features.
  • “plurality” means two or more, unless otherwise specifically defined.
  • Embodiments of the present application provide a driving substrate, a manufacturing method thereof, and a display panel. Each will be described in detail below. It should be noted that the description sequence of the following embodiments is not intended to limit the preferred sequence of the embodiments.
  • An embodiment of the present application provides a driving substrate.
  • the driving substrate includes a display area and a non-display area, and the non-display area is located on at least one side of the display area.
  • the driving substrate includes a substrate, a first thin film transistor structure and a second thin film transistor structure.
  • the first thin film transistor structure is disposed on the substrate and corresponds to the non-display area.
  • the first TFT structure includes a first light shielding layer, a first active layer, a first gate, a first source and a first drain.
  • the first light shielding layer is multiplexed as the second grid.
  • the first light shielding layer is electrically connected to the first grid.
  • the second thin film transistor structure is located on the substrate and corresponds to the display area.
  • the second TFT structure includes a second light shielding layer, a second active layer, a third gate, a second source and a second drain.
  • the second light shielding layer is electrically connected to the second source.
  • the first light-shielding layer can not only be used to shield the first active layer from light to prevent the stability of the first active layer from being affected by light; and, since the first light-shielding layer is multiplexed as the second gate, And the first light-shielding layer is electrically connected to the first gate, thus forming two conductive channels, increasing the on-state current, thereby effectively suppressing the negative drift of the threshold voltage, and improving the mobility of carriers, thereby facilitating Narrow bezel design.
  • the second light-shielding layer can not only be used for light-shielding the second active layer to prevent light from affecting the stability of the second active layer; Both the second active layer and the third gate have overlapping regions, and parasitic capacitances are formed between the second light shielding layer, the second active layer and the third gate respectively.
  • the driving substrate is working, as the voltage applied to the data signal line is different, the voltage on the second drain will change accordingly, so that the voltage on the second light-shielding layer will also change accordingly, thereby affecting the voltage of the second active layer. electrical properties.
  • the second light-shielding layer By connecting the second light-shielding layer to the second source to form an equipotential, the voltage change on the second light-shielding layer can be prevented from affecting the electrical properties of the second active layer.
  • the non-display area may include a gate driving area.
  • FIG. 1 is a schematic plan view of a driving substrate provided by an embodiment of the present application.
  • FIG. 2 is a schematic diagram of the first structure of the driving substrate provided by the embodiment of the present application.
  • the driving substrate 10 includes a display area AA and a non-display area NA, and the non-display area NA is located on at least one side of the display area AA.
  • the non-display area NA includes a gate driving area GOA.
  • the driving substrate 10 includes a substrate 11 , a first thin film transistor structure T1 and a second thin film transistor structure T2 .
  • the first TFT structure T1 is disposed on the substrate 11 and corresponds to the non-display area NA.
  • the first thin film transistor structure T1 includes a first light shielding layer LS1 , a first active layer 12 a, a first gate 12 b, a first source 12 c and a first drain 12 d.
  • the first light shielding layer LS1 is multiplexed as the second gate 12e.
  • the first light shielding layer LS1 is electrically connected to the first gate 12b.
  • the second TFT structure T2 is located on the substrate 11 and corresponds to the display area AA.
  • the second TFT structure T2 includes a second light shielding layer LS2, a second active layer 13a, a third gate 13b, a second source 13c and a second drain 13d.
  • the second light shielding layer LS2 is electrically connected to the second source electrode 13c.
  • the first light-shielding layer LS1 can not only be used to shade the first active layer 12a, preventing light from affecting the stability of the first active layer 12a;
  • Two gates 12e, and the first light-shielding layer LS1 is electrically connected to the first gate 12b, thus forming two conductive channels, increasing the on-state current, thereby effectively suppressing the negative drift of the threshold voltage, and improving the current carrying capacity.
  • the second light shielding layer LS2 can not only be used to shield the second active layer 13a from light, preventing the light from affecting the stability of the second active layer 13a; and the second light shielding layer LS2 is electrically connected to the second source electrode 13c, because The second light-shielding layer LS2 overlaps with the second active layer 13a and the third gate 13b, and parasitic capacitances are formed between the second light-shielding layer LS2, the second active layer 13a and the third gate 13b.
  • the voltage on the second drain 13d will change accordingly, so that the voltage on the second light-shielding layer LS2 will also change accordingly, thereby affecting the second active Electrical properties of layer 13a.
  • the voltage change on the second light-shielding layer LS2 can be prevented from affecting the electrical properties of the second active layer 13a.
  • the first light-shielding layer LS1 and the second light-shielding layer LS2 are located on the substrate 11
  • the driving substrate 10 further includes a buffer layer 16 , a gate insulating layer 17 , a connection electrode 12 f , an interlayer dielectric layer 18 and a passivation layer 19 .
  • the buffer layer 16 is located on a side of the first light shielding layer LS1 away from the substrate 11 .
  • the gate insulating layer 17 is located on the side of the first active layer 12a away from the buffer layer 16, and covers the first active layer 12a and the second active layer 13a.
  • the gate insulating layer 17 includes a first via hole h1, the first via The hole h1 penetrates the gate insulating layer 17 and the buffer layer 16 .
  • the connection electrode 12f is disposed in the first via hole h1.
  • the interlayer dielectric layer 18 is located on the side of the first gate 12 b away from the gate insulating layer 17 , and the interlayer dielectric layer 18 includes a second via hole h2 and a third via hole h3 . Wherein, the second via hole h2 and the third via hole h3 penetrate through the interlayer dielectric layer 18 .
  • the first source electrode 12c is electrically connected to the first active layer 12a through the second via hole h2.
  • the first drain electrode 12d is electrically connected to the first active layer 12a through the third via hole h3.
  • the passivation layer 19 is located on the side of the interlayer dielectric layer 18 away from the first gate 12b.
  • the driving substrate 10 may further include a third thin film transistor structure T3 disposed on the substrate 11 and corresponding to the display area AA.
  • the third thin film transistor structure T3 includes a third active layer 14a, a fourth gate 14b, a third source 14c and a third drain 14d.
  • the first light-shielding layer LS1 and the second light-shielding layer LS2 are arranged in the same layer.
  • the first active layer 12a, the second active layer 13a and the third active layer 14a are arranged in the same layer.
  • the first gate 12b, the third gate 13b and the fourth gate 14b are arranged in the same layer.
  • the first source 12c, the first drain 12d, the second source 13c, the second drain 13d, the third source 14c and the third drain 14d are arranged in the same layer.
  • the second thin film transistor structure T2 in the embodiment of the present application may be a driving thin film transistor
  • the third thin film transistor structure T3 may be a switching thin film transistor
  • the driving circuit architecture located in the display area AA is 2T1C (that is, two thin film transistors and a capacitor).
  • the 2T1C driving circuit architecture has a simple manufacturing process, and since two thin film transistors are used to drive a sub-pixel unit This facilitates miniaturization.
  • the first active layer 12a is an amorphous silicon active layer
  • the second active layer 13a and the third active layer 14a are metal oxide active layers.
  • the active layer of the thin film transistor in the display area AA of the driving substrate 10 and the active layer of the thin film transistor in the non-display area NA are made of different materials
  • the thin film transistor in the display area AA of the driving substrate 10 is made of different materials.
  • the active layer is made of metal oxide semiconductor material, so that when the resolution of the display product is very high, due to the relatively high mobility of the metal oxide semiconductor material, it can also meet the charging rate requirements of the high resolution display product.
  • the active layer of the thin film transistor in the non-display area NA of the drive substrate 10 is made of a non-metal oxide semiconductor material, which can prevent the threshold voltage V th of the thin film transistor from drifting under long-term bias, and ensure that the characteristics of the thin film transistor will not changes to ensure the normal scanning function of the circuit in the non-display area NA.
  • the first active layer 12a may be a metal oxide active layer
  • the second active layer 13a and the third active layer 14a may be metal oxide active layers.
  • both the display area AA and the non-display area NA of the driving substrate 10 are made of metal oxide semiconductor materials. Therefore, the preparation of the first active layer 12 a , the second active layer 13 a and the third active layer 14 a can be completed simultaneously through one mask process, which simplifies the process of the driving substrate 10 .
  • the number of gallium atoms in the first sub-active layer and the third sub-active layer may be the same or different.
  • the first sub-active layer includes a nitrogen-doped InGaZnO active layer
  • the third sub-active layer includes a nitrogen-doped InGaZnO active layer. Due to the strong binding ability of nitrogen atoms and oxygen vacancies, the introduction of nitrogen elements can occupy oxygen vacancies, which can effectively control the carrier concentration and defect concentration in the active layer, thereby improving the mobility of the display panel and improving the driving substrate. reliability.
  • At least one of phosphorus, fluorine, selenium or tellurium may be doped into the first sub-active layer and/or the third sub-active layer.
  • the driving substrate 10 may further include a fourth thin film transistor structure T4 disposed on the substrate 11 and corresponding to the display area AA.
  • the fourth thin film transistor structure T4 includes a fourth active layer 15a, a fifth gate 15b, a fourth source 15c and a fourth drain 15d.
  • the fourth active layer 15a and the third active layer 14a are arranged in the same layer.
  • the fifth gate 15b and the fourth gate 14b are arranged in the same layer.
  • the fourth source 15c, the fourth drain 15d, the third source 14c, and the third drain 14d are arranged in the same layer.
  • the second thin film transistor structure T2 in the embodiment of the present application may be a driving thin film transistor
  • the third thin film transistor structure T3 may be a switching thin film transistor
  • the fourth thin film transistor structure T4 may be a sensing thin film transistor.
  • the architecture of the driving circuit located in the display area AA is 3T1C (that is, three thin film transistors and one capacitor).
  • 3T1C that is, three thin film transistors and one capacitor.
  • V data the data voltage
  • the written V data will be transmitted to the gate of the driving TFT and stored on the storage capacitor C st , while the source of the driving TFT is in a floating state, and its initial potential is uncertain, so the 2T driving structure
  • the lower monitor has severe flicker (Flicker).
  • another gate line can be used to control the writing of the source voltage of the drive TFT, that is, there are 2 gate lines, which greatly improves the display effect, and the 3T drive architecture can also accurately drive the TFT mobility. Detection, to further improve the display quality, most of the current large-size OLED displays use 3T drive architecture.
  • the gate insulating layer 17 may be a structure provided on the entire surface, and the first gate 12b may extend inward. It can be understood that the in-plane width of the first active layer 12a is smaller than the in-plane width of the first gate 12b, and the in-plane width of the first light shielding layer LS1 is greater than the in-plane width of the first active layer 12a. Therefore, the first via hole h1 directly penetrates the gate insulating layer 17, so that the connection electrode 12f will not be short-circuited with the first active layer 12a.
  • FIG. 3 is a schematic diagram of a second structure of the driving substrate provided by the embodiment of the present application.
  • the driving substrate 10 includes a display area AA and a non-display area NA, and the non-display area NA is located on at least one side of the display area AA.
  • the non-display area NA includes a gate driving area GOA.
  • the second TFT structure T2 includes a second light shielding layer LS2, a second active layer 13a, a third gate 13b, a second source 13c and a second drain 13d.
  • the second light shielding layer LS2 is electrically connected to the second source electrode 13c.
  • the first light-shielding layer LS1 can not only be used to shade the first active layer 12a, preventing light from affecting the stability of the first active layer 12a;
  • Two gates 12e, and the first light-shielding layer LS1 is electrically connected to the first gate 12b, thus forming two conductive channels, increasing the on-state current, thereby effectively suppressing the negative drift of the threshold voltage, and improving the current carrying capacity.
  • the second light shielding layer LS2 can not only be used to shield the second active layer 13a from light, preventing the light from affecting the stability of the second active layer 13a; and the second light shielding layer LS2 is electrically connected to the second source electrode 13c, because The second light-shielding layer LS2 overlaps with the second active layer 13a and the third gate 13b, and parasitic capacitances are formed between the second light-shielding layer LS2, the second active layer 13a and the third gate 13b.
  • the voltage on the second drain 13d will change accordingly, so that the voltage on the second light-shielding layer LS2 will also change accordingly, thereby affecting the second active Electrical properties of layer 13a.
  • the voltage change on the second light-shielding layer LS2 can be prevented from affecting the electrical properties of the second active layer 13a.
  • the first light-shielding layer LS1 and the second light-shielding layer LS2 are located on the substrate 11
  • the driving substrate 10 further includes a buffer layer 16 , a gate insulating layer 17 , a connection electrode 12 f , an interlayer dielectric layer 18 and a passivation layer 19 .
  • the connection electrode 12f includes a first connection electrode 12f1, a second connection electrode 12f2, and a connection portion 12f3, and the first connection electrode 12f1 and the second connection electrode 12f2 are connected through the connection portion 12f3.
  • the buffer layer 16 is located on a side of the first light shielding layer LS1 away from the substrate 11 .
  • the gate insulating layer 17 is located on a side of the first active layer 12 a away from the buffer layer 16 .
  • the interlayer dielectric layer 18 is located on a side of the first gate 12 b away from the gate insulating layer 17 .
  • the connecting portion 12 f3 is located on the interlayer dielectric layer 18 , and the interlayer dielectric layer 18 includes a first via hole h1 , a second via hole h2 , a third via hole h3 and a fourth via hole h4 .
  • the first via hole h1 , the second via hole h2 and the third via hole h3 penetrate through the interlayer dielectric layer 18 .
  • the fourth via hole h4 penetrates through the interlayer dielectric layer 18 and the buffer layer 16 .
  • the first source 12c and the first drain 12d are electrically connected to the first active layer 12a through the second via hole h2 and the third via hole h3 respectively.
  • the first connection electrode 12f1 is disposed in the first via hole h1
  • the second connection electrode 12f2 is disposed in the fourth via hole h4.
  • the passivation layer 19 is located on the side of the interlayer dielectric layer 18 away from the first gate 12b, and covers the first source 12c, the first drain 12d and the connecting electrode 12f.
  • the auxiliary electrode 13e is disposed in the first contact hole cnt1.
  • the second source electrode 13c and the second drain electrode 13d are electrically connected to the second active layer 13a through the second contact hole cnt2 and the third contact hole cnt3, respectively.
  • the substrate 11 includes a first flexible layer, a first barrier layer, a second flexible layer, and a second barrier layer that are sequentially stacked.
  • the first barrier layer is used to prevent water and oxygen from penetrating through one side of the first flexible layer to the structure above the first barrier layer, so as to prevent damage to the driving substrate 10 .
  • the materials of the first barrier layer, the second barrier layer and the buffer layer 16 include but not limited to silicon-containing oxide, nitride or oxynitride.
  • the material of the first barrier layer is at least one of SiO x , SiN x or SiO x N y .
  • the material of the first flexible layer can be the same as that of the second flexible layer, which can include PI (polyimide), PET (polyethylene dicarboxylate), PEN (polyethylene naphthalate), At least one of PC (polycarbonate), PES (polyethersulfone), PAR (aromatic fluorotoluene containing polyarylate), or PCO (polycyclic olefin).
  • the buffer layer 16 may be a silicon nitride layer and a silicon oxide layer stacked in layers, wherein the silicon nitride layer is used to block the intrusion of water and oxygen from one side of the second flexible layer, thereby causing damage to the film layer above the driving substrate 10. damage, the silicon oxide layer serves to insulate the thin-film transistors above it.
  • the materials of the source electrode 13c, the second drain electrode 13d, the third source electrode 14c, the third drain electrode 14d, the fourth source electrode 15c, the fourth drain electrode 15d, the connecting electrode 12f and the auxiliary electrode 13e include silver (Ag), Magnesium (Mg), Aluminum (Al), Tungsten (W), Copper (Cu), Nickel (Ni), Chromium (Cr), Molybdenum (Mo), Titanium (Ti), Platinum (Pt), Tantalum (Ta), One or any combination of neodymium (Nd) or scandium (Sc) metals, their alloys, their nitrides, etc.
  • FIG. 4 is a flow chart of the first step of the method for manufacturing the driving substrate provided in the embodiment of the present application.
  • the manufacturing method of the driving substrate includes the following steps:
  • Step B001 providing a substrate 11 .
  • Step B002 forming a first TFT structure T1 and a second TFT structure T2 on the substrate 11 .
  • the first thin film transistor structure T1 includes a first light shielding layer LS1 , a first active layer 12 a, a first gate 12 b, a first source 12 c and a first drain 12 d.
  • the first light shielding layer LS1 is multiplexed as the second gate 12e.
  • the first light shielding layer LS1 is electrically connected to the first gate 12b.
  • the second TFT structure T2 includes a second light shielding layer LS2, a second active layer 13a, a third gate 13b, a second source 13c and a second drain 13d.
  • the second light shielding layer LS2 is electrically connected to the second source electrode 13c. Please refer to Figure 5.
  • step B002 also includes forming a third TFT structure T3 and a fourth TFT structure T4.
  • the third TFT structure T3 includes a third active layer 14a, a fourth gate 14b, a third source 14c and a third drain 14d.
  • the fourth thin film transistor structure T4 includes a fourth active layer 15a, a fifth gate 15b, a fourth source 15c and a fourth drain 15d.
  • Step B002 may specifically include: firstly, forming a light-shielding material layer LS on the substrate 11 , and patterning the light-shielding material layer LS to form a first light-shielding layer LS1 and a second light-shielding layer LS2 .
  • the buffer layer 16 is formed on the first light shielding layer LS1 and the second light shielding layer LS2.
  • a semiconductor material layer 121 is formed on the buffer layer 16, and the semiconductor material layer 121 is patterned to form a first active layer 12a, a second active layer 13a, a third active layer 14a and a fourth active layer. Layer 15a.
  • a gate insulating layer 17 is formed on the buffer layer 16 , and the gate insulating layer 17 is processed by a photolithography process to form a first via hole h1 .
  • the first metal layer M1 is formed on the gate insulating layer 17, and the first metal layer M1 is patterned to form the first gate 12b, the third gate 13b, the fourth gate 14b, the fifth gate 15b, connecting the electrode 12f and the auxiliary electrode 13e.
  • the connection electrode 12f is disposed in the first via hole h1, and the first grid 12b and the first light shielding layer LS1 are electrically connected through the connection electrode 12f.
  • an interlayer dielectric layer 18 is formed on the first gate 12b, and the interlayer dielectric layer 18 is processed by using a yellow light process to form the second via hole h2, the third via hole h3, and the first contact hole cnt1 , the second contact hole cnt2, the third contact hole cnt3, the fourth contact hole cnt4, the fifth contact hole cnt5, the sixth contact hole cnt6 and the seventh contact hole cnt7.
  • a second metal layer M2 is formed on the interlayer dielectric layer 18, and the second metal layer M2 is patterned to form the first source 12c, the first drain 12d, the second source 13c, the second drain electrode 13d, the third source electrode 14c, the third drain electrode 14d, the fourth source electrode 15c, the fourth drain electrode 15d and the auxiliary electrode 13e.
  • the first source 12c and the first drain 12d are electrically connected to the first active layer 12a through the second via hole h2 and the third via hole h3 respectively.
  • the auxiliary electrode 13e is disposed in the first contact hole cnt1.
  • the second source electrode 13c and the second drain electrode 13d are electrically connected to the second active layer 13a through the second contact hole cnt2 and the third contact hole cnt3, respectively.
  • the third source 14c and the third drain 14d are electrically connected to the third active layer 14a through the fourth contact hole cnt4 and the fifth contact hole cnt5, respectively.
  • the fourth source electrode 15c and the fourth drain electrode 15d are electrically connected to the fourth active layer 15a through the sixth contact hole cnt6 and the seventh contact hole cnt7, respectively.
  • a passivation layer 19 is formed on the interlayer dielectric layer 18 , thereby forming the driving substrate 10 .
  • the gate insulating layer 17 may be a structure provided on the entire surface, and the first gate 12b may extend inward. It can be understood that the in-plane width of the first active layer 12a is smaller than the in-plane width of the first gate 12b, and the in-plane width of the first light shielding layer LS1 is greater than the in-plane width of the first active layer 12a. Therefore, the first via hole h1 directly penetrates the gate insulating layer 17, so that the connection electrode 12f will not be short-circuited with the first active layer 12a.
  • the first light-shielding layer LS1 can not only be used to shade the first active layer 12a, preventing light from affecting the stability of the first active layer 12a;
  • Two gates 12e, and the first light-shielding layer LS1 is electrically connected to the first gate 12b, thus forming two conductive channels, increasing the on-state current, thereby effectively suppressing the negative drift of the threshold voltage, and improving the current carrying capacity.
  • the mobility of the son which is conducive to the design of narrow borders.
  • the voltage on the second drain 13d will change accordingly, so that the voltage on the second light-shielding layer LS2 will also change accordingly, thereby affecting the second active Electrical properties of layer 13a.
  • the voltage change on the second light-shielding layer LS2 can be prevented from affecting the electrical properties of the second active layer 13a.
  • step B002 may specifically include:
  • the buffer layer 16 is formed on the first light shielding layer LS1 and the second light shielding layer LS2.
  • an insulating material layer 171 is formed on the first active layer 12a, the second active layer 13a, the third active layer 14a, and the fourth active layer 15a.
  • the insulating material layer 171 is patterned to form the gate insulating layer 17 .
  • a second metal layer M2 is formed on the interlayer dielectric layer 18, and the second metal layer M2 is patterned to form the first source 12c, the first drain 12d, the second source 13c, the second drain electrode 13d, third source electrode 14c, third drain electrode 14d, fourth source electrode 15c, fourth drain electrode 15d, connection electrode 12f, and auxiliary electrode 13e.
  • the connection electrode 12f includes a first connection electrode 12f1 , a second connection electrode 12f2 and a connection portion 12f3 , and the first connection electrode 12f1 and the second connection electrode 12f2 are connected through the connection portion 12f3 .
  • the first connection electrode 12f1 is disposed in the first via hole h1.
  • the second connection electrode 12f2 is disposed in the fourth via hole h4.
  • the first source 12c and the first drain 12d are electrically connected to the first active layer 12a through the second via hole h2 and the third via hole h3 respectively.
  • the auxiliary electrode 13e is disposed in the first contact hole cnt1.
  • the second source electrode 13c and the second drain electrode 13d are electrically connected to the second active layer 13a through the second contact hole cnt2 and the third contact hole cnt3, respectively.
  • the third source 14c and the third drain 14d are electrically connected to the third active layer 14a through the fourth contact hole cnt4 and the fifth contact hole cnt5, respectively.
  • the fourth source electrode 15c and the fourth drain electrode 15d are electrically connected to the fourth active layer 15a through the sixth contact hole cnt6 and the seventh contact hole cnt7, respectively.
  • a passivation layer 19 is formed on the interlayer dielectric layer 18 to form the driving substrate 10 .
  • the first light-shielding layer LS1 and the first gate 12b are electrically connected through the connection electrode 12f, since the connection electrode 12f is set on the same layer as the first source electrode 12c, that is, the connection electrode 12f The same masking process as the first source electrode 12c may be performed. Therefore, the driving substrate 10 of the embodiment of the present application further improves the carrier mobility of the non-display area NA without increasing the process cost, thereby realizing the narrow frame design.
  • the embodiment of the present application further provides a display panel, and the display panel 100 includes the driving substrate 10 and the light emitting function layer 20 described in any one of the above embodiments.
  • the light emitting functional layer 20 is disposed on the driving substrate 10 and corresponds to the display area AA.
  • the light emitting functional layer 20 includes an anode 20a, a light emitting layer 20b and a cathode 20c.
  • the display panel 100 also includes a planarization layer 21 and a pixel definition layer 22 .
  • a planarization layer 21 is provided on the passivation layer 19 .
  • the anode 20a is electrically connected to the second source 13c through a via hole.
  • the material of the anode 20a may include indium tin oxide, silver and indium tin oxide stacked in sequence.
  • the pixel definition layer 22 has an opening, and the light emitting layer 20 b is defined in the opening of the pixel definition layer 22 .
  • the cathode 20c covers the light emitting layer 20b and part of the pixel definition layer 22 .

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Abstract

本申请公开了一种驱动基板及其制作方法、显示面板，驱动基板包括显示区和非显示区。驱动基板包括衬底、第一薄膜晶体管结构和第二薄膜晶体管结构。第一薄膜晶体管结构设置于衬底上，且对应于非显示区。第一薄膜晶体管结构包括第一遮光层、第一有源层、第一栅极。第一遮光层复用为第二栅极。第一遮光层与第一栅极电连接。

Description

驱动基板及其制作方法、显示面板 技术领域
本申请涉及显示技术领域，尤其涉及一种驱动基板及其制作方法、显示面板。
 背景技术
随着显示技术的发展，对大尺寸高品质显示器件的需求也越来越多，其中氧化物半导体由于其良好的特性和制备工艺优势常被用于大尺寸高品质OLED（Organic Light-Emitting Diode，有机发光二极管）显示应用中。阵列基板栅极驱动技术(Gate DriveronArray，简称GOA)，是将栅极驱动电路集成在显示面板的阵列基板上，以实现逐行扫描的驱动方式，从而可以省掉栅极驱动电路部分，具有降低生产成本和实现面板窄边框设计的优点，为多种显示器所使用。GOA技术作为一种主流显示技术，在高品质显示器件中实现低成本和实现边框（Border）缩减中具有明显的优势。众所周知，GOA区域需要采用大电流驱动，因此如果采用常规的器件结构，需要把TFT（Thin Film Transistor，薄膜晶体管）尺寸变大来增大电流，TFT的尺寸在一定程度上限制了GOA电路大小及边框的大小，因此，提升GOA区域TFT载流子迁移率可以减小驱动基板的尺寸，从而实现窄边框设计。
故，有必要提出一种新的技术方案，以解决上述技术问题。
 技术问题
本申请实施例提供一种驱动基板及其制作方法、显示面板，用于减小驱动基板的尺寸，从而实现窄边框设计。
 技术解决方案
本申请实施例提供一种驱动基板，包括显示区和非显示区，所述非显示区位于所述显示区的至少一侧，所述驱动基板包括：
衬底；
第一薄膜晶体管结构，设置于所述衬底上，且对应于所述非显示区，所述第一薄膜晶体管结构包括第一遮光层、第一有源层、第一栅极、第一源极和第一漏极，所述第一遮光层复用为第二栅极，所述第一遮光层与所述第一栅极电连接；
第二薄膜晶体管结构，位于所述衬底上，且对应于所述显示区，所述第二薄膜晶体管结构包括第二遮光层，第二有源层、第三栅极、第二源极和第二漏极，所述第二遮光层和所述第二源极电连接。
在本申请实施例提供的驱动基板中，所述第一遮光层位于所述衬底上，所述驱动基板还包括：
缓冲层，位于所述第一遮光层远离所述衬底的一面；
栅极绝缘层，位于所述第一有源层远离所述缓冲层的一面，且覆盖所述第一有源层，所述栅极绝缘层包括第一过孔，所述第一过孔贯穿所述栅极绝缘层和所述缓冲层；
连接电极，所述连接电极设置在所述第一过孔内；
层间介质层，位于所述第一栅极远离所述栅极绝缘层的一面，所述层间介质层包括第二过孔和第三过孔；
其中，所述第二过孔和所述第三过孔贯穿所述层间介质层，所述第一源极和所述第一漏极分别通过所述第二过孔和所述第三过孔与所述第一有源层电连接；
钝化层，位于所述层间介质层远离所述第一栅极的一面。
在本申请实施例提供的驱动基板中，所述驱动基板还包括：
缓冲层，位于所述第一遮光层远离所述衬底的一面；
栅极绝缘层，位于所述第一有源层远离所述缓冲层的一面；
层间介质层，位于所述第一栅极远离所述栅极绝缘层的一面，所述层间介质层包括第一过孔、第二过孔、第三过孔和第四过孔；
其中，所述第一过孔、所述第二过孔和所述第三过孔贯穿所述层间介质层，所述第四过孔贯穿所述层间介质层和所述缓冲层，所述第一源极和所述第一漏极分别通过所述第二过孔和所述第三过孔与所述第一有源层电连接；
连接电极，所述连接电极包括第一连接电极、第二连接电极和连接部，所述第一连接电极和所述第二连接电极通过所述连接部连接，所述连接部位于所述层间介质层上，所述第一连接电极设置在所述第一过孔内，所述第二连接电极设置在所述第四过孔内；
钝化层，位于所述层间介质层远离所述第一栅极的一面，且覆盖所述第一源极、第一漏极和所述连接电极。
在本申请实施例提供的驱动基板中，所述连接电极与所述第一源极同层设置。
在本申请实施例提供的驱动基板中，所述驱动基板还包括：
第三薄膜晶体管结构，位于所述衬底上，且对应于所述显示区，所述第三薄膜晶体管结构包括第三有源层、第四栅极、第三源极和第三漏极。
在本申请实施例提供的驱动基板中，所述第一遮光层和所述第二遮光层同层设置；
所述第一有源层、所述第二有源层和所述第三有源层同层设置；
所述第一栅极、所述第三栅极和所述第四栅极同层设置；
所述第一源极、所述第一漏极、所述第二源极、所述第二漏极、所述第三源极和所述第三漏极同层设置。
在本申请实施例提供的驱动基板中，所述驱动基板还包括：
第四薄膜晶体管结构，位于衬底上，且对应于所述显示区，所述第四薄膜晶体管结构包括第四有源层、第五栅极、第四源极和第四漏极；其中
所述第四有源层和所述第三有源层同层设置；
所述第五栅极和所述第四栅极同层设置；
所述第四源极、所述第四漏极和所述第三源极、所述第三漏极同层设置。
在本申请实施例提供的驱动基板中，所述第一遮光层于所述衬底上的正投影覆盖所述第一有源层于所述衬底上的正投影。
在本申请实施例提供的驱动基板中，所述第一有源层为非晶硅有源层或金属氧化物有源层，所述第二有源层和所述第三有源层为金属氧化物有源层。
相应的，本申请实施例还提供一种显示面板，所述显示面板包括驱动基板和发光功能层，所述发光功能层设置在所述驱动基板上，且位于所述显示区，所述驱动基板包括：
衬底；
第一薄膜晶体管结构，设置于所述衬底上，且对应于所述非显示区，所述第一薄膜晶体管结构包括第一遮光层、第一有源层、第一栅极、第一源极和第一漏极，所述第一遮光层复用为第二栅极，所述第一遮光层与所述第一栅极电连接；
第二薄膜晶体管结构，位于所述衬底上，且对应于所述显示区，所述第二薄膜晶体管结构包括第二遮光层，第二有源层、第三栅极、第二源极和第二漏极，所述第二遮光层和所述第二源极电连接。
在本申请实施例提供的显示面板中，所述驱动基板还包括：
缓冲层，位于所述第一遮光层远离所述衬底的一面；
栅极绝缘层，位于所述第一有源层远离所述缓冲层的一面，且覆盖所述第一有源层，所述栅极绝缘层包括第一过孔，所述第一过孔贯穿所述栅极绝缘层和所述缓冲层；
连接电极，所述连接电极设置在所述第一过孔内；
层间介质层，位于所述第一栅极远离所述栅极绝缘层的一面，所述层间介质层包括第二过孔和第三过孔；
其中，所述第二过孔和所述第三过孔贯穿所述层间介质层，所述第一源极和所述第一漏极分别通过所述第二过孔和所述第三过孔与所述第一有源层电连接；
钝化层，位于所述层间介质层远离所述第一栅极的一面。
在本申请实施例提供的显示面板中，所述驱动基板还包括：
缓冲层，位于所述第一遮光层远离所述衬底的一面；
栅极绝缘层，位于所述第一有源层远离所述缓冲层的一面；
层间介质层，位于所述第一栅极远离所述栅极绝缘层的一面，所述层间介质层包括第一过孔、第二过孔、第三过孔和第四过孔；
其中，所述第一过孔、所述第二过孔和所述第三过孔贯穿所述层间介质层，所述第四过孔贯穿所述层间介质层和所述缓冲层，所述第一源极和所述第一漏极分别通过所述第二过孔和所述第三过孔与所述第一有源层电连接；
连接电极，所述连接电极包括第一连接电极、第二连接电极和连接部，所述第一连接电极和所述第二连接电极通过所述连接部连接，所述连接部位于所述层间介质层上，所述第一连接电极设置在所述第一过孔内，所述第二连接电极设置在所述第四过孔内；
钝化层，位于所述层间介质层远离所述第一栅极的一面，且覆盖所述第一源极、第一漏极和所述连接电极。
在本申请实施例提供的显示面板中，所述连接电极与所述第一源极同层设置。
在本申请实施例提供的显示面板中，所述驱动基板还包括：
第三薄膜晶体管结构，位于所述衬底上，且对应于所述显示区，所述第三薄膜晶体管结构包括第三有源层、第四栅极、第三源极和第三漏极。
在本申请实施例提供的显示面板中，所述第一遮光层和所述第二遮光层同层设置；
所述第一有源层、所述第二有源层和所述第三有源层同层设置；
所述第一栅极、所述第三栅极和所述第四栅极同层设置；
所述第一源极、所述第一漏极、所述第二源极、所述第二漏极、所述第三源极和所述第三漏极同层设置。
在本申请实施例提供的显示面板中，所述驱动基板还包括：
第四薄膜晶体管结构，位于衬底上，且对应于所述显示区，所述第四薄膜晶体管结构包括第四有源层、第五栅极、第四源极和第四漏极；其中
所述第四有源层和所述第三有源层同层设置；
所述第五栅极和所述第四栅极同层设置；
所述第四源极、所述第四漏极和所述第三源极、所述第三漏极同层设置。
在本申请实施例提供的显示面板中，所述第一遮光层于所述衬底上的正投影覆盖所述第一有源层于所述衬底上的正投影。
相应的，本申请实施例还提供一种驱动基板的制作方法，所述驱动基板的制作方法包括以下步骤：
提供一衬底；
在所述衬底上形成第一薄膜晶体管结构和第二薄膜晶体管结构，所述第一薄膜晶体管结构包括第一遮光层、第一有源层、第一栅极、第一源极和第一漏极，所述第一遮光层复用为第二栅极，所述第一遮光层和所述第一栅极电连接，所述第二薄膜晶体管结构包括第二遮光层，第二有源层、第三栅极、第二源极和第二漏极，所述第二遮光层和所述第二源极电连接。
在本申请实施例提供的驱动基板的制作方法中，所述在所述衬底上形成第一薄膜晶体管结构和第二薄膜晶体管结构的步骤还包括：
在所述衬底上形成遮光材料层，并对所述遮光材料层图案化，以形成所述第一遮光层和所述第二遮光层；
在所述第一遮光层和所述第二遮光层上形成缓冲层；
在所述缓冲层上形成半导体材料层，并对所述半导体材料层图案化，以形成所述第一有源层和所述第二有源层；
在所述缓冲层上形成栅极绝缘层，并利用黄光制程对所述栅极绝缘层进行处理，以形成第一过孔；
在所述栅极绝缘层上形成第一金属层，并对所述第一金属层图案化，以形成所述第一栅极、所述第三栅极和连接电极，所述连接电极设置在所述第一过孔内，所述第一栅极和所述第一遮光层通过所述连接电极电连接；
在所述第一栅极上形成层间介质层，并利用黄光制程对所述层间介质层进行处理，以形成第二过孔、第三过孔、第一接触孔、第二接触孔和第三接触孔；
在所述层间介质层上形成第二金属层，并对所述第二金属层图案化，以形成所述第一源极、所述第一漏极、所述第二源极、所述第二漏极和辅助电极，所述第一源极和所述第一漏极分别通过所述第二过孔和所述第三过孔与所述第一有源层电连接，所述辅助电极设置在所述第一接触孔内，所述第二源极和所述第二漏极分别通过所述第二接触孔和所述第三接触孔与所述第二有源层电连接；
在所述层间介质层上形成钝化层。
在本申请实施例提供的驱动基板的制作方法中，所述在所述衬底上形成第一薄膜晶体管结构和第二薄膜晶体管结构的步骤还包括：
在所述衬底上形成遮光材料层，并对所述遮光材料层图案化，以形成所述第一遮光层和所述第二遮光层；
在所述第一遮光层和所述第二遮光层上形成缓冲层；
在所述缓冲层上形成半导体材料层，并对所述半导体材料层图案化，以形成所述第一有源层和所述第二有源层；
在所述第一有源层和所述第二有源层上形成绝缘材料层；
在所述绝缘材料层上形成第一金属层，并对所述第一金属层图案化，以形成所述第一栅极、所述第三栅极；
利用所述第一栅极、所述第三栅极为自对准，对所述绝缘材料层图案化，以形成栅极绝缘层；
在所述第一栅极上形成层间介质层，并利用黄光制程对所述层间介质层进行处理，以形成第一过孔、第二过孔、第三过孔、第四过孔、第一接触孔、第二接触孔和第三接触孔；
在所述层间介质层上形成第二金属层，并对所述第二金属层图案化，以形成所述第一源极、所述第一漏极、连接电极、所述第二源极、所述第二漏极和辅助电极，其中，所述连接电极包括第一连接电极、第二连接电极和连接部，所述第一连接电极和所述第二连接电极通过所述连接部连接，所述第一连接电极设置在所述第一过孔内，所述第二连接电极设置在所述第四过孔内，所述第一源极和所述第一漏极分别通过所述第二过孔和所述第三过孔电连接；所述辅助电极设置在所述第一接触孔内，所述第二源极、所述第二漏极分别通过所述第二接触孔和所述第三接触孔与所述有源层电连接；
在所述层间介质层上形成钝化层。
 有益效果
本申请实施例提供一种驱动基板及其制作方法、显示面板，驱动基板包括显示区和非显示区，非显示区位于显示区的至少一侧。驱动基板包括衬底、第一薄膜晶体管结构和第二薄膜晶体管结构。第一薄膜晶体管结构设置于衬底上，且对应于非显示区。第一薄膜晶体管结构包括第一遮光层、第一有源层、第一栅极、第一源极和第一漏极。第一遮光层复用为第二栅极。第一遮光层与第一栅极电连接。第二薄膜晶体管结构位于所述衬底上，且对应于显示区。第二薄膜晶体管结构包括第二遮光层，第二有源层、第三栅极、第二源极和第二漏极。第二遮光层和第二源极电连接。在本申请实施例中，第一遮光层不仅能用于为第一有源层遮光，防止光照影响第一有源层的稳定性；并且，由于第一遮光层复用为第二栅极，且第一遮光层和第一栅极电连接，因此形成了两个导电沟道，增大了开态电流，进而有效抑制了阈值电压的负漂，提高了载流子的迁移率，从而利于窄边框设计。另外，第二遮光层不仅能用于为第二有源层遮光，防止光照影响第二有源层的稳定性；并且，第二遮光层和第二源极电连接，由于第二遮光层与第二有源层和第三栅极均存在重叠区域，第二遮光层与第二有源层和第三栅极之间分别会形成寄生电容。在驱动基板工作时，随着数据信号线上加载的电压不同，第二漏极上的电压会随之变化，使得第二遮光层上的电压也会随之改变从而影响第二有源层的电性能。通过将第二遮光电极与第二源极连接形成等电位，可以避免第二遮光层上的电压变化影响第二有源层的电性能。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的驱动基板的一种平面示意图；
图2为本申请实施例提供的驱动基板的第一种结构示意图；
图3为本申请实施例提供的驱动基板的第二种结构示意图；
图4为本申请实施例提供的驱动基板的制作方法的一种步骤流程图；
图5为本申请实施例提供的驱动基板的制作方法的第一种示意图；
图6为本申请实施例提供的驱动基板的制作方法的第二种示意图；
图7为本申请实施例提供显示面板的结构示意图。
 本发明的实施方式
为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请作进一步地详细描述，请参照附图中的图式，其中相同的组件符号代表相同的组件，以下的说明是基于所示的本申请具体实施例，其不应被视为限制本申请未在此详述的其他具体实施例。本说明书所使用的词语“实施例”意指实例、示例或例证。
在本申请的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
本申请实施例提供一种驱动基板及其制作方法、显示面板。以下分别进行详细说明。需说明的是，以下实施例的描述顺序不作为对实施例优选顺序的限定。
本申请实施例提供一种驱动基板，驱动基板包括显示区和非显示区，非显示区位于显示区的至少一侧。驱动基板包括衬底、第一薄膜晶体管结构和第二薄膜晶体管结构。第一薄膜晶体管结构设置于衬底上，且对应于非显示区。第一薄膜晶体管结构包括第一遮光层、第一有源层、第一栅极、第一源极和第一漏极。第一遮光层复用为第二栅极。第一遮光层与第一栅极电连接。第二薄膜晶体管结构位于衬底上，且对应于显示区。第二薄膜晶体管结构包括第二遮光层，第二有源层、第三栅极、第二源极和第二漏极。第二遮光层和第二源极电连接。在本申请实施例中，第一遮光层不仅能用于为第一有源层遮光，防止光照影响第一有源层的稳定性；并且，由于第一遮光层复用为第二栅极，且第一遮光层和第一栅极电连接，因此形成了两个导电沟道，增大了开态电流，进而有效抑制了阈值电压的负漂，提高了载流子的迁移率，从而利于窄边框设计。另外，第二遮光层不仅能用于为第二有源层遮光，防止光照影响第二有源层的稳定性；并且，第二遮光层和第二源极电连接，由于第二遮光层与第二有源层和第三栅极均存在重叠区域，第二遮光层与第二有源层和第三栅极之间分别会形成寄生电容。在驱动基板工作时，随着数据信号线上加载的电压不同，第二漏极上的电压会随之变化，使得第二遮光层上的电压也会随之改变从而影响第二有源层的电性能。通过将第二遮光层与第二源极连接形成等电位，可以避免第二遮光层上的电压变化影响第二有源层的电性能。
需要说明的是，在本申请实施例中，非显示区可以包括栅极驱动区。
下面通过具体实施例对本申请提供的驱动基板进行详细的阐述。
请参考图1和图2，图1为本申请实施例提供的驱动基板的一种平面结构示意图。图2为本申请实施例提供的驱动基板的第一种结构示意图。驱动基板10包括显示区AA和非显示区NA，非显示区NA位于显示区AA的至少一侧。非显示区NA包括栅极驱动区GOA。
驱动基板10包括衬底11、第一薄膜晶体管结构T1和第二薄膜晶体管结构T2。第一薄膜晶体管结构T1设置于衬底11上，且对应于非显示区NA。第一薄膜晶体管结构T1包括第一遮光层LS1、第一有源层12a、第一栅极12b、第一源极12c和第一漏极12d。第一遮光层LS1复用为第二栅极12e。第一遮光层LS1与第一栅极12b电连接。第二薄膜晶体管结构T2位于衬底11上，且对应于显示区AA。第二薄膜晶体管结构T2包括第二遮光层LS2，第二有源层13a、第三栅极13b、第二源极13c和第二漏极13d。第二遮光层LS2和第二源极13c电连接。在本申请实施例中，第一遮光层LS1不仅能用于为第一有源层12a遮光，防止光照影响第一有源层12a的稳定性；并且，由于第一遮光层LS1复用为第二栅极12e，且第一遮光层LS1和第一栅极12b电连接，因此形成了两个导电沟道，增大了开态电流，进而有效抑制了阈值电压的负漂，提高了载流子的迁移率，从而利于窄边框设计。另外，第二遮光层LS2不仅能用于为第二有源层13a遮光，防止光照影响第二有源层13a的稳定性；并且，第二遮光层LS2和第二源极13c电连接，由于第二遮光层LS2与第二有源层13a和第三栅极13b均存在重叠区域，第二遮光层LS2与第二有源层13a和第三栅极13b之间分别会形成寄生电容。在驱动基板工作时，随着数据信号线上加载的电压不同，第二漏极13d上的电压会随之变化，使得第二遮光层LS2上的电压也会随之改变从而影响第二有源层13a的电性能。通过将第二遮光层LS2与第二源极13c连接形成等电位，可以避免第二遮光层LS2上的电压变化影响第二有源层13a的电性能。
进一步的，第一遮光层LS1和第二遮光层LS2位于衬底11上，驱动基板10还包括缓冲层16、栅极绝缘层17、连接电极12f、层间介质层18和钝化层19。缓冲层16位于第一遮光层LS1远离衬底11的一面。栅极绝缘层17位于第一有源层12a远离缓冲层16的一面，且覆盖第一有源层12a和第二有源层13a，栅极绝缘层17包括第一过孔h1，第一过孔h1贯穿栅极绝缘层17和缓冲层16。连接电极12f设置在第一过孔h1内。层间介质层18位于第一栅极12b远离栅极绝缘层17的一面，层间介质层18包括第二过孔h2和第三过孔h3。其中，第二过孔h2和第三过孔h3贯穿层间介质层18。第一源极12c通过第二过孔h2与第一有源层12a电连接。第一漏极12d通过第三过孔h3与第一有源层12a电连接。钝化层19位于层间介质层18远离第一栅极12b的一面。
在一些实施例中，第一遮光层LS1于衬底11上的正投影覆盖第一有源层12a于衬底11上的正投影。在本申请实施例中，由于第一遮光层LS1于衬底11上的正投影覆盖第一有源层12a于衬底11上的正投影，使得具有光线照射至第一有源层12a上时，可以使得光线完全被第一遮光层LS1遮挡，从而提高驱动基板10的稳定性。
可选的，在一些实施例中，驱动基板10还可以包括第三薄膜晶体管结构T3，第三薄膜晶体管结构T3设置在衬底11上，且对应于显示区AA。第三薄膜晶体管结构T3包括第三有源层14a、第四栅极14b、第三源极14c和第三漏极14d。在本申请实施例中，第一遮光层LS1和第二遮光层LS2同层设置。第一有源层12a、第二有源层13a和第三有源层14a同层设置。第一栅极12b、第三栅极13b和第四栅极14b同层设置。第一源极12c、第一漏极12d、第二源极13c、第二漏极13d、第三源极14c和第三漏极14d同层设置。
应该理解的是，本申请实施例中的第二薄膜晶体管结构T2可以是驱动薄膜晶体管，第三薄膜晶体管结构T3可以是开关薄膜晶体管。
在本申请实施例中，位于显示区AA的驱动电路架构为2T1C（即两个薄膜晶体管和一个电容），2T1C驱动电路架构具有制备工艺简单，且由于利用两个薄膜晶体管驱动一个子像素单元，其利于实现微型化。
在一些实施例中，第一有源层12a为非晶硅有源层，第二有源层13a和第三有源层14a为金属氧化物有源层。在本申请实施例中，驱动基板10的显示区AA的薄膜晶体管的有源层和非显示区NA的薄膜晶体管的有源层采用不同的材料制成，驱动基板10的显示区AA的薄膜晶体管的有源层采用金属氧化物半导体材料制成，这样当显示产品的分辨率很高时，由于金属氧化物半导体材料的迁移率比较高，也能够满足高分辨率显示产品的充电率要求。驱动基板10的非显示区NA的薄膜晶体管的有源层采用非金属氧化物的半导体材料制成，这样能够防止薄膜晶体管在长期偏压作用下阈值电压V th漂移，保证薄膜晶体管的特性不会发生变化，保证非显示区NA的电路正常的扫描功能。
在一些实施例中，第一有源层12a可以是金属氧化物有源层，第二有源层13a和第三有源层14a可以是金属氧化物有源层。在本申请实施例中，驱动基板10的显示区AA和非显示区NA的均采用金属氧化物半导体材料制成。因此，可通过一道掩模工艺同时完成第一有源层12a、第二有源层13a和第三有源层14a的制备，简化了驱动基板10的工艺制程。
在一些实施例中，第一有源层12a可以包括依次叠层设置的第一子有源层第二子有源层和第三子有源层，其中，第一子有源层和第三子有源层中镓的原子数大于第二子有源层中镓的原子数。由于镓与氧原子的结合能力强，可以有效抑制深能级缺陷的产生，从而提高器件的稳定性，从而改善显示面板的可靠度。第二子有源层中铟原子数、镓原子数和锌原子数的比值为铟：镓：锌=1:1:1，保证了驱动基板10的导电性和迁移率。
在一些实施例中，第一子有源层的材料包括铟镓锌氧化物，其中，第一子有源层中铟原子数、镓原子数和锌原子数的比值为铟：镓：锌=M:1:N，其中，0＜M＜1，0＜N＜1。例如，在一实施方式中，第一子有源层中铟原子数、镓原子数和锌原子数的比值为铟：镓：锌=0.1:1:0.2、0.4:1:0.2、0.3:1:0.3或0.1:1:0.8中的任意一种。
第三子有源层的材料包括铟镓锌氧化物，第三子有源层中铟原子数、镓原子数和锌原子数的比值为铟：镓：锌=X:1:Y，0＜X＜1，0＜Y＜1。例如，在一实施方式中，第一子有源层中铟原子数、镓原子数和锌原子数的比值为铟：镓：锌=0.3:1:0.2、0.4:1:0.2、0.3:1:0.3或0.6:1:0.8中的任意一种。
需要说明的是，第一子有源层和第三子有源层中镓的原子数可以相同也可以不同。
第二子有源层的材料包括铟镓锌氧化物，其中，第二子有源层中铟原子数、镓原子数和锌原子数的比值为铟：镓：锌=1:1:1。
在一些实施例中，第一子有源层包括氮元素掺杂的铟镓锌氧化物有源层，第三子有源层包括氮元素掺杂的铟镓锌氧化物有源层。由于氮原子与氧空位具有较强的结合能力，引入氮元素可以占据氧空位，有效调控了有源层中载流子浓度与缺陷浓度，从而提高了显示面板的迁移率以及改善了驱动基板的可靠度。
在一些实施例中，还可以将磷、氟、硒或碲中的至少一者掺杂至第一子有源层和/或第三子有源层中。
在一些实施例中，驱动基板10还可以包括第四薄膜晶体管结构T4，第四薄膜晶体管结构T4设置在衬底11上，且对应于显示区AA。第四薄膜晶体管结构T4包括第四有源层15a、第五栅极15b、第四源极15c和第四漏极15d。第四有源层15a和第三有源层14a同层设置。第五栅极15b和第四栅极14b同层设置。第四源极15c、第四漏极15d和第三源极14c、第三漏极14d同层设置。
应该理解的是，本申请实施例中的第二薄膜晶体管结构T2可以是驱动薄膜晶体管，第三薄膜晶体管结构T3可以是开关薄膜晶体管，第四薄膜晶体管结构T4可以是感应薄膜晶体管。
在本申请实施例中，位于显示区AA的驱动电路架构为3T1C（即三个薄膜晶体管和一个电容），在2T驱动架构下，对于单颗子像素，只有一条Gate line来控制数据电压(V data)的写入，写入的V data会传到驱动TFT的栅极并存储在存储电容C st上，而驱动TFT的源极处于悬空（Floating）状态，其初始电位不定，因此2T驱动架构下显示器存在较严重的闪烁（Flicker）。而3T驱动架构下，可以通过另一条Gate line控制驱动TFT源极电压的写入，即有2条Gate line，从而极大改善显示效果，并且3T驱动架构下还能进行准确的驱动TFT迁移率侦测，进一步提升显示质量，当前大尺寸OLED显示器大多采用3T驱动架构。
应该理解的是，在本申请实施例中，栅极绝缘层17可以为整面设置的结构，第一栅极12b可以向面内延伸。可以理解为，第一有源层12a在面内的宽度小于第一栅极12b的在面内的宽度，且第一遮光层LS1在面内的宽度大于第一有源层12a在面内的宽度，因此，第一过孔h1直接贯穿栅极绝缘层17，从而，连接电极12f不会与第一有源层12a短接。
请参考图3，图3为本申请实施例提供的驱动基板的第二种结构示意图。驱动基板10包括显示区AA和非显示区NA，非显示区NA位于显示区AA的至少一侧。非显示区NA包括栅极驱动区GOA。
驱动基板10包括衬底11、第一薄膜晶体管结构T1和第二薄膜晶体管结构T2。第一薄膜晶体管结构T1设置于衬底11上，且对应于非显示区NA。第一薄膜晶体管结构T1包括第一遮光层LS1、第一有源层12a、第一栅极12b、第一源极12c和第一漏极12d。第一遮光层LS1复用为第二栅极12e。第一遮光层LS1与第一栅极12b电连接。第二薄膜晶体管结构T2位于衬底11上，且对应于显示区AA。第二薄膜晶体管结构T2包括第二遮光层LS2，第二有源层13a、第三栅极13b、第二源极13c和第二漏极13d。第二遮光层LS2和第二源极13c电连接。在本申请实施例中，第一遮光层LS1不仅能用于为第一有源层12a遮光，防止光照影响第一有源层12a的稳定性；并且，由于第一遮光层LS1复用为第二栅极12e，且第一遮光层LS1和第一栅极12b电连接，因此形成了两个导电沟道，增大了开态电流，进而有效抑制了阈值电压的负漂，提高了载流子的迁移率，从而利于窄边框设计。另外，第二遮光层LS2不仅能用于为第二有源层13a遮光，防止光照影响第二有源层13a的稳定性；并且，第二遮光层LS2和第二源极13c电连接，由于第二遮光层LS2与第二有源层13a和第三栅极13b均存在重叠区域，第二遮光层LS2与第二有源层13a和第三栅极13b之间分别会形成寄生电容。在驱动基板工作时，随着数据信号线上加载的电压不同，第二漏极13d上的电压会随之变化，使得第二遮光层LS2上的电压也会随之改变从而影响第二有源层13a的电性能。通过将第二遮光层LS2与第二源极13c连接形成等电位，可以避免第二遮光层LS2上的电压变化影响第二有源层13a的电性能。
进一步的，第一遮光层LS1和第二遮光层LS2位于衬底11上，驱动基板10还包括缓冲层16、栅极绝缘层17、连接电极12f、层间介质层18和钝化层19。连接电极12f包括第一连接电极12f1、第二连接电极12f2和连接部12f3，第一连接电极12f1和第二连接电极12f2通过连接部12f3连接。缓冲层16位于第一遮光层LS1远离衬底11的一面。栅极绝缘层17位于第一有源层12a远离缓冲层16的一面。层间介质层18位于第一栅极12b远离栅极绝缘层17的一面。连接部12f3位于层间介质层18上，层间介质层18包括第一过孔h1、第二过孔h2、第三过孔h3和第四过孔h4。其中，第一过孔h1、第二过孔h2和第三过孔h3贯穿层间介质层18。第四过孔h4贯穿层间介质层18和缓冲层16。第一源极12c和第一漏极12d分别通过第二过孔h2和第三过孔h3与第一有源层12a电连接。第一连接电极12f1设置在第一过孔h1内，第二连接电极12f2设置在第四过孔h4内。钝化层19位于层间介质层18远离第一栅极12b的一面，且覆盖第一源极12c、第一漏极12d和连接电极12f。
辅助电极13e设置在第一接触孔cnt1内。第二源极13c和第二漏极13d分别通过第二接触孔cnt2和第三接触孔cnt3与第二有源层13a电连接。
在本申请实施例中，第一遮光层LS1和第一栅极12b通过连接电极12f电连接，由于连接电极12f与第一源极12c同层设置，即连接电极12f与第一源极12c可以通过同一道掩模工艺制程。因此，本申请实施例的驱动基板10在不增加工艺成本的情况下，进一步提高了非显示区NA的载流子迁移率，从而实现了窄边框的设计。
应该理解的是，在本申请实施例中，栅极绝缘层17通过以第一栅极12b为自对准形成，连接电极12f与第一源极12c同层设置，第一过孔h1直接贯穿层间介质层18，第四过孔h4直接贯穿层间介质层18和缓冲层16，从而，连接电极12f不会与第一有源层12a短接。
可选的，在一些实施例中，衬底11包括依次层叠设置的第一柔性层、第一阻挡层、第二柔性层、第二阻挡层。第一阻挡层用于防止水氧通过第一柔性层的一侧渗透至第一阻挡层上面的结构，防止损坏驱动基板10。在一些实施例中，第一阻挡层、第二阻挡层和缓冲层16的材质包括但不限于含硅的氧化物、氮化物或氮氧化物。例如，第一阻挡层的材质为SiO x、SiN x或SiO xN y中的至少一种。第一柔性层的材料可以和第二柔性层的材料相同，其可以包括PI（聚酰亚胺）、PET（聚二甲酸乙二醇酯）、PEN（聚萘二甲酸乙二醇脂）、PC（聚碳酸酯）、PES（聚醚砜）、PAR（含有聚芳酯的芳族氟甲苯）或PCO（多环烯烃）中的至少一种。缓冲层16可以是叠层设置的氮化硅层和氧化硅层，其中，氮化硅层的用于阻挡水氧由第二柔性层的一侧入侵，从而对驱动基板10上方的膜层造成损害，氧化硅层用于保温上方的薄膜晶体管。
第一有源层12a、第二有源层13a、第三有源层14a和第四有源层15a间隔设置在缓冲层16上。第一有源层12a、第二有源层13a、第三有源层14a和第四有源层15a的材质可以是铟镓锌氧化物、铟锌锡氧化物或铟镓锌锡氧化物中的一种或其任意组合。或者，第一有源层12a、第二有源层13a、第三有源层14a和第四有源层15a的材质也可以是LTPO(Low Temperature Polycrystalline Oxide，低温多晶氧化物)。第一遮光层LS1、第二遮光层LS2、第一栅极12b、第三栅极13b、第四栅极14b、第五栅极15b、第一源极12c、第一漏极12d、第二源极13c、第二漏极13d、第三源极14c、第三漏极14d、第四源极15c、第四漏极15d、连接电极12f和辅助电极13e的材质包括如银(Ag)、镁(Mg)、铝(Al)、钨(W)、铜(Cu)、镍(Ni)、铬(Cr)、钼(Mo)、钛(Ti)、铂(Pt)、钽(Ta)、钕(Nd)或钪(Sc)的金属、它们的合金、它们的氮化物等中的一种或其任意组合。
栅极绝缘层17、层间介质层18和钝化层19的材质包括氧化硅、氮化硅或氮氧化硅中的一种或其任意组合。
相应的，请参考图4，图4为本申请实施例提供的驱动基板的制作方法的第一种步骤流程图。驱动基板的制作方法包括以下步骤：
步骤B001：提供一衬底11。
步骤B002：在衬底11上形成第一薄膜晶体管结构T1和第二薄膜晶体管结构T2。第一薄膜晶体管结构T1包括第一遮光层LS1、第一有源层12a、第一栅极12b、第一源极12c和第一漏极12d。第一遮光层LS1复用为第二栅极12e。第一遮光层LS1和第一栅极12b电连接。第二薄膜晶体管结构T2包括第二遮光层LS2，第二有源层13a、第三栅极13b、第二源极13c和第二漏极13d。第二遮光层LS2和第二源极13c电连接。请参考图5。
进一步的，步骤B002还包括形成第三薄膜晶体管结构T3和第四薄膜晶体管结构T4。其中，第三薄膜晶体管结构T3包括第三有源层14a、第四栅极14b、第三源极14c和第三漏极14d。第四薄膜晶体管结构T4包括第四有源层15a、第五栅极15b、第四源极15c和第四漏极15d。
步骤B002具体可以包括：首先，在衬底11上形成遮光材料层LS，并对遮光材料层LS图案化，以形成第一遮光层LS1和第二遮光层LS2。
其次，在第一遮光层LS1和第二遮光层LS2上形成缓冲层16。
接下来，在缓冲层16上形成半导体材料层121，并对半导体材料层121图案化，以形成第一有源层12a、第二有源层13a、第三有源层14a和第四有源层15a。
然后，在缓冲层16上形成栅极绝缘层17，并利用黄光制程对栅极绝缘层17进行处理，以形成第一过孔h1。
随后，在栅极绝缘层17上形成第一金属层M1，并对第一金属层M1图案化，以形成第一栅极12b、第三栅极13b、第四栅极14b、第五栅极15b、连接电极12f和辅助电极13e。连接电极12f设置在第一过孔h1内，第一栅极12b和第一遮光层LS1通过连接电极12f电连接。
接下来，在第一栅极12b上形成层间介质层18，并利用黄光制程对层间介质层18进行处理，以形成第二过孔h2、第三过孔h3、第一接触孔cnt1、第二接触孔cnt2、第三接触孔cnt3、第四接触孔cnt4、第五接触孔cnt5、第六接触孔cnt6和第七接触孔cnt7。
接下来，在层间介质层18上形成第二金属层M2，并对第二金属层M2图案化，以形成第一源极12c、第一漏极12d、第二源极13c、第二漏极13d、第三源极14c、第三漏极14d、第四源极15c、第四漏极15d和辅助电极13e。第一源极12c和第一漏极12d分别通过第二过孔h2和第三过孔h3与第一有源层12a电连接。辅助电极13e设置在第一接触孔cnt1内。第二源极13c和第二漏极13d分别通过第二接触孔cnt2和第三接触孔cnt3与第二有源层13a电连接。第三源极14c和第三漏极14d分别通过第四接触孔cnt4和第五接触孔cnt5与第三有源层14a电连接。第四源极15c和第四漏极15d分别通过第六接触孔cnt6和第七接触孔cnt7与第四有源层15a电连接。
最后，在层间介质层18上形成钝化层19，由此，形成驱动基板10。
在本申请实施例提供的驱动基板的制作方法中，栅极绝缘层17可以为整面设置的结构，第一栅极12b可以向面内延伸。可以理解为，第一有源层12a在面内的宽度小于第一栅极12b的在面内的宽度，且第一遮光层LS1在面内的宽度大于第一有源层12a在面内的宽度，因此，第一过孔h1直接贯穿栅极绝缘层17，从而，连接电极12f不会与第一有源层12a短接。在本申请实施例中，第一遮光层LS1不仅能用于为第一有源层12a遮光，防止光照影响第一有源层12a的稳定性；并且，由于第一遮光层LS1复用为第二栅极12e，且第一遮光层LS1和第一栅极12b电连接，因此形成了两个导电沟道，增大了开态电流，进而有效抑制了阈值电压的负漂，提高了载流子的迁移率，从而利于窄边框设计。另外，第二遮光层LS2不仅能用于为第二有源层13a遮光，防止光照影响第二有源层13a的稳定性；并且，第二遮光层LS2和第二源极13c电连接，由于第二遮光层LS2与第二有源层13a和第三栅极13b均存在重叠区域，第二遮光层LS2与第二有源层13a和第三栅极13b之间分别会形成寄生电容。在驱动基板工作时，随着数据信号线上加载的电压不同，第二漏极13d上的电压会随之变化，使得第二遮光层LS2上的电压也会随之改变从而影响第二有源层13a的电性能。通过将第二遮光层LS2与第二源极13c连接形成等电位，可以避免第二遮光层LS2上的电压变化影响第二有源层13a的电性能。
在一些实施例中，请参考图6，步骤B002具体可以包括：
首先，在衬底11上形成遮光材料层LS，并对遮光材料层LS图案化，以形成第一遮光层LS1和第二遮光层LS2。
其次，在第一遮光层LS1和第二遮光层LS2上形成缓冲层16。
接下来，在缓冲层16上形成半导体材料层121，并对半导体材料层121图案化，以形成第一有源层12a、第二有源层13a、第三有源层14a和第四有源层15a。
然后，在第一有源层12a、第二有源层13a、第三有源层14a和第四有源层15a上形成绝缘材料层171。
随后，在栅极绝缘层17上形成第一金属层M1，并对第一金属层M1图案化，以形成第一栅极12b、第三栅极13b、第四栅极14b、第五栅极15b。
接下来，利用第一栅极12b、第三栅极13b、第四栅极14b、第五栅极15b为自对准，对绝缘材料层171图案化，以形成栅极绝缘层17。
接下来，在第一栅极12a上形成层间介质层18，并利用黄光制程对层间介质层18进行处理，以形成第一过孔h1、第二过孔h2、第三过孔h3、第一接触孔cnt1、第二接触孔cnt2、第三接触孔cnt3、第四接触孔cnt4、第五接触孔cnt5、第六接触孔cnt6和第七接触孔cnt7。
接下来，在层间介质层18上形成第二金属层M2，并对第二金属层M2图案化，以形成第一源极12c、第一漏极12d、第二源极13c、第二漏极13d、第三源极14c、第三漏极14d、第四源极15c、第四漏极15d、连接电极12f和辅助电极13e。其中，连接电极12f包括第一连接电极12f1、第二连接电极12f2和连接部12f3，第一连接电极12f1和第二连接电极12f2通过连接部12f3连接。第一连接电极12f1设置在第一过孔h1内。第二连接电极12f2设置在第四过孔h4内。第一源极12c和第一漏极12d分别通过第二过孔h2和第三过孔h3与第一有源层12a电连接。辅助电极13e设置在第一接触孔cnt1内。第二源极13c和第二漏极13d分别通过第二接触孔cnt2和第三接触孔cnt3与第二有源层13a电连接。第三源极14c和第三漏极14d分别通过第四接触孔cnt4和第五接触孔cnt5与第三有源层14a电连接。第四源极15c和第四漏极15d分别通过第六接触孔cnt6和第七接触孔cnt7与第四有源层15a电连接。
最后，在层间介质层18上形成钝化层19，以此形成驱动基板10。
在本申请实施例提供的驱动基板的制作方法中，第一遮光层LS1和第一栅极12b通过连接电极12f电连接，由于连接电极12f与第一源极12c同层设置，即连接电极12f与第一源极12c可以通过同一道掩模工艺制程。因此，本申请实施例的驱动基板10在不增加工艺成本的情况下，进一步提高了非显示区NA的载流子迁移率，从而实现了窄边框的设计。
相应的，请参考图7，本申请实施例还提供一种显示面板，显示面板100包括上述任一实施例所述的驱动基板10以及发光功能层20。发光功能层20设置在驱动基板10上，且对应于显示区AA。
具体的，发光功能层20包括阳极20a、发光层20b和阴极20c。显示面板100还包括平坦化层21和像素定义层22。平坦化层21设置在钝化层19上。阳极20a通过过孔与第二源极13c电连接。阳极20a的材料可以包括依次层叠设置的氧化铟锡、银和氧化铟锡。像素定义层22具有开口，发光层20b限定于像素定义层22的开口内。阴极20c覆盖发光层20b以及像素定义层22的一部分。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种驱动基板，其中，包括显示区和非显示区，所述非显示区位于所述显示区的至少一侧，所述驱动基板包括：
    衬底；
    第一薄膜晶体管结构，设置于所述衬底上，且对应于所述非显示区，所述第一薄膜晶体管结构包括第一遮光层、第一有源层、第一栅极、第一源极和第一漏极，所述第一遮光层复用为第二栅极，所述第一遮光层与所述第一栅极电连接；
    第二薄膜晶体管结构，位于所述衬底上，且对应于所述显示区，所述第二薄膜晶体管结构包括第二遮光层，第二有源层、第三栅极、第二源极和第二漏极，所述第二遮光层和所述第二源极电连接。
  2. 根据权利要求1所述的驱动基板，其中，所述第一遮光层位于所述衬底上，所述驱动基板还包括：
    缓冲层，位于所述第一遮光层远离所述衬底的一面；
    栅极绝缘层，位于所述第一有源层远离所述缓冲层的一面，且覆盖所述第一有源层，所述栅极绝缘层包括第一过孔，所述第一过孔贯穿所述栅极绝缘层和所述缓冲层；
    连接电极，所述连接电极设置在所述第一过孔内；
    层间介质层，位于所述第一栅极远离所述栅极绝缘层的一面，所述层间介质层包括第二过孔和第三过孔；
    其中，所述第二过孔和所述第三过孔贯穿所述层间介质层，所述第一源极和所述第一漏极分别通过所述第二过孔和所述第三过孔与所述第一有源层电连接；
    钝化层，位于所述层间介质层远离所述第一栅极的一面。
  3. 根据权利要求1所述的驱动基板，其中，所述驱动基板还包括：
    缓冲层，位于所述第一遮光层远离所述衬底的一面；
    栅极绝缘层，位于所述第一有源层远离所述缓冲层的一面；
    层间介质层，位于所述第一栅极远离所述栅极绝缘层的一面，所述层间介质层包括第一过孔、第二过孔、第三过孔和第四过孔；
    其中，所述第一过孔、所述第二过孔和所述第三过孔贯穿所述层间介质层，所述第四过孔贯穿所述层间介质层和所述缓冲层，所述第一源极和所述第一漏极分别通过所述第二过孔和所述第三过孔与所述第一有源层电连接；
    连接电极，所述连接电极包括第一连接电极、第二连接电极和连接部，所述第一连接电极和所述第二连接电极通过所述连接部连接，所述连接部位于所述层间介质层上，所述第一连接电极设置在所述第一过孔内，所述第二连接电极设置在所述第四过孔内；
    钝化层，位于所述层间介质层远离所述第一栅极的一面，且覆盖所述第一源极、第一漏极和所述连接电极。
  4. 根据权利要求3所述的驱动基板，其中，所述连接电极与所述第一源极同层设置。
  5. 根据权利要求3所述的驱动基板，其中，所述驱动基板还包括：
    第三薄膜晶体管结构，位于所述衬底上，且对应于所述显示区，所述第三薄膜晶体管结构包括第三有源层、第四栅极、第三源极和第三漏极。
  6. 根据权利要求5所述的驱动基板，其中，所述第一遮光层和所述第二遮光层同层设置；
    所述第一有源层、所述第二有源层和所述第三有源层同层设置；
    所述第一栅极、所述第三栅极和所述第四栅极同层设置；
    所述第一源极、所述第一漏极、所述第二源极、所述第二漏极、所述第三源极和所述第三漏极同层设置。
  7. 根据权利要求6所述的驱动基板，其中，所述驱动基板还包括：
    第四薄膜晶体管结构，位于衬底上，且对应于所述显示区，所述第四薄膜晶体管结构包括第四有源层、第五栅极、第四源极和第四漏极；其中
    所述第四有源层和所述第三有源层同层设置；
    所述第五栅极和所述第四栅极同层设置；
    所述第四源极、所述第四漏极和所述第三源极、所述第三漏极同层设置。
  8. 根据权利要求1所述的驱动基板，其中，所述第一遮光层于所述衬底上的正投影覆盖所述第一有源层于所述衬底上的正投影。
  9. 根据权利要求5所述的驱动基板，其中，所述第一有源层为非晶硅有源层或金属氧化物有源层，所述第二有源层和所述第三有源层为金属氧化物有源层。
  10. 一种显示面板，其中，所述显示面板包括驱动基板和发光功能层，所述发光功能层设置在所述驱动基板上，且位于所述显示区，所述驱动基板包括：
    衬底；
    第一薄膜晶体管结构，设置于所述衬底上，且对应于所述非显示区，所述第一薄膜晶体管结构包括第一遮光层、第一有源层、第一栅极、第一源极和第一漏极，所述第一遮光层复用为第二栅极，所述第一遮光层与所述第一栅极电连接；
    第二薄膜晶体管结构，位于所述衬底上，且对应于所述显示区，所述第二薄膜晶体管结构包括第二遮光层，第二有源层、第三栅极、第二源极和第二漏极，所述第二遮光层和所述第二源极电连接。
  11. 根据权利要求10所述的显示面板，其中，所述驱动基板还包括：
    缓冲层，位于所述第一遮光层远离所述衬底的一面；
    栅极绝缘层，位于所述第一有源层远离所述缓冲层的一面，且覆盖所述第一有源层，所述栅极绝缘层包括第一过孔，所述第一过孔贯穿所述栅极绝缘层和所述缓冲层；
    连接电极，所述连接电极设置在所述第一过孔内；
    层间介质层，位于所述第一栅极远离所述栅极绝缘层的一面，所述层间介质层包括第二过孔和第三过孔；
    其中，所述第二过孔和所述第三过孔贯穿所述层间介质层，所述第一源极和所述第一漏极分别通过所述第二过孔和所述第三过孔与所述第一有源层电连接；
    钝化层，位于所述层间介质层远离所述第一栅极的一面。
  12. 根据权利要求10所述的显示面板，其中，所述驱动基板还包括：
    缓冲层，位于所述第一遮光层远离所述衬底的一面；
    栅极绝缘层，位于所述第一有源层远离所述缓冲层的一面；
    层间介质层，位于所述第一栅极远离所述栅极绝缘层的一面，所述层间介质层包括第一过孔、第二过孔、第三过孔和第四过孔；
    其中，所述第一过孔、所述第二过孔和所述第三过孔贯穿所述层间介质层，所述第四过孔贯穿所述层间介质层和所述缓冲层，所述第一源极和所述第一漏极分别通过所述第二过孔和所述第三过孔与所述第一有源层电连接；
    连接电极，所述连接电极包括第一连接电极、第二连接电极和连接部，所述第一连接电极和所述第二连接电极通过所述连接部连接，所述连接部位于所述层间介质层上，所述第一连接电极设置在所述第一过孔内，所述第二连接电极设置在所述第四过孔内；
    钝化层，位于所述层间介质层远离所述第一栅极的一面，且覆盖所述第一源极、第一漏极和所述连接电极。
  13. 根据权利要求12所述的显示面板，其中，所述连接电极与所述第一源极同层设置。
  14. 根据权利要求12所述的显示面板，其中，所述驱动基板还包括：
    第三薄膜晶体管结构，位于所述衬底上，且对应于所述显示区，所述第三薄膜晶体管结构包括第三有源层、第四栅极、第三源极和第三漏极。
  15. 根据权利要求14所述的显示面板，其中，所述第一遮光层和所述第二遮光层同层设置；
    所述第一有源层、所述第二有源层和所述第三有源层同层设置；
    所述第一栅极、所述第三栅极和所述第四栅极同层设置；
    所述第一源极、所述第一漏极、所述第二源极、所述第二漏极、所述第三源极和所述第三漏极同层设置。
  16. 根据权利要求15所述的显示面板，其中，所述驱动基板还包括：
    第四薄膜晶体管结构，位于衬底上，且对应于所述显示区，所述第四薄膜晶体管结构包括第四有源层、第五栅极、第四源极和第四漏极；其中
    所述第四有源层和所述第三有源层同层设置；
    所述第五栅极和所述第四栅极同层设置；
    所述第四源极、所述第四漏极和所述第三源极、所述第三漏极同层设置。
  17. 根据权利要求10所述的显示面板，其中，所述第一遮光层于所述衬底上的正投影覆盖所述第一有源层于所述衬底上的正投影。
  18. 一种驱动基板的制作方法，其中，所述驱动基板的制作方法包括以下步骤：
    提供一衬底；
    在所述衬底上形成第一薄膜晶体管结构和第二薄膜晶体管结构，所述第一薄膜晶体管结构包括第一遮光层、第一有源层、第一栅极、第一源极和第一漏极，所述第一遮光层复用为第二栅极，所述第一遮光层和所述第一栅极电连接，所述第二薄膜晶体管结构包括第二遮光层，第二有源层、第三栅极、第二源极和第二漏极，所述第二遮光层和所述第二源极电连接。
  19. 根据权利要求18所述的驱动基板的制作方法，其中，所述在所述衬底上形成第一薄膜晶体管结构和第二薄膜晶体管结构的步骤还包括：
    在所述衬底上形成遮光材料层，并对所述遮光材料层图案化，以形成所述第一遮光层和所述第二遮光层；
    在所述第一遮光层和所述第二遮光层上形成缓冲层；
    在所述缓冲层上形成半导体材料层，并对所述半导体材料层图案化，以形成所述第一有源层和所述第二有源层；
    在所述缓冲层上形成栅极绝缘层，并利用黄光制程对所述栅极绝缘层进行处理，以形成第一过孔；
    在所述栅极绝缘层上形成第一金属层，并对所述第一金属层图案化，以形成所述第一栅极、所述第三栅极和连接电极，所述连接电极设置在所述第一过孔内，所述第一栅极和所述第一遮光层通过所述连接电极电连接；
    在所述第一栅极上形成层间介质层，并利用黄光制程对所述层间介质层进行处理，以形成第二过孔、第三过孔、第一接触孔、第二接触孔和第三接触孔；
    在所述层间介质层上形成第二金属层，并对所述第二金属层图案化，以形成所述第一源极、所述第一漏极、所述第二源极、所述第二漏极和辅助电极，所述第一源极和所述第一漏极分别通过所述第二过孔和所述第三过孔与所述第一有源层电连接，所述辅助电极设置在所述第一接触孔内，所述第二源极和所述第二漏极分别通过所述第二接触孔和所述第三接触孔与所述第二有源层电连接；
    在所述层间介质层上形成钝化层。
  20. 根据权利要求18所述的驱动基板的制作方法，其中，所述在所述衬底上形成第一薄膜晶体管结构和第二薄膜晶体管结构的步骤还包括：
    在所述衬底上形成遮光材料层，并对所述遮光材料层图案化，以形成所述第一遮光层和所述第二遮光层；
    在所述第一遮光层和所述第二遮光层上形成缓冲层；
    在所述缓冲层上形成半导体材料层，并对所述半导体材料层图案化，以形成所述第一有源层和所述第二有源层；
    在所述第一有源层和所述第二有源层上形成绝缘材料层；
    在所述绝缘材料层上形成第一金属层，并对所述第一金属层图案化，以形成所述第一栅极、所述第三栅极；
    利用所述第一栅极、所述第三栅极为自对准，对所述绝缘材料层图案化，以形成栅极绝缘层；
    在所述第一栅极上形成层间介质层，并利用黄光制程对所述层间介质层进行处理，以形成第一过孔、第二过孔、第三过孔、第四过孔、第一接触孔、第二接触孔和第三接触孔；
    在所述层间介质层上形成第二金属层，并对所述第二金属层图案化，以形成所述第一源极、所述第一漏极、连接电极、所述第二源极、所述第二漏极和辅助电极，其中，所述连接电极包括第一连接电极、第二连接电极和连接部，所述第一连接电极和所述第二连接电极通过所述连接部连接，所述第一连接电极设置在所述第一过孔内，所述第二连接电极设置在所述第四过孔内，所述第一源极和所述第一漏极分别通过所述第二过孔和所述第三过孔电连接；所述辅助电极设置在所述第一接触孔内，所述第二源极、所述第二漏极分别通过所述第二接触孔和所述第三接触孔与所述第二有源层电连接；
    在所述层间介质层上形成钝化层。
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