WO2023153334A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2023153334A1
WO2023153334A1 PCT/JP2023/003640 JP2023003640W WO2023153334A1 WO 2023153334 A1 WO2023153334 A1 WO 2023153334A1 JP 2023003640 W JP2023003640 W JP 2023003640W WO 2023153334 A1 WO2023153334 A1 WO 2023153334A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor device
heat sink
sealing resin
convex portion
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2023/003640
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English (en)
French (fr)
Japanese (ja)
Inventor
世羽 東出
勝巳 宮脇
俊一 阿部
巧弥 長峯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to US18/729,548 priority Critical patent/US20250096063A1/en
Priority to GB2408859.3A priority patent/GB2629261A/en
Priority to JP2023580222A priority patent/JPWO2023153334A1/ja
Publication of WO2023153334A1 publication Critical patent/WO2023153334A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/40—Encapsulations, e.g. protective coatings characterised by their materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/22—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections
    • H10W40/226—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections characterised by projecting parts, e.g. fins to increase surface area
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/247—Dispositions of multiple bumps
    • H10W72/248—Top-view layouts, e.g. mirror arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/877—Bump connectors and die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/40—Encapsulations, e.g. protective coatings characterised by their materials
    • H10W74/47—Encapsulations, e.g. protective coatings characterised by their materials comprising organic materials, e.g. plastics or resins
    • H10W74/473—Encapsulations, e.g. protective coatings characterised by their materials comprising organic materials, e.g. plastics or resins containing a filler
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink

Definitions

  • the present disclosure relates to semiconductor devices.
  • a semiconductor chip using a semiconductor such as Si is mounted on a wiring substrate.
  • a semiconductor device for example, a semiconductor chip using a semiconductor such as Si is mounted on a wiring substrate.
  • such a semiconductor device is generally provided with a structure in which the semiconductor chip and heat sink are sealed with resin in order to prevent failure due to water droplets or conductive foreign matter.
  • Sealing with resin is generally performed by resin molding using a mold. At this time, if the mold and the heat sink come into contact with each other, the semiconductor chip bonded to the heat sink may be damaged. Therefore, the radiator plate is buried in the sealing resin at the stage of sealing with the resin.
  • the sealing resin is resin such as epoxy and has low thermal conductivity, it impedes the heat dissipation of the semiconductor device. Therefore, it is necessary to improve the heat dissipation of the semiconductor device by exposing the embedded heat sink from the sealing resin by some method.
  • Both tools and heat sinks used for cutting or polishing have inclination and distortion.
  • the resin is partially removed by cutting or polishing to expose the heat sink from the resin.
  • a part of the surface to be exposed remains covered with the sealing resin. Therefore, in order to completely expose one surface of the heat sink from the sealing resin, it is necessary to continue cutting or polishing after the heat sink begins to be exposed.
  • a tool used for cutting, polishing, or the like comes into contact with the edge or corner of the heat sink, stress is generated on the heat sink in the direction of peeling off the semiconductor chip.
  • the joint surface between the heat sink and the semiconductor chip is peeled off due to the stress, the heat conduction from the semiconductor chip to the heat sink is hindered, and the heat dissipation of the semiconductor device is lowered.
  • the present disclosure has been made to solve the above problems, and even if a process of exposing the heat sink buried in the sealing resin is applied during manufacturing, the bonding surface between the semiconductor chip and the heat sink It is an object of the present invention to provide a semiconductor device capable of suppressing delamination and thereby suppressing deterioration of heat dissipation.
  • a semiconductor device includes a substrate, a semiconductor chip, a radiator plate, and a sealing resin.
  • the sealing resin seals the semiconductor chip and the side surface of the heat sink, and the top surface of the heat sink is the exposed surface that is exposed from the top surface of the sealing resin.
  • a concave portion is provided, and the convex portion is a portion that protrudes from the outer periphery of the exposed surface in the direction in which the side surface is facing, and the concave portion is sandwiched between the heat sinks from above and below and is located on the outer periphery of the exposed surface.
  • This is a semiconductor device in which at least the upper surface of the projection or at least the lower surface of the recess is in contact with the sealing resin.
  • FIG. 1 illustrates an example of a semiconductor device according to a first embodiment
  • FIG. FIG. 2 is a cross-sectional view taken along line AA in FIG. 1 of an example of the semiconductor device of Embodiment 1
  • FIG. 4 is a diagram showing another example of the semiconductor device of Embodiment 1
  • 4 is a cross-sectional view taken along line BB of FIG. 3 of another example of the semiconductor device of Embodiment 1
  • FIG. FIG. 10 illustrates a semiconductor device according to a second embodiment
  • 6 is a cross-sectional view of the semiconductor device of Embodiment 2, taken along line CC of FIG. 5
  • FIG. FIG. 12 illustrates a semiconductor device according to a third embodiment
  • FIG. 8 is a cross-sectional view of the semiconductor device of Embodiment 3 taken along line DD in FIG. 7
  • FIG. 12 illustrates a semiconductor device according to a fourth embodiment
  • FIG. 1 shows a semiconductor device 100 of this embodiment.
  • FIG. 2 is a cross-sectional view of the semiconductor device 100 taken along line AA of FIG.
  • a semiconductor device 100 includes a substrate 1 , a semiconductor chip 2 , electrodes 3 , a joint portion 4 , a heat sink 5 , a joint material 7 , and a sealing resin 8 .
  • the substrate 1 has an upper surface 1a and a lower surface 1b.
  • the semiconductor chip 2 has an upper surface 2a and a circuit surface 2b which is a lower surface.
  • the circuit surface 2b of the semiconductor chip 2 faces the upper surface 1a of the substrate 1. In other words, the semiconductor chip 2 is mounted face down on the substrate 1 .
  • Electrodes 3 are formed on the circuit surface 2 b of the semiconductor chip 2 .
  • the electrode 3 and the substrate 1 are joined together via the joining portion 4 .
  • a radiator plate 5 is bonded to the upper surface 2a of the semiconductor chip 2 with a bonding material 7 interposed therebetween.
  • the upper surface of the heat sink 5 is an exposed surface 5a exposed from the upper surface 8a of the sealing resin 8.
  • the exposed surface 5a of the heat sink 5 and the upper surface 8a of the sealing resin 8 are substantially flush with each other.
  • a convex portion 6a is provided on the side surface 50 of the heat sink 5.
  • the convex portion 6a is a portion that protrudes in the direction in which the side surface 50 faces from the outer periphery of the exposed surface 5a, and is a portion that does not overlap the exposed surface 5a in plan view.
  • the sealing resin 8 seals the semiconductor chip 2 , the joint portion 4 , the electrode 3 , the joint material 7 , the convex portion 6 a , the upper surface 1 a of the substrate 1 and the side surface 50 of the heat sink 5 . That is, the sealing resin 8 is in contact with at least the upper surface of the convex portion 6a.
  • the substrate 1 may be a wiring substrate using a general insulator as a base material.
  • the base material of the substrate 1 requires insulation and heat resistance.
  • the base material of the substrate 1 is, for example, a paper phenol base material, or a glass epoxy base material obtained by impregnating glass fiber with an epoxy resin. If the frequency of the electrical signal applied to the semiconductor device 100 exceeds 1 GHz, materials with lower dielectric loss are preferred. Such materials with lower dielectric loss are, for example, glass substrates or ceramic substrates such as alumina.
  • the substrate 1 may be a flexible printed circuit board using polyimide resin or various high-molecular polymers.
  • a circuit pattern necessary for the operation of the semiconductor device 100 is formed on the surface of the substrate 1 .
  • the circuit pattern is formed by a conductor.
  • the conductor is a highly conductive and workable conductor, such as a metal such as aluminum, copper, nickel, gold, or silver, or an alloy thereof.
  • the method of forming the circuit pattern may be selected from various methods such as a subtractive method or an additive method, and an appropriate method is selected according to the circuit pattern width required for the semiconductor chip 2 and the distance between the circuit patterns. OK.
  • the subtractive method is a method of forming a circuit pattern by removing unnecessary portions other than the circuit pattern from the copper-clad laminate by etching or the like.
  • the additive method is a method of forming a circuit pattern by laminating conductors necessary for the circuit pattern by vapor deposition, plating, or the like.
  • a solder resist, a positioning pattern, or the like may be formed on the upper surface 1a and the lower surface 1b of the substrate 1.
  • the solder resist is intended to prevent short circuits between circuits due to solder wetting and spreading.
  • the positioning pattern is a pattern used for positioning the semiconductor chip 2 when the semiconductor chip 2 is mounted on the substrate 1 .
  • the semiconductor chip 2 is a semiconductor chip in which a planar semiconductor element is formed on the circuit surface 2b side of the semiconductor substrate.
  • the planar semiconductor device may be an active device or a passive device or both.
  • the material of the semiconductor substrate is Si, SiC, GaAs, GaN, or the like.
  • the length of one side is about 0.05 mm to 30 mm and the thickness is about 50 ⁇ m to 750 ⁇ m.
  • Electrodes 3 are formed on the circuit surface 2 b of the semiconductor chip 2 . A current can be supplied to the circuit formed on the semiconductor chip 2 from the outside of the semiconductor chip 2 via the electrodes 3 .
  • the electrode 3 and the substrate 1 are joined together via the joining portion 4 .
  • five electrodes 3 and five joints 4 are shown in FIG. 1 as an example, any number of electrodes 3 and joints 4 can be provided according to the functions required for the semiconductor chip 2 . Moreover, the electrodes 3 and the joints 4 may be provided at arbitrary positions according to the functions required for the semiconductor chip 2 .
  • a ground conductor layer may be provided on the upper surface 2a of the semiconductor chip 2.
  • the ground conductor is, for example, copper, aluminum, gold plating, or the like.
  • the material of the electrode 3 is, for example, a highly conductive metal material such as copper or aluminum.
  • the surface of the electrode 3 may be plated with nickel or gold to prevent oxidation or corrosion.
  • the electrode 3 may be formed by an additive method using plating, vapor deposition, sputtering, or the like, or may be formed by a subtractive method using etching or the like.
  • the material of the joint 4 is, for example, a highly conductive metal material such as gold, silver, copper, aluminum, or tin.
  • the joint portion 4 serves to electrically connect the substrate 1 and the electrode 3 .
  • the thickness of the joint portion 4 is at least three times the maximum diameter of the filler contained in the sealing resin 8, which will be described later.
  • the joint 4 may be attached to either the electrode 3 or the substrate 1 in advance before the step of joining the electrode 3 and the substrate 1, or may be attached to the electrode 3 and the substrate 1 in the step of joining the electrode 3 and the substrate 1. may be supplied.
  • the method of joining the joint 4 to the electrode 3 and the substrate 1 includes, for example, a metal diffusion joining method of joining by applying heat, pressure and ultrasonic waves, a method of joining by soldering or brazing, or a conductive method.
  • a method of adhering with an adhesive and the like can be mentioned.
  • the material of the heat sink 5 is preferably a material with high thermal conductivity.
  • the material of the heat sink 5 is, for example, a metal, a ceramic material, a material containing carbon, or a composite material obtained by combining these materials at an arbitrary ratio.
  • the metal as the material of the heat sink 5 is, for example, gold, silver, copper, aluminum, tungsten, molybdenum, or the like.
  • the ceramic material as the material of the heat sink 5 is, for example, aluminum nitride or boron nitride.
  • the material containing carbon as the material of the heat sink 5 is, for example, graphite, graphene, diamond, or the like.
  • the dimensions of the heat sink 5 are designed to effectively dissipate the heat generated by the semiconductor chip.
  • the external dimensions of the semiconductor chip 2 when viewed from above are a rectangle of X mm ⁇ Y mm (only X is shown in FIG. 1), and the thickness of the heat sink 5 is Assuming that the thickness is T 1 , the outer dimensions of the heat sink 5 when viewed from above are preferably (X+2T 1 ) mm ⁇ (Y+2T 1 ) mm or more. Moreover, it is desirable that the semiconductor chip 2 is arranged in the central portion of the heat sink 5 in plan view.
  • the dimensions of the heat sink 5 may be designed based on the external dimensions of the heat generating area.
  • the heat sink 5 has a size of (A+2T mm) ⁇ (B+2T mm) or more. desirable.
  • the region 20 is arranged in the central portion of the heat sink 5 in plan view.
  • FIG. 1 shows a semiconductor device 100 in which the semiconductor chip 2 heats up intensively in the region 20 .
  • a plurality of heat sinks 5 may be mounted on one semiconductor chip 2, or one heat sink 5 may be mounted so as to cover all the heat generating locations. You can In any case, the heat generated by the semiconductor chip 2 can be effectively dissipated by mounting the radiator plate 5 so as to satisfy the above-described external dimension conditions for each heat-generating portion.
  • a convex portion 6 a is provided on the side surface 50 of the heat sink 5 , and the sealing resin 8 is in contact with the upper side of the convex portion 6 a , so that the heat sink 5 is supported by the sealing resin 8 . Therefore, separation between the heat sink 5 and the semiconductor chip 2 is less likely to occur when an external force is applied to the heat sink 5 .
  • the projected area of the convex portion 6a with respect to the plane along the exposed surface 5a is the exposure of the heat sink 5. It is preferably 10% or more of the area of the surface 5a (corresponding to the area of the portion hatched with sparse oblique lines indicated by reference numeral 5 in FIG. 2). Since the projecting area of the convex portion 6a with respect to the plane along the exposed surface 5a is large, the effect that the heat sink 5 is supported by the sealing resin 8 is increased.
  • the material of the projections 6a is the same as the material of the heat sink 5 other than the projections 6a.
  • the shape of the convex portion 6a is not particularly limited.
  • the convex portion 6a may have a quadrangular prism shape with the side surface 50 of the heat sink 5 as the bottom surface, or may have a triangular pyramid shape with the side surface 50 of the heat sink 5 as the bottom surface.
  • the thickness T4 of the convex portion 6a is preferably 10% or more of the thickness T1 of the heat sink 5. As shown in FIG. The thicker the protrusion 6a, the higher the strength of the protrusion 6a. When the thickness of the convex portion 6a varies depending on the position in the in-plane direction, the thickest portion of the base of the convex portion 6a, that is, the portion overlapping the contour of the exposed surface 5a in plan view is the thickness T1 of the heat sink 5. of 10% or more.
  • a distance T3 in the thickness direction between the upper surface 8a of the sealing resin 8 and the upper surface of the projection 6a is preferably 10% or more of the thickness T2 of the sealing resin 8.
  • the distance between the upper surface 8a of the sealing resin 8 and the upper surface of the projection 6a is It is sufficient that the distance in the thickness direction is 10% or more of the thickness T2 of the sealing resin 8 at the location where the distance in the thickness direction is the largest.
  • the convex portion 6a is located inside the semiconductor device 100 from the side surface of the sealing resin 8. As shown in FIG. That is, the convex portion 6 a does not reach the side surface of the sealing resin 8 and is not exposed from the side surface of the sealing resin 8 .
  • FIG. 3 is a diagram showing a semiconductor device 101 that is a modification of the semiconductor device 100 of this embodiment.
  • FIG. 4 is a cross-sectional view of the semiconductor device 101 taken along line BB in FIG.
  • the semiconductor device 101 differs from the semiconductor device 100 in that the side surface 50 of the heat sink 5 is provided with a concave portion 6b instead of the convex portion 6a.
  • Semiconductor device 101 is similar to semiconductor device 100 in other respects.
  • the recessed portion 6b is a portion that is sandwiched between the radiator plates 5 from above and below and that is recessed in the direction opposite to the direction in which the side surface 50 faces from the outer periphery of the exposed surface 5a.
  • the sealing resin 8 seals the radiator plate 5 at the concave portion 6b. That is, at least the lower surface of the concave portion 6b is in contact with the sealing resin 8. As shown in FIG.
  • the thickness T5 of the recess 6b is preferably 10% or more of the thickness T2 of the sealing resin 8. As shown in FIG. The thicker the recess 6b, the higher the strength of the portion of the sealing resin 8 located within the recess 6b. When the thickness of the recessed portion 6b varies depending on the position in the in-plane direction, the thickest portion of the base of the recessed portion 6b, that is, the portion overlapping the contour of the exposed surface 5a in plan view, is equal to the thickness T2 of the sealing resin 8. 10% or more is sufficient.
  • the bottom surface of the concave portion 6b that is, the inner end portion in plan view, be outside the center of the radiator plate 5.
  • the shape of the recess 6b is not particularly limited.
  • the concave portion 6b may have a quadrangular prism shape with the side surface 50 of the heat sink 5 as the bottom surface, or a triangular pyramid shape with the side surface 50 of the heat sink 5 as the bottom surface.
  • FIG. 2 shows a case in which two projections 6a are provided on the side surface of the heat sink 5
  • FIG. 4 shows a case in which four recesses 6b are provided on the side surface of the heat sink 5.
  • any number of protrusions 6a or recesses 6b may be provided at any location to suit the required functionality.
  • the convex portion 6a or the concave portion 6b can be formed by scraping off the radiator plate 5 by a method such as cutting, grinding, polishing, etching, or laser processing.
  • the protrusions 6a or the recesses 6b can also be formed by adding a side structure to the heat sink 5 by a method such as plating or vapor deposition.
  • the heat sink 5 and the projections 6a, or the portion of the heat sink 5 around the recess 6b and the other portion of the heat sink 5 are firmly attached to each other so as not to separate. It is desirable to form the convex portion 6a or the concave portion 6b as shown in FIG.
  • the bonding material 7 is desirably a bonding material that satisfactorily bonds to the surfaces of both the semiconductor chip 2 and the heat sink 5 . It is desirable that the thermal conductivity of the bonding material 7 is high.
  • the bonding material 7 is, for example, silver sintered material, conductive adhesive, or solder.
  • the silver sintered material used as the bonding material 7 is, for example, silver particles of about several nanometers dispersed in a small amount of solvent.
  • the silver sintered material used as the bonding material 7 is desirably a material that is sintered at a temperature lower than the heat-resistant temperature of the semiconductor chip 2 .
  • the sintering temperature of the bonding material 7 is desirably 300° C. or less, more desirably 200° C. or less.
  • the conductive adhesive used as the bonding material 7 is, for example, a conductive adhesive obtained by mixing conductive particles such as silver, copper, gold, or nickel into resin such as epoxy resin, acrylic resin, or silicone resin. is.
  • the conductive particles may be resin particles coated with a metal such as silver, copper, gold, or nickel by plating or vapor deposition.
  • the conductive adhesive used as the bonding material 7 may be either one-liquid type or two-liquid mixed type conductive adhesive, and various types such as thermosetting, moisture curing, and ultraviolet curing. of any type of conductive adhesive.
  • the solder used as the bonding material 7 is, for example, a eutectic solder containing 38% by weight of lead in addition to tin, a lead-free solder containing 3% by weight of silver and 0.5% by weight of copper in addition to tin, Or a solder containing 80% gold by weight in addition to tin. In either case, solder that can be soldered at a temperature lower than the heat resistance temperature of the substrate 1 and the semiconductor chip 2 is used as the bonding material 7 .
  • the bonding material 7 has such a viscosity that it is easy to adjust the application amount and does not flow out from the applied area.
  • the viscosity of the bonding material 7 is, for example, 10 Pa ⁇ s to 100 Pa ⁇ s, preferably 20 Pa ⁇ s to 50 Pa ⁇ s.
  • the amount of the bonding material 7 applied is such that a fillet is formed on the side surface of the semiconductor chip 2 or the heat sink 5 that is in contact with the bonding material 7 and has a smaller area in a plan view.
  • the application method of the bonding material 7 includes an air dispenser, a constant volume screw dispenser, pin transfer, printing supply, and the like.
  • the sealing resin 8 is, for example, epoxy resin or silicone resin. Fine particles such as silica or boron nitride may be mixed into the sealing resin 8 in order to improve heat dissipation or adjust the coefficient of thermal expansion.
  • the sealing resin 8 seals the constituent elements from the upper surface 1a of the substrate 1 to the exposed surface 5a of the heat sink 5 except for the exposed surface 5a.
  • the outer dimensions of the sealing resin 8 in plan view are the same as the outer dimensions of the substrate 1, and the thickness T2 of the sealing resin 8 is the same as that of the bonding portion 4, the electrode 3, the semiconductor chip 2, and the bonding material 7. It is equal to the total thickness of the heat sink 5 .
  • the bonding material 7 is applied to the upper surface 2 a of the semiconductor chip 2 .
  • the heat sink 5 picked up by a vacuum suction nozzle is mounted on the upper surface 2a of the semiconductor chip 2 coated with the bonding material 7.
  • sealing is performed so that all five surfaces of the substrate 1 excluding the surface of the heat sink 5 that is bonded to the semiconductor chip 2 are covered with the sealing resin 8 .
  • the method of sealing it is desirable to use a transfer method that can fill even a very small gap because the gap between the substrate 1 and the semiconductor chip 2 is small.
  • the sealing resin 8 After the sealing resin 8 is cured, the sealing resin 8 and the substrate 1 are diced to divide into individual pieces.
  • the upper surface of the sealing resin 8 is ground to expose the heat sink 5 from the sealing resin 8 .
  • the semiconductor device 100 or the semiconductor device 101 is manufactured. If necessary, there is no problem even if the order of the above steps is changed.
  • the projecting area of the convex portion 6a or the concave portion 6b when projected onto a plane along the exposed surface 5a is 10% or more of the area of the exposed surface 5a. As shown in FIG. 1 or FIG. 3, the wavy bonding surfaces are engaged with each other and firmly fixed.
  • the projected area of the convex portion 6a or the concave portion 6b with respect to the plane along the exposed surface 5a is, for example, 10% or more of the area of the exposed surface 5a.
  • the thickness T4 of the convex portion 6a is, for example, 10% or more of the thickness T1 of the heat sink 5. As shown in FIG. Thereby, the convex portion 6a has high strength.
  • the distance T3 from the upper surface 8a of the sealing resin 8 to the upper surface of the projection 6a is, for example, 10% or more of the thickness T2 of the sealing resin 8.
  • the sealing resin 8 on the upper side of the convex portion 6a has high strength.
  • the thickness T5 of the recess 6b is 10% or more of the thickness T2 of the sealing resin 8, for example.
  • the sealing resin 8 inside the recess 6b has a high strength, so that the heat sink 5 is firmly fixed by the sealing resin 8. As shown in FIG.
  • the sealing resin 8 and the heat sink 5 are firmly fixed by providing the protrusions 6a or the recesses 6b. Even if a process such as cutting or polishing for exposing 5 is applied, peeling occurring at the joint surface between the semiconductor chip 2 and the heat sink 5 can be suppressed, thereby suppressing deterioration in heat dissipation.
  • FIG. 5 shows a semiconductor device 200 of this embodiment.
  • FIG. 6 is a cross-sectional view of the semiconductor device 200 taken along line CC of FIG.
  • the semiconductor device 200 differs from the semiconductor device 100 of the first embodiment in that the protrusions 9 are provided on the side surface 50 of the heat sink 5 instead of the protrusions 6a.
  • the protrusion 9 is bonded to the semiconductor chip 2 via the bonding material 7 . Thereby, the semiconductor chip 2 can be cooled more effectively.
  • the projections 9 firmly fix the heat sink 5 to the sealing resin 8 .
  • the convex portion 9 does not reach the side surface of the sealing resin 8 and is not exposed from the side surface of the sealing resin 8 .
  • the size of the protrusion 9 may be within a range in which there is no problem in designing the distance between the protrusion 9 and the side surface of the sealing resin 8 or the positional relationship between the protrusion 9 and the semiconductor chip 2 .
  • the thickness T4 of the convex portion 9 is preferably 10% or more of the thickness T1 of the heat sink 5. As shown in FIG.
  • the distance T3 between the upper surface 8a of the sealing resin 8 and the upper surface of the protrusion 9 is preferably 10% or more of the thickness T2 of the sealing resin 8. It is preferable that the projected area of the convex portion 9 with respect to a plane along the exposed surface 5a is 10% or more of the area of the exposed surface 5a.
  • the material of the projections 9 is desirably the same as the material of the radiator plate 5 .
  • the convex portion 9 can be formed in the same manner as the convex portion 6a in the semiconductor device 100 is formed. It is desirable to form the convex portion 9 so that the convex portion 9 and the heat sink plate 5 are strongly attached to each other so that they do not separate from each other.
  • the semiconductor device 200 can be manufactured by a method similar to the manufacturing method of the semiconductor device 100 of the first embodiment.
  • the semiconductor device 200 the semiconductor device 100 ⁇ A-3. function>. Therefore, the radiator plate 5 is firmly fixed to the sealing resin 8 .
  • the semiconductor device 200 can be subjected to a grinding process or the like for exposing the heat sink 5 buried in the sealing resin 8, as in the semiconductor device 100 of the first embodiment. is performed, it is possible to suppress detachment occurring at the joint surface between the semiconductor chip 2 and the heat sink 5, thereby suppressing deterioration in heat dissipation.
  • the convex portion 9 is in contact with the semiconductor chip 2 via the bonding material 7, the heat of the semiconductor chip 2 can be dissipated more effectively. Therefore, a semiconductor device with higher heat dissipation can be provided.
  • FIG. 7 is a cross-sectional view of a semiconductor device 300 according to the third embodiment.
  • FIG. 8 is a cross-sectional view of the semiconductor device 300 along line DD of FIG.
  • the semiconductor device 300 differs from the semiconductor device 100 of the first embodiment in that the protrusions 10 are provided on the side surfaces of the heat sink 5 instead of the protrusions 6a.
  • the outer circumference 10c (see FIG. 7) of the convex portion 10 is indicated by broken lines.
  • the outer circumference 10 c of the convex portion 10 does not reach the side surface of the sealing resin 8 and is not exposed from the side surface of the sealing resin 8 .
  • the convex portion 10 is provided on the side surface of the heat sink 5 over the entire area in the thickness direction.
  • the convex portion 10 has a tapered shape with the exposed surface 5a of the heat sink 5 as the tip and widening in the in-plane direction as the distance from the exposed surface 5a increases.
  • the angle ⁇ (see FIG. 7) formed between the surface of the tapered portion and the exposed surface 5a is greater than 0° and less than 90°. It is preferable that the angle ⁇ is not too large in order to obtain the effect that the heat sink 5 is more firmly fixed by the sealing resin 8 via the projections 10 .
  • the angle ⁇ is, for example, 45° or less.
  • the width L (see FIG. 7) in the thickness direction of the tapered portion of the projection 10 is preferably larger than 1/100 and smaller than 1/2 of the thickness T1 of the heat sink 5 . Moreover, the width L in the thickness direction of the tapered portion of the convex portion 10 is, for example, 10% or more of the thickness T2 of the sealing resin 8 . If the width L in the thickness direction of the tapered portion of the convex portion 10 is large, the strength of the sealing resin 8 supporting the tapered portion of the convex portion 10 increases. It is preferable that the projected area of the convex portion 10 with respect to a plane along the exposed surface 5a is 10% or more of the area of the exposed surface 5a.
  • the convex portion 10 is located on the side of the exposed surface 5a of the side surface of the heat sink 5 and extends along the entire outer circumference in a plan view.
  • the convex portion 10 may be provided only on the outer periphery with which the tool comes into contact.
  • Methods for forming the convex portion 10 include cutting, grinding, polishing, laser processing, etching, and the like.
  • the semiconductor device 300 can be manufactured by a method similar to the manufacturing method of the semiconductor device 100 of the first embodiment.
  • the provision of the protrusions 10 firmly fixes the heat sink 5 to the sealing resin 8 .
  • the provision of the projections 10 distributes the direction of stress generated when a tool contacts the edge of the heat sink 5 during a grinding process or the like. Therefore, it is possible to further suppress the peeling that occurs at the joint surface between the semiconductor chip 2 and the heat sink 5, and to further suppress the deterioration of the heat dissipation.
  • the semiconductor device 300 can be subjected to a grinding process or the like for exposing the heat sink 5 buried in the sealing resin 8, as in the semiconductor device 100 of the first embodiment. is performed, it is possible to suppress detachment occurring at the joint surface between the semiconductor chip 2 and the heat sink 5, thereby suppressing deterioration in heat dissipation.
  • the convex portion 10 Since the convex portion 10 has a tapered shape with the exposed surface 5a as the tip, the stress generated when a tool contacts the edge of the heat sink 5 in a grinding process or the like for exposing the heat sink 5 buried in the sealing resin 8. direction changes. That is, since the tool comes into contact with the tapered portion of the projection 10, the stress generated in the direction of separating the heat sink 5 and the semiconductor chip 2 is reduced. Therefore, delamination that occurs at the joint surface between the semiconductor chip 2 and the heat sink 5 is more effectively suppressed, and deterioration of the heat dissipation of the semiconductor device 300 is more effectively suppressed.
  • FIG. 9 shows a semiconductor device 400 according to the fourth embodiment.
  • a semiconductor device 400 differs from the semiconductor device 100 of the first embodiment in that a region 60 is provided on the surface of the projection 6a.
  • the convex portion 6 a is in contact with the sealing resin 8 in the region 60 .
  • the region 60 may include the entire region of the surface of the projection 6a that is in contact with the sealing resin 8, or one of the regions of the surface of the projection 6a that is in contact with the sealing resin 8. It may contain only parts.
  • a region 60 is a region in which fine unevenness is formed on the surface by surface processing. As a result, the sealing resin 8 gets into the minute irregularities on the region 60, and the protrusions 6a and the sealing resin 8 are strongly bonded. Since the region 60 is provided, the heat sink 5 is firmly fixed to the sealing resin 8 .
  • the roughness of the region 60 is expressed by the arithmetic mean roughness Ra.
  • the arithmetic mean roughness Ra of the region 60 is desirably 0.8 ⁇ m or more and 25 ⁇ m or less.
  • the arithmetic mean roughness Ra in the region 60 is larger than the arithmetic mean roughness Ra in the surface of the radiator plate 5 other than the region 60 .
  • the shape of the minute unevenness on the surface of the region 60 is not particularly limited. For example, it may be fluffed or hemispherical.
  • Etching, plasma processing, blast processing, and the like are available as methods for forming minute unevenness in the region 60 .
  • the semiconductor device 400 can be manufactured by a method similar to that of the semiconductor device 100 of the first embodiment.
  • the semiconductor device 400 is the semiconductor device 100 ⁇ A-3. function>.
  • the sealing resin 8 enters into minute irregularities on the region 60, and an anchor effect can be obtained. Therefore, peeling occurring at the joint surface between the semiconductor chip 2 and the heat sink 5 can be further suppressed.
  • the semiconductor device 400 can be subjected to a grinding process or the like for exposing the heat sink 5 buried in the sealing resin 8, as in the semiconductor device 100 of the first embodiment. is performed, it is possible to suppress peeling that occurs at the joint surface between the semiconductor chip 2 and the heat sink 5 .
  • the heat sink 5 and the sealing resin 8 are fixed more firmly. Therefore, peeling occurring at the joint surface between the semiconductor chip 2 and the heat sink 5 is further effectively suppressed.

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
PCT/JP2023/003640 2022-02-14 2023-02-03 半導体装置 Ceased WO2023153334A1 (ja)

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GB2408859.3A GB2629261A (en) 2022-02-14 2023-02-03 Semiconductor device
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014216326A (ja) * 2013-04-22 2014-11-17 株式会社デンソー 電子装置およびその製造方法
JP2017183521A (ja) * 2016-03-30 2017-10-05 新光電気工業株式会社 半導体装置及び半導体装置の製造方法
WO2019124024A1 (ja) * 2017-12-20 2019-06-27 三菱電機株式会社 半導体パッケージおよびその製造方法
US20210327780A1 (en) * 2020-04-21 2021-10-21 Samsung Electro-Mechanics Co., Ltd. Electronic device module having heat radiating portion and manufacturing method thereof

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08306849A (ja) * 1995-05-10 1996-11-22 Shinko Electric Ind Co Ltd 放熱部材及び該放熱部材を備えた半導体装置
JP4283588B2 (ja) * 2003-04-22 2009-06-24 パナソニック電工株式会社 半導体装置
US8564124B2 (en) * 2006-03-07 2013-10-22 International Rectifier Corporation Semiconductor package
JP2008042063A (ja) * 2006-08-09 2008-02-21 Renesas Technology Corp 半導体装置
US8125077B2 (en) * 2006-09-26 2012-02-28 Utac Thai Limited Package with heat transfer
JP2015070146A (ja) * 2013-09-30 2015-04-13 力成科技股▲分▼有限公司 半導体装置
US9142523B2 (en) * 2013-11-22 2015-09-22 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof
US9812410B2 (en) * 2015-12-31 2017-11-07 Taiwan Semiconductor Manufacturing Company, Ltd. Lid structure for a semiconductor device package and method for forming the same
KR20210017271A (ko) * 2019-08-07 2021-02-17 삼성전기주식회사 반도체 패키지

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014216326A (ja) * 2013-04-22 2014-11-17 株式会社デンソー 電子装置およびその製造方法
JP2017183521A (ja) * 2016-03-30 2017-10-05 新光電気工業株式会社 半導体装置及び半導体装置の製造方法
WO2019124024A1 (ja) * 2017-12-20 2019-06-27 三菱電機株式会社 半導体パッケージおよびその製造方法
US20210327780A1 (en) * 2020-04-21 2021-10-21 Samsung Electro-Mechanics Co., Ltd. Electronic device module having heat radiating portion and manufacturing method thereof

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