WO2023151107A1 - 显示面板 - Google Patents

显示面板 Download PDF

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Publication number
WO2023151107A1
WO2023151107A1 PCT/CN2022/076551 CN2022076551W WO2023151107A1 WO 2023151107 A1 WO2023151107 A1 WO 2023151107A1 CN 2022076551 W CN2022076551 W CN 2022076551W WO 2023151107 A1 WO2023151107 A1 WO 2023151107A1
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WO
WIPO (PCT)
Prior art keywords
pixel
sub
display panel
semiconductor
data line
Prior art date
Application number
PCT/CN2022/076551
Other languages
English (en)
French (fr)
Inventor
刘立旺
余文强
王超
Original Assignee
武汉华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 武汉华星光电技术有限公司 filed Critical 武汉华星光电技术有限公司
Priority to US17/760,773 priority Critical patent/US20240111197A1/en
Publication of WO2023151107A1 publication Critical patent/WO2023151107A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits

Definitions

  • the present application relates to the field of display technology, and in particular to a display panel.
  • Virtual reality (Virtual Reality, VR) and augmented reality (Augmented Reality, AR) technologies have been applied in military and aviation fields.
  • the development of display technology will definitely drive the progress of VR technology and AR technology.
  • the improvement of the resolution and field of view of display devices is the long-term development direction of display technology, and the pixel density (Pixel Per Inch, PPI) is an important factor in determining the resolution and field of view of a display device.
  • Liquid crystal display technology is widely used in VR equipment; a large number of scanning lines, data lines and thin film transistors are arranged in the array substrate of the liquid crystal display device, among which, the data lines are used to transmit data signals to the display device through the thin film transistors, scan The line is used to regulate the timing of the signal transmitted by the data line.
  • an electric field will be generated, and the electric field will affect the semiconductor in the thin-film transistor, resulting in poor performance stability of the thin-film transistor, which in turn leads to poor display effect of the liquid crystal display device.
  • the data line affects the stability of the performance of the thin film transistor.
  • the present application provides a display panel, which is used to alleviate the technical problem that the data lines in the current liquid crystal display device have adverse effects on the performance stability of the thin film transistor.
  • the present application provides a display panel, which includes: a first scan line and a second scan line extending along a first direction and insulated from each other adjacent to each other; a data line and a third data line, and a pixel unit located between the first scan line and the second scan line;
  • the pixel unit includes: a first sub-pixel and a third sub-pixel located between the first data line and the second data line, and a sub-pixel located between the second data line and the third data line the second sub-pixel; the first sub-pixel and the second sub-pixel are arranged along the first direction, the first sub-pixel and the third sub-pixel are arranged along the second direction, the The first sub-pixel includes a first pixel electrode, the second sub-pixel includes a second pixel electrode, and the third sub-pixel includes a third pixel electrode;
  • the display panel further includes a first transistor, the first transistor is electrically connected to one of the first pixel electrode, the second pixel electrode, and the third pixel electrode, and the first transistor includes The first semiconductor, where at least part of the first semiconductor overlaps with the first pixel electrode or the second pixel electrode.
  • the first transistor is electrically connected to the first pixel electrode, and at least part of the first semiconductor overlaps with the first pixel electrode.
  • the display panel further includes a second transistor, and the second transistor is electrically connected to the second pixel electrode or the third pixel electrode;
  • the second transistor includes a second semiconductor at least partially overlapping the second pixel electrode.
  • the display panel further includes a third transistor, the third transistor includes a third semiconductor, and the second transistor is located between the first transistor and the third transistor.
  • the second transistor is electrically connected to the second pixel electrode
  • the third transistor is electrically connected to the third pixel electrode
  • the first end of the first semiconductor is electrically connected to the first pixel electrode through a first connection hole
  • the first end of the second semiconductor is electrically connected to the first pixel electrode through a second connection hole
  • the second pixel electrode is electrically connected
  • the first end of the third semiconductor is electrically connected to the third pixel electrode through a third connection hole.
  • both the first connection hole and the second connection hole are located on the first side of the first scan line, and the third connection hole is located on the first side of the first scan line.
  • One side is opposite to the second side of the first scan line.
  • the second end of the first semiconductor is electrically connected to the first data line through the fourth connection hole, and the second end of the second semiconductor is electrically connected to the first data line through the fifth connection hole.
  • the second data line is electrically connected, and the second end of the third semiconductor is electrically connected to the third data line through the sixth connection hole.
  • both the fourth connection hole and the fifth connection hole are located on the second side of the first scan line, and the sixth connection hole is located on the first side of the first scan line. side.
  • the second semiconductor is electrically connected to the third pixel electrode
  • the third semiconductor is electrically connected to the second pixel electrode
  • the first end of the first semiconductor is electrically connected to the first pixel electrode through a first connection hole
  • the first end of the second semiconductor is electrically connected to the first pixel electrode through a third connection hole
  • the third pixel electrode is electrically connected
  • the first end of the third semiconductor is electrically connected to the second pixel electrode through the second connection hole.
  • both the first connection hole and the second connection hole are located on the first side of the first scan line, and the third connection hole is located on the first side of the first scan line.
  • One side is opposite to the second side of the first scan line.
  • the second end of the first semiconductor is electrically connected to the first data line through the fourth connection hole, and the second end of the second semiconductor is electrically connected to the first data line through the sixth connection hole.
  • the second data line is electrically connected, and the second end of the third semiconductor is electrically connected to the third data line through the fifth connection hole.
  • both the fourth connection hole and the fifth connection hole are located on the second side of the first scan line, and the sixth connection hole is located on the first side of the first scan line. side.
  • the display panel further includes a fourth data line located on a side of the third data line away from the second data line and extending along the second direction, the third At least part of the semiconductor is located between the third data line and the fourth data line.
  • the third connection hole is located between the second data line and the third data line, and is aligned with the third sub-pixel along the first direction, and is aligned with the third sub-pixel.
  • the second sub-pixels are arranged along the second direction.
  • the display panel further includes a first light-shielding layer, and the first light-shielding layer covers at least the third connection hole.
  • the display panel further includes a second light-shielding layer; the second light-shielding layer is located between the first sub-pixel and the third sub-pixel and extends along the first direction .
  • the first semiconductor includes InGaZnO.
  • the present application also provides a display panel, which includes: a first scan line and a second scan line extending along a first direction and insulated from each other adjacent to each other; a first data line extending along a second direction and adjacent to each other insulated; Two data lines and a third data line, and a pixel unit located between the first scan line and the second scan line;
  • the pixel unit includes: a first sub-pixel and a third sub-pixel located between the first data line and the second data line, and a sub-pixel located between the second data line and the third data line the second sub-pixel; the first sub-pixel and the second sub-pixel are arranged along the first direction, the first sub-pixel and the third sub-pixel are arranged along the second direction, the The first sub-pixel includes a first pixel electrode, the second sub-pixel includes a second pixel electrode, and the third sub-pixel includes a third pixel electrode;
  • the display panel further includes a second transistor, the second transistor includes a second semiconductor, at least part of the second semiconductor overlaps with the second pixel electrode, and the first terminal of the second semiconductor passes through the third
  • the connection hole is electrically connected to the third pixel electrode, and the second semiconductor includes indium gallium zinc oxide;
  • the third connection hole is located between the second data line and the third data line, and is aligned with the third sub-pixel along the first direction, and is aligned with the second sub-pixel along the Arranged in the second direction.
  • the present application provides a display panel, which includes a first sub-pixel and a third sub-pixel located between a first data line and a second data line, and a first sub-pixel located between the second data line and the third data line.
  • the display panel further includes a first transistor, The first transistor is electrically connected to one of the first pixel electrode, the second pixel electrode, and the third pixel electrode, the first transistor includes a first semiconductor, and the first semiconductor At least partially overlapped with the first pixel electrode or the second pixel electrode.
  • the first semiconductor by disposing the first semiconductor at a position at least partially overlapping with the first pixel electrode or the second pixel electrode, so that the disposition position of the first semiconductor and the disposition position of the data line are staggered from each other, the impact of the data line on the first semiconductor is reduced. Influenced by this, the working stability of the thin film transistor is improved, thereby improving the display quality of the display panel.
  • FIG. 1 is a schematic diagram of a first perspective structure of a first display panel provided by an embodiment of the present application.
  • FIG. 2 is a second perspective structural schematic diagram of the first display panel provided by the embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a first display panel including a plurality of pixel units provided by an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a first perspective structure of a second display panel provided by an embodiment of the present application.
  • FIG. 5 is a second perspective structural schematic diagram of a second display panel provided by an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a second display panel including a plurality of pixel units provided by an embodiment of the present application.
  • FIG. 7 is a schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present application.
  • An embodiment of the present application provides a display panel.
  • the display panel includes: a first scan line and a second scan line extending along a first direction and insulated from each other adjacent to each other; line, the second data line and the third data line, and the pixel unit located between the first scan line and the second scan line;
  • the pixel unit includes: located between the first data line and the second scan line The first sub-pixel and the third sub-pixel between the two data lines, and the second sub-pixel located between the second data line and the third data line; the first sub-pixel and the second The sub-pixels are arranged along the first direction, the first sub-pixel and the third sub-pixel are arranged along the second direction, the first sub-pixel includes a first pixel electrode, and the second sub-pixel includes The second pixel electrode, the third sub-pixel includes a third pixel electrode; the display panel further includes a first transistor, and the first transistor is connected to the first pixel electrode, the second pixel electrode and the first pixel electrode.
  • the first transistor includes a first semiconductor, and at least part of the first semiconductor overlaps with the first pixel electrode or the second pixel electrode.
  • the disposition position of the first semiconductor and the disposition position of the data line are staggered from each other, thereby reducing the impact of the data line on the first pixel electrode.
  • the impact of a semiconductor improves the stability of the thin film transistor, thereby improving the display quality of the display panel.
  • FIG. 1 is a first perspective structural schematic diagram of the first display panel provided by the embodiment of the present application
  • FIG. 2 is a first perspective structure diagram of the first display panel provided by the embodiment of the present application
  • 3 is a schematic structural diagram of a first type of display panel including a plurality of pixel units provided by an embodiment of the present application.
  • the first perspective schematic diagram shown in FIG. 1 shows the relative positional relationship of components such as thin film transistors, data lines, scan lines, and pixel electrodes of the display panel
  • the second perspective schematic diagram shown in FIG. 2 The relative positional relationship of the components such as the color resist unit and the light-shielding layer of the display panel is shown.
  • the display panel provided in this embodiment includes a plurality of pixel units, and the plurality of pixel units are distributed in an array in the display panel.
  • the pixel unit is the smallest repeating unit in the display panel, and the display function of the display panel is realized through the cooperative light emission of the plurality of pixel units; each of the pixel units may be the A partial area on the display panel, in which backlight units, data lines, scanning lines, thin film transistors, pixel electrodes, liquid crystals, color resistors, etc. required to realize the light emission of the pixel unit are arranged.
  • the display panel includes: a first scan line S1 and a second scan line S2 extending along the first direction X and insulated from each other adjacent to each other, and a first data line D1 extending along the second direction Y and insulated from each other adjacent to each other.
  • the first data line D1, the second data line D2 and the third data line D3 are arranged adjacent to each other in sequence, and are all used to provide data signals;
  • the first scanning line S1 and the second scanning line S2 are arranged adjacent to each other, And both are used to provide scanning signals.
  • the pixel unit includes: a first sub-pixel P1 and a third sub-pixel P3 located between the first data line D1 and the second data line D2, and a sub-pixel located between the second data line D2 and the second data line D2.
  • the second sub-pixel P2 between the three data lines D3.
  • the first sub-pixel P1 and the second sub-pixel P2 are arranged along the first direction X
  • the first sub-pixel P1 and the third sub-pixel P3 are arranged along the second direction Y
  • the The first sub-pixel P1 includes a first pixel electrode P11
  • the second sub-pixel P2 includes a second pixel electrode P21
  • the third sub-pixel P3 includes a third pixel electrode P31.
  • the first direction X and the second direction Y are two different and non-parallel directions.
  • the first direction X and the second direction Y are perpendicular to each other.
  • the number of sub-pixels arranged along the first direction X in the pixel unit is reduced, which is conducive to reducing the width of each pixel unit along the first direction X without changing the process conditions, and improving the pixel arrangement of the display panel density.
  • the display panel further includes a first transistor T1, a second transistor T2 and a third transistor T3, the first transistor T1 includes a first semiconductor T11, the second transistor T2 includes a second semiconductor T21, and the The third transistor T3 includes a third semiconductor T31.
  • the first transistor T1, the second transistor T2 and the third transistor T3 are arranged along the first direction X, and the second transistor T2 is located between the first transistor T1 and the third transistor T3 between.
  • the first transistor T1 is electrically connected to the first pixel electrode P11
  • the second transistor T2 is electrically connected to the second pixel electrode P21
  • the third transistor T3 is electrically connected to the third pixel electrode P31. electrical connection. At least a part of at least one of the first semiconductor T11 , the second semiconductor T21 and the third semiconductor T31 overlaps with the first pixel electrode P11 or the second pixel electrode P21 . It can be understood that each pixel electrode in the display panel is located in the area between the data lines.
  • At least part of the semiconductor is arranged in the area corresponding to the pixel electrode, so as to realize the staggered distribution of the semiconductor and the data line, effectively reducing the The impact of the data line on the performance of the semiconductor is reduced, the working stability of the thin film transistor is improved, and the display quality of the display panel is improved.
  • the distance between the film layer where the pixel electrode is located and the film layer where the semiconductor is located is much greater than the distance between the film layer where the data line is located and the film layer where the semiconductor is located. Being overlapped with the pixel electrode does not significantly increase the influence of the electric field generated by the pixel electrode on the semiconductor, but greatly weakens the influence of the electric field generated by the data line on the semiconductor.
  • the first semiconductor T11 overlaps the first pixel electrode P11, and at least a part of the second semiconductor T21 overlaps the second pixel electrode P21, thereby weakening the first data.
  • the influence of the line D1 on the first transistor T1 is weakened, and the influence of the second data line D2 on the second transistor T2 is weakened.
  • the display panel further includes a fourth data line D4 located on a side of the third data line D3 away from the second data line D2 and extending along the second direction Y, the third semiconductor At least part of T31 is located between the third data line D3 and the fourth data line D4.
  • This embodiment is beneficial to further weaken the influence of the third data line D3 on the third transistor T3 and improve the display quality of the display panel.
  • At least one of the first semiconductor T11 , the second semiconductor T21 and the third semiconductor T31 includes indium gallium zinc oxide (IGZO).
  • IGZO indium gallium zinc oxide
  • the first semiconductor T11 , the second semiconductor T21 and the third semiconductor T31 use indium gallium zinc oxide (IGZO)
  • the first transistor T1, the second transistor T2 and the third transistor T3 will exhibit smaller leakage currents , so as to further improve the display quality of the display panel.
  • the first semiconductor T11 , the second semiconductor T21 and the third semiconductor T31 may also include other transparent semiconductor materials, which will not be repeated here.
  • first end of the first semiconductor T11 is electrically connected to the first pixel electrode P11 through the first connection hole H1
  • the first end of the second semiconductor T21 is connected to the first pixel electrode P11 through the second connection hole H2.
  • the second pixel electrode P21 is electrically connected
  • the first end of the third semiconductor T31 is electrically connected to the third pixel electrode P31 through the third connection hole H3;
  • the holes H2 are all located on a first side of the first scan line S1
  • the third connection holes H3 are located on a second side of the first scan line S1 opposite to the first side of the first scan line S1 .
  • the second terminal of the first semiconductor T11 is electrically connected to the first data line D1 through the fourth connection hole H4, and the second terminal of the second semiconductor T21 is connected to the second data line D1 through the fifth connection hole H5.
  • the second end of the third semiconductor T31 is electrically connected to the third data line D3 through the sixth connection hole H6; the fourth connection hole H4 and the fifth connection hole H5 are both Located on the second side of the first scan line S1, the sixth connection hole H6 is located on the first side of the first scan line S1.
  • the third connection hole H3 is located between the second data line D2 and the third data line D3, and the third connection hole H3 and the third sub-pixel P3 are located along the first direction X, and the second sub-pixel P2 is arranged along the second direction Y.
  • the third connection hole H3 is arranged in the gap formed after the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are arranged in two rows according to the method described above. In the area, the space of one pixel unit in the display panel is fully utilized, which is conducive to improving the degree of freedom in the location of the third connection hole H3 and improving the process yield.
  • the display panel further includes a seventh connection hole H7, the first end of the first semiconductor T11 is first led out through the first connection hole H1, and further connected to the The first pixel electrode P11, wherein, the first connection hole H1 and the seventh connection hole H7 may partially overlap or not overlap.
  • the display panel further includes an eighth connection hole H8, the first end of the second semiconductor T21 is first led out through the second connection hole H2, and further connected to the second pixel through the eighth connection hole H8.
  • the electrode P21, wherein, the second connection hole H2 may partially overlap with the eighth connection hole H8 or may not overlap.
  • the display panel further includes a ninth connection hole H9, the first end of the third semiconductor T31 is first led out through the third connection hole H3, and further connected to the third pixel through the ninth connection hole H9.
  • the electrode P31, wherein, the third connection hole H3 and the ninth connection hole H9 may partially overlap or not overlap.
  • the ninth connection hole H9 is located between the second data line D2 and the third data line D3, and the ninth connection hole H9 and the third sub-pixel P3 are located along the first direction.
  • X is arranged, and is arranged with the second sub-pixel P2 along the second direction Y.
  • both the third connection hole H3 and the ninth connection hole H9 are arranged after the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are arranged in two rows.
  • the space of the pixel unit is fully utilized, which is conducive to improving the degree of freedom in the positions of the third connection hole H3 and the ninth connection hole H9 and improving the process yield.
  • the display panel further includes a first light-shielding layer B1, the first light-shielding layer B1 is located between the second data line D2 and the third data line D3, and is connected to the third sub-pixel P3 along the
  • the first light-shielding layer B1 is arranged in the first direction X, and the second sub-pixel P2 is arranged along the second direction Y; and the first light-shielding layer B1 covers at least the third connection hole H3; the first light-shielding layer B1
  • the ninth connection hole H9 may also be covered.
  • the first light-shielding layer B1 is used to shield the third connection hole H3, so as to prevent the metal wires in the region where the third connection hole H3 is located from reflecting light and affecting the display effect of the display panel.
  • the first sub-pixel P1 includes a first color-resisting unit C1, the second sub-pixel P2 includes a second color-resisting unit C2, and the third sub-pixel P3 includes a third color-resisting unit C3;
  • the first color resistance unit C1, the second color resistance unit C2 and the third color resistance unit C3 may be one of red resistance, green resistance and blue resistance respectively, and the first color resistance unit C1,
  • the second color-resist unit C2 and the third color-resist unit C3 are used to realize the color light emission of the display panel.
  • the display panel further includes a second light-shielding layer B2 disposed between the first sub-pixel P1 and the third sub-pixel P3, one side of the second light-shielding layer B2 is connected to the first color-resist unit C1 is connected, and the other side of the second light-shielding layer B2 is connected to the third color-resist unit C3.
  • the second light-shielding layer B2 is used to block part of the light emitted by the first sub-pixel P1 and part of the light emitted by the third sub-pixel P3, preventing the first sub-pixel P1 and the third sub-pixel P3 from There is a problem with color mixing.
  • the display panel further includes a third scan line S3 extending along the first direction X and adjacent to the second scan line S2.
  • the pixel unit located between the first scan line S1 and the second scan line S2 described above is the first pixel unit, and will be located between the second scan line S2 and the third scan line Pixel units between S3 are denoted as second pixel units.
  • the display panel further includes a third light-shielding layer B3 disposed between the first pixel unit and the second pixel unit.
  • the third light-shielding layer B3 is used to block part of the light emitted by the first pixel unit and part of the light emitted by the second pixel unit, so as to prevent color mixing between the first pixel unit and the second pixel unit.
  • both the second light-shielding layer B2 and the third light-shielding layer B3 have a strip structure extending along the first direction X
  • the display panel may include multiple strips of the second light-shielding layer B2 and the third light-shielding layer B3. Multiple strips of the third light-shielding layer B3.
  • FIG. 4 is a first perspective structure schematic diagram of the second display panel provided in the embodiment of the present application
  • Fig. 5 is a second display panel provided in the embodiment of the present application
  • FIG. 6 is a schematic structural diagram of a second display panel including a plurality of pixel units provided by an embodiment of the present application. It should be noted that the display panel described in this embodiment has the same or similar structure as the display panel described in the above embodiments, and the features described in the above embodiments are also applicable to this embodiment.
  • This embodiment provides a display panel, including a plurality of pixel units, and the plurality of pixel units are distributed in an array in the display panel.
  • the display panel includes: a first scan line S1 and a second scan line S2 extending along a first direction X and insulated from and adjacent to each other; a first data line D1 and a second data line extending along a second direction Y and insulated from each other.
  • the data line D2 and the third data line D3 and the pixel unit located between the first scan line S1 and the second scan line S2.
  • the first data line D1 , the second data line D2 and the third data line D3 are all used to provide data signals, and the first scan line S1 and the second scan line S2 are all used to provide scan signals.
  • the pixel unit includes: a first sub-pixel P1 and a third sub-pixel P3 located between the first data line D1 and the second data line D2, and a sub-pixel located between the second data line D2 and the second data line D2.
  • the second sub-pixel P2 between the three data lines D3.
  • the first sub-pixel P1 and the second sub-pixel P2 are arranged along the first direction X
  • the first sub-pixel P1 and the third sub-pixel P3 are arranged along the second direction Y
  • the The first sub-pixel P1 includes a first pixel electrode P11
  • the second sub-pixel P2 includes a second pixel electrode P21
  • the third sub-pixel P3 includes a third pixel electrode P31.
  • the first direction X and the second direction Y are two different and non-parallel directions.
  • the first direction X and the second direction Y are perpendicular to each other.
  • the display panel further includes a first transistor T1, a second transistor T2 and a third transistor T3, the first transistor T1 includes a first semiconductor T11, the second transistor T2 includes a second semiconductor T21, and the third transistor T3 includes a third semiconductor T31.
  • the first transistor T1, the second transistor T2 and the third transistor T3 are arranged along the first direction X, and the second transistor T2 is located between the first transistor T1 and the third transistor T3 between.
  • the first transistor T1 is electrically connected to the first pixel electrode P11
  • the second transistor T2 is electrically connected to the third pixel electrode P31
  • the third transistor T3 is electrically connected to the second pixel electrode P21. electrical connection.
  • At least a part of at least one of the first semiconductor T11 , the second semiconductor T21 and the third semiconductor T31 overlaps with the first pixel electrode P11 or the second pixel electrode P21 . It can be understood that each pixel electrode in the display panel is located in the area between the data lines.
  • At least part of the semiconductor is arranged in the area corresponding to the pixel electrode, so as to realize the staggered distribution of the semiconductor and the data line, effectively reducing the The impact of the data line on the performance of the semiconductor is reduced, the working stability of the thin film transistor is improved, and the display quality of the display panel is improved.
  • the first semiconductor T11 overlaps with the first pixel electrode P11, and at least part of the second semiconductor T21 overlaps with the second pixel electrode P21, thereby weakening the first data
  • the influence of the line D1 on the first transistor T1 is weakened, and the influence of the second data line D2 on the second transistor T2 is weakened.
  • the display panel further includes a fourth data line D4 located on a side of the third data line D3 away from the second data line D2 and extending along the second direction Y, the third semiconductor At least part of T31 is located between the third data line D3 and the fourth data line D4.
  • This embodiment is beneficial to further weaken the influence of the third data line D3 on the third transistor T3 and improve the display quality of the display panel.
  • At least one of the first semiconductor T11 , the second semiconductor T21 and the third semiconductor T31 includes indium gallium zinc oxide (IGZO).
  • IGZO indium gallium zinc oxide
  • the first semiconductor T11 , the second semiconductor T21 and the third semiconductor T31 use indium gallium zinc oxide (IGZO)
  • the first transistor T1, the second transistor T2 and the third transistor T3 will exhibit smaller leakage currents , so as to further improve the display quality of the display panel.
  • the first semiconductor T11 , the second semiconductor T21 and the third semiconductor T31 may also include other transparent semiconductor materials, which will not be repeated here.
  • the first end of the first semiconductor T11 is electrically connected to the first pixel electrode P11 through the first connection hole H1
  • the first end of the second semiconductor T21 is electrically connected to the first pixel electrode P11 through the third connection hole H3.
  • the third pixel electrode P31 is electrically connected, and the first end of the third semiconductor T31 is electrically connected to the second pixel electrode P21 through the second connection hole H2; the first connection hole H1 and the second connection
  • the holes H2 are all located on a first side of the first scan line S1
  • the third connection holes H3 are located on a second side of the first scan line S1 opposite to the first side of the first scan line S1 .
  • the second end of the first semiconductor T11 is electrically connected to the first data line D1 through the fourth connection hole H4, and the second end of the second semiconductor T21 is electrically connected to the second data line D1 through the sixth connection hole H6.
  • the second end of the third semiconductor T31 is electrically connected to the third data line D3 through the fifth connection hole H5; the fourth connection hole H4 and the fifth connection hole H5 are both Located on the second side of the first scan line S1, the sixth connection hole H6 is located on the first side of the first scan line S1.
  • the third connection hole H3 is located between the second data line D2 and the third data line D3, and the third connection hole H3 and the third sub-pixel P3 are located along the first direction X, and the second sub-pixel P2 is arranged along the second direction Y.
  • the third connection hole H3 is arranged in the gap formed after the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are arranged in two rows according to the method described above. In the area, the space of one pixel unit in the display panel is fully utilized, which is conducive to improving the degree of freedom in the location of the third connection hole H3 and improving the process yield.
  • the display panel further includes a seventh connection hole H7, the first end of the first semiconductor T11 is first led out through the first connection hole H1, and further connected to the The first pixel electrode P11, wherein, the first connection hole H1 and the seventh connection hole H7 may partially overlap or not overlap.
  • the display panel further includes a ninth connection hole H9, the first end of the second semiconductor T21 is first led out through the third connection hole H3, and further connected to the third pixel through the ninth connection hole H9.
  • the electrode P31, wherein, the third connection hole H3 and the ninth connection hole H9 may partially overlap or not overlap.
  • the ninth connection hole H9 is located between the second data line D2 and the third data line D3, and the ninth connection hole H9 and the third sub-pixel P3 are located along the first direction.
  • X is arranged, and is arranged with the second sub-pixel P2 along the second direction Y.
  • both the third connection hole H3 and the ninth connection hole H9 are arranged after the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are arranged in two rows.
  • the space of the pixel unit is fully utilized, which is conducive to improving the degree of freedom in the positions of the third connection hole H3 and the ninth connection hole H9 and improving the process yield.
  • the display panel further includes an eighth connection hole H8, the first end of the third semiconductor T31 is first led out through the second connection hole H2, and further connected to the second pixel through the eighth connection hole H8.
  • the electrode P21, wherein, the second connection hole H2 may partially overlap with the eighth connection hole H8 or may not overlap.
  • the display panel further includes a first light-shielding layer B1, the first light-shielding layer B1 is located between the second data line D2 and the third data line D3, and is connected to the third sub-pixel P3 along the
  • the first light-shielding layer B1 is arranged in the first direction X, and the second sub-pixel P2 is arranged along the second direction Y; and the first light-shielding layer B1 covers at least the third connection hole H3; the first light-shielding layer B1
  • the ninth connection hole H9 may also be covered.
  • the first light-shielding layer B1 is used to shield the third connection hole H3, so as to prevent the metal wires in the region where the third connection hole H3 is located from reflecting light and affecting the display effect of the display panel.
  • the first sub-pixel P1 includes a first color-resisting unit C1, the second sub-pixel P2 includes a second color-resisting unit C2, and the third sub-pixel P3 includes a third color-resisting unit C3;
  • the first color resistance unit C1, the second color resistance unit C2 and the third color resistance unit C3 may be one of red resistance, green resistance and blue resistance respectively, and the first color resistance unit C1,
  • the second color-resist unit C2 and the third color-resist unit C3 are used to realize the color light emission of the display panel.
  • the display panel further includes a second light-shielding layer B2 disposed between the first sub-pixel P1 and the third sub-pixel P3, one side of the second light-shielding layer B2 is connected to the first color-resist unit C1 is connected, and the other side of the second light-shielding layer B2 is connected to the third color-resist unit C3.
  • the second light-shielding layer B2 is used to block part of the light emitted by the first sub-pixel P1 and part of the light emitted by the third sub-pixel P3, preventing the first sub-pixel P1 and the third sub-pixel P3 from There is a problem with color mixing.
  • the display panel further includes a third scan line S3 extending along the first direction X and adjacent to the second scan line S2.
  • the pixel unit located between the first scan line S1 and the second scan line S2 described above is the first pixel unit, and will be located between the second scan line S2 and the third scan line Pixel units between S3 are denoted as second pixel units.
  • the display panel further includes a third light-shielding layer B3 disposed between the first pixel unit and the second pixel unit.
  • the third light-shielding layer B3 is used to block part of the light emitted by the first pixel unit and part of the light emitted by the second pixel unit, so as to prevent color mixing between the first pixel unit and the second pixel unit.
  • both the second light-shielding layer B2 and the third light-shielding layer B3 have a strip structure extending along the first direction X
  • the display panel may include multiple strips of the second light-shielding layer B2 and the third light-shielding layer B3. Multiple strips of the third light-shielding layer B3.
  • FIG. 7 is a schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present application.
  • the display panel includes a first base substrate 101, a shielding layer 102 disposed on the first base substrate 101, a buffer layer 103 covering the shielding layer 102, a semiconductor layer disposed on the buffer layer 103 104.
  • the gate insulating layer 105 covering the semiconductor layer 104, the gate 106 disposed on the gate insulating layer 105, the interlayer insulating layer 107 covering the gate 106, disposed on the interlayer insulating
  • the shielding layer 102 is used to prevent light from being emitted from the first base substrate 101 to the semiconductor layer 104 .
  • the second terminal of the first transistor T1 shown in FIG. 1 or FIG. 4 , the second terminal of the second transistor T2 and the second terminal of the third transistor T3 can all be equivalent to the semiconductor layer connected to the source 108 One end of 104; the first end of the first transistor T1, the first end of the second transistor T2 and the first end of the third transistor T3 shown in Fig. One end of the semiconductor layer 104 .
  • the pixel electrode 113 may be equivalent to the first pixel electrode P11 or the second pixel electrode P21 or the third pixel electrode P31 shown in FIG. 1 or FIG. 4 .
  • the color-resist layer 115 may be equivalent to the first color-resist unit C1 or the second color-resist unit C2 or the third color-resist unit C3 shown in FIG. 2 or FIG. 5 .
  • the semiconductor layer 104, the gate 106, the source 108 and the drain 109 form a thin film transistor, which is equivalent to the first transistor T1 or the second transistor T2 shown in FIG. 1 or FIG. 4 or the third transistor T3.
  • the liquid crystal layer 114 is provided with a liquid crystal, and the liquid crystal is deflected at various angles under the action of the cross electric field jointly provided by the common electrode 111 and the pixel electrode 113, so that the display panel presents a display of different gray scales. .
  • the display panel also includes a black matrix arranged on the same layer as or adjacent to the color resist layer 115, and the black matrix includes the first light-shielding layer B1 and the second light-shielding layer B1 shown in any one of FIGS. 1 to 6 . B2 and the third light-shielding layer B3.
  • the display panel further includes a backlight module, and the backlight module is disposed on a side of the first base substrate 101 away from the shielding layer 102 .
  • the backlight module is used to provide a backlight for the display panel.
  • An embodiment of the present application further provides a display device, and the display device includes the display panel provided in the embodiment of the present application.
  • the display device may be a notebook computer, a tablet computer, a mobile phone, a computer monitor, a television set, a navigator, and the like, which have the function of displaying images.
  • the display panel provided by the embodiment of the present application, at least one of the first semiconductor, the second semiconductor, and the third semiconductor is arranged at a position at least partially overlapping with the first pixel electrode or the second pixel electrode. , so that the arrangement position of the semiconductor and the arrangement position of the data line are staggered from each other, the influence of the data line on the performance of the semiconductor is reduced, the working stability of the thin film transistor is improved, and the display quality of the display panel is further improved; and the embodiment of the present application adopts Arranging the first sub-pixel and the second sub-pixel along the first direction, and arranging the first sub-pixel and the third sub-pixel along the second direction different from the first direction, reduces the pixel unit arranged along the first direction The number of sub-pixels is conducive to reducing the width of each pixel unit along the first direction without changing the process conditions, and increasing the pixel arrangement density of the display panel.

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Abstract

一种显示面板，显示面板包括第一子像素(P1)、第二子像素(P2)和第三子像素(P3)；显示面板还包括第一晶体管(T1)，第一晶体管(T1)与第一像素电极(P11)、第二像素电极(P21)和第三像素电极(P31)的其中之一电性连接，第一晶体管(T1)包括第一半导体(T11)，第一半导体(T11)的至少局部与第一像素电极(P11)或第二像素电极(P21)重叠设置。

Description

显示面板
本申请要求于2022年02月10日提交中国专利局、申请号为202210123744.7、发明名称为“显示面板”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板。
 背景技术
虚拟现实（Virtual Reality，VR）和增强现实（Augmented Reality，AR）技术已经应用于军事和航空领域。显示技术的发展必将带动VR技术和AR技术的进步，显示装置的分辨率和视角场的提升是显示技术的长期开发方向，而像素密度（Pixel Per Inch，PPI）是决定显示装置分辨率和视角场的重要因素。液晶显示技术在VR装备中的应用较为广泛；在液晶显示装置的阵列基板中设置有大量的扫描线、数据线和薄膜晶体管，其中，数据线用于通过薄膜晶体管向显示装置传递数据信号，扫描线用于调控数据线传递信号的时序。数据线在通电状态下会产生电场，该电场会对薄膜晶体管中的半导体产生影响，导致薄膜晶体管性能稳定性变差，进而导致液晶显示装置的显示效果变差。
 技术问题
目前液晶显示装置存在数据线影响薄膜晶体管性能稳定的技术问题。
 技术解决方案
本申请提供一种显示面板，用于缓解目前液晶显示装置存在的数据线对薄膜晶体管性能稳定性产生不良影响的技术问题。
本申请提供一种显示面板，其包括：沿第一方向延伸且彼此绝缘临近设置的第一扫描线和第二扫描线，沿第二方向延伸且彼此绝缘临近设置的第一数据线、第二数据线和第三数据线，以及位于所述第一扫描线和所述第二扫描线之间的像素单元；
所述像素单元包括：位于所述第一数据线和所述第二数据线之间的第一子像素和第三子像素，以及位于所述第二数据线和所述第三数据线之间的第二子像素；所述第一子像素与所述第二子像素沿所述第一方向排列，所述第一子像素与所述第三子像素沿所述第二方向排列，所述第一子像素包括第一像素电极，所述第二子像素包括第二像素电极，所述第三子像素包括第三像素电极；
所述显示面板还包括第一晶体管，所述第一晶体管与所述第一像素电极、所述第二像素电极和所述第三像素电极的其中之一电性连接，所述第一晶体管包括第一半导体，所述第一半导体的至少局部与所述第一像素电极或所述第二像素电极重叠设置。
在本申请的显示面板中，所述第一晶体管与所述第一像素电极电性连接，所述第一半导体的至少局部与所述第一像素电极重叠。
在本申请的显示面板中，所述显示面板还包括第二晶体管，所述第二晶体管与所述第二像素电极或所述第三像素电极电性连接；
所述第二晶体管包括第二半导体，所述第二半导体的至少局部与所述第二像素电极重叠。
在本申请的显示面板中，所述显示面板还包括第三晶体管，所述第三晶体管包括第三半导体，所述第二晶体管位于所述第一晶体管和所述第三晶体管之间。
在本申请的显示面板中，所述第二晶体管与所述第二像素电极电性连接，所述第三晶体管与所述第三像素电极电性连接。
在本申请的显示面板中，所述第一半导体的第一端通过第一连接孔与所述第一像素电极电性连接，所述第二半导体的第一端通过第二连接孔与所述第二像素电极电性连接，所述第三半导体的第一端通过第三连接孔与所述第三像素电极电性连接。
在本申请的显示面板中，所述第一连接孔和所述第二连接孔均位于所述第一扫描线的第一侧，所述第三连接孔位于与所述第一扫描线的第一侧相对的所述第一扫描线的第二侧。
在本申请的显示面板中，所述第一半导体的第二端通过第四连接孔与所述第一数据线电性连接，所述第二半导体的第二端通过第五连接孔与所述第二数据线电性连接，所述第三半导体的第二端通过第六连接孔与所述第三数据线电性连接。
在本申请的显示面板中，所述第四连接孔和所述第五连接孔均位于所述第一扫描线的第二侧，所述第六连接孔位于所述第一扫描线的第一侧。
在本申请的显示面板中，所述第二半导体与所述第三像素电极电性连接，所述第三半导体与所述第二像素电极电性连接。
在本申请的显示面板中，所述第一半导体的第一端通过第一连接孔与所述第一像素电极电性连接，所述第二半导体的第一端通过第三连接孔与所述第三像素电极电性连接，所述第三半导体的第一端通过第二连接孔与所述第二像素电极电性连接。
在本申请的显示面板中，所述第一连接孔和所述第二连接孔均位于所述第一扫描线的第一侧，所述第三连接孔位于与所述第一扫描线的第一侧相对的所述第一扫描线的第二侧。
在本申请的显示面板中，所述第一半导体的第二端通过第四连接孔与所述第一数据线电性连接，所述第二半导体的第二端通过第六连接孔与所述第二数据线电性连接，所述第三半导体的第二端通过第五连接孔与所述第三数据线电性连接。
在本申请的显示面板中，所述第四连接孔和所述第五连接孔均位于所述第一扫描线的第二侧，所述第六连接孔位于所述第一扫描线的第一侧。
在本申请的显示面板中，所述显示面板还包括位于所述第三数据线的远离所述第二数据线的一侧且沿所述第二方向延伸的第四数据线，所述第三半导体的至少局部位于所述第三数据线与所述第四数据线之间。
在本申请的显示面板中，所述第三连接孔位于所述第二数据线与所述第三数据线之间，且与所述第三子像素沿所述第一方向排列，且与所述第二子像素沿所述第二方向排列。
在本申请的显示面板中，所述显示面板还包括第一遮光层，所述第一遮光层至少覆盖所述第三连接孔。
在本申请的显示面板中，所述显示面板还包括第二遮光层；所述第二遮光层位于所述第一子像素与所述第三子像素之间，且沿所述第一方向延伸。
在本申请的显示面板中，所述第一半导体包括氧化铟镓锌。
本申请还提供一种显示面板，其包括：沿第一方向延伸且彼此绝缘临近设置的第一扫描线和第二扫描线，沿第二方向延伸且彼此绝缘临近设置的第一数据线、第二数据线和第三数据线，以及位于所述第一扫描线和所述第二扫描线之间的像素单元；
所述像素单元包括：位于所述第一数据线和所述第二数据线之间的第一子像素和第三子像素，以及位于所述第二数据线和所述第三数据线之间的第二子像素；所述第一子像素与所述第二子像素沿所述第一方向排列，所述第一子像素与所述第三子像素沿所述第二方向排列，所述第一子像素包括第一像素电极，所述第二子像素包括第二像素电极，所述第三子像素包括第三像素电极；
所述显示面板还包括第二晶体管，所述第二晶体管包括第二半导体，所述第二半导体的至少局部与所述第二像素电极重叠设置，所述第二半导体的第一端通过第三连接孔与所述第三像素电极电性连接，所述第二半导体包括氧化铟镓锌；
所述第三连接孔位于所述第二数据线与所述第三数据线之间，且与所述第三子像素沿所述第一方向排列，且与所述第二子像素沿所述第二方向排列。
 有益效果
本申请提供一种显示面板，该显示面板包括位于第一数据线和第二数据线之间的第一子像素和第三子像素、以及位于第二数据线和第三数据线之间的第二子像素；所述第一子像素包括第一像素电极，所述第二子像素包括第二像素电极，所述第三子像素包括第三像素电极；所述显示面板还包括第一晶体管，所述第一晶体管与所述第一像素电极、所述第二像素电极和所述第三像素电极的其中之一电性连接，所述第一晶体管包括第一半导体，所述第一半导体的至少局部与所述第一像素电极或所述第二像素电极重叠设置。本申请通过将第一半导体设置在与第一像素电极或第二像素电极至少局部重合的位置，使得第一半导体的设置位置与数据线的设置位置彼此错开，减小了数据线对第一半导体的影响，提升了薄膜晶体管的工作稳定性，进而提升了显示面板的显示品质。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的第一种显示面板的第一透视结构示意图。
图2是本申请实施例提供的第一种显示面板的第二透视结构示意图。
图3是本申请实施例提供的包含多个像素单元的第一种显示面板的结构示意图。
图4是本申请实施例提供的第二种显示面板的第一透视结构示意图。
图5是本申请实施例提供的第二种显示面板的第二透视结构示意图。
图6是本申请实施例提供的包含多个像素单元的第二种显示面板的结构示意图。
图7是本申请实施例提供的显示面板的截面结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。
本申请实施例提供一种显示面板，该显示面板包括：沿第一方向延伸且彼此绝缘临近设置的第一扫描线和第二扫描线，沿第二方向延伸且彼此绝缘临近设置的第一数据线、第二数据线和第三数据线，以及位于所述第一扫描线和所述第二扫描线之间的像素单元；所述像素单元包括：位于所述第一数据线和所述第二数据线之间的第一子像素和第三子像素，以及位于所述第二数据线和所述第三数据线之间的第二子像素；所述第一子像素与所述第二子像素沿所述第一方向排列，所述第一子像素与所述第三子像素沿所述第二方向排列，所述第一子像素包括第一像素电极，所述第二子像素包括第二像素电极，所述第三子像素包括第三像素电极；所述显示面板还包括第一晶体管，所述第一晶体管与所述第一像素电极、所述第二像素电极和所述第三像素电极的其中之一电性连接，所述第一晶体管包括第一半导体，所述第一半导体的至少局部与所述第一像素电极或所述第二像素电极重叠设置。本申请实施例通过将第一半导体设置在与第一像素电极或第二像素电极至少局部重合的位置，使得第一半导体的设置位置与数据线的设置位置彼此错开，减小了数据线对第一半导体的影响，提升了薄膜晶体管的工作稳定性，进而提升了显示面板的显示品质。
下面结合附图对本申请实施例提供的显示面板相关技术特征进行说明。
在一种实施例中，请参阅图1至图3，图1是本申请实施例提供的第一种显示面板的第一透视结构示意图，图2是本申请实施例提供的第一种显示面板的第二透视结构示意图，图3是本申请实施例提供的包含多个像素单元的第一种显示面板的结构示意图。需要说明的是，图1所示的第一透视结构示意图示出了显示面板的薄膜晶体管、数据线、扫描线、像素电极等组成元件的相对位置关系；图2所示的第二透视结构示意图示出了显示面板的色阻单元、遮光层等组成元件的相对位置关系。
本实施例提供的显示面板包括多个像素单元，所述多个像素单元在所述显示面板中阵列分布。可以理解，所述像素单元是所述显示面板中的最小重复单元，所述显示面板的显示功能是通过所述多个像素单元的协作发光来实现的；每个所述像素单元可以是所述显示面板上的局部区域，在该局部区域内设置有实现该像素单元发光所需的背光单元、数据线、扫描线、薄膜晶体管、像素电极、液晶、色阻等。
具体地，所述显示面板包括：沿第一方向X延伸且彼此绝缘临近设置的第一扫描线S1和第二扫描线S2，沿第二方向Y延伸且彼此绝缘临近设置的第一数据线D1、第二数据线D2和第三数据线D3，以及位于所述第一扫描线S1和所述第二扫描线S2之间的像素单元。其中，第一数据线D1、第二数据线D2和第三数据线D3依次临近排列，且均用于提供数据信号；所述第一扫描线S1和所述第二扫描线S2彼此临近排列，且均用于提供扫描信号。
所述像素单元包括：位于所述第一数据线D1和所述第二数据线D2之间的第一子像素P1和第三子像素P3，以及位于所述第二数据线D2和所述第三数据线D3之间的第二子像素P2。所述第一子像素P1与所述第二子像素P2沿所述第一方向X排列，所述第一子像素P1与所述第三子像素P3沿所述第二方向Y排列；且所述第一子像素P1包括第一像素电极P11，所述第二子像素P2包括第二像素电极P21，所述第三子像素P3包括第三像素电极P31。所述第一方向X和所述第二方向Y是两个不同且不平行的方向。可选地，所述第一方向X与所述第二方向Y相互垂直。
本实施例通过将第一子像素P1与第二子像素P2沿第一方向X排列，并将第一子像素P1与第三子像素P3沿不同于第一方向X的第二方向Y排列，缩减了所述像素单元中沿第一方向X排列的子像素的数量，有利于在不改变制程条件的前提下，缩小每个像素单元沿第一方向X的宽度，提高显示面板的像素排布密度。
进一步地，所述显示面板还包括第一晶体管T1、第二晶体管T2和第三晶体管T3，所述第一晶体管T1包括第一半导体T11，所述第二晶体管T2包括第二半导体T21，所述第三晶体管T3包括第三半导体T31。所述第一晶体管T1、所述第二晶体管T2和所述第三晶体管T3沿所述第一方向X排列，且所述第二晶体管T2位于所述第一晶体管T1和所述第三晶体管T3之间。
所述第一晶体管T1与所述第一像素电极P11电性连接，所述第二晶体管T2与所述第二像素电极P21电性连接，所述第三晶体管T3与所述第三像素电极P31电性连接。所述第一半导体T11、所述第二半导体T21和所述第三半导体T31的至少其中之一的至少局部与所述第一像素电极P11或所述第二像素电极P21重叠设置。可以理解，所述显示面板中的各个像素电极均位于数据线之间的区域，本实施例将半导体中的至少局部设置在于像素电极对应的区域，实现了半导体与数据线的错开分布，有效减小了数据线对半导体性能的影响，提升了薄膜晶体管的工作稳定性，有利于提升显示面板的显示品质。
此外，在显示面板的膜层结构中，像素电极所在膜层与半导体所在膜层之间的距离要远大于数据线所在膜层与半导体所在膜层之间的距离，因此，本实施例将半导体与像素电极重叠设置，并不会导致像素电极产生的电场对半导体的影响明显增加，却大大削弱了数据线产生的电场对半导体的影响。
具体地，所述第一半导体T11的至少局部与所述第一像素电极P11重叠设置，所述第二半导体T21的至少局部与所述第二像素电极P21重叠设置，从而削弱所述第一数据线D1对所述第一晶体管T1的影响，并削弱所述第二数据线D2对所述第二晶体管T2的影响。
进一步地，所述显示面板还包括位于所述第三数据线D3的远离所述第二数据线D2的一侧且沿所述第二方向Y延伸的第四数据线D4，所述第三半导体T31的至少局部位于所述第三数据线D3与所述第四数据线D4之间。本实施例有利于进一步削弱所述第三数据线D3对所述第三晶体管T3的影响，提升显示面板的显示品质。
可选地，所述第一半导体T11、所述第二半导体T21和所述第三半导体T31的至少其中之一包括氧化铟镓锌（IGZO）。可以理解，氧化铟镓锌是一种透明半导体材料，因此，当将其设置在与像素电极重叠的位置时，不会对显示面板的显示出光产生明显影响；并且所述第一半导体T11、所述第二半导体T21和所述第三半导体T31采用氧化铟镓锌（IGZO）时，所述第一晶体管T1、所述第二晶体管T2和所述第三晶体管T3会表现出更小的漏电流，从而进一步提升显示面板的显示品质。基于此，所述第一半导体T11、所述第二半导体T21和所述第三半导体T31还可以包含其它透明半导体材料，此处不再赘述。
进一步地，所述第一半导体T11的第一端通过第一连接孔H1与所述第一像素电极P11电性连接，所述第二半导体T21的第一端通过第二连接孔H2与所述第二像素电极P21电性连接，所述第三半导体T31的第一端通过第三连接孔H3与所述第三像素电极P31电性连接；所述第一连接孔H1和所述第二连接孔H2均位于所述第一扫描线S1的第一侧，所述第三连接孔H3位于与所述第一扫描线S1的第一侧相对的所述第一扫描线S1的第二侧。
所述第一半导体T11的第二端通过第四连接孔H4与所述第一数据线D1电性连接，所述第二半导体T21的第二端通过第五连接孔H5与所述第二数据线D2电性连接，所述第三半导体T31的第二端通过第六连接孔H6与所述第三数据线D3电性连接；所述第四连接孔H4和所述第五连接孔H5均位于所述第一扫描线S1的第二侧，所述第六连接孔H6位于所述第一扫描线S1的第一侧。
具体地，所述第三连接孔H3位于所述第二数据线D2与所述第三数据线D3之间，且所述第三连接孔H3与所述第三子像素P3沿所述第一方向X排列，且与所述第二子像素P2沿所述第二方向Y排列。本实施例将所述第三连接孔H3设置在所述第一子像素P1、所述第二子像素P2、所述第三子像素P3按上文记载的方法进行两行排列后形成的空白区域内，充分利用了显示面板中一个像素单元的空间，有利于提高第三连接孔H3设置位置的自由度，提升制程良率。
进一步地，所述显示面板还包括第七连接孔H7，所述第一半导体T11的第一端首先通过所述第一连接孔H1引出，并进一步通过所述第七连接孔H7连接至所述第一像素电极P11，其中，所述第一连接孔H1与所述第七连接孔H7可以部分重叠或无重叠。
所述显示面板还包括第八连接孔H8，所述第二半导体T21的第一端首先通过所述第二连接孔H2引出，并进一步通过所述第八连接孔H8连接至所述第二像素电极P21，其中，所述第二连接孔H2与所述第八连接孔H8可以部分重叠或无重叠。
所述显示面板还包括第九连接孔H9，所述第三半导体T31的第一端首先通过所述第三连接孔H3引出，并进一步通过所述第九连接孔H9连接至所述第三像素电极P31，其中，所述第三连接孔H3与所述第九连接孔H9可以部分重叠或无重叠。
并且，所述第九连接孔H9位于所述第二数据线D2与所述第三数据线D3之间，且所述第九连接孔H9与所述第三子像素P3沿所述第一方向X排列，且与所述第二子像素P2沿所述第二方向Y排列。本实施例将所述第三连接孔H3和所述第九连接孔H9均设置在所述第一子像素P1、所述第二子像素P2、所述第三子像素P3进行两行排列后形成的空白区域内，充分利用了像素单元的空间，有利于提高第三连接孔H3和第九连接孔H9设置位置的自由度，提升制程良率。
所述显示面板还包括第一遮光层B1，所述第一遮光层B1位于所述第二数据线D2与所述第三数据线D3之间，且与所述第三子像素P3沿所述第一方向X排列，且与所述第二子像素P2沿所述第二方向Y排列；并且，所述第一遮光层B1至少覆盖所述第三连接孔H3；所述第一遮光层B1还可以覆盖所述第九连接孔H9。本实施例利用第一遮光层B1对所述第三连接孔H3进行遮挡，防止第三连接孔H3所在区域内的金属走线反射光线而影响显示面板的显示效果。
进一步地，所述第一子像素P1包括第一色阻单元C1，所述第二子像素P2包括第二色阻单元C2，所述第三子像素P3包括第三色阻单元C3；所述第一色阻单元C1、所述第二色阻单元C2和所述第三色阻单元C3可以分别是红色阻、绿色阻和蓝色阻中的一种，所述第一色阻单元C1、所述第二色阻单元C2和所述第三色阻单元C3用于实现所述显示面板的彩色发光。
所述显示面板还包括设置在所述第一子像素P1和所述第三子像素P3之间的第二遮光层B2，所述第二遮光层B2的一侧与所述第一色阻单元C1交接，所述第二遮光层B2的另一侧与所述第三色阻单元C3交接。所述第二遮光层B2用于遮挡部分所述第一子像素P1发出的光线和部分所述第三子像素P3发出的光线，防止所述第一子像素P1和所述第三子像素P3出现混色问题。
进一步地，所述显示面板还包括沿所述第一方向X延伸且与所述第二扫描线S2相邻的第三扫描线S3。以上文记载的位于所述第一扫描线S1和所述第二扫描线S2之间的所述像素单元为第一像素单元，并将位于所述第二扫描线S2和所述第三扫描线S3之间的像素单元记为第二像素单元。所述显示面板还包括设置于所述第一像素单元与所述第二像素单元之间的第三遮光层B3。所述第三遮光层B3用于遮挡部分所述第一像素单元发出的光线和部分所述第二像素单元发出的光线，防止所述第一像素单元和所述第二像素单元出现混色问题。
可选地，所述第二遮光层B2和所述第三遮光层B3均具有沿所述第一方向X延伸的条状结构，所述显示面板可以包括多条所述第二遮光层B2和多条所述第三遮光层B3。
在另一种实施例中，请参阅图4至图6，图4是本申请实施例提供的第二种显示面板的第一透视结构示意图，图5是本申请实施例提供的第二种显示面板的第二透视结构示意图，图6是本申请实施例提供的包含多个像素单元的第二种显示面板的结构示意图。需要说明的是，本实施例记载的显示面板与上述实施例记载的显示面板具有相同或相似的结构，在上述实施例中记载的特征同样适用于本实施例。
本实施例提供一种显示面板，包括多个像素单元，所述多个像素单元在所述显示面板中阵列分布。所述显示面板包括：沿第一方向X延伸且彼此绝缘临近设置的第一扫描线S1和第二扫描线S2，沿第二方向Y延伸且彼此绝缘临近设置的第一数据线D1、第二数据线D2和第三数据线D3，以及位于所述第一扫描线S1和所述第二扫描线S2之间的像素单元。第一数据线D1、第二数据线D2和第三数据线D3均用于提供数据信号，所述第一扫描线S1和所述第二扫描线S2均用于提供扫描信号。
所述像素单元包括：位于所述第一数据线D1和所述第二数据线D2之间的第一子像素P1和第三子像素P3，以及位于所述第二数据线D2和所述第三数据线D3之间的第二子像素P2。所述第一子像素P1与所述第二子像素P2沿所述第一方向X排列，所述第一子像素P1与所述第三子像素P3沿所述第二方向Y排列；且所述第一子像素P1包括第一像素电极P11，所述第二子像素P2包括第二像素电极P21，所述第三子像素P3包括第三像素电极P31。所述第一方向X和所述第二方向Y是两个不同且不平行的方向。可选地，所述第一方向X与所述第二方向Y相互垂直。
所述显示面板还包括第一晶体管T1、第二晶体管T2和第三晶体管T3，所述第一晶体管T1包括第一半导体T11，所述第二晶体管T2包括第二半导体T21，所述第三晶体管T3包括第三半导体T31。所述第一晶体管T1、所述第二晶体管T2和所述第三晶体管T3沿所述第一方向X排列，且所述第二晶体管T2位于所述第一晶体管T1和所述第三晶体管T3之间。
所述第一晶体管T1与所述第一像素电极P11电性连接，所述第二晶体管T2与所述第三像素电极P31电性连接，所述第三晶体管T3与所述第二像素电极P21电性连接。所述第一半导体T11、所述第二半导体T21和所述第三半导体T31的至少其中之一的至少局部与所述第一像素电极P11或所述第二像素电极P21重叠设置。可以理解，所述显示面板中的各个像素电极均位于数据线之间的区域，本实施例将半导体中的至少局部设置在于像素电极对应的区域，实现了半导体与数据线的错开分布，有效减小了数据线对半导体性能的影响，提升了薄膜晶体管的工作稳定性，有利于提升显示面板的显示品质。
进一步地，所述第一半导体T11的至少局部与所述第一像素电极P11重叠设置，所述第二半导体T21的至少局部与所述第二像素电极P21重叠设置，从而削弱所述第一数据线D1对所述第一晶体管T1的影响，并削弱所述第二数据线D2对所述第二晶体管T2的影响。
进一步地，所述显示面板还包括位于所述第三数据线D3的远离所述第二数据线D2的一侧且沿所述第二方向Y延伸的第四数据线D4，所述第三半导体T31的至少局部位于所述第三数据线D3与所述第四数据线D4之间。本实施例有利于进一步削弱所述第三数据线D3对所述第三晶体管T3的影响，提升显示面板的显示品质。
可选地，所述第一半导体T11、所述第二半导体T21和所述第三半导体T31的至少其中之一包括氧化铟镓锌（IGZO）。可以理解，氧化铟镓锌是一种透明半导体材料，因此，当将其设置在与像素电极重叠的位置时，不会对显示面板的显示出光产生明显影响；并且所述第一半导体T11、所述第二半导体T21和所述第三半导体T31采用氧化铟镓锌（IGZO）时，所述第一晶体管T1、所述第二晶体管T2和所述第三晶体管T3会表现出更小的漏电流，从而进一步提升显示面板的显示品质。基于此，所述第一半导体T11、所述第二半导体T21和所述第三半导体T31还可以包含其它透明半导体材料，此处不再赘述。
进一步地，所述第一半导体T11的第一端通过第一连接孔H1与所述第一像素电极P11电性连接，所述第二半导体T21的第一端通过第三连接孔H3与所述第三像素电极P31电性连接，所述第三半导体T31的第一端通过第二连接孔H2与所述第二像素电极P21电性连接；所述第一连接孔H1和所述第二连接孔H2均位于所述第一扫描线S1的第一侧，所述第三连接孔H3位于与所述第一扫描线S1的第一侧相对的所述第一扫描线S1的第二侧。
所述第一半导体T11的第二端通过第四连接孔H4与所述第一数据线D1电性连接，所述第二半导体T21的第二端通过第六连接孔H6与所述第二数据线D2电性连接，所述第三半导体T31的第二端通过第五连接孔H5与所述第三数据线D3电性连接；所述第四连接孔H4和所述第五连接孔H5均位于所述第一扫描线S1的第二侧，所述第六连接孔H6位于所述第一扫描线S1的第一侧。
具体地，所述第三连接孔H3位于所述第二数据线D2与所述第三数据线D3之间，且所述第三连接孔H3与所述第三子像素P3沿所述第一方向X排列，且与所述第二子像素P2沿所述第二方向Y排列。本实施例将所述第三连接孔H3设置在所述第一子像素P1、所述第二子像素P2、所述第三子像素P3按上文记载的方法进行两行排列后形成的空白区域内，充分利用了显示面板中一个像素单元的空间，有利于提高第三连接孔H3设置位置的自由度，提升制程良率。
进一步地，所述显示面板还包括第七连接孔H7，所述第一半导体T11的第一端首先通过所述第一连接孔H1引出，并进一步通过所述第七连接孔H7连接至所述第一像素电极P11，其中，所述第一连接孔H1与所述第七连接孔H7可以部分重叠或无重叠。
所述显示面板还包括第九连接孔H9，所述第二半导体T21的第一端首先通过所述第三连接孔H3引出，并进一步通过所述第九连接孔H9连接至所述第三像素电极P31，其中，所述第三连接孔H3与所述第九连接孔H9可以部分重叠或无重叠。
并且，所述第九连接孔H9位于所述第二数据线D2与所述第三数据线D3之间，且所述第九连接孔H9与所述第三子像素P3沿所述第一方向X排列，且与所述第二子像素P2沿所述第二方向Y排列。本实施例将所述第三连接孔H3和所述第九连接孔H9均设置在所述第一子像素P1、所述第二子像素P2、所述第三子像素P3进行两行排列后形成的空白区域内，充分利用了像素单元的空间，有利于提高第三连接孔H3和第九连接孔H9设置位置的自由度，提升制程良率。
所述显示面板还包括第八连接孔H8，所述第三半导体T31的第一端首先通过所述第二连接孔H2引出，并进一步通过所述第八连接孔H8连接至所述第二像素电极P21，其中，所述第二连接孔H2与所述第八连接孔H8可以部分重叠或无重叠。
所述显示面板还包括第一遮光层B1，所述第一遮光层B1位于所述第二数据线D2与所述第三数据线D3之间，且与所述第三子像素P3沿所述第一方向X排列，且与所述第二子像素P2沿所述第二方向Y排列；并且，所述第一遮光层B1至少覆盖所述第三连接孔H3；所述第一遮光层B1还可以覆盖所述第九连接孔H9。本实施例利用第一遮光层B1对所述第三连接孔H3进行遮挡，防止第三连接孔H3所在区域内的金属走线反射光线而影响显示面板的显示效果。
进一步地，所述第一子像素P1包括第一色阻单元C1，所述第二子像素P2包括第二色阻单元C2，所述第三子像素P3包括第三色阻单元C3；所述第一色阻单元C1、所述第二色阻单元C2和所述第三色阻单元C3可以分别是红色阻、绿色阻和蓝色阻中的一种，所述第一色阻单元C1、所述第二色阻单元C2和所述第三色阻单元C3用于实现所述显示面板的彩色发光。
所述显示面板还包括设置在所述第一子像素P1和所述第三子像素P3之间的第二遮光层B2，所述第二遮光层B2的一侧与所述第一色阻单元C1交接，所述第二遮光层B2的另一侧与所述第三色阻单元C3交接。所述第二遮光层B2用于遮挡部分所述第一子像素P1发出的光线和部分所述第三子像素P3发出的光线，防止所述第一子像素P1和所述第三子像素P3出现混色问题。
进一步地，所述显示面板还包括沿所述第一方向X延伸且与所述第二扫描线S2相邻的第三扫描线S3。以上文记载的位于所述第一扫描线S1和所述第二扫描线S2之间的所述像素单元为第一像素单元，并将位于所述第二扫描线S2和所述第三扫描线S3之间的像素单元记为第二像素单元。所述显示面板还包括设置于所述第一像素单元与所述第二像素单元之间的第三遮光层B3。所述第三遮光层B3用于遮挡部分所述第一像素单元发出的光线和部分所述第二像素单元发出的光线，防止所述第一像素单元和所述第二像素单元出现混色问题。
可选地，所述第二遮光层B2和所述第三遮光层B3均具有沿所述第一方向X延伸的条状结构，所述显示面板可以包括多条所述第二遮光层B2和多条所述第三遮光层B3。
在一种实施例中，请参阅图7，图7是本申请实施例提供的显示面板的截面结构示意图。所述显示面板包括第一衬底基板101、设置于所述第一衬底基板101上的遮挡层102、覆盖所述遮挡层102的缓冲层103、设置于所述缓冲层103上的半导体层104、覆盖所述半导体层104的栅极绝缘层105、设置于所述栅极绝缘层105上的栅极106、覆盖所述栅极106的层间绝缘层107、设置于所述层间绝缘层107上的源极108和漏极109、覆盖所述源极108和漏极109的平坦层110、设置于所述平坦层110上的公共电极111、覆盖所述公共电极111的钝化层112、设置于所述钝化层112上的像素电极113、位于所述钝化层112上的液晶层114、位于所述液晶层114上的色阻层115、以及位于所述色阻层115上的第二衬底基板116。
所述遮挡层102用于防止光线从所述第一衬底基板101射向所述半导体层104。图1或图4所示的第一晶体管T1的第二端、第二晶体管T2的第二端和第三晶体管T3的第二端均可以相当于与所述源极108连接的所述半导体层104的一端；图1或图4所示的第一晶体管T1的第一端、第二晶体管T2的第一端和第三晶体管T3的第一端均可以相当于与所述漏极109连接的所述半导体层104的一端。所述像素电极113可以相当于图1或图4所示的第一像素电极P11或第二像素电极P21或第三像素电极P31。所述色阻层115可以相当于图2或图5所示的第一色阻单元C1或第二色阻单元C2或第三色阻单元C3。
所述半导体层104、所述栅极106、所述源极108和所述漏极109构成薄膜晶体管，所述薄膜晶体管相当于图1或图4所示的第一晶体管T1或第二晶体管T2或第三晶体管T3。
所述液晶层114内设置有液晶，所述液晶在所述公共电极111和所述像素电极113共同提供的交叉电场的作用下产生多种角度的偏转，从而使显示面板呈现不同灰阶的显示。
所述显示面板还包括与所述色阻层115同层或相邻层设置的黑色矩阵，所述黑色矩阵包括图1至图6中任一所示的第一遮光层B1、第二遮光层B2和第三遮光层B3。
进一步地，所述显示面板还包括背光模组，所述背光模组设置于所述第一衬底基板101的远离所述遮挡层102的一侧。所述背光模组用于为所述显示面板提供背光源。
本申请实施例还提供一种显示装置，所述显示装置包括本申请实施例提供的显示面板。所述显示装置可以是笔记本电脑、平板电脑、手机、电脑显示器、电视机、导航仪等具有显示画面功能的仪器。
综上所述，本申请实施例提供的显示面板，通过将第一半导体、第二半导体、第三半导体中的至少其中之一设置在与第一像素电极或第二像素电极至少局部重合的位置，使得半导体的设置位置与数据线的设置位置彼此错开，减小了数据线对半导体性能的影响，提升了薄膜晶体管的工作稳定性，进而提升了显示面板的显示品质；并且本申请实施例通过将第一子像素与第二子像素沿第一方向排列，并将第一子像素与第三子像素沿不同于第一方向的第二方向排列，缩减了像素单元中沿第一方向排列的子像素的数量，有利于在不改变制程条件的前提下，缩小每个像素单元沿第一方向的宽度，提高显示面板的像素排布密度。
需要说明的是，虽然本申请以具体实施例揭露如上，但上述实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种显示面板，其包括：沿第一方向延伸且彼此绝缘临近设置的第一扫描线和第二扫描线，沿第二方向延伸且彼此绝缘临近设置的第一数据线、第二数据线和第三数据线，以及位于所述第一扫描线和所述第二扫描线之间的像素单元；
    所述像素单元包括：位于所述第一数据线和所述第二数据线之间的第一子像素和第三子像素，以及位于所述第二数据线和所述第三数据线之间的第二子像素；所述第一子像素与所述第二子像素沿所述第一方向排列，所述第一子像素与所述第三子像素沿所述第二方向排列，所述第一子像素包括第一像素电极，所述第二子像素包括第二像素电极，所述第三子像素包括第三像素电极；
    所述显示面板还包括第一晶体管，所述第一晶体管与所述第一像素电极、所述第二像素电极和所述第三像素电极的其中之一电性连接，所述第一晶体管包括第一半导体，所述第一半导体的至少局部与所述第一像素电极或所述第二像素电极重叠设置。
  2. 根据权利要求1所述的显示面板，其中，所述第一晶体管与所述第一像素电极电性连接，所述第一半导体的至少局部与所述第一像素电极重叠。
  3. 根据权利要求2所述的显示面板，其中，所述显示面板还包括第二晶体管，所述第二晶体管与所述第二像素电极或所述第三像素电极电性连接；
    所述第二晶体管包括第二半导体，所述第二半导体的至少局部与所述第二像素电极重叠。
  4. 根据权利要求3所述的显示面板，其中，所述显示面板还包括第三晶体管，所述第三晶体管包括第三半导体，所述第二晶体管位于所述第一晶体管和所述第三晶体管之间。
  5. 根据权利要求4所述的显示面板，其中，所述第二晶体管与所述第二像素电极电性连接，所述第三晶体管与所述第三像素电极电性连接。
  6. 根据权利要求5所述的显示面板，其中，所述第一半导体的第一端通过第一连接孔与所述第一像素电极电性连接，所述第二半导体的第一端通过第二连接孔与所述第二像素电极电性连接，所述第三半导体的第一端通过第三连接孔与所述第三像素电极电性连接。
  7. 根据权利要求6所述的显示面板，其中，所述第一连接孔和所述第二连接孔均位于所述第一扫描线的第一侧，所述第三连接孔位于与所述第一扫描线的第一侧相对的所述第一扫描线的第二侧。
  8. 根据权利要求7所述的显示面板，其中，所述第一半导体的第二端通过第四连接孔与所述第一数据线电性连接，所述第二半导体的第二端通过第五连接孔与所述第二数据线电性连接，所述第三半导体的第二端通过第六连接孔与所述第三数据线电性连接。
  9. 根据权利要求8所述的显示面板，其中，所述第四连接孔和所述第五连接孔均位于所述第一扫描线的第二侧，所述第六连接孔位于所述第一扫描线的第一侧。
  10. 根据权利要求4所述的显示面板，其中，所述第二半导体与所述第三像素电极电性连接，所述第三半导体与所述第二像素电极电性连接。
  11. 根据权利要求10所述的显示面板，其中，所述第一半导体的第一端通过第一连接孔与所述第一像素电极电性连接，所述第二半导体的第一端通过第三连接孔与所述第三像素电极电性连接，所述第三半导体的第一端通过第二连接孔与所述第二像素电极电性连接。
  12. 根据权利要求11所述的显示面板，其中，所述第一连接孔和所述第二连接孔均位于所述第一扫描线的第一侧，所述第三连接孔位于与所述第一扫描线的第一侧相对的所述第一扫描线的第二侧。
  13. 根据权利要求12所述的显示面板，其中，所述第一半导体的第二端通过第四连接孔与所述第一数据线电性连接，所述第二半导体的第二端通过第六连接孔与所述第二数据线电性连接，所述第三半导体的第二端通过第五连接孔与所述第三数据线电性连接。
  14. 根据权利要求13所述的显示面板，其中，所述第四连接孔和所述第五连接孔均位于所述第一扫描线的第二侧，所述第六连接孔位于所述第一扫描线的第一侧。
  15. 根据权利要求4所述的显示面板，其中，所述显示面板还包括位于所述第三数据线的远离所述第二数据线的一侧且沿所述第二方向延伸的第四数据线，所述第三半导体的至少局部位于所述第三数据线与所述第四数据线之间。
  16. 根据权利要求4所述的显示面板，其中，所述第三连接孔位于所述第二数据线与所述第三数据线之间，且与所述第三子像素沿所述第一方向排列，且与所述第二子像素沿所述第二方向排列。
  17. 根据权利要求16所述的显示面板，其中，所述显示面板还包括第一遮光层，所述第一遮光层至少覆盖所述第三连接孔。
  18. 根据权利要求17所述的显示面板，其中，所述显示面板还包括第二遮光层；所述第二遮光层位于所述第一子像素与所述第三子像素之间，且沿所述第一方向延伸。
  19. 根据权利要求1所述的显示面板，其中，所述第一半导体包括氧化铟镓锌。
  20. 一种显示面板，其包括：沿第一方向延伸且彼此绝缘临近设置的第一扫描线和第二扫描线，沿第二方向延伸且彼此绝缘临近设置的第一数据线、第二数据线和第三数据线，以及位于所述第一扫描线和所述第二扫描线之间的像素单元；
    所述像素单元包括：位于所述第一数据线和所述第二数据线之间的第一子像素和第三子像素，以及位于所述第二数据线和所述第三数据线之间的第二子像素；所述第一子像素与所述第二子像素沿所述第一方向排列，所述第一子像素与所述第三子像素沿所述第二方向排列，所述第一子像素包括第一像素电极，所述第二子像素包括第二像素电极，所述第三子像素包括第三像素电极；
    所述显示面板还包括第二晶体管，所述第二晶体管包括第二半导体，所述第二半导体的至少局部与所述第二像素电极重叠设置，所述第二半导体的第一端通过第三连接孔与所述第三像素电极电性连接，所述第二半导体包括氧化铟镓锌；
    所述第三连接孔位于所述第二数据线与所述第三数据线之间，且与所述第三子像素沿所述第一方向排列，且与所述第二子像素沿所述第二方向排列。
PCT/CN2022/076551 2022-02-10 2022-02-17 显示面板 WO2023151107A1 (zh)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20080020335A (ko) * 2006-08-31 2008-03-05 삼성전자주식회사 박막 트랜지스터 어레이 기판
CN101540329A (zh) * 2008-03-19 2009-09-23 群康科技(深圳)有限公司 薄膜晶体管基板及其制造工艺
US20160216570A1 (en) * 2015-01-26 2016-07-28 Samsung Display Co., Ltd. Liquid crystal display device
CN112817187A (zh) * 2021-02-05 2021-05-18 武汉华星光电技术有限公司 显示面板及显示装置
CN113311624A (zh) * 2021-04-06 2021-08-27 Tcl华星光电技术有限公司 一种阵列基板及显示面板
CN214278585U (zh) * 2021-02-05 2021-09-24 武汉华星光电技术有限公司 显示面板及显示装置

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003066488A (ja) * 2001-08-30 2003-03-05 Hitachi Ltd 液晶表示装置
KR101085142B1 (ko) * 2004-12-24 2011-11-21 엘지디스플레이 주식회사 수평 전계 박막 트랜지스터 기판 및 그 제조 방법
JP4822406B2 (ja) * 2005-09-26 2011-11-24 ルネサスエレクトロニクス株式会社 表示制御駆動装置および表示システム
JP4591451B2 (ja) * 2007-01-10 2010-12-01 ソニー株式会社 半導体装置および表示装置
CN101127361B (zh) * 2007-09-25 2010-07-21 友达光电股份有限公司 像素结构与液晶显示面板
US8692756B2 (en) * 2009-09-08 2014-04-08 Sharp Kabushiki Kaisha Liquid crystal display device and method for manufacturing same
CN102157562B (zh) * 2011-01-18 2013-07-10 上海交通大学 底栅金属氧化物薄膜晶体管的制备方法
CN202404339U (zh) * 2012-01-12 2012-08-29 京东方科技集团股份有限公司 阵列基板及包括该阵列基板的显示装置
CN103149760B (zh) * 2013-02-19 2015-03-11 合肥京东方光电科技有限公司 薄膜晶体管阵列基板、制造方法及显示装置
CN103217840B (zh) * 2013-04-18 2015-09-16 合肥京东方光电科技有限公司 一种阵列基板、制备方法以及液晶显示装置
CN108227325B (zh) * 2018-01-25 2021-07-09 上海天马微电子有限公司 液晶显示面板与显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20080020335A (ko) * 2006-08-31 2008-03-05 삼성전자주식회사 박막 트랜지스터 어레이 기판
CN101540329A (zh) * 2008-03-19 2009-09-23 群康科技(深圳)有限公司 薄膜晶体管基板及其制造工艺
US20160216570A1 (en) * 2015-01-26 2016-07-28 Samsung Display Co., Ltd. Liquid crystal display device
CN112817187A (zh) * 2021-02-05 2021-05-18 武汉华星光电技术有限公司 显示面板及显示装置
CN214278585U (zh) * 2021-02-05 2021-09-24 武汉华星光电技术有限公司 显示面板及显示装置
CN113311624A (zh) * 2021-04-06 2021-08-27 Tcl华星光电技术有限公司 一种阵列基板及显示面板

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