WO2023145317A1 - 半導体モジュールおよび半導体ユニット - Google Patents

半導体モジュールおよび半導体ユニット Download PDF

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Publication number
WO2023145317A1
WO2023145317A1 PCT/JP2022/047073 JP2022047073W WO2023145317A1 WO 2023145317 A1 WO2023145317 A1 WO 2023145317A1 JP 2022047073 W JP2022047073 W JP 2022047073W WO 2023145317 A1 WO2023145317 A1 WO 2023145317A1
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Prior art keywords
chip
transistor
pad
sub
electrode
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Ceased
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PCT/JP2022/047073
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English (en)
French (fr)
Japanese (ja)
Inventor
勲 田古部
謙伍 大森
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Rohm Co Ltd
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Rohm Co Ltd
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Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to CN202280089939.2A priority Critical patent/CN118591886A/zh
Priority to JP2023576700A priority patent/JPWO2023145317A1/ja
Priority to DE112022006552.4T priority patent/DE112022006552T5/de
Publication of WO2023145317A1 publication Critical patent/WO2023145317A1/ja
Priority to US18/782,945 priority patent/US20240387513A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/051—Manufacture or treatment of FETs having PN junction gates
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/061—Manufacture or treatment of FETs having Schottky gates
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/80—FETs having rectifying junction gate electrodes
    • H10D30/83—FETs having PN junction gate electrodes
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    • H10D30/00—Field-effect transistors [FET]
    • H10D30/80—FETs having rectifying junction gate electrodes
    • H10D30/87—FETs having Schottky gate electrodes, e.g. metal-semiconductor FETs [MESFET]
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
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    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/101—Integrated devices comprising main components and built-in components, e.g. IGBT having built-in freewheel diode
    • H10D84/141—VDMOS having built-in components
    • H10D84/148—VDMOS having built-in components the built-in components being breakdown diodes, e.g. Zener diodes
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    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
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    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/911—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using passive elements as protective elements
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/611—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using diodes as protective elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/811—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using FETs as protective elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/886—Die-attach connectors and strap connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/761—Package configurations characterised by the relative positions of pads or connectors relative to package parts of strap connectors
    • H10W90/763—Package configurations characterised by the relative positions of pads or connectors relative to package parts of strap connectors between laterally-adjacent chips

Definitions

  • the present disclosure relates to semiconductor modules and semiconductor units.
  • a discrete semiconductor device in which a power transistor is formed as one type of main transistor (see Patent Document 1, for example).
  • a semiconductor module includes: a first chip including a main transistor including a main drift layer; a second chip including a part, a connecting member electrically connecting the main transistor and the active clamp circuit, and a sealing resin sealing the first chip, the second chip, and the connecting member , wherein the sub-transistor includes a sub-drift layer made of a material different from that of the main drift layer.
  • a semiconductor unit which is one aspect of the present disclosure, is provided separately from the semiconductor module and the first chip and the second chip in the sealing resin, and includes a driver circuit for driving the main transistor. 3 chips; and a control connection member that electrically connects the third chip, the first chip, and the second chip.
  • FIG. 1 is a plan view showing the schematic internal configuration of the semiconductor module of the first embodiment.
  • FIG. 2 is a cross-sectional view of the semiconductor module taken along line F2-F2 in FIG.
  • FIG. 3 is a cross-sectional view of the semiconductor module cut along line F3-F3 in FIG. 4 is a back view of the semiconductor module of FIG. 1.
  • FIG. 5 is a cross-sectional view showing a schematic cross-sectional structure of a main transistor in a semiconductor module.
  • FIG. 6 is a cross-sectional view showing a schematic cross-sectional structure of a clamp transistor of an active clamp circuit in a semiconductor module.
  • FIG. 7 is a cross-sectional view showing a schematic cross-sectional structure of a clamp capacitor of an active clamp circuit in a semiconductor module.
  • FIG. 8 is a cross-sectional view showing a schematic cross-sectional structure of a pull-down resistor of an active clamp circuit in a semiconductor module.
  • FIG. 9 is a circuit diagram of a semiconductor module.
  • FIG. 10 is a graph showing transitions of the drain-source voltage of the main transistor, the gate-source voltage, and the gate-source voltage of the clamping transistor.
  • FIG. 11 is a plan view showing the schematic internal configuration of the semiconductor module of the second embodiment.
  • 12 is a plan view of the semiconductor module of FIG. 11.
  • FIG. 13 is a cross-sectional view of the semiconductor module taken along line F13-F13 in FIG. 11.
  • FIG. FIG. 14 is a plan view showing the schematic internal configuration of the second chip in the semiconductor module.
  • FIG. 15 is a cross-sectional view showing a schematic cross-sectional structure of the second chip cut along line F15-F15 of FIG. 14.
  • FIG. FIG. 16 is a plan view showing the schematic internal configuration of the semiconductor module of the third embodiment.
  • 17 is a cross-sectional view of the semiconductor module taken along line F17-F17 in FIG. 16.
  • FIG. 18 is a cross-sectional view of the semiconductor module taken along line F18-F18 in FIG. 16.
  • FIG. FIG. 19 is a plan view showing the schematic internal configuration of the semiconductor unit of the fourth embodiment.
  • FIG. 20 is a plan view mainly showing the connection configuration of the semiconductor units of FIG. 19.
  • FIG. FIG. 21 is a plan view of the semiconductor unit.
  • FIG. 22 is a cross-sectional view of the semiconductor unit taken along line F22-F22 in FIG. 21.
  • FIG. 23 is a cross-sectional view of the semiconductor unit taken along line F23-F23 in FIG. 21.
  • FIG. FIG. 24 is a circuit diagram of a semiconductor unit.
  • FIG. 25 is a cross-sectional view showing a schematic cross-sectional structure of a pull-down resistor in a semiconductor module of a modification.
  • FIG. 26 is a cross-sectional view showing a schematic cross-sectional structure of a pull-down resistor in a semiconductor module of a modification.
  • FIG. 27 is a circuit diagram of a semiconductor module of a modification.
  • FIG. 28 is a cross-sectional view showing a schematic cross-sectional structure of a protection diode in the semiconductor module of FIG. 27.
  • FIG. FIG. 29 is a circuit diagram of a semiconductor module of a modification.
  • FIG. 30 is a circuit diagram of a semiconductor module of a modification.
  • FIG. 31 is a circuit diagram of a semiconductor unit of a modification.
  • FIG. 1 shows a schematic internal configuration of a semiconductor module.
  • the components inside the semiconductor module are indicated by solid lines for convenience of explanation.
  • the semiconductor module 10 electrically connects a first chip 20 including a main transistor 21, a second chip 30 including an active clamp circuit 40, and the main transistor 21 and the active clamp circuit 40.
  • a connection member 50 and a sealing resin 60 that seals the first chip 20 , the second chip 30 , and the connection member 50 are provided.
  • the sealing resin 60 is made of an insulating resin material. As such a resin material, for example, epoxy resin, acrylic resin, phenol resin, or the like can be used.
  • the sealing resin 60 forms the outer surface of the semiconductor module 10 .
  • the sealing resin 60 has a rectangular flat plate shape.
  • the sealing resin 60 has a resin surface 61, a resin back surface 62 facing the opposite side of the resin surface 61 (see FIG. 2 for both), and first to fourth resin side surfaces intersecting both the resin surface 61 and the resin back surface 62. 63-66.
  • the first to fourth resin side surfaces 63 to 66 are orthogonal to both the resin front surface 61 and the resin back surface 62 .
  • the arrangement direction of the resin front surface 61 and the resin back surface 62 is defined as “z direction”. It can also be said that the z direction is the thickness direction of the sealing resin 60 . Also, viewing the semiconductor module 10 from the z-direction is referred to as “plan view”. In the following description, “planar view” includes the meaning of "viewing from the thickness direction of the sealing resin 60". Also, the two directions orthogonal to each other in the direction orthogonal to the z-direction are defined as “x-direction” and "y-direction”.
  • the shape of the sealing resin 60 in plan view is a rectangular shape having a longitudinal direction and a lateral direction.
  • the sealing resin 60 is arranged such that its longitudinal direction is along the y direction and its short side direction is along the x direction.
  • the first resin side surface 63 and the second resin side surface 64 constitute both end surfaces of the sealing resin 60 in the y direction
  • the third resin side surface 65 and the fourth resin side surface 66 constitute both end surfaces of the sealing resin 60 in the x direction. are doing.
  • the semiconductor module 10 further includes a first die pad 71 on which the first chip 20 is mounted and a second die pad 72 on which the second chip 30 is mounted.
  • Each die pad 71, 72 is made of a metal material such as copper (Cu) or aluminum (Al).
  • Each of the die pads 71 and 72 has a rectangular shape in plan view.
  • the first die pad 71 and the second die pad 72 are aligned in the lateral direction (x direction) of the sealing resin 60 and are spaced apart in the longitudinal direction (y direction) of the sealing resin 60 . In this embodiment, as shown in FIG. 2, the die pads 71 and 72 are arranged at positions aligned with each other in the z direction.
  • the die pads 71 and 72 are not exposed from the resin back surface 62 because the die pads 71 and 72 are arranged on the resin surface 61 side and separated in the z-direction with respect to the resin back surface 62 .
  • the semiconductor module 10 may be configured such that at least one of the first die pad 71 and the second die pad 72 is exposed from the resin back surface 62 .
  • the first chip 20 includes a chip front surface 20s and a chip rear surface 20r facing opposite sides in the z direction.
  • the chip front surface 20 s faces the same side as the resin front surface 61
  • the chip rear surface 20 r faces the same side as the resin rear surface 62 .
  • the chip rear surface 20 r faces the first die pad 71 .
  • the first chip 20 is bonded to the first die pad 71 with a first bonding material AD1. More specifically, the first bonding material AD1 bonds the chip rear surface 20r and the first die pad 71 together.
  • a conductive bonding material such as solder paste or silver (Ag) paste is used as the first bonding material AD1.
  • a drain pad PD1, a source pad PS1, and a gate pad PG1 are formed on the chip surface 20s.
  • the drain pad PD1, the source pad PS1 and the gate pad PG1 are arranged apart from each other.
  • the x direction which is the arrangement direction of the drain pads PD1 and the source pads PS1
  • the arrangement direction of the first chip 20 and the second chip 30 is orthogonal to the arrangement direction (first direction) of the drain pads PD1 and the source pads PS1.
  • the y direction which is the direction in which the first chips 20 and the second chips 30 are arranged, corresponds to the "second direction".
  • the drain pad PD1 is a pad electrically connected to the drain electrode 21D of the main transistor 21 (see FIG. 5).
  • the drain pad PD1 is positioned closer to the fourth resin side surface 66 than both the source pad PS1 and the gate pad PG1.
  • the source pad PS1 is a pad electrically connected to the source electrode 21S of the main transistor 21 (see FIG. 5).
  • the source pad PS1 is positioned closer to the third resin side surface 65 than both the drain pad PD1 and the gate pad PG1.
  • the gate pad PG1 is a pad electrically connected to the gate electrode 21G of the main transistor 21 (see FIG. 5).
  • the gate pad PG1 is located between the drain pad PD1 and the source pad PS1 in the x direction. Note that the layout of the drain pad PD1, the source pad PS1, and the gate pad PG1 can be arbitrarily changed.
  • the second chip 30 includes a chip front surface 30s and a chip rear surface 30r facing opposite sides in the z direction.
  • the chip front surface 30 s faces the same side as the resin front surface 61
  • the chip rear surface 30 r faces the same side as the resin rear surface 62 .
  • the chip rear surface 30 r faces the second die pad 72 .
  • the second chip 30 is bonded to the second die pad 72 with a second bonding material AD2. More specifically, the second bonding material AD2 bonds the chip rear surface 30r and the second die pad 72 together.
  • a conductive bonding material is used for the second bonding material AD2, like the first bonding material AD1.
  • a source pad PS2, a pad PG2, and a capacitor pad PCA are formed on the chip surface 30s.
  • source pad PS2, pad PG2 and capacitor pad PCA are arranged apart from each other.
  • the pads PS2, PG2 and PCA are arranged apart from each other in plan view.
  • the pads PS2, PG2 and PCA are spaced apart from each other in a direction perpendicular to the arrangement direction (y direction) of the first chip 20 and the second chip 30.
  • the source pad PS2 is a pad connected to the source electrode 41S of the clamping transistor 41 of the active clamping circuit 40 (both see FIG. 6).
  • the source pad PS2 is positioned closer to the third resin side surface 65 than both the pad PG2 and the capacitor pad PCA.
  • the pad PG2 is a pad connected to the gate electrode 41G (see FIG. 6) of the clamping transistor 41 via the pull-down resistor 43.
  • Capacitor pad PCA is a pad connected to clamp capacitor 42 (see FIG. 6) of active clamp circuit 40 . When viewed in the y direction, the pad PG2 and the capacitor pad PCA are formed at positions overlapping each other. The pad PG2 is located closer to the first resin side surface 63 than the capacitor pad PCA.
  • the semiconductor module 10 further includes a drain terminal 81, a source terminal 82, and a gate terminal 83 that constitute external terminals.
  • Each terminal 81 to 83 is exposed from the resin rear surface 62 .
  • Each of the terminals 81-83 is formed of, for example, a plated layer of a conductive material.
  • the conductive material for example, Cu, Al, CuAl alloy or the like can be used.
  • both the drain terminal 81 and the source terminal 82 are arranged closer to the resin back surface 62 with respect to the first die pad 71 and the second die pad 72 in the z direction. Therefore, neither the first die pad 71 nor the second die pad 72 are exposed from the resin back surface 62 .
  • Both the drain terminal 81 and the source terminal 82 are arranged so as to partially overlap the first die pad 71 when viewed in the z-direction.
  • both the drain terminal 81 and the source terminal 82 are arranged so as to partially overlap the second die pad 72 .
  • the gate terminal 83 is integrated with the second die pad 72 .
  • a mounting portion of the second die pad 72 on which the second chip 30 is mounted is arranged closer to the resin surface 61 (see FIG. 2) than the gate terminals 83 are.
  • the connecting portion that connects the mounting portion and the gate terminal 83 is inclined toward the resin back surface 62 (see FIG. 2) from the mounting portion toward the gate terminal 83 . Note that the connecting portion does not have to be inclined.
  • the gate terminal 83 and the second die pad 72 may be provided separately and electrically connected to each other by a connection member such as a wire.
  • connection member 50 includes a first connection member 51, a second connection member 52, and a third connection member 53.
  • each connecting member 51 to 53 is made of, for example, a metal plate.
  • the metal plate for example, Cu, Al, CuAl alloy, or the like can be used.
  • the connection members 51 to 53 are not limited to metal plates, and may be formed by metal plating, for example. In other words, each of the connection members 51 to 53 may be made of a plated layer.
  • the first connection member 51 is configured to electrically connect the source terminal 82, the source pad PS1 of the first chip 20, and the source pad PS2 and pad PG2 of the second chip 30.
  • the source terminal 82, the source electrode 21S of the main transistor 21, the source electrode 41S of the clamping transistor 41 and the pull-down resistor 43 are electrically connected.
  • the second connection member 52 is configured to electrically connect the drain terminal 81, the drain pad PD1 of the first chip 20, and the capacitor pad PCA of the second chip 30. Thereby, the drain terminal 81, the drain electrode 21D of the main transistor 21, and the clamping capacitor 42 are electrically connected.
  • the third connection member 53 is configured to electrically connect the gate pad PG ⁇ b>1 of the first chip 20 and the second die pad 72 . Thereby, the gate electrode 21G of the main transistor 21 and the gate terminal 83 are electrically connected.
  • the shape of the first connection member 51 in plan view is not limited to the shape of the first connection member 51 shown in FIG. 1, and can be arbitrarily changed. Similarly, the shapes of the second connecting member 52 and the third connecting member 53 can be changed arbitrarily.
  • FIG. 5 is a cross-sectional view showing an example of a schematic cross-sectional structure of the first chip 20. As shown in FIG. It should be noted that some hatching lines are omitted from the viewpoint of visibility of the drawing.
  • the first chip 20 has a semiconductor substrate 22 .
  • the semiconductor substrate 22 is formed in a rectangular plate shape.
  • Semiconductor substrate 22 may be formed of silicon (Si), silicon carbide (SiC), gallium nitride (GaN), sapphire, or other substrate material.
  • semiconductor substrate 22 may be a Si substrate.
  • the thickness of semiconductor substrate 22 is, for example, 200 ⁇ m or more and 1500 ⁇ m or less.
  • a main transistor 21 is formed on a semiconductor substrate 22 .
  • the main transistor 21 includes a buffer layer 23 formed on a semiconductor substrate 22, an electron transit layer 24 forming a main drift layer formed on the buffer layer 23, and an electron supply layer formed on the electron transit layer 24. 25 and
  • Each of the buffer layer 23, the electron transit layer 24, and the electron supply layer 25 has a thickness in the z direction. Therefore, "planar view” includes the meaning of "viewing from the thickness direction of the main drift layer (electron transit layer)".
  • the buffer layer 23 is located between the semiconductor substrate 22 and the electron transit layer 24 and is made of any material that can alleviate the lattice mismatch between the semiconductor substrate 22 and the electron transit layer 24 .
  • Buffer layer 23 includes one or more nitride semiconductor layers.
  • Buffer layer 23 may include, for example, at least one of an aluminum nitride (AlN) layer, an aluminum gallium nitride (AlGaN) layer, and graded AlGaN layers having different aluminum compositions.
  • the buffer layer 23 may be formed by a single AlN layer, a single AlGaN layer, a layer having an AlGaN/GaN superlattice structure, a layer having an AlN/AlGaN superlattice structure, or a layer having an AlN/GaN superlattice structure. may be configured.
  • buffer layer 23 includes a first buffer layer that is an AlN layer formed on semiconductor substrate 22 and a second buffer layer that is an AlGaN layer formed on the AlN layer.
  • the first buffer layer is, for example, an AlN layer having a thickness of 200 nm
  • the second buffer layer has, for example, a structure in which a plurality of AlGaN layers are laminated.
  • an impurity may be introduced into a part of the buffer layer 23 to make it semi-insulating.
  • the impurity is carbon (C) or iron (Fe), for example, and the impurity concentration can be, for example, 4 ⁇ 10 16 cm ⁇ 3 or higher.
  • the electron transit layer 24 is made of a nitride semiconductor, such as a GaN layer.
  • the thickness of the electron transit layer 24 is, for example, 300 nm or more and 2 ⁇ m or less, more preferably 300 nm or more and 400 nm or less. In one example, the thickness of the electron transit layer 24 is 350 nm.
  • the main transistor 21 can be said to be a GaN transistor in which the electron transit layer 24 as the main drift layer is made of GaN.
  • impurities may be introduced into a part of the electron transit layer 24 to make the electron transit layer 24 other than the surface layer region semi-insulating.
  • the impurity is C, for example, and the concentration of the impurity can be, for example, 1 ⁇ 10 19 cm ⁇ 3 or higher in peak concentration.
  • the electron transit layer 24 can include a plurality of GaN layers with different impurity concentrations, for example, a C-doped GaN layer and a non-doped GaN layer.
  • the C concentration in the C-doped GaN layer can be 9 ⁇ 10 18 cm ⁇ 3 or more and 9 ⁇ 10 19 cm ⁇ 3 or less.
  • the electron supply layer 25 is made of a nitride semiconductor having a bandgap larger than that of the electron transit layer 24, such as an AlGaN layer. Since the bandgap increases as the Al composition increases, the electron supply layer 25, which is an AlGaN layer, has a larger bandgap than the electron transit layer 24, which is a GaN layer.
  • the electron supply layer 25 has a thickness of, for example, 5 nm or more and 20 nm or less. In one example, the electron supply layer 25 has a thickness of 8 nm or more and 15 nm or less.
  • the electron transit layer 24 and the electron supply layer 25 are composed of nitride semiconductors having lattice constants different from each other.
  • the lattice-mismatched junction between the electron transit layer 24 and the electron supply layer 25 gives strain to the electron supply layer 25 , and this strain induces a two-dimensional electron gas (2DEG) 26 in the electron transit layer 24 .
  • the 2DEG 26 spreads in the electron transit layer 24 at a position near the heterojunction interface between the electron transit layer 24 and the electron supply layer 25 (for example, a distance of several nanometers from the interface). This 2DEG 26 functions as a current path (channel) of the main transistor 21 .
  • the main transistor 21 includes a gate layer 27 formed on a portion of the electron supply layer 25, a gate electrode 21G formed on the gate layer 27, a passivation layer 28, a source electrode 21S, a drain electrode 21D, further includes The passivation layer 28 covers the electron supply layer 25, the gate layer 27, and the gate electrode 21G, and includes a first opening 28A and a second opening 28B.
  • the source electrode 21S is in contact with the electron supply layer 25 through the first opening 28A.
  • the drain electrode 21D is in contact with the electron supply layer 25 through the second opening 28B.
  • the gate layer 27 is made of a nitride semiconductor containing acceptor-type impurities.
  • the gate layer 27 is composed of any material having a smaller bandgap than the electron supply layer 25, which is an AlGaN layer, for example.
  • the gate layer 27 is a GaN layer (p-type GaN layer) doped with acceptor-type impurities.
  • Acceptor-type impurities can include at least one of zinc (Zn), magnesium (Mg), and C.
  • the maximum concentration of acceptor-type impurities in gate layer 27 is, for example, 7 ⁇ 10 18 cm ⁇ 3 or more and 1 ⁇ 10 20 cm ⁇ 3 or less.
  • the main transistor 21 includes a gate layer 27 made of a nitride semiconductor containing acceptor-type impurities, thereby depleting the 2DEG 26 in the region immediately below the gate layer 27 . This allows the main transistor 21 to operate normally off. That is, the main transistor 21 is a normally-off transistor.
  • Gate layer 27 includes a bottom surface 27r in contact with electron supply layer 25 and a top surface 27s opposite bottom surface 27r.
  • the gate electrode 21G is formed on the upper surface 27s of the gate layer 27.
  • the gate layer 27 includes a ridge portion 27C including an upper surface 27s on which the gate electrode 21G is formed, and two extension portions (a first extension portion 27A and a second extension portion 27A) extending outside the ridge portion 27C in plan view. 2 extension 27B).
  • the first extending portion 27A extends from the ridge portion 27C toward the first opening 28A in plan view.
  • the first extending portion 27A is separated from the first opening 28A.
  • the second extension portion 27B extends from the ridge portion 27C toward the second opening 28B in plan view.
  • the second extending portion 27B is separated from the second opening 28B.
  • the ridge portion 27C is located between the first extension portion 27A and the second extension portion 27B and formed integrally with the first extension portion 27A and the second extension portion 27B. Due to the presence of the first extension portion 27A and the second extension portion 27B, the bottom surface 27r of the gate layer 27 has a larger area than the top surface 27s. In the present embodiment, the second extension portion 27B extends longer toward the outside of the ridge portion 27C in plan view than the first extension portion 27A.
  • the ridge portion 27C corresponds to a relatively thick portion of the gate layer 27 and has a thickness of 80 nm or more and 150 nm or less, for example.
  • the thickness of the gate layer 27, particularly the ridge portion 27C, can be determined in consideration of parameters including the gate threshold voltage.
  • gate layer 27 (ridge portion 27C) has a thickness greater than 110 nm.
  • Each of the first extension portion 27A and the second extension portion 27B has a thickness smaller than the thickness of the ridge portion 27C. In one example, each of the first extension portion 27A and the second extension portion 27B has a thickness equal to or less than half the thickness of the ridge portion 27C.
  • each of the extensions 27A, 27B is a flat portion with a substantially constant thickness.
  • substantially constant thickness means that the thickness is within a manufacturing variation (for example, 20%).
  • each extension 27A, 27B may include a tapered portion in the region adjacent to the ridge 27C having a thickness that tapers away from the ridge 27C.
  • Each extending portion 27A, 27B may include a flat portion having a substantially constant thickness in a region more than a predetermined distance away from the ridge portion 27C. In one example, the flat portion has a thickness of 5 nm or more and 25 nm or less.
  • a gate electrode 21G formed on the ridge portion 27C is composed of one or more metal layers.
  • An example of a metal layer is a TiN layer.
  • the gate electrode 21G may be composed of a first metal layer made of Ti and a second metal layer made of TiN provided on the first metal layer.
  • the thickness of gate electrode 21G is, for example, 50 nm or more and 200 nm or less.
  • Gate electrode 21G can form a Schottky junction with gate layer 27 .
  • Each of the first opening 28A and the second opening 28B of the passivation layer 28 is separated from the gate layer 27, and the gate layer 27 is located between the first opening 28A and the second opening 28B. More specifically, the gate layer 27 is located between the first opening 28A and the second opening 28B and closer to the first opening 28A than the second opening 28B.
  • Passivation layer 28 extends along the top surface of electron supply layer 25, the side surfaces and top surface 27s of gate layer 27, and the side surfaces and top surface of gate electrode 21G, and thus has a non-flat surface.
  • the source electrode 21S and the drain electrode 21D are composed of one or more metal layers.
  • the metal layer is composed of any combination of, for example, a Ti layer, a TiN layer, an Al layer, an AlSiCu layer, and an AlCu layer.
  • At least part of the source electrode 21S is filled in the first opening 28A.
  • At least part of the drain electrode 21D is filled in the second opening 28B.
  • the source electrode 21S is in ohmic contact with the 2DEG 26 immediately below the electron supply layer 25 through the first opening 28A.
  • the drain electrode 21D is in ohmic contact with the 2DEG 26 immediately below the electron supply layer 25 through the second opening 28B.
  • the source electrode 21S includes a source contact portion 21SA filled in the first opening 28A and a source field plate portion 21SB covering the passivation layer 28.
  • the source field plate portion 21SB is formed integrally with the source contact portion 21SA.
  • the source field plate portion 21SB includes an end portion 21SC located between the second opening 28B and the gate layer 27 in plan view.
  • the source field plate portion 21SB extends from the source contact portion 21SA to the end portion 21SC along the surface of the passivation layer 28 toward the drain electrode 21D, but is separated from the drain electrode 21D.
  • Source field plate portion 21SB extends along the non-flat surface of passivation layer 28 and thus has a non-flat surface as well.
  • the source field plate portion 21SB has a function of alleviating electric field concentration near the edge of the gate electrode 21G when a drain voltage is applied to the drain electrode 21D during a zero bias period in which no gate voltage is applied to the gate electrode 21G.
  • the drain electrode 21D and the source electrode 21S are covered with an interlayer insulating layer 29.
  • a wiring layer (not shown) is provided in the interlayer insulating layer 29 .
  • the wiring layers include a drain wiring that electrically connects the drain electrode 21D and the drain pad PD1 (see FIG. 1), a source wiring that electrically connects the source electrode 21S and the source pad PS1 (see FIG. 1), and a gate wiring that electrically connects the gate electrode 21G and the gate pad PG1 (see FIG. 1).
  • the first chip 20 does not include the active clamp circuit 40, but includes the main transistor 21.
  • the main transistor 21 is formed on the semiconductor substrate 22 in the first chip 20 .
  • the active clamp circuit 40 is a circuit that suppresses erroneous turn-on caused by sharp fluctuations in the drain-source voltage when the main transistor 21 is turned off.
  • the active clamp circuit 40 includes a clamp transistor 41 (see FIG. 6), which is an example of a sub-transistor, a clamp capacitor 42 (see FIG. 7), and a pull-down resistor 43 (see FIG. 8).
  • the clamp transistor 41 , clamp capacitor 42 and pull-down resistor 43 are electrically connected to each other within the second chip 30 .
  • the pull-down resistor 43 is formed at a position overlapping the pad PG2.
  • a clamping transistor 41 is mainly formed in the second chip 30 of the present embodiment, and a clamping capacitor 42 is formed in a region different from the region where the clamping transistor 41 is formed.
  • each of the region in which clamping capacitor 42 is formed and the region in which pull-down resistor 43 is formed in plan view is about 1/100 of the area of pad PG2 in plan view.
  • the capacitor pad PCA is shown large in FIG. 1 for the sake of convenience, it is actually smaller than the pad PG2.
  • FIG. 6 is a cross-sectional view showing a partial cross-sectional structure of the active region 41T of the clamping transistor 41 as an example of the schematic cross-sectional structure of the second chip 30. As shown in FIG. It should be noted that some hatching lines are omitted from the viewpoint of visibility of the drawing.
  • the active region 41T of the clamping transistor 41 is a region in which the transistor is formed.
  • the second chip 30 has a semiconductor substrate 44 .
  • the semiconductor substrate 44 is formed in a rectangular plate shape.
  • Semiconductor substrate 44 may be formed of Si, SiC, GaN, sapphire, or other substrate material. In one example, semiconductor substrate 44 may be a Si substrate.
  • the thickness of semiconductor substrate 44 is, for example, 200 ⁇ m or more and 1500 ⁇ m or less.
  • the clamping transistor 41 is formed on the semiconductor substrate 22 . Both clamping capacitor 42 (see FIG. 7) and pull-down resistor 43 (see FIG. 8) are formed on semiconductor substrate 44 .
  • Clamping transistor 41 includes an n ⁇ -type drift layer 45 formed on semiconductor substrate 44 . Therefore, it can be said that the semiconductor substrate 44 supports the drift layer 45 .
  • the drift layer 45 is an example of a sub-drift layer, and is made of a material different from that of the electron transit layer 24 (see FIG. 5) that constitutes the main drift layer.
  • Drift layer 45 is made of a material containing Si, for example. N, P (phosphorus), As (arsenic), or the like, for example, is used as the n-type impurity of drift layer 45 .
  • the impurity concentration of drift layer 45 is, for example, 1 ⁇ 10 13 cm ⁇ 3 or more and 5 ⁇ 10 14 cm ⁇ 3 or less.
  • the clamping transistor 41 is a transistor in which the drift layer 45 constituting the sub-drift layer is made of a material containing Si.
  • the clamping transistor 41 is a Si transistor in which the drift layer 45 is made of Si.
  • the clamp transistor 41 may be a SiC transistor in which the drift layer 45 is made of SiC.
  • a p-type base region 46 is formed on the surface of the drift layer 45 .
  • a p-type dopant for base region 46 for example, B (boron), Al, or the like is used.
  • the impurity concentration of base region 46 is, for example, 1 ⁇ 10 16 cm ⁇ 3 or more and 1 ⁇ 10 18 cm ⁇ 3 or less.
  • a plurality of trenches 47 are arranged side by side on the surface of the base region 46 .
  • Each trench 47 extends, for example, along the y direction and is arranged apart from each other in the x direction.
  • Each trench 47 extends halfway through the drift layer 45 through the base region 46 in the z-direction. Note that each trench 47 may be formed in a grid pattern in a plan view.
  • n + -type source region 48 is formed on both sides of the trench 47 in the x direction on the surface of the base region 46 . It can also be said that the source region 48 is formed on the surface of the drift layer 45 .
  • the impurity concentration of the source region 48 is higher than that of the base region 46, and is, for example, 1 ⁇ 10 19 cm ⁇ 3 or more and 5 ⁇ 10 20 cm ⁇ 3 or less.
  • a p + -type base contact region 46A is formed on the surface of the base region 46 at a position adjacent to the source region 48 in the x direction.
  • the base contact region 46A is formed between two source regions 48 provided between trenches 47 adjacent in the x direction in the x direction. Further, the impurity concentration of each base contact region 46A is higher than that of the base region 46, and is, for example, 5 ⁇ 10 18 cm ⁇ 3 or more and 1 ⁇ 10 20 cm ⁇ 3 or less.
  • An insulating film 49A is integrally formed on both the inner surface of each trench 47 and the surface of the base region 46 .
  • the insulating film 49A is made of a material containing SiO2 , for example.
  • An electrode material made of, for example, polysilicon is embedded in each trench 47 via an insulating film 49A. Thus, a gate electrode 41G is formed.
  • An intermediate insulating film 49B is formed on the insulating film 49A formed on the surface of the base region 46 .
  • Intermediate insulating film 49B is made of a material containing SiO 2 , for example.
  • the thickness of the intermediate insulating film 49B is thicker than the thickness of the insulating film 49A.
  • a source electrode 41S is formed on the intermediate insulating film 49B.
  • An opening 49C exposing the base contact region 46A is formed in both the insulating film 49A and the intermediate insulating film 49B.
  • the source electrode 41S is in contact with the base contact region 46A by being embedded in the opening 49C.
  • a drain electrode 41D is formed on the back surface of the semiconductor substrate 44 opposite to the drift layer 45 in the z direction.
  • Both drain electrode 41D and source electrode 41S are made of a material containing at least one of titanium (Ti), tungsten (W), Al, Cu, and an AlCu alloy, for example.
  • FIG. 7 is a cross-sectional view showing an example of the cross-sectional structure of the clamping capacitor 42.
  • the clamping capacitor 42 is arranged at a position overlapping the capacitor pad PCA in plan view.
  • a region of the second chip 30 that overlaps with the capacitor pad PCA in plan view is a region different from the active region of the clamping transistor 41 . Therefore, as shown in FIG. 7, the insulating film 49A is formed on the semiconductor substrate 44 in the region overlapping the capacitor pad PCA in plan view.
  • the clamping capacitor 42 includes a first electrode 42P and a second electrode 42Q.
  • the first electrode 42P and the second electrode 42Q are arranged apart from each other with an insulating film 49A interposed therebetween. More specifically, two openings 49D and 49E exposing the semiconductor substrate 44 are formed in the insulating film 49A so as to be separated from each other.
  • the first electrode 42P is formed to be embedded in the opening 49D and protrude from the periphery of the opening 49D.
  • the second electrode 42Q is formed so as to be embedded in the opening 49E and protrude from the periphery of the opening 49E.
  • Both the portion of the first electrode 42P protruding from the opening 49D and the portion of the second electrode 42Q protruding from the opening 49E are covered with the intermediate insulating film 49B.
  • the insulating film 49A formed between the first electrode 42P and the second electrode 42Q, in other words, the portion of the insulating film 49A between the openings 49D and 49E constitutes a dielectric layer.
  • the first electrode 42P is electrically connected to the capacitor pad PCA via vias 42V, for example.
  • FIG. 8 is a cross-sectional view showing an example of the cross-sectional structure of the pull-down resistor 43. As shown in FIG. As shown in FIG. 8, the pull-down resistor 43 is arranged at a position overlapping the pad PG2 in plan view.
  • the pull-down resistor 43 includes a first terminal 43P, a second terminal 43Q, and a plate-like resistor portion 43R.
  • the second terminal 43Q is electrically connected to the pad PG2 via via 43V, for example.
  • the first terminal 43P and the second terminal 43Q are arranged apart from each other via the insulating film 49A. More specifically, the insulating film 49A has two openings 49F and 49G that expose the resistance portion 43R and are separated from each other.
  • the first terminal 43P is formed to be embedded in the opening 49F and protrude from the periphery of the opening 49F.
  • the second terminal 43Q is formed to be embedded in the opening 49G and protrude from the periphery of the opening 49G. Both the portion of the first terminal 43P protruding from the opening 49F and the portion of the second terminal 43Q protruding from the opening 49G are covered with the intermediate insulating film 49B.
  • the resistor portion 43R is formed on the semiconductor substrate 44.
  • the resistor portion 43R is made of a material having a higher resistance value than the first terminal 43P and the second terminal 43Q.
  • the resistance section 43R is made of polysilicon, for example.
  • a first terminal 43P and a second terminal 43Q are provided on the resistance portion 43R. Both the first terminal 43P and the second terminal 43Q are electrically connected to the resistance section 43R. More specifically, the terminals 43P, 43Q and the resistance section 43R are in ohmic contact. The first terminals 43P and the second terminals 43Q are formed dispersedly at both ends of the resistance section 43R in the y direction in plan view. Thus, the pull-down resistor 43 is formed in the insulating film 49A and covered with the intermediate insulating film 49B.
  • each of first electrode 42P and second electrode 42Q of clamping capacitor 42, vias 42V and 43V, and first terminal 43P and second terminal 43Q of pull-down resistor 43 is, for example, It can be made of any conductive material including at least one of Cu, Al, AlCu alloys, W, Ti and TiN.
  • the second chip 30 does not include the main transistor 21, but includes the active clamp circuit 40. More specifically, second chip 30 includes clamp transistor 41 , clamp capacitor 42 , and pull-down resistor 43 . In this embodiment, the second chip 30 only includes a clamping transistor 41, a clamping capacitor 42, and a pull-down resistor 43. FIG.
  • FIG. 9 shows the circuit configuration of the semiconductor module 10.
  • the active clamp circuit 40 is connected to the main transistor 21 .
  • the source electrode 41 S of the clamping transistor 41 is connected to the source electrode 21 S of the main transistor 21 .
  • a drain electrode 41D of the clamping transistor 41 is connected to the gate electrode 21G of the main transistor 21 .
  • the clamping capacitor 42 is connected between the drain electrode 21D of the main transistor 21 and the gate electrode 41G of the clamping transistor 41 .
  • a pull-down resistor 43 is connected between the source electrode 41S and the gate electrode 41G of the clamp transistor 41 .
  • Both the drain electrode 21 D of the main transistor 21 and the clamping capacitor 42 are connected to the drain terminal 81 .
  • the source electrode 21S of the main transistor 21, the source electrode 41S of the clamping transistor 41, and the pull-down resistor 43 are each connected to the source terminal 82.
  • Both the gate electrode 21 G of the main transistor 21 and the drain electrode 41 D of the clamp transistor 41 are connected to the gate terminal 83 .
  • a semiconductor module that does not include the second chip 30 is referred to as a "comparative semiconductor module".
  • the comparative semiconductor module has only the first chip 20 .
  • the first chip 20 main transistor 21
  • the first chip 20 main transistor 21
  • the voltage between the drain and the source of the main transistor 21 changes sharply during the period from time t1 to time t2 in the period in which the main transistor 21 is turned off. be. This is caused, for example, by the element to which the main transistor 21 is connected (eg the coil of the DC-DC converter).
  • the gate-source voltage (gate voltage) of the main transistor 21 rises due to the gate-drain parasitic capacitance of the main transistor 21 as indicated by the broken line in the middle of FIG.
  • the main transistor 21 is turned on. In other words, in the comparison semiconductor module, the main transistor 21 is turned on (erroneously turned on) although it should be turned off.
  • the clamping transistor 41 of this embodiment is configured to operate based on the rise of the voltage between the drain and the source of the main transistor 21 . More specifically, the clamping transistor 41 is configured to turn on before the main transistor 21 when the drain-source voltage of the main transistor 21 sharply changes.
  • the capacitance of the clamping capacitor 42 is set so that the voltage of the second electrode 42Q rises faster than the gate-source voltage of the main transistor 21.
  • the capacitance of the clamping capacitor 42 is set smaller than the gate-drain capacitance of the main transistor 21 .
  • the threshold voltage of the clamping transistor 41 may be set lower than the threshold voltage of the main transistor 21 .
  • the clamping transistor 41 having such a clamping capacitor 42 connected to the gate electrode 41G, the voltage between the gate and the source rises due to the sharp change in the voltage between the drain and the source of the main transistor 21 .
  • the clamping transistor 41 is turned on, so that the gate electrode 21G and the source electrode 21S of the main transistor 21 are electrically connected via the clamping transistor 41 .
  • the voltage between the gate and the source of the main transistor 21 starts to drop while rising. Therefore, as indicated by the solid line in the middle of FIG. 10, the gate-source voltage of the main transistor 21 can be suppressed from increasing. This can prevent the main transistor 21 from being erroneously turned on.
  • the active clamp circuit 40 is provided for the comparison semiconductor module as a countermeasure against erroneous ON
  • the active clamp circuit 40 second chip 30
  • the main transistor 21 of the comparative semiconductor module is connected to the active clamp circuit 40 provided on the circuit board by a conductive path such as wiring on the circuit board.
  • the parasitic inductance of the conductive path may delay the operation of the active clamp circuit 40 with respect to a sharp change in the voltage between the drain and the source of the main transistor 21 . Therefore, a sharp change in the voltage between the drain and the source of the main transistor 21 may also increase the voltage between the gate and the source, causing the main transistor 21 to be erroneously turned on.
  • the semiconductor module 10 of this embodiment includes both the first chip 20 and the second chip 30 .
  • semiconductor module 10 includes both main transistor 21 and active clamp circuit 40 .
  • the main transistor 21 and the active clamp circuit 40 can be electrically connected within the semiconductor module 10 . Therefore, compared to the case where the active clamp circuit 40 (second chip 30) is provided on the circuit board outside the comparative semiconductor module, the conductive path between the main transistor 21 and the active clamp circuit 40 is shortened. Therefore, parasitic impedance and parasitic inductance in the conductive path can be reduced. As a result, erroneous turn-on of the main transistor 21 can be suppressed.
  • the semiconductor module 10 includes a first chip 20 including a main transistor 21 including an electron transit layer 24 that constitutes a main drift layer, and a clamp that operates based on the rise of the drain-source voltage of the main transistor 21. a second chip 30 including at least a portion of an active clamp circuit 40 including an active clamp circuit 41, a connection member 50 electrically connecting the main transistor 21 and the active clamp circuit 40, the first chip 20 and the second chip 30 , and a sealing resin 60 that seals the connection member 50 .
  • the clamp transistor 41 includes a drift layer 45 as a sub-drift layer made of a material different from that of the main drift layer (electron transit layer 24).
  • the clamping transistor 41 can suppress an increase in the voltage between the gate and the source of the main transistor 21 when the voltage between the drain and the source of the main transistor 21 changes sharply. Therefore, it is possible to prevent the main transistor 21 from being erroneously turned on.
  • the main transistor 21 and the active clamp circuit 40 are electrically connected within the semiconductor module 10, the conductive path between the main transistor 21 and the active clamp circuit 40 can be shortened. Therefore, the parasitic impedance and parasitic inductance in the conductive path can be reduced, so that erroneous turn-on of the main transistor 21 can be further suppressed.
  • the electron transit layer 24 is a power transistor such as a GaN transistor or a SiC transistor
  • a general-purpose transistor other than a power transistor can be used as the clamping transistor 41 .
  • the main transistor 21 is a GaN transistor in which the electron transit layer 24 is made of GaN.
  • the clamping transistor 41 is a Si transistor having a drift layer 45 made of Si. According to this configuration, the cost of the clamping transistor 41 can be reduced as compared with the case where the clamping transistor 41 is a GaN transistor.
  • the first chip 20 does not include the active clamp circuit 40 but includes the main transistor 21 .
  • the second chip 30 includes a clamping transistor 41 , a clamping capacitor 42 and a pull-down resistor 43 .
  • the clamp transistor 41 , clamp capacitor 42 and pull-down resistor 43 are electrically connected to each other within the second chip 30 .
  • the electrical connection between the first chip 20 and the second chip 30 can be simplified. can.
  • the second chip 30 includes pads PG2.
  • the pad PG2 is connected to the gate electrode 41G of the clamping transistor 41 through the pull-down resistor 43. As shown in FIG.
  • the pull-down resistor 43 is formed at a position overlapping the pad PG2 in plan view and closer to the drift layer 45 than the pad PG2.
  • the active area of the clamping transistor 41 can be increased compared to the case where the pull-down resistor 43 is formed in a region different from the pad PG2 in plan view. Further, when the active region is not enlarged, the area of the second chip 30 in plan view can be reduced.
  • Each of the first connection member 51, the second connection member 52, and the third connection member 53 is formed of a metal plate. According to this configuration, the structure of the sealing resin 60 can be simplified as compared with the case where each connection member 51 to 53 is configured by wiring and vias formed of a plated layer, for example. Therefore, the number of man-hours for manufacturing the semiconductor module 100 can be reduced.
  • the first chip 20 has a drain pad PD1 electrically connected to the drain electrode 21D of the main transistor 21 and a source pad PS1 electrically connected to the source electrode 21S of the main transistor 21.
  • a drain pad PD1 electrically connected to the drain electrode 21D of the main transistor 21
  • a source pad PS1 electrically connected to the source electrode 21S of the main transistor 21.
  • the drain pad PD1 and the source pad PS1 are arranged apart from each other in the x direction.
  • the first chip 20 and the second chip 30 are arranged apart from each other in the y direction.
  • connection member 50 that electrically connects the drain electrode 21D and the source electrode 21S of the main transistor 21 and the active clamp circuit 40 .
  • the active clamp circuit 40 includes a pull-down resistor 43 connected between the source electrode 41S and the gate electrode 41G of the clamp transistor 41, the drain electrode 21D of the main transistor 21 and the gate electrode of the clamp transistor 41. and a clamping capacitor 42 connected between 41G.
  • the sharp voltage change raises the gate-source voltage of the clamping transistor 41, thereby turning on the clamping transistor 41. .
  • an increase in the gate-source voltage of the main transistor 21 is suppressed.
  • the on/off of the clamp transistor 41 is controlled within the semiconductor module 10 instead of being controlled based on the signal from the circuit outside the semiconductor module 10 . 10 eliminates the need to add signal pads. Therefore, it is possible to suppress addition of pads to the semiconductor module 10 by the active clamp circuit 40 .
  • FIG. 11 to 15 A semiconductor module 100 according to the second embodiment will be described with reference to FIGS. 11 to 15.
  • FIG. The semiconductor module 100 of this embodiment differs from the semiconductor module 10 of the first embodiment mainly in the configurations of the first chip 20 and the second chip 30 .
  • the same reference numerals are given to the components common to the first embodiment, and the description thereof will be omitted.
  • FIG. 11 is a plan view mainly showing an example of the arrangement configuration and connection configuration of the first chip 20 and the second chip 30 in the internal structure of the semiconductor module 100.
  • FIG. 12 is a plan view of the semiconductor module 100.
  • FIG. 13 is a cross-sectional view of the semiconductor module 100 taken along line F13-F13 of FIG. 11, and mainly shows cross-sectional structures of the first chip 20 and the second chip 30.
  • openings 113 to 116 which will be described later, are indicated by two-dot chain lines for the sake of convenience.
  • the semiconductor module 100 includes a first chip 20, a second chip 30, and a sealing resin 110 that seals these chips 20,30. Note that in FIG. 11, the chips 20 and 30 in the sealing resin 110 are indicated by solid lines for convenience of explanation.
  • the semiconductor module 100 is formed in a rectangular plate shape.
  • the sealing resin 110 constitutes the outer surface of the semiconductor module 100 . That is, the sealing resin 110 is formed in a rectangular plate shape.
  • the sealing resin 110 includes a resin surface 110s, a resin back surface 110r facing the opposite side of the resin surface 110s (see FIG. 13 for both), and four resin side surfaces intersecting with both the resin surface 110s and the resin back surface 110r. 1 to 4 resin side surfaces 110a to 110d.
  • the first to fourth resin side surfaces 110a to 110d are orthogonal to both the resin surface 110s and the resin back surface 110r.
  • the thickness direction of the sealing resin 110 is defined as the z direction.
  • plane view includes the meaning of "viewed from the thickness direction of the sealing resin 110".
  • the shape of the sealing resin 110 in plan view is a rectangular shape having a longitudinal direction and a lateral direction.
  • the sealing resin 110 is arranged such that its longitudinal direction coincides with the y direction and its lateral direction coincides with the x direction.
  • the first resin side surface 110a and the second resin side surface 110b constitute both end surfaces in the longitudinal direction (y direction) of the sealing resin 110
  • the third resin side surface 110c and the fourth resin side surface 110d constitute the sealing resin side surface. 110 in the lateral direction (x direction).
  • the sealing resin 110 is made of an insulating resin material. As such a resin material, for example, epoxy resin, acrylic resin, phenol resin, or the like can be used.
  • the sealing resin 110 includes a first sealing portion 111 and a second sealing portion 112.
  • the first sealing portion 111 is a support substrate that supports the first chip 20 and the second chip 30 .
  • the first sealing portion 111 includes a resin back surface 110r.
  • the second sealing portion 112 is formed on the first sealing portion 111 and cooperates with the first sealing portion 111 to seal the first chip 20 and the second chip 30 .
  • the second sealing portion 112 includes a resin surface 110s.
  • the first chip 20 is bonded to the first sealing portion 111 with a first bonding material AD1.
  • the second chip 30 is bonded to the first sealing portion 111 with a second bonding material AD2.
  • a conductive bonding material may be used for each of the bonding materials AD1 and AD2, or an insulating bonding material may be used.
  • the first chip 20 differs in shape from the first chip 20 of the first embodiment.
  • the first chip 20 of this embodiment has a rectangular flat plate shape having a longitudinal direction and a lateral direction.
  • the first chip 20 is arranged such that its longitudinal direction matches the longitudinal direction of the sealing resin 110 and its lateral direction matches the lateral direction of the sealing resin 110 .
  • the first chip 20 is formed over most of the sealing resin 110 in plan view.
  • the first chip 20 includes a drain pad PD electrically connected to the drain electrode 21D (see FIG. 6) of the main transistor 21 and a main transistor electrically connected to the source electrode 21S of the main transistor 21 (see FIG. 6). It includes a source pad PSM, a sense source pad PSS, and a gate pad PG electrically connected to the gate electrode 21G of the main transistor 21 (see FIG. 6).
  • the drain pad PD is arranged closer to the third resin side surface 110c than the center of the sealing resin 110 in the x direction.
  • Each of the main source pad PSM, the sense source pad PSS, and the gate pad PG is arranged closer to the fourth resin side surface 110d than the center of the sealing resin 110 in the x direction.
  • Gate pad PG is arranged closer to first resin side surface 110a than main source pad PSM and sense source pad PSS.
  • the main transistor 21 includes an active region 21T.
  • the active region 21T is a region in which transistors are formed.
  • the active region 21T is formed in a rectangular shape having a longitudinal direction and a lateral direction in plan view.
  • the active region 21T is formed such that its longitudinal direction matches the longitudinal direction of the first chip 20 and its lateral direction matches the lateral direction of the first chip 20 .
  • the drain pad PD is arranged closer to the third resin side surface 110c than the active region 21T.
  • Each of the main source pad PSM, the sense source pad PSS, and the gate pad PG is arranged closer to the fourth resin side surface 110d than the active region 21T.
  • the second chip 30 has a different shape compared to the second chip 30 of the first embodiment.
  • the second chip 30 of this embodiment has a rectangular flat plate shape having a longitudinal direction and a lateral direction.
  • the area (second area) of the second chip 30 in plan view is smaller than the area (first area) of the first chip 20 in plan view.
  • the second area is less than or equal to half the first area.
  • the second area is 1 ⁇ 5 or less of the first area.
  • the second area is 1/10 or less of the first area.
  • the second chip 30 is arranged such that its longitudinal direction matches the lateral direction of the sealing resin 110 and its lateral direction matches the longitudinal direction of the sealing resin 110 .
  • the second chip 30 is arranged closer to the first resin side surface 110a than the first chip 20 is. Therefore, the first chip 20 and the second chip 30 are arranged apart from each other in the longitudinal direction (y direction) of the sealing resin 110 .
  • the longitudinal direction of the first chip 20 matches the arrangement direction of the first chip 20 and the second chip 30 .
  • the longitudinal direction of the second chip 30 is orthogonal to the arrangement direction of the first chip 20 and the second chip 30 in plan view.
  • the second chip 30 is arranged closer to the fourth resin side surface 110d with respect to the center of the sealing resin 110 in the x direction. In other words, it can be said that the second chip 30 is arranged closer to the gate pad PG than to the drain pad PD of the first chip 20 .
  • the second chip 30 includes a first pad PA, a second pad PB, and a third pad PC. These pads PA to PC are aligned with each other in the lateral direction (y direction) of the second chip 30 and are spaced apart from each other in the longitudinal direction (x direction) of the second chip 30 . Each of the pads PA to PC is arranged at the center of the second chip 30 in the lateral direction (y direction).
  • the first pads PA are arranged at the ends of the x-direction ends of the second chip 30 that are closer to the third resin side surface 110c.
  • the first pad PA is arranged closer to the drain pad PD than the second pad PB and the third pad PC in the x direction.
  • the third pads PC are arranged at the ends closer to the fourth resin side surface 110d among both ends of the second chip 30 in the x direction.
  • the third pad PC is arranged closer to the gate pad PG than the first pad PA and the second pad PB in the x direction.
  • the third pad PC is arranged so as to overlap with the gate pad PG when viewed in the y direction.
  • the second pads PB are arranged in the center of the second chip 30 in the x direction.
  • the first pad PA and the second pad PB are arranged closer to the third resin side surface 110c than the sense source pad PSS and the gate pad PG. That is, the first pad PA and the second pad PB are arranged at positions shifted toward the third resin side surface 110c with respect to the sense source pad PSS and the gate pad PG when viewed in the y direction.
  • the semiconductor module 100 includes a connecting member 120 that electrically connects the first chip 20 and the second chip 30 .
  • Connecting member 120 includes a conductive material.
  • a conductive material For example, Cu, Al, CuAl alloy, or the like can be used as the conductive material.
  • the connection member 120 is formed of a metal plate made of a conductive material.
  • the connection member 120 is arranged on the first chip 20 and the second chip 30 . For this reason, the connecting member 120 is formed so as to span between the first chip 20 and the second chip 30 .
  • the connection member 120 is sealed with a second sealing portion 112 (sealing resin 110).
  • the connecting member 120 includes a first connecting member 121, a second connecting member 122, a third connecting member 123, and a fourth connecting member .
  • the first connection member 121 electrically connects the drain pad PD of the first chip 20 and the first pad PA of the second chip 30 .
  • the first connection member 121 is connected over the entire surface of the drain pad PD.
  • the first connection member 121 is bonded to both the drain pad PD and the first pad PA by ultrasonic bonding or the like.
  • the second connection member 122 electrically connects the main source pad PSM of the first chip 20 and the second pad PB of the second chip 30 .
  • the second connection member 122 is formed so as to avoid the sense source pads PSS.
  • the second connection member 122 is joined to both the main source pad PSM and the second pad PB.
  • the third connection member 123 electrically connects the gate pad PG of the first chip 20 and the third pad PC of the second chip 30 .
  • the third connection member 123 is joined to both the gate pad PG and the third pad PC.
  • the fourth connection member 124 is electrically connected to the sense source pad PSS of the first chip 20.
  • the fourth connection member 124 is joined to the sense source pad PSS. Note that the fourth connection member 124 may be integrated with the second connection member 122 .
  • the semiconductor module 100 has a drain terminal 131, a main source terminal 132, a sense source terminal 133, and a gate terminal . These terminals 131 to 134 are formed on the resin surface 110s. In plan view, these terminals 131 to 134 are arranged apart from each other.
  • the drain terminal 131 is arranged at a position overlapping the drain pad PD of the first chip 20 in plan view. In other words, the drain terminal 131 is arranged at a position overlapping the first connection member 121 (see FIG. 11) in plan view.
  • the drain terminal 131 is electrically connected to the drain pad PD via the first connection member 121 .
  • a first opening 113 exposing the first connection member 121 is formed in the sealing resin 110 at a position where the drain terminal 131 is formed.
  • the drain terminal 131 is formed so as to fill the first opening 113 and partially protrude from the first opening 113 to the resin surface 110s.
  • the main source terminal 132 is arranged at a position overlapping the main source pad PSM of the first chip 20 in plan view. In other words, the main source terminal 132 is arranged at a position overlapping the second connection member 122 in plan view. Main source terminal 132 is electrically connected to main source pad PSM via second connection member 122 . In one example, as shown in FIGS. 12 and 13, a second opening 114 exposing the second connecting member 122 is formed in the sealing resin 110 at a position where the main source terminal 132 is formed. The main source terminal 132 is formed so as to fill the second opening 114 and partially protrude from the second opening 114 to the resin surface 110s.
  • the sense source terminal 133 is arranged at a position overlapping the sense source pad PSS of the first chip 20 in plan view. Sense source terminal 133 is electrically connected to sense source pad PSS. In one example, as shown in FIGS. 12 and 13, a third opening 115 exposing the fourth connection member 124 is formed in the sealing resin 110 at a position where the sense source terminal 133 is formed. The third opening 115 is formed apart from the second opening 114 in the y direction. The sense source terminal 133 is formed so as to fill the third opening 115 and partially protrude from the third opening 115 to the resin surface 110s.
  • the gate terminal 134 is arranged at a position overlapping the gate pad PG of the first chip 20 in plan view.
  • the gate terminal 134 is electrically connected to the gate pad PG via the third connection member 123 .
  • a fourth opening 116 exposing the third connection member 123 is formed in the sealing resin 110 at a position where the gate terminal 134 is formed.
  • the gate terminal 134 is formed so as to fill the fourth opening 116 and partially protrude from the fourth opening 116 to the resin surface 110s.
  • a surface insulating layer 135 is formed on the resin surface 110s.
  • the surface insulating layer 135 is formed so as to cover the outer peripheries of the terminals 131-134.
  • each of terminals 131 - 134 includes a portion exposed from surface insulating layer 135 .
  • FIG. 14 is a plan view mainly showing an example of the planar structure of the active clamp circuit 40 of the second chip 30.
  • FIG. 15 is a cross-sectional view of the second chip 30 cut along line F15-F15 in FIG. It mainly shows the internal connection structure. Note that in FIG. 14, the clamping transistor 41, the clamping capacitor 42, and the pull-down resistor 43 are indicated by solid lines from the viewpoint of easiness of viewing the drawing.
  • the second chip 30 includes a first chip side 30a, a second chip side 30b, a third chip side 30c, and a fourth chip side 30d.
  • the first chip side surface 30a and the second chip side surface 30b constitute both end surfaces of the second chip 30 in the lateral direction (y direction).
  • the third chip side surface 30c and the fourth chip side surface 30d constitute both end surfaces of the second chip 30 in the longitudinal direction (x direction).
  • the first chip side surface 30a faces the same side as the first resin side surface 110a (see FIG. 12)
  • the second chip side surface 30b faces the same side as the second resin side surface 110b (see FIG. 12).
  • the third chip side surface 30c faces the same side as the third resin side surface 110c (see FIG. 12)
  • the fourth chip side surface 30d faces the same side as the fourth resin side surface 110d (see FIG. 12).
  • the clamping transistor 41, the clamping capacitor 42, and the pull-down resistor 43 of the active clamping circuit 40 are formed at mutually different positions in plan view.
  • the clamping capacitor 42 and the pull-down resistor 43 are arranged closer to the third chip side surface 30 c than the clamping transistor 41 .
  • the pull-down resistor 43 is arranged closer to the first chip side surface 30a than the clamping capacitor 42 .
  • the clamping transistor 41 includes an active region 41T in which a transistor is formed.
  • the active area 41T is a rectangular area having a longitudinal direction and a lateral direction.
  • the active region 41T is formed in a rectangular shape with the x direction as the longitudinal direction and the y direction as the lateral direction.
  • the longitudinal direction of the active region 41T matches the longitudinal direction of the second chip 30 .
  • the longitudinal direction of the first chip 20 is the y direction
  • the lateral direction is the x direction. are doing.
  • the clamping transistor 41 of this embodiment uses a MOSFET with a lateral structure. Therefore, each of the drain electrode 41D, the source electrode 41S, and the gate electrode 41G of the clamping transistor 41 is exposed from the surface of the intermediate insulating film 49B.
  • a drain region 46B is formed on the surface of the base region 46 so as to be separated from the source region 48 .
  • the drain electrode 41D is in contact with the drain region 46B.
  • the source electrode 41S is in contact with the source region 48.
  • the clamping transistor 41 of this embodiment has a gate electrode 41G formed on an insulating film 49A formed on a base region 46 instead of a gate trench.
  • the gate electrode 41G is covered with an intermediate insulating film 49B.
  • both the first electrode 42P and the second electrode 42Q of the clamping capacitor 42 are configured by a plurality of wirings.
  • the first electrode 42P includes a plurality of (two in this embodiment) first wirings extending in the y direction and second wirings extending in the x direction.
  • the two first wirings are arranged apart from each other in the x direction.
  • the second wiring connects the ends of the two first wirings near the second chip side surface 30b in the x direction.
  • the second electrode 42Q includes a plurality of (two in this embodiment) third wirings extending in the y direction and fourth wirings extending in the x direction.
  • the two third wirings are arranged apart from each other in the x direction.
  • the third wiring is arranged so as to face the first wiring of the first electrode 42P in the x direction.
  • the first wirings and the third wirings are alternately arranged in the x direction.
  • the fourth wiring is arranged closer to the first chip side surface 30a than the second wiring of the first electrode 42P in the y direction.
  • the fourth wiring connects the ends of the two third wirings near the first chip side surface 30a in the x direction.
  • the clamping capacitor 42 is formed in an insulating film 49A and covered with an intermediate insulating film 49B, as in the first embodiment.
  • the pull-down resistor 43 has the same configuration as the pull-down resistor 43 of the first embodiment. As shown in FIG. 15, in this embodiment, the clamping transistor 41, the clamping capacitor 42, and the pull-down resistor 43 are aligned in the thickness direction (z direction) of the semiconductor substrate 44 (see FIG. 6). formed.
  • the wiring layer 140 includes a clamping drain wiring 141 , a clamping source wiring 142 and a clamping gate wiring 143 .
  • the clamping drain wiring 141 is electrically connected to each of the plurality of drain electrodes 41D of the clamping transistor 41 .
  • the clamping drain wiring 141 is formed closer to the second chip side surface 30b than the active region 41T.
  • the drain wiring 141 for clamping is formed in a belt shape whose longitudinal direction is the x direction in plan view. This clamping drain wiring 141 indicates a portion where a plurality of clamping drain wirings 141 (see FIG. 15) formed on the active region 41T are joined.
  • the clamping source wiring 142 is electrically connected to each of the plurality of source electrodes 41S of the clamping transistor 41 .
  • the clamping source wiring 142 is formed in a band shape with the x direction being the longitudinal direction, closer to the first chip side surface 30a than the active region 41T.
  • the clamping source wiring 142 indicates a portion that joins a plurality of clamping source wirings 142 (see FIG. 15) formed on the active region 41T.
  • the clamping gate wiring 143 is electrically connected to each of the plurality of gate electrodes 41G of the clamping transistor 41 .
  • the clamping gate wiring 143 is shown as a small rectangular shape adjacent to the active region 41T in the x direction, but it is actually routed over the entire active region 41T.
  • the wiring layer 140 further includes a first connection wiring 151, a second connection wiring 152, a third connection wiring 153, a fourth connection wiring 154, and a fifth connection wiring 155.
  • the first connection wiring 151 electrically connects the clamping capacitor 42 and the first pad PA (see FIG. 11). More specifically, the first connection wiring 151 connects the second wiring of the first electrode 42P of the clamping capacitor 42 and the first pad PA. Since the first pad PA is electrically connected to the drain electrode 21D of the main transistor 21 by the first connection member 121 shown in FIG. 11, the first connection wiring 151 is electrically connected to the drain electrode 21D. It can be said. Thereby, the first electrode 42P of the clamping capacitor 42 is electrically connected to the drain electrode 21D.
  • the second connection wiring 152 electrically connects both the clamping capacitor 42 and the pull-down resistor 43 and the gate electrode 41G of the clamping transistor 41 . More specifically, the second connection wiring 152 electrically connects both the fourth wiring of the second electrode 42Q of the clamping capacitor 42 and the first terminal 43P of the pull-down resistor 43 and the gate electrode 41G. . It can be said that the second connection wiring 152 is a part of the clamping gate wiring 143 connected to the gate electrode 41G. That is, the clamping gate wiring 143 includes the second connection wiring 152 .
  • the second connection wiring 152 is formed closer to the third chip side surface 30c than the active region 41T.
  • the second connection wiring 152 is formed between the clamping capacitor 42 and the pull-down resistor 43 in the y direction.
  • the third connection wiring 153 is a connection wiring that electrically connects the pull-down resistor 43 and the source electrode 41 S of the clamp transistor 41 . More specifically, the third connection wiring 153 electrically connects the second terminal 43Q of the pull-down resistor 43 and the source electrode 41S. It can be said that the third connection wiring 153 is a part of the clamping source wiring 142 connected to the source electrode 41S. That is, the clamp source wiring 142 includes the third connection wiring 153 . In plan view, the third connection wiring 153 is formed closer to the first chip side surface 30a and the third chip side surface 30c than the active region 41T.
  • the fourth connection wiring 154 electrically connects the source electrode 41S of the clamping transistor 41 and the second pad PB. More specifically, the fourth connection wiring 154 connects the clamping source wiring 142 and the second pad PB (see FIG. 11). In this embodiment, the fourth connection wiring 154 is integrated with the clamping source wiring 142 . Therefore, it can be said that the fourth connection wiring 154 is a part of the clamping source wiring 142 . That is, the clamp source wiring 142 includes the fourth connection wiring 154 .
  • the fourth connection wiring 154 is formed closer to the first chip side surface 30a than the active region 41T in plan view.
  • the fourth connection wiring 154 is formed at a position overlapping the second pad PB in plan view. Note that the formation position of the fourth connection wiring 154 can be arbitrarily changed. In one example, the fourth connection wiring 154 may be formed at a position overlapping the active region 41T in plan view.
  • the fifth connection wiring 155 electrically connects the drain electrode 41D of the clamping transistor 41 and the third pad PC (see FIG. 11). Since the third pad PC is electrically connected to the gate electrode 21G of the main transistor 21 by the third connection member 123, the drain electrode 41D is electrically connected to the gate electrode 21G.
  • the fifth connection wiring 155 is formed closer to the fourth chip side surface 30d than the active region 41T.
  • the fifth connection wiring 155 is formed at a position overlapping the third pad PC in plan view. Note that the formation position of the fifth connection wiring 155 can be arbitrarily changed. In one example, the fifth connection wiring 155 may be formed at a position overlapping the active region 41T in plan view.
  • Each wiring of the clamping capacitor 42, each of the terminals 43P and 43Q of the pull-down resistor 43, each of the wirings 141 to 143, and each of each of the connection wirings 151 to 155 are made of at least Cu, Al, AlCu alloy, W, Ti, and TiN, for example. It can be constructed from any conductive material, including one. In addition, according to this embodiment, the same effects as those of the first embodiment can be obtained.
  • FIG. 16 to 18 A semiconductor module 200 according to the third embodiment will be described with reference to FIGS. 16 to 18.
  • FIG. The semiconductor module 200 of this embodiment differs from the semiconductor module 100 of the second embodiment mainly in the configuration of the first chip 20 and the connection configuration between the first chip 20 and the second chip 30 .
  • the same reference numerals are given to the components common to the second embodiment, and the description thereof will be omitted.
  • FIG. 16 is a plan view of the semiconductor module 200.
  • FIG. FIG. 17 is a plan view mainly showing an example of the cross-sectional structure of the first chip 20 and its periphery in the internal structure of the semiconductor module 200.
  • FIG. 18 is a cross-sectional view mainly showing an example of the cross-sectional structure of the first chip 20, the second chip 30, and their periphery in the internal structure of the semiconductor module 200. As shown in FIG.
  • the semiconductor module 200 includes a first chip 20, a second chip 30, and a sealing resin 110 that seals these chips 20,30.
  • the chips 20 and 30 in the sealing resin 110 are indicated by two-dot chain lines for convenience of explanation.
  • the first chip 20 and the second chip 30 are aligned in the lateral direction (x direction) of the sealing resin 110 and arranged apart from each other in the longitudinal direction (y direction) of the sealing resin 110. It is
  • the first chip 20 has a different pad configuration compared to the first chip 20 of the second embodiment.
  • the first chip 20 of this embodiment includes multiple drain pads PD, gate pads PG, and multiple source pads PS.
  • the first chip 20 of this embodiment does not have the sense source pads PSS of the second embodiment.
  • the drain pads PD and source pads PS are alternately arranged in the longitudinal direction of the first chip 20 (the y direction in this embodiment).
  • the gate pad PG is arranged at one of both ends of the first chip 20 in the longitudinal direction, which is closer to the second chip 30 .
  • a drain terminal 131, a main source terminal 132, and a gate terminal 134 are formed on the resin surface 110s (see FIG. 17).
  • the sense source terminal 133 is not formed on the resin surface 110s.
  • the semiconductor module 200 includes a connection member 210 that connects the first chip 20 and the second chip 30 together.
  • the connection member 210 is arranged closer to the resin surface 110s than the chips 20 and 30 are.
  • the connection member 210 is sealed with a second sealing portion 112 (sealing resin 110).
  • part of the connecting member 210 is exposed from the second sealing portion 112 (sealing resin 110) to constitute the drain terminal 131, the main source terminal 132, and the gate terminal 134. are doing.
  • a drain terminal 131, a main source terminal 132, and a gate terminal 134 are covered with a surface insulating layer 135 as in the second embodiment.
  • the drain terminal 131, the main source terminal 132, and the gate terminal 134 are partly exposed from the surface insulating layer 135 as in the second embodiment.
  • connection member 210 includes a first connection member 211, a second connection member 212 and a third connection member 213.
  • Each connection member 211 to 213 includes a first portion that joins with each chip 20, 30, a second portion that is exposed from the resin surface 110s, and a third portion that connects the first portion and the second portion. . Since the second portion is formed closer to the resin surface 110s than the first portion, the third portion is formed to bend in the z direction.
  • the first connection member 211 connects each drain pad PD of the first chip 20 and the first pad PA of the second chip 30 .
  • a portion of the first connection member 211 exposed from the sealing resin 110 constitutes the drain terminal 131 .
  • the first connection member 211 includes a comb-shaped portion joined to each drain pad PD and a comb-shaped portion extending from the end of the comb-shaped portion closer to the second chip 30 toward the second chip 30 . an extending extension. The extension is joined to the first pad PA.
  • the second connection member 212 connects each source pad PS of the first chip 20 and the second pad PB of the second chip 30 .
  • a portion of the second connection member 212 exposed from the sealing resin 110 constitutes the main source terminal 132 .
  • the second connection member 212 includes a comb tooth-shaped portion joined to each source pad PS and an end portion of the comb tooth shape near the second chip 30 in the y direction to the second chip 30 . and an extension extending toward. The extension is joined to the second pad PB.
  • the third connection member 213 connects the gate pad PG of the first chip 20 and the third pad PC of the second chip 30 .
  • a portion of the third connection member 213 exposed from the sealing resin 110 is electrically connected to the gate terminal 134 .
  • the shape of the third connection member 213 in plan view is a crank shape formed so as to avoid the first connection member 211 .
  • the first sealing portion 111 is provided with a first die pad 220 on which the first chip 20 is mounted and a second die pad 230 on which the second chip 30 is mounted.
  • Each die pad 220, 230 is made of a metal material such as Cu, Al, CuAl alloy, for example.
  • each die pad 220, 230 uses a Cu frame.
  • the first sealing portion 111 is formed so as to cover side surfaces of the die pads 220 and 230 . In other words, the die pads 220 and 230 are exposed from the first sealing portion 111 (resin back surface 110r).
  • the first sealing portion 111 is provided with a first heat dissipation structure 221 that radiates the heat of the first die pad 220 to the outside of the first sealing portion 111 .
  • the first heat dissipation structure 221 includes a plurality of vias and a heat dissipation pad formed on the resin back surface 110r. A plurality of vias connect the thermal pad and the first die pad 220 .
  • the first sealing portion 111 is provided with a second heat dissipation structure 231 that radiates the heat of the second die pad 230 to the outside of the first sealing portion 111 . Since the configuration of the second heat dissipation structure 231 is the same as the configuration of the first heat dissipation structure 221, detailed description thereof will be omitted.
  • the first chip 20 is bonded to the first die pad 220 with the first bonding material AD1.
  • the second chip 30 is bonded to the second die pad 230 with a second bonding material AD2.
  • a conductive bonding material such as solder paste or Ag paste is used for each of the bonding materials AD1 and AD2.
  • a back surface insulating layer 136 is formed on the resin back surface 110r.
  • Back insulating layer 136 is made of a material containing at least one of SiO 2 and SiN.
  • the back insulating layer 136 is formed so as to cover the outer peripheries of the heat dissipation structures 221 and 231 .
  • each heat dissipation structure 221 , 231 includes a portion exposed from the back insulating layer 136 .
  • the first chip 20 is mounted on the first die pad 220 exposed from the resin rear surface 110 r of the sealing resin 110 .
  • the first die pad 220 is made of metal material.
  • FIG. 3 differs from the third embodiment mainly in the number of first chips 20 and second chips 30 and the addition of a third chip 310 .
  • the same reference numerals are given to the components common to the third embodiment, and the description thereof will be omitted.
  • FIG. FIG. 19 is a plan view mainly showing an example of the arrangement configuration of the first chip 20, the second chip 30, and the later-described third chip 310 in the internal structure of the semiconductor module 300.
  • FIG. 20 is a plan view mainly showing an example of the configuration of wiring layers in the internal structure of the semiconductor module 300.
  • FIG. 21 is a plan view of the semiconductor module 300.
  • FIG. FIG. 22 is an example of the cross-sectional structure of the semiconductor module 200 taken along line F22-F22 of FIG. 21, and is a cross-sectional view mainly showing the first chip 20 and its surroundings.
  • FIG. 23 is an example of a cross-sectional structure of the semiconductor module 200 taken along line F23-F23 of FIG.
  • the semiconductor unit 400 includes a semiconductor module 300 and a third chip 310.
  • a third chip 310 is provided separately from the first chip 20 and the second chip 30 .
  • the third chip 310 is sealed with the sealing resin 350 of the semiconductor module 300 .
  • the configuration of the semiconductor module 300 is different from that of the second embodiment. More specifically, the semiconductor module 300 includes a plurality of (two in this embodiment) first chips 20, a plurality of (two in this embodiment) second chips 30, each first chip 20 and each second and a sealing resin 350 that seals the two chips 30 .
  • the chips 20, 30, and 310 in the sealing resin 350 are indicated by solid lines for convenience of explanation.
  • the two first chips 20 are separately referred to as “first chip 20A” and “first chip 20B", respectively.
  • the two second chips 30 are separately referred to as a "second chip 30A" and a "second chip 30B", respectively.
  • the semiconductor module 300 is formed in a rectangular plate shape.
  • the sealing resin 350 constitutes the outer surface of the semiconductor module 300 . That is, the sealing resin 350 is formed in a rectangular plate shape.
  • the sealing resin 350 includes a resin surface 350s, a resin back surface 350r facing the opposite side of the resin surface 350s (see FIG. 22 for both), and four resin side surfaces intersecting with both the resin surface 350s and the resin back surface 350r. and first to fourth resin side surfaces 350a to 350d.
  • the first to fourth resin side surfaces 350a to 350d are orthogonal to both the resin front surface 350s and the resin back surface 350r.
  • the thickness direction of the sealing resin 350 is defined as the z direction.
  • plane view includes the meaning of "viewed from the thickness direction of the sealing resin 350".
  • the shape of the sealing resin 350 in plan view is a rectangular shape having a longitudinal direction and a lateral direction.
  • the longitudinal direction of the sealing resin 350 is the y direction
  • the lateral direction of the sealing resin 350 is the x direction.
  • the first resin side surface 350a and the second resin side surface 350b constitute both end surfaces in the y direction
  • the third resin side surface 350c and the fourth resin side surface 350d constitute both end surfaces in the x direction.
  • the sealing resin 350 is made of an insulating resin material.
  • a resin material for example, epoxy resin, acrylic resin, phenol resin, or the like can be used.
  • the first chips 20A and 20B are aligned with each other in the longitudinal direction (y direction) of the sealing resin 350 and arranged apart from each other in the lateral direction (x direction) of the sealing resin 110 .
  • the first chips 20A and 20B are arranged to be biased in the y direction with respect to the sealing resin 350 .
  • the first chips 20A and 20B are arranged closer to the second resin side surface 350b than the first resin side surface 350a of the sealing resin 350 in plan view.
  • the first chips 20A and 20B are arranged so that their longitudinal direction is the y direction and their lateral direction is the x direction.
  • the third chip 310 is arranged apart from each of the first chips 20A and 20B in a direction orthogonal to the arrangement direction of the first chips 20A and 20B in plan view. More specifically, the third chip 310 is arranged closer to the first resin side surface 350a than the first chips 20A and 20B in the y direction.
  • the third chip 310 is formed in a rectangular plate shape.
  • the shape of the third chip 310 in plan view is a rectangular shape having a longitudinal direction and a lateral direction. In this embodiment, the third chip 310 is arranged such that its longitudinal direction is the x direction and its lateral direction is the y direction.
  • the longitudinal direction of the third chip 310 is perpendicular to both the longitudinal direction of the sealing resin 350 and the longitudinal direction of the first chips 20A and 20B, and the lateral direction of the third chip 310 is perpendicular to the sealing resin. 350 and the short directions of the first chips 20A and 20B.
  • the third chip 310 is arranged at a position partially overlapping each of the first chips 20A and 20B. In this embodiment, the third chip 310 is arranged in the center of the sealing resin 350 in the x direction.
  • the third chip 310 includes a chip front surface 310s and a chip rear surface 310r (see FIG. 23) facing opposite sides in the z direction.
  • the chip front surface 310s faces the same side as the resin front surface 350s
  • the chip rear surface 310r faces the same side as the resin rear surface 350r.
  • the third chip 310 includes a semiconductor substrate, a driver circuit 311 formed on the semiconductor substrate and individually driving the first chips 20A and 20B, and a plurality of electrode pads 312 electrically connected to the driver circuit 311. and including. Each electrode pad 312 is exposed from the chip surface 310s.
  • the second chips 30A, 30B are arranged closer to the first resin side surface 350a than the first chips 20A, 20B.
  • the second chip 30A is arranged between the third chip 310 and the first chip 20A in the y direction.
  • the second chip 30B is arranged between the third chip 310 and the first chip 20B in the y direction.
  • the second chip 30A is arranged at a position adjacent to the first chip 20A in the y direction.
  • the second chip 30B is arranged at a position adjacent to the first chip 20B in the y direction.
  • the semiconductor module 300 includes wiring layers 320 .
  • the wiring layer 320 includes at least two types of wiring layers: a wiring layer including vias extending in the z-direction and wirings extending in a direction orthogonal to the z-direction, and a wiring layer composed only of vias extending in the z-direction. include.
  • the wiring layer 320 is a wiring layer that connects the first chips 20A, 20B, the second chips 30A, 30B, and the third chip 310 .
  • the wiring layer 320 includes a first connection wiring 321 , a second connection wiring 322 , a third connection wiring 323 , a fourth connection wiring 324 and a fifth connection wiring 325 .
  • the wiring layer 320 also includes a plurality of driver wirings 326 connected to the third chip 310 .
  • Each connection wiring 321 to 325 and each driver wiring 326 extends in a direction orthogonal to the z-direction and does not include a portion bent in the z-direction.
  • Each connection wiring 321 to 325 and each driver wiring 326 are formed by metal plating.
  • the first connection wiring 321 connects the source pad PS of the first chip 20A and the drain pad PD of the first chip 20B to the second pad PB of the second chip 30A and the first pad PA of the second chip 30B.
  • the first connection wiring 321 includes a comb-shaped portion, a first extension, and a second extension.
  • the comb-like portion is electrically connected to the source pad PS of the first chip 20A and the drain pad PD of the first chip 20B by, for example, a plurality of vias.
  • the first extension extends from the end of the comb tooth-like portion closer to the second chip 30A toward the second chip 30A.
  • the first extension is electrically connected to the second pads PB of the second chip 30A by vias, for example.
  • the second extension extends from the end of the comb tooth-like portion closer to the second chip 30B toward the second chip 30B.
  • the second extension is electrically connected to the first pads PA of the second chip 30B by vias, for example.
  • the second connection wiring 322 connects the drain pad PD of the first chip 20A and the first pad PA of the second chip 30A.
  • the second connection wiring 322 has a portion closer to the third resin side surface 350 c than the first connection wiring 321 .
  • the second connection wiring 322 includes a comb-shaped portion electrically connected to each drain pad PD, and an end of the comb-shaped portion closer to the second chip 30A to the second chip 30A. and an extension extending toward.
  • the comb tooth-shaped portion is electrically connected to each drain pad PD by, for example, a plurality of vias.
  • the extension is electrically connected to the first pad PA by vias, for example.
  • the third connection wiring 323 connects the source pad PS of the first chip 20B and the second pad PB of the second chip 30B.
  • the third connection wiring 323 has a portion closer to the fourth resin side surface 350 d than the first connection wiring 321 .
  • the third connection wiring 323 includes a comb tooth-shaped portion and an extension portion.
  • the comb tooth-shaped portion is electrically connected to the source pad PS by, for example, a plurality of vias.
  • the extension is electrically connected to the second pad PB by vias, for example.
  • the fourth connection wiring 324 connects the gate pad PG of the first chip 20A, the third pad PC of the second chip 30A, and the electrode pad 312 of the third chip 310 .
  • the fourth connection wiring 324 is electrically connected to the gate pad PG and the electrode pad 312 by vias, for example.
  • the fifth connection wiring 325 connects the gate pad PG of the first chip 20B, the third pad PC of the second chip 30B and the electrode pad 312 of the third chip 310 .
  • the fifth connection wiring 325 is electrically connected to the gate pad PG and the electrode pad 312 by vias, for example.
  • both the fourth connection wiring 324 and the fifth connection wiring 325 correspond to the "connection member for control".
  • the plurality of driver wirings 326 are individually connected to the plurality of electrode pads 312 of the third chip 310 .
  • Each driver wiring 326 extends outward from the third chip 310 toward one of the first resin side surface 350a, the third resin side surface 350c, and the fourth resin side surface 350d in plan view.
  • the semiconductor module 200 includes a drain terminal 331, a source terminal 332, an output terminal 333, and a plurality of driver terminals 334.
  • Each terminal 331 to 334 is formed on the resin surface 350s.
  • portions of the drain terminal 331, the source terminal 332, and the output terminal 333 that are not exposed from the sealing resin 350 are indicated by broken lines.
  • the drain terminal 331, the source terminal 332, and the output terminal 333 are aligned with each other in the y direction and arranged apart from each other in the x direction.
  • the drain terminal 331, the source terminal 332, and the output terminal 333 are arranged to be biased toward the second resin side surface 350b rather than the first resin side surface 350a in the y direction.
  • the drain terminal 331 is arranged at a position overlapping with the second connection wiring 322 (see FIG. 20)
  • the source terminal 332 is arranged at a position overlapping with the third connection wiring 323 (see FIG. 20)
  • the output terminal 333 is arranged at a position overlapping the first connection wiring 321 (see FIG. 20).
  • the plurality of driver terminals 334 are arranged to be closer to the first resin side surface 350a than the second resin side surface 350b in the y direction.
  • the plurality of driver terminals 334 are arranged in a line along the first resin side surface 350a, the third resin side surface 350c, and the fourth resin side surface 350d in plan view.
  • the drain terminal 331 is a terminal electrically connected to the drain electrode 21D (see FIG. 20) of the main transistor 21 of the first chip 20A.
  • the shape of the drain terminal 331 in plan view is the same as the shape of the comb tooth-like portion of the second connection wiring 322 in plan view.
  • the drain terminal 331 is electrically connected to the second connection wiring 322 .
  • the source terminal 332 is a terminal electrically connected to the source electrode 21S (see FIG. 20) of the main transistor 21 of the first chip 20B.
  • the shape of the source terminal 332 in plan view is the same as the shape of the comb-like portion of the third connection wiring 323 in plan view.
  • the source terminal 332 is electrically connected to the third connection wiring 323 .
  • the output terminal 333 is a terminal electrically connected to both the source electrode 21S (see FIG. 20) of the main transistor 21 of the first chip 20A and the drain electrode 21D (see FIG. 20) of the main transistor 21 of the first chip 20B. is.
  • the output terminal 333 is electrically connected to the first connection wiring 321 .
  • Each of the drain terminal 331, the source terminal 332, and the output terminal 333 is formed on the resin surface 350s (see FIG. 22) and covered with the surface insulating layer 370 in a partially exposed state.
  • a portion of the drain terminal 331, the source terminal 332, and the output terminal 333 exposed from the surface insulating layer 370 has a rectangular shape in a plan view with the y direction being the longitudinal direction and the x direction being the lateral direction.
  • Surface insulating layer 370 is made of a material containing SiO 2 or SiN, for example.
  • the plurality of driver terminals 334 are terminals electrically connected to the driver circuit 311 .
  • the plurality of driver terminals 334 are electrically connected to the plurality of driver wirings 326 individually. More specifically, each driver terminal 334 is connected to the second via of each driver wiring 326 .
  • the sealing resin 350 includes a first sealing portion 351, a second sealing portion 352, and a third sealing portion 353.
  • Each of the sealing portions 351-353 is made of the same material, for example.
  • the first sealing portion 351 is a support member that supports the chips 20A, 20B, 30A, 30B, and 310. Each chip 20A, 20B, 30A, 30B, 310 is bonded to the first sealing portion 351 by bonding materials AD1 to AD3, for example.
  • the first sealing portion 351 constitutes a resin rear surface 350r.
  • the first sealing portion 351 has a first die pad 361 on which the first chip 20A is mounted, a second die pad 362 on which the first chip 20B is mounted, and a third die pad 363 on which the second chip 30A is mounted. , and a fourth die pad 364 on which the second chip 30B is mounted.
  • a fifth die pad corresponding to the third chip 310 may be formed.
  • the first sealing portion 351 includes a first heat dissipation structure 365 for dissipating the heat of the first die pad 361 to the outside of the sealing resin 350 and a second heat dissipation structure 365 for dissipating the heat of the second die pad 362 to the outside of the sealing resin 350 .
  • a heat dissipation structure 366 is formed.
  • the first sealing portion 351 includes a third heat dissipation structure (not shown) for dissipating the heat of the third die pad 363 to the outside of the sealing resin 350, and the heat of the fourth die pad 364 to the outside of the sealing resin 350.
  • a fourth heat dissipation structure 367 is formed to dissipate heat to.
  • the first heat dissipation structure 365 includes a plurality of vias formed in a portion overlapping the first die pad 361 in plan view, and a heat dissipation pad formed on the resin back surface 350r. A plurality of vias connect the first die pad 361 and the heat dissipation pad. Both the second heat dissipation structure 366 and the fourth heat dissipation structure 367 have the same configuration as the first heat dissipation structure 365, so detailed description thereof will be omitted. Each of die pads 361 and 362 and each of heat dissipation structures 365, 366 and 367 is made of the same material as wiring layer 320, for example.
  • the outer peripheral edge of the heat dissipation pad of each heat dissipation structure 365, 366, 367 is covered with a back surface insulating layer 380 covering the resin back surface 350r. In other words, the thermal pads are exposed from the back insulating layer 380 .
  • a third chip 310 is mounted on the first sealing portion 351 . More specifically, the third chip 310 is bonded to the first sealing portion 351 with a third bonding material AD3.
  • the third bonding material AD3 may be a conductive bonding material or an insulating bonding material. In this way, the third chip 310 is directly mounted on the first sealing portion 351 without being mounted on the die pad.
  • the second sealing portion 352 seals the chips 20A, 20B, 30A, 30B, and 310 in cooperation with the first sealing portion 351 .
  • the third sealing portion 353 is provided on the second sealing portion 352 .
  • the third sealing portion 353 forms a resin surface 350s.
  • a drain terminal 331 , a source terminal 332 , an output terminal 333 and a plurality of driver terminals 334 are formed on the third sealing portion 353 .
  • the wiring layer 320 is formed over the second sealing portion 352 and the third sealing portion 353 .
  • the second connection wiring 322 and the third connection wiring 323 (see both FIG. 20) in the wiring layer 320 are formed as follows. That is, the first via of the wiring layer 320 penetrates the portion of the second sealing portion 352 that covers the first chips 20A and 20B in the z direction.
  • the wiring of the wiring layer 320 is formed on the second sealing portion 352 .
  • the wiring is covered with the third sealing portion 353 .
  • the second via of the wiring layer 320 penetrates the third sealing portion 353 in the z direction.
  • the second connection wiring 322 and the third connection wiring 323 of the wiring layer 320 are formed by a plurality of vias penetrating in the z-direction through a portion of the second sealing portion 352 covering the first chips 20A and 20B, and the third sealing portion. It includes a plurality of vias passing through portion 353 in the z-direction.
  • the fourth connection wiring 324 and the fifth connection wiring 325 are formed as follows. That is, the first via of the wiring layer 320 penetrates the portion of the second sealing portion 352 that covers the first chips 20A and 20B in the z direction. The wiring of the wiring layer 320 is formed on the second sealing portion 352 . The wiring is covered with the third sealing portion 353 . The second via of the wiring layer 320 penetrates the portion of the second sealing portion 352 covering the third chip 310 in the z-direction.
  • circuit configuration of semiconductor unit A schematic circuit configuration of the semiconductor unit 400 will be described with reference to FIG. For convenience of explanation, the detailed circuit configuration of the driver circuit 311 is omitted.
  • the main transistor 21 of the first chip 20A is called “main transistor 21A”
  • the main transistor 21 of the first chip 20B is called “main transistor 21B”.
  • the active clamp circuit 40 of the first chip 20A is referred to as “active clamp circuit 40A”
  • the active clamp circuit 40 of the first chip 20B is referred to as "active clamp circuit 40B”.
  • the main transistor 21A and the active clamp circuit 40A are electrically connected, and the main transistor 21B and the active clamp circuit 40B are electrically connected.
  • the drain electrode 21D of the main transistor 21A is connected to the drain terminal 331, and the source electrode 21S of the main transistor 21B is connected to the source terminal 332.
  • a source electrode 21S of the main transistor 21A is connected to a drain electrode 21D of the main transistor 21B.
  • the output terminal 333 is connected to a node N between the source electrode 21S of the main transistor 21A and the drain electrode 21D of the main transistor 21B.
  • Each of the gate electrodes 21G of the main transistors 21A and 21B is connected to the driver circuit 311.
  • the driver circuit 311 is connected to a plurality of driver terminals 334 .
  • each of the source electrodes 21S of the main transistors 21A and 21B may be connected to the driver circuit 311.
  • FIG. 1
  • the driver circuit 311 when a control signal for driving the main transistors 21A and 21B is input to the driver terminal 334 from an external device, the driver circuit 311 receives the control signal input to the driver circuit 311 through the driver terminal 334. A drive signal for driving the main transistors 21A and 21B is generated according to the signal. The driver circuit 311 then outputs the drive signal to the gate electrodes 21G of the main transistors 21A and 21B.
  • the main transistors 21A and 21B are complementarily turned on and off based on the drive signal input to their gate electrodes 21G.
  • Semiconductor unit 400 includes first chips 20A, 20B, second chips 30A, 30B, and third chip 310, and first chips 20A, 20B, second chips 30A, 30B, and third chip 310. and a sealing resin 350 that seals the .
  • the main transistors 21 of the first chips 20A and 20B and the driver circuit 311 of the third chip 310 can be electrically connected within the semiconductor unit 400. Therefore, compared to the case where the main transistors 21 of the first chips 20A and 20B and the driver circuits 311 are electrically connected by a circuit board outside the semiconductor unit 400, the main transistors 21 of the first chips 20A and 20B and the drivers The conductive path to and from circuit 311 can be shortened. Therefore, parasitic impedance and parasitic inductance due to the length of the conductive path can be reduced.
  • the third chip 310 is arranged apart from the first chips 20A and 20B in a direction orthogonal to the arrangement direction of the first chips 20A and 20B in plan view. According to this configuration, compared to the case where the third chip 310 is arranged adjacent to one of the first chips 20A and 20B in the arrangement direction of the first chips 20A and 20B, the main Reducing variations in the length of the conductive path between the gate electrode 21G of the transistor 21 and the driver circuit 311 and the length of the conductive path between the gate electrode 21G of the main transistor 21 and the driver circuit 311 in the first chip 20B be able to.
  • the configurations of the drain pad PD1, source pad PS1 and gate pad PG1 of the main transistor 21 in the first embodiment are the same as those of the drain pad PD, source pad PS and gate pad PG of the main transistor 21 in the third and fourth embodiments. configuration can be changed. Similarly, the pad configuration of the main transistor 21 of the second embodiment may be changed to the pad configuration of the main transistor 21 of the third and fourth embodiments.
  • a part of the active clamp circuit 40 may be formed in the first chip 20 .
  • a clamping transistor 41 of an active clamping circuit 40 is formed in the first chip 20 .
  • a clamping capacitor 42 of an active clamping circuit 40 is formed in the first chip 20 .
  • the pull-down resistor 43 of the active clamp circuit 40 is formed in the first chip 20 .
  • a clamping transistor 41 and a clamping capacitor 42 are formed in the first chip 20 .
  • the first chip 20 is formed with a clamping transistor 41 and a pull-down resistor 43 .
  • the first chip 20 is formed with a clamping capacitor 42 and a pull-down resistor 43 .
  • the main drift layer is The constituent material can be changed arbitrarily.
  • the main drift layer may be formed as a drift layer made of a material containing Si.
  • the sub-drift layer is made of a material different from the material containing Si (for example, a material containing GaN).
  • the configuration of the pull-down resistor 43 can be arbitrarily changed.
  • the pull-down resistor 43 is configured as in the first modification shown in FIG. 25 or the second modification shown in FIG. can be changed.
  • the pull-down resistor 43 of the first modified example includes a bellows-shaped connection path 43A.
  • 43 A of connection paths are comprised by 2DEG26 in this embodiment.
  • the 2DEG 26 of the pull-down resistor 43 is formed in a bellows shape in plan view. Therefore, the connection path 43A includes a meandering portion formed in a bellows shape.
  • the pull-down resistor 43 includes a meandering resistance component.
  • the resistance component of the meandering portion is set according to the length and width of the meandering portion. Each of the length and width of the meandering portion is set according to the desired resistance value of pull-down resistor 43, for example.
  • the first terminal 43P and the second terminal 43Q of the pull-down resistor 43 form both ends of the bellows-shaped portion.
  • the first terminal 43P is electrically connected to the end of the connection path 43A near the clamping capacitor 42 .
  • the second terminal 43Q is electrically connected to the end of the connection path 43A closer to the clamping transistor 41 .
  • the first terminal 43P and the second terminal 43Q are electrically connected to each other via the connection path 43A.
  • the first terminal 43P and the second terminal 43Q are provided on the electron supply layer 25. As shown in FIG. More specifically, the first terminal 43P and the second terminal 43Q are formed on the electron supply layer 25 and are in ohmic contact with the electron supply layer 25 .
  • the pull-down resistor 43 of the second modified example is composed of a normally-on transistor and is configured to include the ON resistance of the normally-on transistor. More specifically, the pull-down resistor 43 includes an electron transit layer 24, an electron supply layer 25, and a passivation layer 28, like the main transistor 21 of each embodiment. On the other hand, the pull-down resistor 43 does not include the gate layer 27 unlike the main transistor 21 of each embodiment.
  • the pull-down resistor 43 electrically connects the first terminal 43P corresponding to the drain electrode, the second terminal 43Q corresponding to the source electrode, the third terminal 43S corresponding to the gate electrode, the first terminal 43P, and the second terminal 43Q. and a connection path (not shown) that physically connects.
  • the connection path is composed of the 2DEG 26 and formed in a bellows shape in plan view.
  • a third terminal 43 ⁇ /b>S is formed on the passivation layer 28 .
  • the third terminal 43S is arranged closer to the second terminal 43Q.
  • the pull-down resistor 43 includes a wiring 43C connecting the first terminal 43P and the third terminal 43S.
  • the wiring 43C can be made of any conductive material including at least one of Cu, Al, AlCu alloy, W, Ti, and TiN, for example.
  • the clamping capacitor 42 may be formed at a position overlapping the pad PG2 of the second chip 30 in plan view. In this case, the clamping capacitor 42 is positioned closer to the drift layer 45 than the pad PG2.
  • both the clamping capacitor 42 and the pull-down resistor 43 may be formed at positions overlapping the pads PG2 of the second chip 30 in plan view. In this case, both the clamping capacitor 42 and the pull-down resistor 43 are positioned closer to the drift layer 45 than the pad PG2.
  • both the clamping capacitor 42 and the pull-down resistor 43 may be formed at positions different from the pads PG2 of the second chip 30 in plan view.
  • the circuit configuration of the active clamp circuit 40 can be changed arbitrarily.
  • the active clamp circuit 40 may be modified as in the following first to third modified examples.
  • FIG. 27 shows the circuit configuration of the active clamp circuit 40 of the first modified example.
  • the active clamp circuit 40 further includes a protection diode 500 connected between the source electrode 41S and the gate electrode 41G of the clamp transistor 41.
  • a Zener diode for example, is used as the protection diode 500 .
  • An anode electrode 501 of the protection diode 500 is electrically connected to the source electrode 41S, and a cathode electrode 502 of the protection diode 500 is electrically connected to the gate electrode 41G.
  • the protective diode 500 is configured to prevent a voltage higher than the gate-source rated voltage from being applied to the gate electrode 41G of the clamping transistor 41 . Therefore, excessive increase in the gate-source voltage of the clamping transistor 41 is suppressed.
  • FIG. 28 shows a schematic cross-sectional structure of a protection diode 500 of a first modified example. As shown in FIG. 28, the protection diode 500 is formed, for example, in the second chip 30 at a position overlapping the pad PG2 in plan view.
  • the protection diode 500 includes an anode electrode 501 and a cathode electrode 502 , a drift layer 45 electrically connecting each of the anode electrode 501 and the cathode electrode 502 , and a well region 503 different in conductivity type from the drift layer 45 .
  • well region 503 is a p-type semiconductor region.
  • Anode electrode 501 is electrically connected to pad PG2 via via 504, for example.
  • Both the anode electrode 501 and cathode electrode 502 can be composed of any conductive material including, for example, Cu, Al, AlCu alloys, W, Ti, TiN.
  • the anode electrode 501 and the cathode electrode 502 are arranged apart from each other on the insulating film 49A. More specifically, two openings 49H and 49J that expose the drift layer 45 are formed separately from each other in the insulating film 49A.
  • the anode electrode 501 is formed so as to be embedded in the opening 49H and protrude from the periphery of the opening 49H.
  • the cathode electrode 502 is formed to be embedded in the opening 49J and protrude from the periphery of the opening 49J. Both the portion of the anode electrode 501 protruding from the opening 49H and the portion of the cathode electrode 502 protruding from the opening 49J are covered with the intermediate insulating film 49B.
  • a shunt resistor may be used instead of the protection diode 500.
  • the shunt resistor is configured to suppress application of a voltage higher than the gate-source rated voltage to the gate electrode 41G (see FIG. 27) of the clamping transistor 41. FIG. This configuration prevents the gate-source voltage of the clamping transistor 41 from becoming excessively large.
  • FIG. 29 shows the circuit configuration of the active clamp circuit 40 of the second modified example.
  • the active clamp circuit 40 further includes a capacitor 510 connected between the source electrode 41S and the gate electrode 41G of the clamp transistor 41.
  • Capacitor 510 includes a first electrode 511 and a second electrode 512 .
  • the first electrode 511 is electrically connected to the gate electrode 41 G of the clamping transistor 41 and the first terminal 43 P of the pull-down resistor 43 .
  • the second electrode 512 is electrically connected to the source electrode 41S of the clamping transistor 41 and the second terminal 43Q of the pull-down resistor 43.
  • FIG. 29 shows the circuit configuration of the active clamp circuit 40 of the second modified example.
  • the active clamp circuit 40 further includes a capacitor 510 connected between the source electrode 41S and the gate electrode 41G of the clamp transistor 41.
  • Capacitor 510 includes a first electrode 511 and a second electrode 512 .
  • the first electrode 511 is electrically connected to the gate electrode 41 G of the clamping transistor 41
  • the capacitor 510 is configured to suppress application of a voltage higher than the gate-source rated voltage to the gate electrode 41G of the clamping transistor 41 . Therefore, excessive increase in the gate-source voltage of the clamping transistor 41 is suppressed.
  • the capacitor 510 may be formed in the same manner as the clamping capacitor 42 .
  • the capacitor 510 may be provided, for example, in the second chip 30 at a position overlapping the gate pad PG1.
  • the capacitor 510 may be formed at a position different from that of the clamping transistor 41, the clamping capacitor 42, and the pull-down resistor 43 in plan view.
  • FIG. 30 shows the circuit configuration of the active clamp circuit 40 of the third modified example.
  • the active clamp circuit 40 further includes a protection transistor 520 for suppressing malfunction of the clamp transistor 41 .
  • Protection transistor 520 includes a drain electrode 521 , a source electrode 522 and a gate electrode 523 .
  • the protection transistor 520 is connected between the source electrode 41S and the gate electrode 41G of the clamp transistor 41.
  • the drain electrode 521 of the protection transistor 520 is connected to the gate electrode 41G of the clamp transistor 41
  • the source electrode 522 of the protection transistor 520 is connected to the source electrode 41S of the clamp transistor 41.
  • a gate electrode 523 of the protection transistor 520 is connected to the gate terminal 83 .
  • the protection transistor 520 is a normally-off transistor.
  • the protection transistor 520 When the main transistor 21 is on, the protection transistor 520 is on.
  • the protection transistor 520 connects the gate electrode 41G of the clamping transistor 41 and the source electrode 41S of the clamping transistor 41 . Therefore, the protection transistor 520 reliably turns off the clamp transistor 41 when the main transistor 21 is in the ON state. Accordingly, even if noise or the like is applied to the wiring to which the gate electrode 41G of the clamping transistor 41 is connected, it is possible to prevent the main transistor 21 from turning off at unintended timing.
  • the protective transistor 520 is turned off when the main transistor 21 is turned off. Therefore, the clamping transistor 41 becomes operable according to the drain-source voltage of the main transistor 21 . Thus, as described in the first embodiment, the clamping transistor 41 can suppress the gate-source voltage rise of the main transistor 21 .
  • At least one of the active clamp circuits 40 of the first modification and the second modification may include the protection transistor 520 of the third modification. As a result, it is possible to protect the clamping transistor 41 when the main transistor 21 is turned off and to suppress malfunction of the clamping transistor 41 when the main transistor 21 is turned on.
  • At least part of the active clamp circuit 40 may be formed in the third chip 310 . More specifically, part of the active clamp circuit 40 may be formed on the second chip 30 , and elements of the active clamp circuit 40 that are not formed on the second chip 30 may be formed on the third chip 310 .
  • all of the active clamp circuits 40A and 40B may be formed on the third chip 310.
  • the active clamp circuit 40 may be formed on the output side of the driver circuit 311 of the third chip 310, for example.
  • driver circuit 311 includes a push-pull circuit (not shown) configured to output a gate signal to the gate of main transistor 21 .
  • the active clamp circuit 40 is formed between the push-pull circuit and the output terminal (electrode pad 312 ) of the driver circuit 311 .
  • the second chip 30 may be omitted from the semiconductor unit 400 .
  • a semiconductor module 10 , 100 , 200 may include a plurality of first chips 20 .
  • the semiconductor modules 10 , 100 , 200 may have a plurality of second chips 30 .
  • the semiconductor modules 10 , 100 , 200 may comprise multiple first chips 20 and multiple second chips 30 .
  • semiconductor module 10, 100, 200 includes a plurality of first chips 20 and a plurality of second chips 30, for example, the number of first chips 20 and the number of second chips 30 are equal to each other.
  • the arrangement position of the second chip 30 with respect to the first chip 20 can be arbitrarily changed.
  • the second chip 30 may be spaced apart from the first chip 20 in the x-direction.
  • the second chip 30 is arranged at a position overlapping the first chip 20 when viewed in the x direction.
  • the first chip 20 and the second chip 30 are electrically connected to each other by a wiring layer formed of a metal plate or a plating layer.
  • the electrical connection structure is not limited to this.
  • the first chip 20 and the second chip 30 may be electrically connected to each other by wires.
  • the number of third chips 310 can be changed arbitrarily.
  • the number of third chips 310 may vary according to the number of first chips 20 .
  • the number of third chips 310 may be two.
  • the arrangement positions of the second chips 30A and 30B can be arbitrarily changed.
  • the second chips 30A and 30B may be arranged between the first chips 20A and 20B in the x direction.
  • the second chips 30A and 30B may be aligned in the x direction and spaced apart in the y direction.
  • the second chips 30A and 30B may be distributed on both sides of the third chip 310 in the x direction.
  • the third chip 310, the first chips 20A and 20B, and the second chips 30A and 30B are electrically connected to each other by wiring layers formed of plating layers.
  • the electrical connection structure between the first chips 20A, 20B and the second chips 30A, 30B is not limited to this.
  • third chip 310, first chips 20A and 20B, and second chips 30A and 30B may be electrically connected to each other by wires.
  • the number of second chips 30 can be arbitrarily changed.
  • the second chip 30 includes an active clamp circuit 40 electrically connected to the main transistor 21 of the first chip 20A and an active clamp circuit 40 electrically connected to the main transistor 21 of the first chip 20B. ,including. That is, the second chip 30 may include multiple active clamp circuits 40 .
  • the semiconductor unit may be configured to include any one of the semiconductor modules 10, 100, and 200 of the first to third embodiments and the third chip 310.
  • the third chip 310 is sealed with the sealing resins 60, 110 of the semiconductor modules 10, 100, 200.
  • a first member is formed on a second member means that in some embodiments the first member may be placed directly on the second member in contact with the second member, but in other implementations the first member may be disposed directly on the second member. It is contemplated that the configuration allows the first member to be positioned over the second member without contacting the second member. That is, the term “on” does not exclude structures in which another member is formed between the first member and the second member.
  • the z-direction used in the present disclosure does not necessarily have to be the vertical direction, nor does it have to match the vertical direction perfectly.
  • the various structures according to this disclosure are not limited to the z-direction "top” and “bottom” described herein being the vertical “top” and “bottom”.
  • the x-direction may be vertical, or the y-direction may be vertical.
  • references herein to "at least one of A and B” should be understood to mean “A only, or B only, or both A and B.”
  • Appendix Technical ideas that can be grasped from the above embodiment and modifications are described below. It should be noted that for the purpose of aid in understanding and not for the purpose of limitation, the corresponding reference numerals in the embodiments are shown in parentheses for the configurations described in the appendix. Reference numerals are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.
  • a first chip (20) comprising a main transistor (21) comprising a main drift layer (24); a second chip (30) including at least part of an active clamp circuit (40) including a sub-transistor (41) that operates based on the rise of the drain-source voltage of the main transistor (21); a connection member (50) electrically connecting the main transistor (21) and the active clamp circuit (40); a sealing resin (60) for sealing the first chip (20), the second chip (30), and the connection member (50); A semiconductor module (10) wherein the sub-transistor (41) includes a sub-drift layer (45) made of a material different from that of the main drift layer (24).
  • the main transistor (21) is a GaN transistor in which the main drift layer (24) is made of GaN
  • the main transistor (21) includes a drain electrode (21D), a source electrode (21S) and a gate electrode (21G), a drain terminal (81) electrically connected to the drain electrode (21D); a source terminal (82) electrically connected to the source electrode (21S); a gate terminal (83) electrically connected to the gate electrode (21G);
  • the semiconductor module according to appendix 1 or 2.
  • the sub-transistor (41) includes a drain electrode (41D), a source electrode (41S) and a gate electrode (41G); A source electrode (41S) of the sub-transistor (41) is connected to a source electrode (21S) of the main transistor (21), A drain electrode (41D) of the sub-transistor (41) is connected to a gate electrode (21G) of the main transistor (21),
  • the active clamp circuit (40) comprises: a pull-down resistor (43) connected between the source electrode (41S) and the gate electrode (41G) of the sub-transistor (41); a clamping capacitor (42) connected between the drain electrode (21D) of the main transistor (21) and the gate electrode (41G) of the sub-transistor (41); 4.
  • the semiconductor module according to any one of Appendices 1 to 3.
  • the first chip (20) does not include the active clamp circuit (40) but includes the main transistor (21);
  • the first chip (20) is a drain pad (PD1) electrically connected to the drain electrode (21D) of the main transistor (21); a source pad (PS1) electrically connected to the source electrode (21S) of the main transistor (21); When viewed from the thickness direction (z direction) of the main drift layer (24), the drain pad (PD1) and the source pad (PS1) are arranged apart from each other in the first direction, When viewed from the thickness direction (z direction) of the main drift layer (24), the first chip (20) and the second chip (30) are separated from each other in a second direction perpendicular to the first direction. 7.
  • the semiconductor module according to any one of Appendices 4 to 6, wherein the semiconductor modules are arranged in parallel.
  • the second chip (30) has a semiconductor substrate (44) supporting the sub-drift layer (45), A source region (48) electrically connected to a source electrode (41S) of the sub-transistor (41) is formed on the surface of the sub-drift layer (45), A drain electrode (41D) of the sub-transistor (41) is formed on the back surface of the semiconductor substrate (44) opposite to the sub-drift layer (45).
  • the semiconductor module according to .
  • a drain region (46B) electrically connected to the drain electrode (41D) of the sub-transistor (41) and a source electrode (41S) of the sub-transistor (41) are formed on the surface of the sub-drift layer (45).
  • a source region (48) electrically connected to is formed apart from each other.
  • the second chip (30) includes a pad (PG2) connected to the gate electrode (41G) of the sub-transistor (41) through the pull-down resistor (43), At least one of the pull-down resistor (43) and the clamping capacitor (42) is positioned to overlap the pad (PG2) when viewed from the thickness direction (z direction) of the sub-drift layer (45).
  • the semiconductor module according to any one of appendices 4 to 9, wherein the semiconductor module is formed at a position closer to the sub-drift layer (45) than the pad (PG2).
  • connection member (50) is a first connecting member (51) electrically connecting the source electrode (41S) and the gate electrode (41G) of the sub-transistor (41) and the source electrode (21S) of the main transistor (21); a second connection member (52) electrically connecting the clamping capacitor (42) and the drain electrode (21D) of the main transistor (21); a third connecting member (53) connecting the gate electrode (21G) of the main transistor (21) and the drain electrode (41D) of the sub-transistor (41);
  • the semiconductor module according to any one of Appendices 4 to 9.
  • each of said first connection member (51), said second connection member (52), and said third connection member (53) is formed of a metal plate.
  • the second chip (30) has a capacitor pad (PCA) electrically connected to the clamping capacitor (42), 14.
  • PCA capacitor pad
  • a plurality of the first chips (20A, 20B) are provided and arranged apart from each other, When viewed from the thickness direction (z direction) of the sealing resin (350), the second chips (30A, 30B) are arranged in a direction orthogonal to the arrangement direction of the plurality of first chips (20A, 20B). 15.
  • Appendix 16 16. The semiconductor module according to appendix 15, wherein a plurality of second chips (30A, 30B) are provided and are arranged apart from each other in the arrangement direction of the plurality of first chips (20A, 20B).
  • a third chip is provided separately from the first chip (20) and the second chip (30) in the sealing resin (350) and includes a driver circuit (311) for driving the main transistor (21). a chip (310); control connection members (324, 325) electrically connecting the third chip (310) to the first chip (20) and the second chip (30);
  • a semiconductor unit (400) comprising:
  • Both the main transistor (21) and the sub-transistor (41) have drain electrodes (21D, 41D), source electrodes (21S, 41S) and gate electrodes (21G, 41G),
  • the control connection members (324, 325) electrically connect the driver circuit (311), the drain electrode (41D) of the sub-transistor (41), and the gate electrode (21G) of the main transistor (21).
  • (Appendix 21) a gate electrode (523) connected between the source electrode (41S) and the gate electrode (41G) of the sub-transistor (41) and electrically connected to the gate electrode (21G) of the main transistor (21); 22.
  • the second chip (30) includes a semiconductor substrate (44),
  • the clamping capacitor (42) is a first electrode (42P) and a second electrode (42Q) provided on the semiconductor substrate (44) and separated from each other; a dielectric layer (49A) provided on the semiconductor substrate (44) and interposed between the first electrode (42P) and the second electrode (42Q); 15.
  • the semiconductor module according to any one of Appendices 4 to 14.
  • connection path (43A) electrically connecting the drain electrode (41D) of the sub-transistor (41) and the source electrode (41S) of the sub-transistor (41);
  • the connection path (43A) includes a meandering portion, 15.
  • the second chip (30) includes a semiconductor substrate (44),
  • the pull-down resistor (43) is a first terminal (43P); a second terminal (43Q); a plate-like resistor portion (43R) formed on the semiconductor substrate (44) and having a resistance value higher than that of the first terminal (43P) and the second terminal (43Q); including Both the first terminal (43P) and the second terminal (43Q) are provided on the resistor section (43R) and are electrically connected to the resistor section (43R) Any one of Appendices 4 to 14 1.
  • the semiconductor module according to claim 1.
  • the sub-transistor (41) is configured to turn on before the main transistor (21) with respect to the rise of the drain-source voltage of the main transistor (21). 25.
  • the semiconductor module according to any one of 1 to 24.
  • Chip back surface 40, 40A, 40B Active clamp circuit 41... Clamp Transistor 41D... Drain electrode 41S... Source electrode 41G... Gate electrode 41T... Active region 42... Clamping capacitor 42P... First electrode 42Q... Second electrode 42V... Via 43... Pull-down resistor 43A... Connection path 43C... Wiring 43P...
  • Second connecting member 53 Third connecting member 60
  • Sealing resin 61 Resin surface 62 Resin Rear surface 63 First resin side surface 64 Second resin side surface 65 Third resin side surface 66 Fourth resin side surface 71 First die pad 72 Second die pad 81 Drain terminal 82 Source terminal 83

Landscapes

  • Junction Field-Effect Transistors (AREA)
PCT/JP2022/047073 2022-01-28 2022-12-21 半導体モジュールおよび半導体ユニット Ceased WO2023145317A1 (ja)

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JP2011204877A (ja) * 2010-03-25 2011-10-13 Panasonic Corp 電界効果トランジスタ及びその評価方法
WO2014034895A1 (ja) * 2012-08-30 2014-03-06 富士電機株式会社 イグナイタ、イグナイタの制御方法および内燃機関用点火装置
JP2016051886A (ja) * 2009-05-28 2016-04-11 インターナショナル・レクティファイアー・コーポレーションＩｎｔｅｒｎａｔｉｏｎａｌ Ｒｅｃｔｉｆｉｅｒ Ｃｏｒｐｏｒａｔｉｏｎ モノリシック集積ｉｉｉ−ｖ族及びｉｖ族複合半導体デバイス及び集積回路
US20170179935A1 (en) * 2015-12-18 2017-06-22 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and circuit protecting method
JP2020188177A (ja) * 2019-05-16 2020-11-19 ローム株式会社 半導体装置

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JPH11289045A (ja) * 1998-04-03 1999-10-19 Toyota Autom Loom Works Ltd 電圧駆動型半導体素子の保護回路、および過電圧保護機能を備えた電圧駆動型半導体回路
JP2016051886A (ja) * 2009-05-28 2016-04-11 インターナショナル・レクティファイアー・コーポレーションＩｎｔｅｒｎａｔｉｏｎａｌ Ｒｅｃｔｉｆｉｅｒ Ｃｏｒｐｏｒａｔｉｏｎ モノリシック集積ｉｉｉ−ｖ族及びｉｖ族複合半導体デバイス及び集積回路
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WO2014034895A1 (ja) * 2012-08-30 2014-03-06 富士電機株式会社 イグナイタ、イグナイタの制御方法および内燃機関用点火装置
US20170179935A1 (en) * 2015-12-18 2017-06-22 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and circuit protecting method
JP2020188177A (ja) * 2019-05-16 2020-11-19 ローム株式会社 半導体装置

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US20240387513A1 (en) 2024-11-21

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