WO2023142697A1 - 阵列基板和显示面板 - Google Patents

阵列基板和显示面板 Download PDF

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Publication number
WO2023142697A1
WO2023142697A1 PCT/CN2022/137259 CN2022137259W WO2023142697A1 WO 2023142697 A1 WO2023142697 A1 WO 2023142697A1 CN 2022137259 W CN2022137259 W CN 2022137259W WO 2023142697 A1 WO2023142697 A1 WO 2023142697A1
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WIPO (PCT)
Prior art keywords
layer
area
wiring
metal wiring
array substrate
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PCT/CN2022/137259
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English (en)
French (fr)
Inventor
陈国朵
李荣荣
Original Assignee
绵阳惠科光电科技有限公司
惠科股份有限公司
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Publication of WO2023142697A1 publication Critical patent/WO2023142697A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13458—Terminal pads

Definitions

  • the present application relates to the field of display technology, in particular to an array substrate and a display panel having the array substrate.
  • Thin Film Transistor-Liquid Crystal Display has many advantages such as thin body, power saving, and no radiation, so it is widely used in LCD TVs, mobile phones, personal digital assistants (Personal Digital Assistant, Electronic devices such as PDAs), digital cameras, computer screens, projectors or laptop screens play a dominant role in the display field. Therefore, in the current rapidly developing liquid crystal display technology, thin film transistor liquid crystal displays are widely favored by people.
  • TFT-LCD usually includes a display panel and a backlight module.
  • the display panel is generally provided with a display area and a binding area and a fanout (Fanout) area arranged around the display area, wherein the fanout area is connected to the display area.
  • Fanout Fanout
  • the bonding area to realize the transmission of data signals.
  • COA CF on Array
  • the purpose of the present application is to provide an array substrate and a display panel having the array substrate.
  • the line width of the first trace in the linear area of the array substrate is partially widened to be equal to that of the bonding lead in the bonding area, or the line width of the first trace in the linear area of the array substrate is partially widened to be greater than that of the oblique line area
  • the line width is smaller than the line width of the bonding lead, so that the line width of the straight line area of the binding area and the fan-out area transitions smoothly, so as to avoid the infiltration of water vapor due to the large change of the line width at the junction of the straight line area and the binding area The problem.
  • the present application provides an array substrate, the array substrate includes a binding area and a fan-out area connected to the binding area, the fan-out area includes a straight line area and a diagonal line area, and the straight line
  • the area is connected between the oblique line area and the binding area
  • the binding area includes a plurality of bonding leads
  • the straight line area includes a plurality of first routing lines
  • the oblique line area includes a plurality of second wires
  • Two wirings the first wiring is electrically connected to the binding lead, the second wiring is electrically connected to the first wiring, and the first wiring adjacent to the binding area in the straight line area
  • the line width of a trace within the first preset length is equal to the line width of the bonding lead; or, the line of the first trace adjacent to the bonding area in the straight line area within the second preset length
  • the width is not less than the line width of the second wiring and does not exceed the line width of a plurality of bonding leads, and the first wiring adjacent to the bonding area in
  • the present application provides a display panel, which includes the above-mentioned array substrate, a color filter substrate, and a liquid crystal layer located between the array substrate and the color filter substrate.
  • the line width of the straight line area is equal to the line width of the bonding wire within a section of a preset length on the side of the straight line area close to the binding area; or the straight line
  • the line width of the side adjacent to the binding area in the second preset length changes regularly and is not less than the line width of the oblique line area and does not exceed the line width of the binding lead, and the side adjacent to the binding area is larger than the line width away from One side of the binding area realizes a smooth transition of the line width from the binding area to the oblique line area, improves the line yield of the array substrate, effectively improves the usability of the array substrate, and improves the display effect and quality of the display panel.
  • the application widens the line width of the straight line area to be equal to the line width of the binding lead or wider than the predetermined design line width,
  • the resistance of the first wiring in the straight line area is effectively reduced, thereby effectively improving the signal driving and transmission of the array substrate, improving the performance of the array substrate, and effectively improving the use effect of the display panel.
  • FIG. 1 is a schematic diagram of an overall structure of an array substrate disclosed in an embodiment of the present application.
  • Fig. 2 is a schematic cross-sectional structure diagram of the bonding area and the fan-out area of the array substrate disclosed in the embodiment of the present application;
  • FIG. 3 is a schematic partial cross-sectional view of the binding area and the linear area of the array substrate disclosed in the first embodiment of the present application;
  • FIG. 4 is a schematic partial cross-sectional view of the binding area and the linear area of the array substrate disclosed in the second embodiment of the present application;
  • FIG. 5 is a schematic partial cross-sectional view of a fan-out area of an array substrate disclosed in an embodiment of the present application
  • FIG. 6 is a schematic diagram of the layer structure of the array substrate disclosed in the first embodiment of the present application along the direction from II to III in FIG. 2;
  • FIG. 7 is a schematic diagram of the layer structure of the array substrate disclosed in the second embodiment of the present application along the direction from II to III in FIG. 2;
  • FIG. 8 is a schematic diagram of the layer structure of the array substrate disclosed in the third embodiment of the present application along the direction from II to III in FIG. 2 .
  • connection and “connection” mentioned in this application all include direct and indirect connection (connection) unless otherwise specified.
  • connection should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection.
  • Ground connection, or integral connection can be mechanical connection; can be directly connected, can also be indirectly connected through an intermediary, and can be internal communication between two components.
  • first and second in the specification and claims of the present application and the drawings are used to distinguish different objects, rather than to describe a specific order.
  • the embodiment of the present application provides an array substrate 100, please refer to FIG. 1, FIG. 2, FIG. 3, FIG. 4 and FIG. It is a schematic cross-sectional structure diagram of the binding area and the fan-out area of the array substrate disclosed in the embodiment of the present application.
  • FIG. 3 is a partial cross-sectional schematic diagram of the binding area and the linear area of the array substrate disclosed in the first embodiment of the application.
  • FIG. 4 is A schematic partial cross-sectional view of the bonding area and the linear area of the array substrate disclosed in the second embodiment of the present application, and
  • FIG. 5 is a schematic partial cross-sectional view of the fan-out area of the array substrate disclosed in the embodiment of the present application.
  • the bonding area 20 is electrically connected with the fan-out area 30, as shown in Figure 3 and Figure 5, the bonding area 20 includes a plurality of bonding leads (Bonding lead) 568, and the fan-out area 30 includes a straight line a region 32 and a slash region 34, wherein the slash region 34 is adjacent to one side of the straight region 32, and the opposite side of the straight region 32 is adjacent to the binding region 20, That is, the straight line region 32 is connected between the oblique line region 34 and the binding region 20 .
  • the straight line area 32 includes a plurality of first wires 322, the oblique area 34 includes a plurality of second wires 342, the first wires 322 adjacent to the bonding area 20 in the straight line area 32
  • the line width within the first preset length is equal to the line width of the binding lead 568;
  • the line width of the first wiring 322 adjacent to the binding area 20 in the straight line area 32 within the second preset length is not less than the line width of the second wiring 342 and does not exceed a plurality of the The line width of the bonding wire 568, and at the same time, the first wiring 322 adjacent to the bonding area 20 side in the straight line area 32 is close to the bonding area 20 side within the second preset length
  • the width is greater than the line width on the side away from the binding area 20, that is, the straight line area 32 is connected between the oblique line area 34 and the binding area 20, then the line in the straight line area 32
  • One end of the first wiring 322 is close to the binding area 20, and the opposite end of the first wiring 322 is far away from the binding area 20, then the first wiring 322 adjacent to the binding area 20 is at the
  • the line width close to the binding area 20 within two preset lengths is greater than the line width away from the binding area 20, thereby realizing that the line width of the binding lead 568 of the binding area 20 is equal to
  • the line widths of the multiple first traces 322 on the side of the straight line area 32 adjacent to the binding area 20 within the second preset length may be in a gradual form, that is, the straight line
  • the line widths of the plurality of first traces on the side adjacent to the binding area within the second preset length gradually decrease along the direction from close to the binding area to away from the binding area, for example,
  • the line width variation of the plurality of first traces 322 on the side of the straight line area 32 adjacent to the binding area 20 within the second preset length presents a smooth curve or a plurality of uniformly reduced broken line segments (that is, in the The axial section of the first wire 322 within the preset length may change regularly such as multiple superimposed isosceles trapezoids or trapezoids).
  • the bonding area 20 is adjacent to the fan-out area 30, and the two are electrically connected, and the multiple bonding wires 568 of the bonding area 20 can be connected to each other. parallel and spaced apart.
  • the straight line area 32 is adjacent to the binding area 20, and the two are electrically connected, and the plurality of first traces 322 in the straight line area 32 can be arranged in parallel and at intervals, and the first A trace 322 is electrically connected to a corresponding bond wire 568 .
  • the oblique line area 34 is adjacent to the straight line area 32 and electrically connected between them.
  • the plurality of second traces 342 in the oblique line area 34 can be arranged in parallel and at intervals, and the The second wires 342 are electrically connected to the corresponding first wires 322 . That is, the first wire 322 is connected between the bonding wire 568 and the second wire 342 .
  • the binding area 20 is electrically connected to the fan-out area 30, the binding area 20 includes a bonding wire 568, the fan-out area 30 includes a straight line area 32 and a diagonal line area 34, the The line width of the straight line area 32 is equal to the line width of the binding lead 568 within a section of a preset length on the side of the straight line area 32 close to the binding area 20; or, the line area 32 is adjacent to the The line width of the plurality of first traces 322 on one side of the bonding area 20 within the second preset length is not less than the line width of the plurality of second traces 342 and is not greater than the plurality of bonding leads 568 At the same time, the line width of the plurality of first traces 322 on the side adjacent to the binding area 20 of the straight line area 32 is larger than that on the side of the binding area 20 in the second preset length.
  • the line width on one side of the bonding area 20 realizes a smooth transition from the line width of the bonding lead 568 of the bonding area 20 to the line width of the first wiring 322 of the straight line area 32, thereby avoiding
  • the problem of infiltration improves the yield rate of the lines of the array substrate and effectively improves the performance of the array substrate 100 .
  • the array substrate 100 also includes a connection area 10, an active display area (Active area, AA) and a peripheral functional area, the connection area 10 is located in the active display area, and the binding area 20
  • the fan-out area 30 is located in the peripheral functional area, and the fan-out area 30 is disposed adjacent to the effective display area and is electrically connected to the connection area 10 .
  • the connection area 10 can receive electrical signals from the fan-out area 30
  • the bonding area 20 is disposed adjacent to the fan-out area 30 and can send electrical signals to the fan-out area 30 .
  • the fan-out area 30 further includes a data signal line (not shown) connected to the effective display area, and the effective display area is a part mainly displaying images.
  • a driving integrated circuit Integrated Circuit, IC
  • a plurality of wires can be arranged in the fan-out area 30 and distributed in a fan shape to connect the wires in the effective display area and the driving circuits in the peripheral functional area.
  • the surface indicated by the first boundary line s in FIG. 2 is the junction of the bonding area 20 and the fan-out area 30 .
  • one side of the first boundary s in FIG. 2 (the upper side of the first boundary s shown in FIG. 2 ) is the fan-out area 30 of the array substrate 100
  • the other side of the first boundary s (the upper side of the first boundary s shown in FIG.
  • the wire used to connect the bonding area 20 and the fan-out area 30 usually has a large line width transition at the junction position, and reverse chamfers or undercuts are prone to occur during the manufacturing process. Water vapor infiltrates and leads to poor line formation, thereby affecting the yield rate of line connections, and further affecting the reliability of signal transmission on the array substrate 100 .
  • FIGS. 6 to 8 Please refer to FIGS. 6 to 8 together.
  • the surface shown by the second boundary line m in FIGS. 6 to 8 is the junction of the binding area 20 and the fan-out area 30.
  • the left part of the second boundary m in FIG. 8 is the bonding region 20 of the array substrate 100
  • the right part of the second boundary m in FIGS. 6 to 8 is the fan-out region 30 of the array substrate 100 . It can be seen from FIG. 2 that the first boundary s is coplanar with the second boundary m.
  • FIG. 6 is a schematic diagram of the layer structure of the array substrate disclosed in the first embodiment of the present application along the direction from II to III in FIG. 2 .
  • the array substrate 100 may include an organic layer 52, a protective layer 53, an insulating layer (Gate Insulator, GI) 54, a metal wiring layer 56, and a base substrate sequentially stacked from top to bottom.
  • the base substrate 58 is located at the lowest layer of the array substrate 100 .
  • the base substrate 58 is located at the lowest layer of the layer structure of the array substrate 100, and is used to support other structural layers of the array substrate 100 located thereon;
  • the metal wiring layer 56 is disposed on the base substrate 58, the metal wiring layer 56 includes the bonding wire 568, the first wiring 322 and the second wiring 342, the The first wiring 322 is connected between the bonding wire 568 and the second wiring 342;
  • the insulating layer 54 is located on the metal wiring layer 56, and the insulating layer 54 may be made of inorganic materials such as silicon nitride and silicon oxide;
  • the protective layer 53 is located on the insulating layer 54, and is used to protect the array substrate 100 inside itself from damage;
  • the organic layer 52 is located on the protective layer 53, and the organic layer 52 may be made of soluble polytetrafluoroethylene (Polyfluoroalkoxy, Teflon PFA, PFA).
  • the metal wiring layer 56 includes a first wiring part 561, a second wiring part 563 and a third wiring part 565, and the first wiring part 561, the second wiring part 563 and the third wiring part 565 are sequentially connected, wherein, the area of the metal wiring layer 56 corresponding to the second wiring part 563 includes the bonding wire 568, and the metal wiring layer 56 corresponds to the first The area of the three-trace portion 565 includes the first trace 322 .
  • the array substrate 100 is provided with at least one via hole 567, and the via hole 567 sequentially passes through the organic layer 52, the protection layer 53 and the insulating layer 54 to expose the second trace of the metal wiring layer 56. Line portion 563.
  • the via hole 567 sequentially penetrates through the organic layer 52 , the protective layer 53 and the insulating layer 54 until the second wiring portion 563 of the metal wiring layer 56 , that is, the via hole 567 A groove structure with the second wiring portion 563 of the metal wiring layer 56 as a bottom wall is formed in the array substrate 100 .
  • the array substrate 100 further includes a conductive film 51, the conductive film 51 can be made of indium tin oxide (Indium Tin Oxide, ITO), the conductive film 51 covers the corresponding via hole 567
  • ITO Indium Tin Oxide
  • the second wiring portion 563 of the metal wiring layer 56 at the bottom and the sidewall of the via hole 567, the conductive film 51 also covers the surface area of the organic layer 52 facing away from the protective layer 53 , that is, the conductive film 51 serves as the upper surface of the array substrate 100 .
  • the via hole 567 sequentially penetrates through the organic layer 52, the protective layer 53 and the insulating layer 54 and exposes the second wiring portion 563, and the conductive film 51 covers the second wiring portion 563 , so the conductive film 51 is connected to the second wiring portion 563 of the metal wiring layer 56 in the via hole 567 .
  • the binding wire 568 is used to realize the electrical connection between the second wiring part 563 of the metal wiring layer 56 and the conductive film 51, that is, the conductive film 51
  • the via hole 567 is connected to the second wiring portion 563 of the metal wiring layer 56 through the bonding wire 568 .
  • FIG. 7 is a schematic diagram of the layer structure of an array substrate disclosed in the second embodiment of the present application along the direction from II to III in FIG. 2 .
  • the array substrate 200 may include an organic layer 52, a protective layer 53, a metal wiring layer 57, an insulating layer 54, and a substrate substrate 58 that are sequentially stacked from top to bottom.
  • the substrate 58 is located at the lowest layer of the layer structure of the array substrate 100 .
  • the base substrate 58 is located on the lowermost layer of the array substrate 100, and is used to support other structural layers of the array substrate 100 located thereon;
  • the insulating layer 54 is located on the base substrate 58, and the insulating layer 54 may be made of inorganic materials such as silicon nitride and silicon oxide;
  • the metal wiring layer 57 is disposed on the insulating layer 54, the metal wiring layer 57 includes the bonding wire 568, the first wiring 322 and the second wiring 342, the first wiring A trace 322 is connected between the binding lead 568 and the second trace 342;
  • the protection layer 53 is located on the metal wiring layer 57 and is used to protect the array substrate including itself from damage;
  • the organic layer 52 is located on the protection layer 53 , and the organic layer 52 may be made of soluble polytetrafluoroethylene.
  • the metal wiring layer 57 includes a first wiring part 571, a second wiring part 573 and a third wiring part 575, and the first wiring part 571, the second wiring part 573 and the third wiring part 575 are connected sequentially, wherein, the area of the metal wiring layer 57 corresponding to the second wiring part 573 includes the bonding wire 568, and the metal wiring layer 57 corresponds to the third wiring
  • the area of the line portion 575 includes the first trace 322 .
  • the array substrate 200 is provided with at least one via hole 577 , and the via hole 577 sequentially passes through the organic layer 52 and the protection layer 53 to expose the second wiring portion 573 of the metal wiring layer 57 .
  • the via hole 577 sequentially penetrates through the organic layer 52 and the protective layer 53 until the second wiring portion 573 of the metal wiring layer 57 , that is, the via hole 577 is formed in the array substrate 100 A groove structure with a part of the second wiring portion 573 of the metal wiring layer 57 as the bottom wall is formed.
  • the array substrate 200 further includes a conductive film 51, the conductive film 51 may be made of indium tin oxide, and the conductive film 51 covers the metal wiring corresponding to the bottom of the via hole 577
  • the second wiring portion 573 of the layer 57 and the sidewall of the via hole 577, the conductive film 51 also covers the surface area of the organic layer 52 facing away from the protective layer 53, that is, the The conductive film 51 serves as the upper surface of the array substrate 200 .
  • the via hole 577 sequentially penetrates the organic layer 52 and the protective layer 53 and exposes the second wiring part 573, and the conductive film 51 covers the second wiring part 573, the conductive The film 51 is connected to the second trace part 573 of the metal trace layer 57 in the via hole 577 .
  • the bonding wire 568 is used to connect the second wiring part 573 of the metal wiring layer 57 to the conductive film 51, that is, the conductive film 51 is connected to the via hole. 577 is connected to the second wiring portion 573 of the metal wiring layer 57 through the bonding wire 568 .
  • FIG. 8 is a schematic diagram of the layer structure of the binding region and the linear region of the third embodiment of the array substrate disclosed in the present application.
  • the array substrate 300 may include an organic layer 52, a protective layer 53, a second metal wiring layer 57a, an insulating layer 54, a first metal wiring layer 56a, and a base substrate 58.
  • the base substrate 58 is located at the lowest layer of the array substrate 100 .
  • the first metal wiring layer 56a may have the same material as the metal wiring layer 56 in the array substrate 100 in the above-mentioned first embodiment, and the second metal wiring layer The wiring layer 57 a may be made of the same material as the metal wiring layer 57 in the array substrate 200 in the second embodiment, which is not specifically limited in the present application.
  • the base substrate 58 is located on the lowermost layer of the array substrate 100, and is used to support other structural layers of the array substrate 100 located thereon;
  • the first metal wiring layer 56a is located on the base substrate 58 and corresponds to the bonding area 20, that is, the orthographic projection of the first metal wiring layer 56a on the base substrate 58 It is equal to the length of the bonding area 20 (that is, it is located on the left side of the first boundary line m of the array substrate 100), and one end of the first metal wiring layer 56a and the base substrate 58 are located on the One end of the bonding area 20 is aligned, and the first metal wiring layer 56 a includes a part of the bonding wire 568 .
  • the insulating layer 54 is disposed on the first metal wiring layer 56 a and the base substrate 58 , and the insulating layer 54 may be made of inorganic materials such as silicon nitride and silicon oxide. Specifically, the insulating layer 54 may be in an "L" shape as a whole, and the insulating layer 54 may include a connected first insulating portion 541 and a second insulating portion 543, and the first insulating portion 541 is located on the first insulating portion 543.
  • the second insulating portion 543 is located on the base substrate 58 corresponding to the fan-out area 30 , and the upper surface of the second insulating portion 543 is flush with the upper surface of the first insulating portion 541 . That is, the first insulating portion 541 of the insulating layer 54 is disposed on the first metal wiring layer 56a and corresponds to the binding region 20, and the second insulating portion 543 is disposed on the base substrate 58 corresponds to the fan-out area 30.
  • the thickness of the first insulating portion 541 is smaller than the thickness of the second insulating portion 543 .
  • the second metal wiring layer 57a is disposed on the insulating layer 54; that is, the first insulating portion 541 corresponds to the binding area 20, and is located between the first metal wiring layer 56a and the insulating layer 54. Between the second metal wiring layer 57a, the second insulating portion 543 corresponds to the fan-out region 30, and is located between the base substrate 58 and the second metal wiring layer 57a, the first The second metal wiring layer 57a includes another part of the binding wire 568, the first wiring 322 and the second wiring 342, that is, the binding wiring 568 respectively belongs to the first metal wiring layer 56a and the second metal wiring layer 57a, that is, a part of the binding wire 568 belongs to the first metal wiring layer 56a, and another part of the binding wiring 568 belongs to the second metal wiring layer 57a.
  • the protection layer 53 is located on the second metal wiring layer 57a, and is used to protect the array substrate including itself from damage;
  • the organic layer 52 is located on the protection layer 53 , and the organic layer 52 may be made of soluble polytetrafluoroethylene.
  • the second metal wiring layer 57a includes a first wiring part 571, a second wiring part 573 and a third wiring part 575, the first wiring part 571, the second wiring part 573 and the third wiring part 575 are sequentially connected, the area of the second metal wiring layer 57a corresponding to the second wiring part 573 includes the bonding wire 568, and the second metal wiring layer 57a corresponds to the The area of the third routing portion 575 includes the first routing 322 .
  • the array substrate 300 is provided with at least one first via hole 572, and the first via hole 572 sequentially penetrates through the organic layer 52, the protective layer 53, the second metal wiring layer 57a, the insulating layer 54 to expose the first metal wiring layer 56a.
  • the first via hole 572 sequentially penetrates through the organic layer 52, the protective layer 53, the second metal wiring layer 57a, the first insulating portion 541 of the insulating layer 54 until the first A metal wiring layer 56a, that is, the first via hole 572 forms a groove in the array substrate 300 with the area of the first metal wiring layer 56a corresponding to the first via hole 572 as the bottom wall structure.
  • the array substrate 300 is provided with at least one second via hole 574, and the second via hole 574 sequentially passes through the organic layer 52 and the protective layer 53 to expose the second trace of the second metal trace layer 57a.
  • Line part 573 That is, the second via hole 574 sequentially penetrates through the organic layer 52 and the protective layer 53 until the second wiring portion 573 of the second metal wiring layer 57a, that is, the second via hole 574
  • a groove structure is formed in the array substrate 300 with the area of the second wiring portion 573 of the second metal wiring layer 57a corresponding to the second via hole 574 as the bottom wall.
  • the array substrate 300 further includes a conductive film 51
  • the conductive film 51 may be made of indium tin oxide (Indium Tin Oxide, ITO), and the conductive film 51 covers the The first metal wiring layer 56a at the bottom of the hole 572 and the sidewall of the first via hole 572 and the second metal wiring layer 57a corresponding to the bottom of the second via hole 574 and the second via hole 574
  • the conductive film 51 also covers the surface area on the side of the organic layer 52 facing away from the protective layer 53 and on the sides surrounding the first via hole 572 and the second via hole 574, and also That is, the conductive film 51 serves as the upper surface of the array substrate 200 .
  • the second via hole 574 sequentially penetrates through the organic layer 52 and the protective layer 53 until the second line portion 573 of the second metal line layer 57a, while the conductive film 51 covers the The surface area of the first metal wiring layer 56a corresponding to the first via hole 572 and the surface area of the second wiring part 573 corresponding to the second via hole 574, the conductive film 51 in the first
  • the via hole 572 is connected to the first metal wiring layer 56a
  • the conductive film 51 is connected to the first metal wiring layer 57a in the first via hole 572 and the second via hole 574.
  • the two trace parts 573 are connected.
  • the binding wire 568 is used to realize the connection between the first metal wiring layer 56a, the second wiring part 573 of the second metal wiring layer 57a and the conductive film 51.
  • the conductive film 51 is connected to the first metal wiring layer 56a through the bonding wire 568 in the first via hole 572, and the conductive film 51 is connected to the first metal wiring layer 56a in the first via hole 572.
  • a via hole 572 and the second via hole 574 are connected to the second wiring portion 573 of the second metal wiring layer 57a through the bonding wire 568 .
  • FIG. 3 is a schematic partial cross-sectional view of the binding region and the linear region of the array substrate disclosed in the first embodiment of the present application
  • Fig. 4 is a schematic diagram of the array substrate disclosed in the second embodiment of the present application
  • FIG. 5 is a partial cross-sectional schematic view of the fan-out area of the array substrate disclosed in the embodiment of the present application.
  • the distance between the first straight line a and the second straight line b is the length of a plurality of binding leads 568
  • the first straight line a is the distance between the binding area 20 and the second straight line b.
  • the junction position of the straight line area 32 that is, one side of the first straight line a is the straight line area 32 (the upper side of the first straight line a in FIG. 3 or FIG. 4 is the straight line area 32)
  • the other side of the first straight line a is the binding region 20 (the lower side of the first straight line a in FIG. 3 or FIG. 4 is the binding region 20 ).
  • the fan-out area 30 includes the adjacent straight line area 32 and oblique line area 34 , and the straight line area 32 is adjacent to the binding area 20 , and the two are electrically connected, and the plurality of first wires 322 in the straight line region 32 are electrically connected to the corresponding bonding wires 568 .
  • the oblique line area 34 is adjacent to the straight line area 32 and is electrically connected therebetween.
  • the plurality of second wires 342 in the oblique area 34 are electrically connected to the corresponding first wires 322 .
  • the line width of the side of the straight line area 32 adjacent to the binding area 20 within the first preset length is equal to the line width of the binding lead 568, wherein
  • the first preset length means that the predetermined design line width of the side of the first wiring 322 adjacent to the binding area 20 within the first preset length is larger than the second wiring of the oblique line area 34
  • W refers to the line width of the second wires 342 in the oblique area 34
  • S refers to the distance between two adjacent second wires 342 in the oblique area 34 .
  • the predetermined design line width refers to the line width of the first line selected and used by the array substrate before the line optimization is performed.
  • the ratio of "W” to “S” will affect the manufacturing process of the array substrate 100, and the specific value of the ratio of "W” to “S” can be the minimum value. There is no specific limit to the application.
  • the line width of the plurality of first traces 322 on the side of the straight line area 32 adjacent to the binding area 20 within the second preset length is not less than
  • the line width of the multiple second traces 342 does not exceed the line width of the multiple bonding leads 568, and the multiple first traces 322 on the side of the straight line area 32 adjacent to the bonding area 20 are in the
  • the line width on the side close to the binding region 20 within the second preset length is greater than the line width on the side farther from the binding region 20, and at the same time, the straight line region 32 is adjacent to the binding region 20 side.
  • the line width of the first traces 322 within the second preset length may be in a gradual form, that is, the multiple first traces on the side of the straight line area adjacent to the binding area are within the second preset length.
  • the line width within the length gradually decreases along the direction from close to the binding area to away from the binding area, for example, the straight line area 32 is adjacent to a plurality of the first traces on one side of the binding area 20 322 within the second preset length, the change of line width presents a regular change such as a smooth curve or a plurality of evenly reduced folded line segments, realizing the line width of the binding lead 568 in the binding area 20 to the straight line area 32
  • the smooth transition of the line width of the first wiring 322 can improve the yield of the wiring of the array substrate 100 .
  • the second preset length means that the predetermined design line width of the plurality of first traces 322 on the side of the straight line area 32 adjacent to the binding area 20 within the second preset length is greater than the The specific value of the ratio of "W" to "S" in the slash area 34, and at the same time, the plurality of first traces 322 on the side of the straight line area 32 adjacent to the bonding area 20 have a second preset length
  • the predetermined design line width within should ensure the complete layout of the GOA (Gate on Array) circuit or driver integrated circuit in the fan-out area 30.
  • W refers to the line width of the second routing 342 in the oblique area 34
  • S refers to the width of two adjacent second routings 342 in the oblique area 34 . spacing.
  • the predetermined design line width refers to the line width of the first line selected and used by the array substrate before the line optimization is performed.
  • the ratio of "W” to “S” will affect the manufacturing process of the array substrate 300, and the specific value of the ratio of "W” to “S” can be the minimum value. There is no specific limit to the application.
  • the embodiment of the present application also provides a display panel, the display panel includes the array substrate of any of the above embodiments, the color filter substrate, and the array substrate and color filter substrate.
  • an embodiment of the present application also provides a display device, the display device includes a backlight module and the display panel described in the above-mentioned embodiments, and the display panel is arranged on the backlight module. On the light output side of the group, the backlight module provides backlight for the display panel.
  • the display device also includes other structures, and this application only lists structures related to the invention point, and the display device provided in the embodiment of the application can be a notebook computer display screen, a liquid crystal display, a liquid crystal TV, Digital photo frames, mobile phones, tablet computers and any other products or components with display functions.
  • the display device also includes other necessary components and components such as a drive board, a power supply board, a high voltage board, and a key control board. supplemented, and will not be repeated here.
  • the display device can be used in electronic equipment including but not limited to tablet computers, notebook computers, desktop computers, etc., for example, TFT-LCD.
  • the specific type of the display device is not particularly limited, and those skilled in the art can design correspondingly according to the specific usage requirements of the electronic device to which the display device is applied, so details will not be repeated here.
  • the display device can also be used in electronic devices including functions such as personal digital assistants (Personal Digital Assistant, PDA) and/or music players, such as mobile phones, tablet computers, wearable electronic devices with wireless communication functions (such as smart watches).
  • PDA Personal Digital Assistant
  • music players such as mobile phones, tablet computers, wearable electronic devices with wireless communication functions (such as smart watches).
  • the aforementioned electronic equipment may also be other electronic devices, such as a laptop computer (Laptop) with a touch-sensitive surface (eg, a touch panel).
  • the electronic device can have a communication function, that is, it can pass 2G (second-generation mobile phone communication technical specification), 3G (third-generation mobile phone communication technical specification), 4G (fourth-generation mobile phone communication technical specification) , 5G (fifth-generation mobile phone communication technology specification) or W-LAN (wireless local area network) or communication methods that may appear in the future to establish communication with the network.
  • 2G second-generation mobile phone communication technical specification
  • 3G third-generation mobile phone communication technical specification
  • 4G fourth-generation mobile phone communication technical specification
  • 5G fifth-generation mobile phone communication technology specification
  • W-LAN wireless local area network
  • the fan-out area 30 is electrically connected to the connection area 10
  • the binding area 20 is electrically connected to the fan-out area 30, and the binding area 20 includes a bonding area.
  • Fixed lead 568, fan-out area 30 includes straight line area 32 and oblique line area 34, and the line width of straight line area 32 is equal to the line of binding lead 568 in the segment of preset length on the side of straight line area 32 close to bonding area 20 or the line width of the side of the straight line area 32 adjacent to the binding area 20 in the second preset length is regularly changed and is not less than the line width of the oblique line area 34 and does not exceed the line width of the binding lead 568 and is adjacent to One side of the binding area is larger than the side away from the binding area, realizing a smooth transition of the line width from the binding area 20 to the oblique line area 34, and avoiding the large change in line width at the junction of the straight line area and the binding area.
  • the line width of the bonding lead in the bonding area is usually greater than the predetermined design line width of the straight line area. Widening effectively reduces the resistance of the first wiring in the straight line area, thereby effectively improving the signal driving and transmission of the array substrate, improving the performance of the array substrate, and effectively improving the use effect of the display panel and the display device.

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Abstract

一种阵列基板(100)和显示面板。其中，阵列基板(100)中第一走线(322)在第一预设长度内的线宽等于绑定引线(568)的；或者，第一走线(322)在第二预设长度内的线宽不小于第二走线(342)的且不超过绑定引线(568)的，且靠近绑定区(20)一侧大于远离绑定区(20)一侧的线宽。通过加宽第一走线(322)的线宽使阵列基板(100)的走线平滑过渡，以避免水汽渗入影响阵列基板(100)使用性能。

Description

阵列基板和显示面板
本申请要求于2022年01月26日提交中国专利局，申请号为202210095166.0，申请名称为“阵列基板和显示面板”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板以及具有该阵列基板的显示面板。
背景技术
薄膜晶体管液晶显示器(Thin Film Transistor-Liquid Crystal Display，TFT-LCD)具有机身薄、省电、无辐射等众多优点，因此被广泛应用于液晶电视、移动电话、个人数字助理(Personal Digital Assistant，PDA)、数字相机、计算机屏幕、投影机或笔记本电脑屏幕等电子装置，在显示领域中具有主导地位。因此，在当前迅速发展的液晶显示技术中，薄膜晶体管液晶显示器受到人们的广泛青睐。
TFT-LCD通常包括显示面板及背光模组，显示面板中一般设置有显示区域以及设置于显示区域周边的绑定区和扇出(Fanout)区，其中，所述扇出区连接所述显示区域和绑定区，以实现数据信号的传输。然而，在基于COA(CF on Array)产品中的扇出区走线设计中，由于绑定区的焊接引线(Bonding lead)的线宽大于扇出区走线的线宽，使得绑定区和扇出区交界处线宽过渡较大，导致制程中容易在绑定区和扇出区交界处产生底切(undercut)，进而造成水汽渗入致使成线不良的问题。
发明内容
本申请的目的是提供一种阵列基板以及具有该阵列基板的显示面板。阵列基板的直线区的第一走线的线宽部分加宽至与绑定区的绑定引线相等，或阵列基板的直线区的第一走线的线宽部分加宽至大于斜线区的线宽且小于绑定引线的线宽，使得绑定区和扇出区的直线区的线宽平滑过渡，以避免在直线区与绑定区交界处由于线宽变化较大，进而造成水汽渗入的问题。
为实现本申请的目的，本申请提供了如下的技术方案：
第一方面，本申请提供了一种阵列基板，所述阵列基板包括绑定区以及与所述绑定区连接的扇出区，所述扇出区包括直线区和斜线区，所述直线区连接于所述斜线区和所述绑定区之间，所述绑定区包括多条绑定引线，所述直线区包括多条第一走线，所述斜线区包括多条第二走线，所述第一走线与所述绑定引线电连接，所述第二走线与所述第一走线电连接，所述直线区内邻接所述绑定区的所述第一走线在第一预设长度内的线宽等于所述绑定引线的线宽；或者，所述直线区内邻接所述绑定区的第一走线在第二预设长度内的线宽不小于所述第二走线的线宽且不超过多条所述绑定引线的线宽，且所述直线区内邻接所述绑定区的所述第一走线在第二预设长度内靠近所述绑定区一侧的线宽大于所述第一走线远离所述绑定区一侧的线宽。
第二方面，本申请提供了一种显示面板，所述显示面板包括上述的阵列基板、彩膜基板以及位于所述阵列基板和所述彩膜基板之间的液晶层。
综上所述，在本申请提供的阵列基板和显示面板中，将直线区靠近绑定区的一侧在预设长度的区段内直线区的线宽等于绑定引线的线宽；或直线区邻接绑定区的一侧在第二预设长度内的线宽呈规律性变化且不小于斜线区的线宽且不超过绑定引线的线宽且邻接绑定区的一侧大于远离绑定区的一侧，实现绑定区到斜线区线宽的平滑过渡，提高了阵列基板的线的良率，有效提高了阵列基板的使用性能，提高显示面板的显示效果和品质。此外，由于绑定区的绑定引线的线宽通常大于直线区的预定设计线宽，本申请将直线区的线宽加宽为等于绑定引线的线宽或较预定设计线宽加宽，有效减小了直线区的第一走线的电阻，从而有效提升了阵列基板的信号驱动和传输，提升了阵列基板的使用性能，有效提升显示面板的使用效果。
附图说明
为了更清楚地说明本申请实施方式或现有技术中的技术方案，下面将对实施方式或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施方式，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例公开的一种阵列基板的整体结构示意图；
图2为本申请实施例公开的阵列基板的绑定区和扇出区的截面结构示意图；
图3为本申请第一实施例公开的阵列基板的绑定区与直线区的局部截面示意图；
图4为本申请第二实施例公开的阵列基板的绑定区与直线区的局部截面示意图；
图5为本申请实施例公开的阵列基板的扇出区的局部截面示意图；
图6为本申请第一实施例公开的阵列基板沿图2中由II至III方向的层结构示意图；
图7为本申请第二实施例公开的阵列基板沿图2中由II至III方向的层结构示意图；
图8为本申请第三实施例公开的阵列基板沿图2中由II至III方向的层结构示意图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的较佳实施方式。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施方式。相反地，提供这些实施方式的目的是使对本申请的公开内容理解的更加透彻全面。
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本文中为部件所编序号本身，例如“第一”、“第二”等，仅用于区分所描述的对象，不具有任何顺序或技术含义。而本申请所说“连接”、“联接”，如无特别说明，均包括直接和间接连接(联接)。本申请中所提到的方向用语，例如，“上”、“下”、“前”、“后”、“左”、“右”、“内”、“外”、“侧面”等，仅是参考附加图式的方向，因此，使用的方向用语是为了更好、更清楚地说明及理解本申请，而不是指示或暗指所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸地连接，或者一体地连接；可以是机械连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。需要说明的是，本申 请的说明书和权利要求书及所述附图中的术语“第一”、“第二”等是用于区别不同对象，而不是用于描述特定顺序。
本申请实施例提供一种阵列基板100，请参阅图1、图2、图3、图4和图5，其中，图1为本申请实施例公开的一种阵列基板的整体结构示意图，图2为本申请实施例公开的阵列基板的绑定区和扇出区的截面结构示意图，图3为本申请第一实施例公开的阵列基板的绑定区与直线区的局部截面示意图，图4为本申请第二实施例公开的阵列基板的绑定区与直线区的局部截面示意图，图5为本申请实施例公开的阵列基板的扇出区的局部截面示意图。
在本申请实施例提供的阵列基板100中，如图1和图2所示，所述阵列基板100至少可以包括绑定区(Bonding Area)20和扇出区(Fanout Area)30，其中，所述绑定区20与所述扇出区30电连接，如图3和图5所示，所述绑定区20包括多条绑定引线(Bonding lead)568，所述扇出区30包括直线区32和斜线区34，其中，所述斜线区34与所述直线区32的一侧相邻接，所述直线区32相对的另一侧与所述绑定区20相邻接，即所述直线区32连接于所述斜线区34和所述绑定区20之间。所述直线区32包括多条第一走线322，所述斜线区34包括多条第二走线342，所述直线区32内邻接所述绑定区20的所述第一走线322在第一预设长度内的线宽等于所述绑定引线568的线宽；
或者，所述直线区32内邻接所述绑定区20的第一走线322在第二预设长度内的线宽不小于所述第二走线342的线宽且不超过多条所述绑定引线568的线宽，同时所述直线区32内邻接所述绑定区20一侧的所述第一走线322在第二预设长度内靠近所述绑定区20一侧的线宽大于远离所述绑定区20一侧的线宽，也即是，所述直线区32连接于所述斜线区34和所述绑定区20之间，则所述直线区32内的第一走线322的一端靠近所述绑定区20，第一走线322相对的另一端远离所述绑定区20，则邻接所述绑定区20的所述第一走线322在第二预设长度内靠近所述绑定区20的线宽大于远离所述绑定区20的线宽，从而实现了所述绑定区20的所述绑定引线568的线宽到所述直线区32的第一走线322的线宽的平滑过渡，进而提升所述阵列基板100走线的良率。
在本申请实施例中，所述直线区32邻接所述绑定区20一侧的多条所述第一走线322在第二预设长度内的线宽可以为渐变形式，即所述直线区邻接所述绑定区一侧的多条所述第一走线在第二预设长度内的线宽沿由靠近所述绑定区 至远离所述绑定区的方向渐变缩小，例如，所述直线区32邻接所述绑定区20一侧的多条所述第一走线322在第二预设长度内的线宽变化呈现为平滑的曲线或多个均匀缩小折线段(即在预设长度内所述第一走线322的轴截面可为多个叠加的等腰梯形或梯形)等规律性变化。
在本申请实施例中，所述绑定区20与所述扇出区30相邻接，且二者之间电连接，所述绑定区20的多条所述绑定引线568之间可相平行且间隔设置。所述直线区32与所述绑定区20相邻接，且二者之间电连接，所述直线区32的多条第一走线322之间可相平行且间隔设置，且所述第一走线322与对应的绑定引线568电连接。所述斜线区34与所述直线区32相邻接，且二者之间电连接，所述斜线区34的多条第二走线342之间可相平行且间隔设置，且所述第二走线342与对应的第一走线322电连接。也即为，所述第一走线322连接于所述绑定引线568与所述第二走线342之间。
综上所述，所述绑定区20与所述扇出区30电连接，所述绑定区20包括绑定引线568，所述扇出区30包括直线区32和斜线区34，所述直线区32靠近所述绑定区20的一侧在预设长度的区段内所述直线区32的线宽等于所述绑定引线568的线宽；或者，所述直线区32邻接所述绑定区20一侧的多条所述第一走线322在第二预设长度内的线宽不小于多条第二走线342的线宽且不超过多条所述绑定引线568的线宽，同时所述直线区32邻接所述绑定区20一侧的多条所述第一走线322在第二预设长度内靠近所述绑定区20一侧的线宽大于远离所述绑定区20一侧的线宽，实现所述绑定区20的所述绑定引线568的线宽到所述直线区32的第一走线322的线宽的平滑过渡，从而避免了在所述直线区与所述绑定区交界处由于线宽变化较大，导致制程中，例如蚀刻过程中容易在绑定区和扇出区交界处产生底切(undercut)，进而造成水汽渗入的问题，提高了所述阵列基板的线的良率，有效提高了所述阵列基板100的使用性能。
请继续参阅图1，所述阵列基板100还包括连接区10、有效显示区域(Active area，AA)及外围功能区，所述连接区10位于所述有效显示区域内，所述绑定区20与所述扇出区30位于所述外围功能区，所述扇出区30邻接所述有效显示区域设置且与所述连接区10之间电连接。所述连接区10可以接收来自所述扇出区30的电信号，所述绑定区20邻接所述扇出区30设置且可以向所述扇出区30发送电信号。
在本申请一实施例中，所述扇出区30还包括连接所述有效显示区域的数据信号线(图未示)，所述有效显示区域为主要显示影像的部份。所述绑定区20内可设置有驱动集成电路(Integrated Circuit，IC)，用以供驱动IC来接合于面板上。所述扇出区30内可设置多条走线，并呈扇形分布，用以连接所述有效显示区域内的线路与所述外围功能区的驱动电路。
请继续参阅图2，图2中第一界线s示出的面为所述绑定区20和所述扇出区30的交界位置。具体为，图2中第一界线s的一侧(图2中所示第一界线s的上侧)为所述阵列基板100的扇出区30，第一界线s的另一侧(图2中所示第一界线s的下侧)为所述阵列基板100的绑定区20。
需要说明的是，现有市场中，连接所述绑定区20和所述扇出区30使用的导线通常在交界位置处线宽过渡较大，在制程中容易出现逆倒角或底切进而造成水汽渗入致使成线不良的问题，从而影响线连接的良率，进而影响所述阵列基板100信号传输的可靠性。
请一并参阅图6至图8，图6至图8中的第二界线m示出的面为所述绑定区20和所述扇出区30的交界位置，具体为，图6至图8中的第二界线m的左侧部分为所述阵列基板100的绑定区20，图6至图8中的第二界线m的右侧部分为所述阵列基板100的扇出区30。结合图2可知，所述第一界线s与所述第二界线m共面。
请参阅图3、图4和图6，图6为本申请第一实施例公开的阵列基板沿图2中由II至III方向的层结构示意图。在本申请实施例中，所述阵列基板100可包括由上至下依次层叠设置的有机层52、保护层53、绝缘层(Gate Insulator，GI)54、金属走线层56、以及衬底基板58，所述衬底基板58位于所述阵列基板100的最下层。具体地，所述衬底基板58位于所述阵列基板100层结构的最下层，用于支撑位于其上的所述阵列基板100的其他结构层；
所述金属走线层56设置于所述衬底基板58上，所述金属走线层56包括所述绑定引线568、所述第一走线322和所述第二走线342，所述第一走线322连接于所述绑定引线568和所述第二走线342之间；
所述绝缘层54位于所述金属走线层56上，所述绝缘层54可以由氮化硅、氧化硅等无机材料制成；
所述保护层53位于所述绝缘层54上，用于保护其自身在内的所述阵列基 板100不受损害；
所述有机层52位于所述保护层53上，所述有机层52可由可溶性聚四氟乙烯(Polyfluoroalkoxy，Teflon PFA，PFA)制成。
在其中一个实施例中，所述金属走线层56包括第一走线部分561、第二走线部分563以及第三走线部分565，所述第一走线部分561、第二走线部分563以及第三走线部分565依次连接，其中，所述金属走线层56对应所述第二走线部分563的区域包括所述绑定引线568，所述金属走线层56对应所述第三走线部分565的区域包括所述第一走线322。所述阵列基板100设有至少一个过孔567，所述过孔567依次贯穿所述有机层52、所述保护层53和所述绝缘层54以露出所述金属走线层56的第二走线部分563。也即为，所述过孔567依次贯穿所述有机层52、所述保护层53和所述绝缘层54直至所述金属走线层56的第二走线部分563，即所述过孔567在阵列基板100内形成了以所述金属走线层56的第二走线部分563为底壁的凹槽结构。
在本申请实施例中，所述阵列基板100还包括导电膜51，所述导电膜51可以由氧化铟锡(Indium Tin Oxide，ITO)制成，所述导电膜51覆盖对应所述过孔567底部的所述金属走线层56的第二走线部分563和所述过孔567的侧壁，所述导电膜51还覆盖所述有机层52背对所述保护层53一侧的表面区域，也即为，所述导电膜51作为所述阵列基板100的上表面。由于所述过孔567依次贯穿所述有机层52、所述保护层53和所述绝缘层54并露出所述第二走线部分563，且所述导电膜51覆盖所述第二走线部分563上，因此所述导电膜51在所述过孔567内与所述金属走线层56的第二走线部分563连接。
在本申请实施例中，所述绑定引线568用于实现所述金属走线层56的第二走线部分563与所述导电膜51之间的电连接，即所述导电膜51在所述过孔567内通过所述绑定引线568与所述金属走线层56的第二走线部分563连接。
请参阅图3、图4和图7，图7为本申请第二实施例公开的一种阵列基板沿图2中由II至III方向的层结构示意图。
在本申请实施例中，所述阵列基板200可以包括由上至下依次层叠设置的有机层52、保护层53、金属走线层57、绝缘层54、以及衬底基板58，所述衬底基板58位于所述阵列基板100层结构的最下层。具体地，所述衬底基板58位于所述阵列基板100的最下层，用于支撑位于其上的所述阵列基板100的其 他结构层；
所述绝缘层54位于所述衬底基板58上，所述绝缘层54可以由氮化硅、氧化硅等无机材料制成；
所述金属走线层57设置于所述绝缘层54上，所述金属走线层57包括所述绑定引线568、所述第一走线322和所述第二走线342，所述第一走线322连接于所述绑定引线568和所述第二走线342之间；
所述保护层53位于所述金属走线层57上，用于保护其自身在内的所述阵列基板不受损害；
所述有机层52位于所述保护层53上，所述有机层52可由可溶性聚四氟乙烯制成。
在其中一个实施例中，所述金属走线层57包括第一走线部分571、第二走线部分573以及第三走线部分575，所述第一走线部分571、第二走线部分573以及第三走线部分575依次连接，其中，所述金属走线层57对应第二走线部分573的区域包括所述绑定引线568，所述金属走线层57对应所述第三走线部分575的区域包括所述第一走线322。所述阵列基板200开设有至少一个过孔577，所述过孔577依次贯穿所述有机层52和所述保护层53以露出所述金属走线层57的第二走线部分573。也即为，所述过孔577依次贯穿所述有机层52和所述保护层53直至所述金属走线层57的第二走线部分573，即所述过孔577在阵列基板100内形成了以所述金属走线层57的第二走线部分573的部分区域为底壁的凹槽结构。
在本申请实施例中，所述阵列基板200还包括导电膜51，所述导电膜51可以由氧化铟锡制成，所述导电膜51覆盖对应所述过孔577底部的所述金属走线层57的第二走线部分573和所述过孔577的侧壁，所述导电膜51还覆盖所述有机层52背对所述保护层53一侧的表面区域，也即为，所述导电膜51作为所述阵列基板200的上表面。由于所述过孔577依次贯穿所述有机层52和所述保护层53并露出所述第二走线部分573，且所述导电膜51覆盖所述第二走线部分573上，所述导电膜51在所述过孔577内与所述金属走线层57的第二走线部分573连接。
在本申请实施例中，所述绑定引线568用于所述金属走线层57的第二走线部分573与所述导电膜51连接，也即为所述导电膜51在所述过孔577内通过 所述绑定引线568与所述金属走线层57的第二走线部分573连接。
请参阅图3、图4和图8，图8为本申请公开的阵列基板的第三实施例的绑定区和直线区层结构的示意图。
在本申请实施例中，所述阵列基板300可以包括有机层52、保护层53、第二金属走线层57a、绝缘层54、第一金属走线层56a以及衬底基板58，所述衬底基板58位于所述阵列基板100的最下层。
在本申请实施例中，所述第一金属走线层56a可以与上述第一实施例中的所述阵列基板100中的所述金属走线层56具有相同的材料，所述第二金属走线层57a可以与上述第二实施例中的所述阵列基板200中的所述金属走线层57具有相同的材料，本申请对此不做具体限制。
具体地，所述衬底基板58位于所述阵列基板100的最下层，用于支撑位于其上的所述阵列基板100的其他结构层；
所述第一金属走线层56a位于所述衬底基板58上且对应所述绑定区20，也即为，所述第一金属走线层56a在所述衬底基板58上的正投影与所述绑定区20的长度相等(即位于所述阵列基板100的第一界线m的左侧)，且所述第一金属走线层56a的一端与所述衬底基板58位于所述绑定区20的一端对齐，所述第一金属走线层56a包括所述绑定引线568的一部分。
所述绝缘层54设置于所述第一金属走线层56a和所述衬底基板58上，所述绝缘层54可以由氮化硅、氧化硅等无机材料制成。具体为，所述绝缘层54整体可为“L”形，所述绝缘层54可包括相连接的第一绝缘部分541和第二绝缘部分543，所述第一绝缘部分541位于所述第一金属走线层56a上且对应所述绑定区20，也即为，所述第一绝缘部分541在所述衬底基板58上的正投影与所述第一金属走线层56a在所述衬底基板58上的正投影重合。所述第二绝缘部分543位于所述衬底基板58上对应所述扇出区30的位置，所述第二绝缘部分543的上表面与所述第一绝缘部分541的上表面平齐。也即为，所述绝缘层54的第一绝缘部分541设置于所述第一金属走线层56a上且对应所述绑定区20，所述第二绝缘部分543设置于所述衬底基板58上对应所述扇出区30。所述第一绝缘部分541的厚度小于所述第二绝缘部分543的厚度。
所述第二金属走线层57a设置于所述绝缘层54上；也即为，所述第一绝缘部分541对应所述绑定区20，且位于所述第一金属走线层56a与所述第二金属 走线层57a之间，所述第二绝缘部分543对应所述扇出区30，且位于所述衬底基板58与所述第二金属走线层57a之间，所述第二金属走线层57a包括所述绑定引线568的另一部分、所述第一走线322和第二走线342，也即为，所述绑定引线568分别属于第一金属走线层56a和第二金属走线层57a，即所述绑定引线568的一部分属于第一金属走线层56a，所述绑定引线568的另一部分属于所述第二金属走线层57a。
所述保护层53位于所述第二金属走线层57a上，用于保护其自身在内的所述阵列基板不受损害；
所述有机层52位于所述保护层53上，所述有机层52可由可溶性聚四氟乙烯制成。
在其中一个实施例中，所述第二金属走线层57a包括第一走线部分571、第二走线部分573以及第三走线部分575，第一走线部分571、第二走线部分573以及第三走线部分575依次连接，所述第二金属走线层57a对应所述第二走线部分573的区域包括所述绑定引线568，所述第二金属走线层57a对应所述第三走线部分575的区域包括所述第一走线322。所述阵列基板300设有至少一个第一过孔572，所述第一过孔572依次贯穿所述有机层52、所述保护层53、所述第二金属走线层57a、所述绝缘层54的第一绝缘部分541以露出所述第一金属走线层56a。也即为，所述第一过孔572依次贯穿所述有机层52、所述保护层53、所述第二金属走线层57a、所述绝缘层54的第一绝缘部分541直至所述第一金属走线层56a，即所述第一过孔572在所述阵列基板300内形成了以所述第一金属走线层56a对应所述第一过孔572的区域为底壁的凹槽结构。
所述阵列基板300设有至少一个第二过孔574，所述第二过孔574依次贯穿所述有机层52和所述保护层53以露出所述第二金属走线层57a的第二走线部分573。也即为，所述第二过孔574依次贯穿所述有机层52和所述保护层53直至所述第二金属走线层57a的第二走线部分573，即所述第二过孔574在阵列基板300内形成了以所述第二金属走线层57a的第二走线部分573对应所述第二过孔574的区域为底壁的凹槽结构。
在本申请实施例中，所述阵列基板300还包括导电膜51，所述导电膜51可以由氧化铟锡(Indium Tin Oxide，ITO)制成，所述导电膜51覆盖对应所述第一过孔572底部的所述第一金属走线层56a和所述第一过孔572的侧壁以及对 应所述第二过孔574底部的第二金属走线层57a和所述第二过孔574的侧壁，所述导电膜51还覆盖所述有机层52背对所述保护层53的一侧且位于所述第一过孔572和所述第二过孔574周侧的表面区域，也即为，所述导电膜51作为所述阵列基板200的上表面。由于所述第一过孔572依次贯穿所述有机层52、所述保护层53、所述第二金属走线层57a、所述绝缘层54的第一绝缘部分541直至所述第一金属走线层56a，所述第二过孔574依次贯穿所述有机层52和所述保护层53直至所述第二金属走线层57a的第二走线部分573，同时所述导电膜51覆盖所述第一金属走线层56a对应所述第一过孔572的表面区域和所述第二走线部分573对应所述第二过孔574的表面区域，所述导电膜51在所述第一过孔572内与所述第一金属走线层56a连接，所述导电膜51在所述第一过孔572和所述第二过孔574内与所述第二金属走线层57a的第二走线部分573连接。
在本申请实施例中，所述绑定引线568用于实现所述第一金属走线层56a、所述第二金属走线层57a的第二走线部分573与所述导电膜51之间的电连接，也即为，所述导电膜51在所述第一过孔572内通过所述绑定引线568与所述第一金属走线层56a连接，所述导电膜51在所述第一过孔572和所述第二过孔574内通过所述绑定引线568与所述第二金属走线层57a的第二走线部分573连接。
请继续参阅图3、图4和图5，图3为本申请第一实施例公开的阵列基板的绑定区与直线区局部截面示意图；图4为本申请第二实施例公开的阵列基板的绑定区与直线区局部截面示意图；图5为本申请实施例公开的阵列基板的扇出区的的局部截面示意图。如图3和图4所示，第一直线a与第二直线b之间的距离为多条所述绑定引线568的长度，所述第一直线a为所述绑定区20与所述直线区32的交界位置，即所述第一直线a的一侧为所述直线区32(图3或图4中所述第一直线a的上侧为所述直线区32)，所述第一直线a的另一侧为所述绑定区20(图3或图4中所述第一直线a的下侧为所述绑定区20)。
在本申请实施例中，如图5所示，所述扇出区30包括相邻接的所述直线区32和斜线区34，所述直线区32与所述绑定区20相邻接，且二者之间电连接，所述直线区32的多条第一走线322与对应的绑定引线568电连接。所述斜线区34与所述直线区32相邻接，且二者之间电连接，所述斜线区34的多条第二走线342与对应的第一走线322电连接。
请继续参阅图3，在本申请实施例中，所述直线区32邻接所述绑定区20的 一侧在第一预设长度内的线宽等于所述绑定引线568的线宽，其中，所述第一预设长度是指所述第一走线322邻接所述绑定区20一侧在第一预设长度内的预定设计线宽大于所述斜线区34的第二走线342的“W”与“S”的比值的特定值。其中，“W”是指所述斜线区34的第二走线342线宽，“S”是指所述斜线区34的相邻两条第二走线342的间距。
在其中一个实施例中，所述预定设计线宽是指阵列基板在未进行走线优化前选定使用的第一走线的线宽。
在其中一个实施例中，所述“W”与“S”的比值会影响到制作所述阵列基板100的制程，所述“W”与“S”的比值的特定值可以取最小值，本申请对此不做具体限制。
请继续参阅图4，在本申请其他实施例中，所述直线区32邻接所述绑定区20一侧的多条所述第一走线322在第二预设长度内的线宽不小于多条第二走线342的线宽且不超过多条所述绑定引线568的线宽，所述直线区32邻接所述绑定区20一侧的多条所述第一走线322在第二预设长度内靠近所述绑定区20一侧的线宽大于远离所述绑定区20一侧的线宽，同时，所述直线区32邻接所述绑定区20一侧的多条所述第一走线322在第二预设长度内的线宽可以为渐变形式，即所述直线区邻接所述绑定区一侧的多条所述第一走线在第二预设长度内的线宽沿由靠近所述绑定区至远离所述绑定区的方向渐变缩小，例如，所述直线区32邻接所述绑定区20一侧的多条所述第一走线322在第二预设长度内的线宽变化呈现为平滑的曲线或多个均匀缩小折线段等规律性变化，实现所述绑定区20的绑定引线568的线宽到所述直线区32的第一走线322的线宽的平滑过渡，进而提升所述阵列基板100走线的良率。其中，所述第二预设长度是指所述直线区32邻接所述绑定区20一侧的多条所述第一走线322在第二预设长度内的预定设计线宽大于所述斜线区34的“W”与“S”的比值的特定值，同时，所述直线区32邻接所述绑定区20一侧的多条所述第一走线322在第二预设长度内的预定设计线宽应当保证GOA(Gate on Array)电路或驱动集成电路在所述扇出区30的完整布局。
在本申请实施例中，“W”是指所述斜线区34的第二走线342的线宽，“S”是指所述斜线区34的相邻两条第二走线342的间距。
在其中一个实施例中，所述预定设计线宽是指阵列基板在未进行走线优化 前选定使用的第一走线的线宽。
在其中一个实施例中，所述“W”与“S”的比值会影响到制作所述阵列基板300的制程，所述“W”与“S”的比值的特定值可以取最小值，本申请对此不做具体限制。
基于相同的构思，针对上述任一实施例的阵列基板，本申请实施例还提供了一种显示面板，所述显示面板包括上述任一实施例的阵列基板、彩膜基板以及位于阵列基板和彩膜基板之间的液晶层。具体地，所述彩膜基板置于所述导电膜51远离所述衬底基板58的一侧，所述液晶层置于所述阵列基板和所述彩膜基板之间。
基于相同的构思，针对上述的显示面板，本申请实施例还提供了一种显示装置，所述显示装置包括背光模组以及上述实施例中所述的显示面板，所述显示面板设置于背光模组的出光侧，所述背光模组为所述显示面板提供背光。可以理解的是，所述显示装置还包括其他结构，本申请只列出了与发明点相关的结构，而且，本申请实施方式提供的显示装置可以是笔记本电脑显示屏、液晶显示器、液晶电视、数码相框、手机、平板电脑等任何具有显示功能的产品或部件。
在其中一个实施例中，所述显示装置还包括驱动板、电源板、高压板、按键控制板等其他必要的部件和组成，本领域技术人员可根据该显示装置的具体类型和实际功能进行相应地补充，在此不再赘述。
可以理解地，所述显示装置可用于包括但不限于平板电脑、笔记本电脑、台式电脑等电子设备，例如，TFT-LCD。根据本申请的实施例，该显示装置的具体种类不受特别的限制，本领域技术人员可根据应用该显示装置的电子装置的具体的使用要求进行相应地设计，在此不再赘述。
可以理解地，所述显示装置还可用于包含诸如个人数字助理(Personal Digital Assistant，PDA)和/或音乐播放器功能的电子设备，诸如手机、平板电脑、具备无线通讯功能的可穿戴电子设备(如智能手表)等。上述电子设备也可以是其它电子装置，诸如具有触敏表面(例如触控面板)的膝上型计算机(Laptop)等。在一些实施例中，所述电子设备可以具有通信功能，即可以通过2G(第二代手机通信技术规格)、3G(第三代手机通信技术规格)、4G(第四代手机通信技术规格)、5G(第五代手机通信技术规格)或W-LAN(无线局域网)或今后 可能出现的通信方式与网络建立通信。为简明起见，对此本申请实施例不做进一步限定。
综上所述，在本申请提供的阵列基板100、显示面板和显示装置中，扇出区30与连接区10电连接，绑定区20与扇出区30电连接，绑定区20包括绑定引线568，扇出区30包括直线区32和斜线区34，直线区32靠近绑定区20的一侧在预设长度的区段内直线区32的线宽等于绑定引线568的线宽；或直线区32邻接绑定区20的一侧在第二预设长度内的线宽呈规律性变化且不小于斜线区34的线宽且不超过绑定引线568的线宽且邻接绑定区的一侧大于远离绑定区的一侧，实现绑定区20到斜线区34线宽的平滑过渡，避免了在直线区与绑定区交界位置处由于线宽变化较大，尤其是COA产品中的扇出区走线设计中，过孔边缘过度线宽差异较大，容易产生的逆倒角或底切导致的水汽渗入造成的线不良的问题，提高了阵列基板的线的良率，有效提高了阵列基板的使用性能，提高显示装置的显示效果和品质。此外，现有市场中，绑定区的绑定引线的线宽通常大于直线区的预定设计线宽，本申请将直线区的线宽加宽为等于绑定引线的线宽或较预定设计线宽加宽，有效减小了直线区的第一走线的电阻，从而有效提升了阵列基板的信号驱动和传输，提升了阵列基板的使用性能，有效提升显示面板和显示装置的使用效果。
对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (20)

  1. 一种阵列基板，所述阵列基板包括绑定区以及与所述绑定区连接的扇出区，所述扇出区包括直线区和斜线区，所述直线区连接于所述斜线区和所述绑定区之间，所述绑定区包括多条绑定引线，所述直线区包括多条第一走线，所述斜线区包括多条第二走线，所述第一走线与所述绑定引线电连接，所述第二走线与所述第一走线电连接，其中，所述直线区内邻接所述绑定区的所述第一走线在第一预设长度内的线宽等于所述绑定引线的线宽；或者，
    所述直线区内邻接所述绑定区的第一走线在第二预设长度内的线宽不小于所述第二走线的线宽且不超过多条所述绑定引线的线宽，且所述直线区内邻接所述绑定区的所述第一走线在第二预设长度内靠近所述绑定区一侧的线宽大于所述第一走线远离所述绑定区一侧的线宽。
  2. 如权利要求1所述的阵列基板，其中，所述阵列基板包括有机层、保护层、绝缘层、金属走线层以及衬底基板，其中，所述金属走线层设置于所述衬底基板上，所述绝缘层位于所述金属走线层上，所述保护层位于所述绝缘层上，所述有机层位于所述保护层上，所述金属走线层包括所述绑定引线、所述第一走线和所述第二走线，所述第一走线连接于所述绑定引线和所述第二走线之间。
  3. 如权利要求2所述的阵列基板，其中，所述阵列基板开设有过孔，所述阵列基板还包括导电膜，所述金属走线层包括第一走线部分、第二走线部分以及第三走线部分，所述第一走线部分、所述第二走线部分以及所述第三走线部分依次连接；
    所述过孔依次贯穿所述有机层、所述保护层和所述绝缘层以露出所述金属走线层的第二走线部分，所述导电膜覆盖对应所述过孔底部的所述金属走线层的第二走线部分和所述过孔的侧壁，所述导电膜还覆盖所述有机层背对所述保护层一侧的表面区域；
    所述导电膜在所述过孔内通过所述绑定引线与所述金属走线层的第二走线部分电连接。
  4. 如权利要求1所述的阵列基板，其中，所述阵列基板包括有机层、保护层、金属走线层、绝缘层、以及衬底基板，其中，所述绝缘层位于所述衬底基板上，所述金属走线层设置于所述绝缘层上，所述保护层位于所述金属走线层上，所述有机层位于所述保护层上，所述金属走线层包括所述绑定引线、所述第一走线和所述第二走线，所述第一走线连接于所述绑定引线和所述第二走线 之间。
  5. 如权利要求4所述的阵列基板，其中，所述阵列基板开设有过孔，所述阵列基板还包括导电膜，所述金属走线层包括第一走线部分、第二走线部分以及第三走线部分，所述第一走线部分、所述第二走线部分以及所述第三走线部分依次连接；
    所述过孔依次贯穿所述有机层和所述保护层以露出所述金属走线层的第二走线部分，所述导电膜覆盖对应所述过孔底部的所述金属走线层的第二走线部分和所述过孔的侧壁，所述导电膜还覆盖所述有机层背对所述保护层一侧的表面区域；
    所述导电膜在所述过孔内通过所述绑定引线与所述金属走线层的第二走线部分电连接。
  6. 如权利要求1所述的阵列基板，其中，所述阵列基板包括有机层、保护层、第二金属走线层、绝缘层、第一金属走线层以及衬底基板，其中，所述第一金属走线层位于所述衬底基板上且对应所述绑定区，所述绝缘层包括相连接的第一绝缘部分和第二绝缘部分，所述第一绝缘部分位于所述第一金属走线层上且对应所述绑定区，所述第二绝缘部分位于所述衬底基板上对应所述扇出区的位置；所述第二金属走线层设置于所述绝缘层上，所述保护层位于所述第二金属走线层上，所述有机层位于所述保护层上，所述第一金属走线层包括所述绑定引线的一部分，所述第二金属走线层包括所述绑定引线的另一部分、所述第一走线和所述第二走线。
  7. 如权利要求6所述的阵列基板，其中，所述阵列基板开设有第一过孔和第二过孔，所述阵列基板包括导电膜，所述第二金属走线层包括第一走线部分、第二走线部分以及第三走线部分，所述第一走线部分、所述第二走线部分以及所述第三走线部分依次连接；
    所述第一过孔依次贯穿所述有机层、所述保护层、所述第二金属走线层、所述绝缘层的第一绝缘部分以露出所述第一金属走线层，所述第二过孔依次贯穿所述有机层和所述保护层以露出所述第二金属走线层的第二走线部分；
    所述导电膜覆盖对应所述第一过孔底部的所述第一金属走线层和所述第一过孔的侧壁以及对应所述第二过孔底部的第二金属走线层和所述第二过孔的侧壁，所述导电膜还覆盖所述有机层背对所述保护层的一侧且位于所述第一过孔和所述第二过孔周侧的表面区域；
    所述导电膜在所述第一过孔内通过绑定引线与所述第一金属走线层电连接，所述导电膜在所述第一过孔和所述第二过孔内通过绑定引线与所述第二金属走线层的第二走线部分电连接。
  8. 如权利要求1所述的阵列基板，其中，所述第一预设长度是指所述第一走线邻接所述绑定区一侧在第一预设长度内的预定设计线宽大于所述斜线区的第二走线的线宽与相邻两条所述第二走线的间距的比值的特定值。
  9. 如权利要求1所述的阵列基板，其中，所述第二预设长度是指所述直线区邻接所述绑定区一侧的多条所述第一走线在第二预设长度内的预定设计线宽大于所述斜线区的线宽与相邻两条第二走线的间距的比值的特定值，且所述直线区邻接所述绑定区一侧的多条所述第一走线在第二预设长度内的线宽沿由靠近所述绑定区至远离所述绑定区的方向渐变缩小。
  10. 如权利要求2所述的阵列基板，其中，所述第一预设长度是指所述第一走线邻接所述绑定区一侧在第一预设长度内的预定设计线宽大于所述斜线区的第二走线的线宽与相邻两条所述第二走线的间距的比值的特定值；或者，
    所述第二预设长度是指所述直线区邻接所述绑定区一侧的多条所述第一走线在第二预设长度内的预定设计线宽大于所述斜线区的线宽与相邻两条第二走线的间距的比值的特定值，且所述直线区邻接所述绑定区一侧的多条所述第一走线在第二预设长度内的线宽沿由靠近所述绑定区至远离所述绑定区的方向渐变缩小。
  11. 一种显示面板，其中，所述显示面板包括阵列基板、彩膜基板以及位于所述阵列基板和所述彩膜基板之间的液晶层，其中，所述阵列基板包括绑定区以及与所述绑定区连接的扇出区，所述扇出区包括直线区和斜线区，所述直线区连接于所述斜线区和所述绑定区之间，所述绑定区包括多条绑定引线，所述直线区包括多条第一走线，所述斜线区包括多条第二走线，所述第一走线与所述绑定引线电连接，所述第二走线与所述第一走线电连接，其中，所述直线区内邻接所述绑定区的所述第一走线在第一预设长度内的线宽等于所述绑定引线的线宽；或者，
    所述直线区内邻接所述绑定区的第一走线在第二预设长度内的线宽不小于所述第二走线的线宽且不超过多条所述绑定引线的线宽，且所述直线区内邻接所述绑定区的所述第一走线在第二预设长度内靠近所述绑定区一侧的线宽大于所述第一走线远离所述绑定区一侧的线宽。
  12. 如权利要求11所述的显示面板，其中，所述阵列基板包括有机层、保护层、绝缘层、金属走线层以及衬底基板，所述金属走线层设置于所述衬底基板上，所述绝缘层位于所述金属走线层上，所述保护层位于所述绝缘层上，所述有机层位于所述保护层上，所述金属走线层包括所述绑定引线、所述第一走线和所述第二走线，所述第一走线连接于所述绑定引线和所述第二走线之间。
  13. 如权利要求12所述的显示面板，其中，所述阵列基板开设有过孔，所述阵列基板还包括导电膜，所述金属走线层包括第一走线部分、第二走线部分以及第三走线部分，所述第一走线部分、所述第二走线部分以及所述第三走线部分依次连接；
    所述过孔依次贯穿所述有机层、所述保护层和所述绝缘层以露出所述金属走线层的第二走线部分，所述导电膜覆盖对应所述过孔底部的所述金属走线层的第二走线部分和所述过孔的侧壁，所述导电膜还覆盖所述有机层背对所述保护层一侧的表面区域；
    所述导电膜在所述过孔内通过所述绑定引线与所述金属走线层的第二走线部分电连接。
  14. 如权利要求11所述的显示面板，其中，所述阵列基板包括有机层、保护层、金属走线层、绝缘层、以及衬底基板，其中，所述绝缘层位于所述衬底基板上，所述金属走线层设置于所述绝缘层上，所述保护层位于所述金属走线层上，所述有机层位于所述保护层上，所述金属走线层包括所述绑定引线、所述第一走线和所述第二走线，所述第一走线连接于所述绑定引线和所述第二走线之间。
  15. 如权利要求14所述的显示面板，其中，所述阵列基板开设有过孔，所述阵列基板还包括导电膜，所述金属走线层包括第一走线部分、第二走线部分以及第三走线部分，所述第一走线部分、所述第二走线部分以及所述第三走线部分依次连接；
    所述过孔依次贯穿所述有机层和所述保护层以露出所述金属走线层的第二走线部分，所述导电膜覆盖对应所述过孔底部的所述金属走线层的第二走线部分和所述过孔的侧壁，所述导电膜还覆盖所述有机层背对所述保护层一侧的表面区域；
    所述导电膜在所述过孔内通过所述绑定引线与所述金属走线层的第二走线部分电连接。
  16. 如权利要求11所述的显示面板，其中，所述阵列基板包括有机层、保护层、第二金属走线层、绝缘层、第一金属走线层以及衬底基板，其中，所述第一金属走线层位于所述衬底基板上且对应所述绑定区，所述绝缘层包括相连接的第一绝缘部分和第二绝缘部分，所述第一绝缘部分位于所述第一金属走线层上且对应所述绑定区，所述第二绝缘部分位于所述衬底基板上对应所述扇出区的位置；所述第二金属走线层设置于所述绝缘层上，所述保护层位于所述第二金属走线层上，所述有机层位于所述保护层上，所述第一金属走线层包括所述绑定引线的一部分，所述第二金属走线层包括所述绑定引线的另一部分、所述第一走线和所述第二走线。
  17. 如权利要求16所述的显示面板，其中，所述阵列基板开设有第一过孔和第二过孔，所述阵列基板包括导电膜，所述第二金属走线层包括第一走线部分、第二走线部分以及第三走线部分，所述第一走线部分、所述第二走线部分以及所述第三走线部分依次连接；
    所述第一过孔依次贯穿所述有机层、所述保护层、所述第二金属走线层、所述绝缘层的第一绝缘部分以露出所述第一金属走线层，所述第二过孔依次贯穿所述有机层和所述保护层以露出所述第二金属走线层的第二走线部分；
    所述导电膜覆盖对应所述第一过孔底部的所述第一金属走线层和所述第一过孔的侧壁以及对应所述第二过孔底部的第二金属走线层和所述第二过孔的侧壁，所述导电膜还覆盖所述有机层背对所述保护层的一侧且位于所述第一过孔和所述第二过孔周侧的表面区域；
    所述导电膜在所述第一过孔内通过绑定引线与所述第一金属走线层电连接，所述导电膜在所述第一过孔和所述第二过孔内通过绑定引线与所述第二金属走线层的第二走线部分电连接。
  18. 如权利要求11所述的显示面板，其中，所述第一预设长度是指所述第一走线邻接所述绑定区一侧在第一预设长度内的预定设计线宽大于所述斜线区的第二走线的线宽与相邻两条所述第二走线的间距的比值的特定值。
  19. 如权利要求11所述的显示面板，其中，所述第二预设长度是指所述直线区邻接所述绑定区一侧的多条所述第一走线在第二预设长度内的预定设计线宽大于所述斜线区的线宽与相邻两条第二走线的间距的比值的特定值，且所述直线区邻接所述绑定区一侧的多条所述第一走线在第二预设长度内的线宽沿由靠近所述绑定区至远离所述绑定区的方向渐变缩小。
  20. 如权利要求12所述的显示面板，其中，所述第一预设长度是指所述第一走线邻接所述绑定区一侧在第一预设长度内的预定设计线宽大于所述斜线区的第二走线的线宽与相邻两条所述第二走线的间距的比值的特定值；或者，
    所述第二预设长度是指所述直线区邻接所述绑定区一侧的多条所述第一走线在第二预设长度内的预定设计线宽大于所述斜线区的线宽与相邻两条第二走线的间距的比值的特定值，且所述直线区邻接所述绑定区一侧的多条所述第一走线在第二预设长度内的线宽沿由靠近所述绑定区至远离所述绑定区的方向渐变缩小。
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