WO2023142495A1 - 一种预充电方法及使用该方法的存储器装置 - Google Patents

一种预充电方法及使用该方法的存储器装置 Download PDF

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WO2023142495A1
WO2023142495A1 PCT/CN2022/119200 CN2022119200W WO2023142495A1 WO 2023142495 A1 WO2023142495 A1 WO 2023142495A1 CN 2022119200 W CN2022119200 W CN 2022119200W WO 2023142495 A1 WO2023142495 A1 WO 2023142495A1
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bit line
voltage
latch
page buffer
memory device
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PCT/CN2022/119200
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English (en)
French (fr)
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安圣薰
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东芯半导体股份有限公司
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

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  • the invention relates to the field of flash memory, in particular to a precharging method and a memory device using the method.
  • NAND memory is a kind of non-volatile memory, which has the advantages of fast access speed, low power consumption and small size, which makes it widely used as solid-state hard disk and other data processing in mobile devices, notebook computers and servers storage media in the system.
  • a known type of NAND flash memory device includes a memory cell array including a plurality of word lines extending in rows, a plurality of bit lines extending in columns, and a column decoder and a page buffer. Corresponding multiple unit strings.
  • the page buffer is electrically connected to the bit line and is used for providing proper driving voltage to the bit line during programming.
  • the bit line coupled to the memory cell to be programmed in the page can be floated or discharged, while the bit line coupled to the memory cell to be programmed cannot be programmed.
  • the bit lines of the memory cells may be precharged to program inhibit prior to application of the programming pulse.
  • the voltage of the bit line is defined by the latched data of the page buffer. For example, when the latched data in the page buffer is 0, the voltage of the bit line is GND, and when the latched data in the page buffer is 1, the voltage of the bit line is VDD.
  • the density of semiconductor components inside the integrated circuit will increase accordingly, so that the distance between the semiconductor dimensions will decrease accordingly, and the distance between the conductive parts used to conduct electrical signals in the semiconductor components will also be correspondingly This will directly lead to an increase in the parasitic capacitance generated between any two adjacent conductive components.
  • the parasitic capacitance generated between adjacent conductive components and the interference caused by the parasitic capacitance become more and more serious.
  • the memory includes multiple bit lines and multiple word lines, wherein the multiple bit lines are usually formed on the substrate and arranged in parallel along a predetermined direction.
  • the distance between adjacent bit lines is also gradually shortened, resulting in a large parasitic capacitance between adjacent bit lines, and the phenomenon of capacitive coupling is prone to occur, thus Affects the performance of semiconductor memory.
  • the capacitive load on the bit line exceeds the latch driving capability of the page buffer, the latched data of the page buffer may be corrupted.
  • the bit line with heavy load is connected to the page buffer, the latched data of the page buffer may be reversed, thereby affecting the normal operation of the memory.
  • the present invention provides a kind of precharging method, and described precharging method comprises the following steps: Step 1, carry out precharging to all bit lines; Step 2, according to the value of the latch in the page buffer The bit line voltage is set, wherein, when the value on the latch is "1", the bit line voltage connected to the page buffer is raised to a high level; when the value on the latch is "0" , keep the voltage of the bit line connected to the page buffer at a low level.
  • Adopting the precharging method provided in the present invention will reduce the change of the voltage value on the latch node caused by the coupling capacitance, and can effectively reduce the influence of the coupling capacitance between the bit lines on the memory device, so that there is a voltage on the bit line.
  • the memory device also works well with large capacitive loads.
  • the voltage of the bit line is controlled by cutting off the control voltage CON.
  • the voltage on the bit line increases with the increase of the cut-off control signal CON, and the voltage difference between the cut-off control signal CON and the bit line is equal to that of the transistor threshold voltage.
  • the voltage of the cut-off control signal CON is a gradually increasing voltage.
  • the cut-off control signal CON is a voltage that gradually increases
  • the voltage on the selected bit line BL(i) is also a voltage that gradually increases, so that the voltage on the adjacent non-selected bit line BL(i-1) rises It will be segmented and the amplitude will be smaller, and then the voltage reduction value ⁇ V(1) on the latch node Q will also decrease.
  • the voltage of the cut-off control signal CON is a stepped voltage.
  • Another aspect of the present invention also provides a memory device using the precharging method, wherein the memory device includes a voltage source, a page buffer, a bit line, and a memory unit, and the page buffer is electrically connected to to a voltage source, and connected to a bit line in the memory device, through which it is connected to a memory cell in the memory device; wherein the page buffer includes a latch, when the value on the latch is "1" , precharge the bit line connected to the page buffer to a high level; when the value on the latch is "0", keep the bit line connected to the page buffer at a low level.
  • the page buffer includes a control circuit and a bit line driver circuit
  • the control circuit is used to generate a control signal
  • the control signal is used to control the bit line driver circuit, selectively line to apply a program voltage or a program inhibit voltage.
  • the bit line driving circuit includes a bit line selection unit, a precharging unit, and a sensing and latching unit.
  • FIG. 1 is a schematic diagram of a NAND memory device with a page buffer.
  • FIG. 2 is a circuit diagram of a bit line driving circuit of a page buffer.
  • FIG. 3 is a waveform diagram of each node during an all bit line programming operation in the prior art.
  • Figure 3(a) is the waveform diagram during normal operation
  • Figure 3(b) is the waveform diagram during abnormal operation.
  • FIG. 4 is a waveform diagram of precharging a bit line provided by the present invention.
  • FIG. 5( a ) and FIG. 5( b ) are schematic diagrams of the shutdown control signal CON.
  • FIG. 1 is a schematic diagram of a NAND memory device with a page buffer in the prior art.
  • a schematic diagram of a NAND memory device includes a voltage source VDD, a page buffer 100 , a bit line 102 , and word lines and memory cells not shown in FIG. 1 .
  • the page buffer 100 is electrically connected to the voltage source VDD, and the page buffer 100 is also connected to the bit line BL in the memory device, and is connected to the memory cells in the memory device through the bit line BL.
  • the page buffer 100 includes a control circuit, which generates a control signal when the data feature is written in response to the data feature to be stored, and then selectively applies a programming voltage or a programming inhibiting voltage to the bit line in the memory device.
  • the bit line driving circuit 101 is controlled by the control signal generated by the control circuit to increase the bit line voltage of the unselected bit lines to increase the operating margin of the selected bit lines in the memory.
  • the page buffer 100 further includes at least a bit line driving circuit 101, and the bit line driving circuit 101 applies a programming voltage or a programming inhibiting voltage to the bit lines in the memory device according to the control signal generated by the control circuit.
  • the bit line driver circuit 101 includes a latch circuit. During the read operation, the latch is used to temporarily store the data read from the memory cell. During the programming operation, the data read from the outside is stored in the latch. These data are then transferred to the storage unit.
  • the bit line 102 is used to connect the page buffer 100 and the memory cells. Since the bit lines 102 are metal lines placed in parallel, there is a relatively large capacitance between the bit lines. In FIG . c.
  • bit line 102 can also be connected to the page buffer 100 through a bit line clamp transistor, and the bit line clamp transistor is controlled to open and close by the bit line control selection signal CON_BL, as long as the bit line selection signal CON_BL is greater than the threshold voltage (which is greater than the voltage of the charging bit line), and the bit line clamp transistor passes current to the corresponding bit line.
  • each bit line is driven by the page buffer, when the voltage on BL(i) is VDD, and the voltage on BL(i-1) and BL(i+1) are both When GND is used, the effective capacitance on BL(i) will reach the maximum at this time, which is 2C. In the process of assigning a value to the bit line BL(i), a larger capacitance value may affect the voltage on the latch, and even cause the data on the latch to flip.
  • FIG. 2 is a circuit diagram of the bit line driving circuit 101 of the page buffer 100 .
  • the bit line driving circuit 101 of the page buffer 100 includes a bit line selection unit 21 , a precharge unit 22 , and a sensing and latch unit 23 .
  • the bit line selection unit 21 is used to select the bit line BL to be sensed.
  • the precharge unit 22 is used to precharge the selected bit line BL and precharge the sensing node S0 before the program operation.
  • NAND flash memory mainly includes three actions: reading, programming and erasing.
  • the sensing node S0 is provided in the precharge unit 21 and connected to the sensing and latch unit 23 .
  • the sense and latch unit 23 includes a latch 239′ for storing data values.
  • the logic value presented on the latch node Q can be changed according to the level of the voltage presented on the sensing node S0 to sense
  • the voltage level of node S0 changes with the programmed or erased state of the cell. That is, in the case of a cell being programmed, the sensing node S0 maintains a high voltage level, and in a case of a cell being erased, the sensing node S0 is discharged to a low voltage level.
  • Latch node Q outputs the logic value present on latch node Q during normal read operations, so latch node Q may function as an output node.
  • the page buffer 100 is set to a program inhibit mode of operation; when a logic value "0" is present on the latch node Q, the page buffer 100 is set for programming mode of operation.
  • the bit line selection unit 21 includes an NMOS transistor 211, and the NMOS transistor 211 selects the bit line on which the operation will be performed in response to the bit line selection signal CON_BL, and the bit line selection signal CON_BL is applied to the gate of the NMOS transistor 211 to be selected
  • the bit line is electrically connected to the precharge unit 21 and the sensing and latch unit 22 .
  • the precharge unit 22 includes a PMOS transistor 221 , NMOS transistors 222 and 223 .
  • the PMOS transistor 221 is disposed between the power supply voltage VDD and the sensing node S0, and is turned on or off in response to the precharge control signal PRECH_N.
  • the bit line BL is precharged to a predetermined level by the power supply voltage VDD.
  • the NMOS transistor 222 is disposed between the bit line selection circuit 21 and the sensing node S0.
  • the NMOS transistor 222 is turned on or off in response to the cut-off control signal CON.
  • the NMOS transistor 222 is used to electrically isolate the bit line BL from the sense node S0.
  • the NMOS transistor 223 is provided between the bit line selection circuit 21 and the power supply VSS.
  • the NMOS transistor 223 responds to the discharge control signal DIS. When the NMOS transistor 223 is turned on, the bit line BL is boosted to VSS through.
  • the sensing and latch unit 23 includes a latch 239 for storing data read during a read operation and data to be programmed.
  • Latch 239 includes two inverters that output data values that are opposite to each other. Latch nodes Q and Q_N are provided at output ports of the two inverters, respectively.
  • the inverter is composed of NMOS transistors and POMS transistors. The gates of the NMOS transistors and POMS transistors in each inverter are connected as input terminals, and the drains are connected as output terminals. The source of the NMOS transistors is grounded, and the source of the PMOS transistors is connected. Power supply VDD.
  • the latch nodes Q and Q_N are respectively set at two output port of an inverter.
  • the NMOS transistor 231 is disposed between the latch node Q and the sense node S0, and in response to the control signal TRAN, will latch the logic value on the node Q (ie, the data stored in the latch 239) during the programming operation. Transfer to the selected bit line BL.
  • the control signal TRAN is activated during a program operation, during which data stored in the latch 239 is transferred to the bit line BL. If the logic value "1" is present on latch node Q during a program operation, the program operation is inhibited. Accordingly, latch 239 is initialized so that the logic value presented on latch node Q is "1".
  • the source of the NMOS transistor 237 is connected to the latch node Q, and the source of the NMOS transistor 236 is connected to the latch node Q_N.
  • NMOS transistor 237 provides a sensing path in response to control signal RST.
  • the control signal RST is activated to a logic high level.
  • the NMOS transistor 236 initializes the latch 239 so that the logical values presented on the latch nodes Q and Q_N are "1" and "0", respectively.
  • Control signal SET is activated to a logic high level to initialize latch 239 during page buffer setup.
  • the NMOS transistor 238 is connected to the terminals of the NMOS transistors 236 and 237, and its gate is connected to the sensing node S0.
  • NMOS transistor 238 is selectively turned on during the sensing period. For example, if the voltage level presented on sense node SO during sensing is a logic high level (ie, the selected memory cell is programmed), NMOS transistor 238 is turned on. If the voltage level present on sense node S0 during the sensing period is a logic low level (ie, the selected memory cell is erased), NMOS transistor 238 is turned off.
  • FIG. 3 is a waveform diagram of each node during an all bit line programming operation in the prior art.
  • BL(1) indicates the bit line whose voltage needs to be set to a high voltage
  • BL(0) indicates the bit line whose voltage needs to be set to a low voltage
  • Q(1) indicates that the value on the latch is "1”
  • Q(0) means the value on the latch is "0”.
  • Figure 3 (a) is a waveform diagram during normal operation. During the programming operation, if the value on the latch is "1", the voltage on the corresponding bit line will be raised to VDD to prohibit programming; if the value on the latch is "0", the The voltage on its corresponding bit line is set to GND for programming operation.
  • bit line BL(i) Assuming that the initial voltage of all bit lines is GND, the value on the latch corresponding to bit line BL(i) is "1", and the value on the latch corresponding to bit line BL(i-1) is "0 ". Therefore, it is necessary to raise the voltage on the bit line BL(i) to VDD. Firstly, the bit line BL(i) is charged, the voltage on the bit line BL(i) will be precharged from GND to VDD, while the voltage on the adjacent bit line BL(i-1) remains at GND. Because of the coupling effect between the capacitors, the voltage on BL(i-1) will also rise slightly.
  • Figure 3(b) is a waveform diagram when it works abnormally.
  • Fig. 3(b) shows the waveform when the latch value in the page buffer flips abnormally when the bit line is driven.
  • the capacitive load on the bit line BL(i) is large enough, the voltage on the latch node Q decreases by the value ⁇ V(1) so that the logic value on the latch node Q drops below the logic threshold, then the latch node The voltage level on Q flips to a low level. This will cause the voltage on the bit line BL(i) to also go to GND even though the memory cell should be inhibited from programming. At this time, the storage device will be abnormal and cannot work normally.
  • FIG. 4 is a waveform diagram of a method for precharging a bit line provided by the present invention.
  • BL(1) indicates the bit line whose voltage needs to be set to a high voltage
  • BL(0) indicates the bit line whose voltage needs to be set to a low voltage
  • Q(1) indicates that the value on the latch is "1”
  • Q(0) means the value on the latch is "0”.
  • the precharging method provided by the present invention firstly, all bit lines are precharged, that is, the tPRECH phase in FIG. 4 (ie, the T1-T2 time period). During this phase, precharging is performed regardless of whether the value on the latch node Q is 0 or 1.
  • the initial voltage of all bit lines will be changed to a higher value.
  • the precharge control signal PRECH_N is pulled down to a low level GND, and the cut-off control voltage CON is pulled up to a high level VDD.
  • the sensing nodes S0 of all bit lines are pulled up to a high level through the PMOS transistor 221 VDD. Because the voltages between the bit lines are equal at this time, there is no influence of the parasitic capacitance between the bit lines, therefore, the NMOS transistor 222 can pull up the voltages of all the bit lines to VDD-Vt in a short time.
  • the precharge control signal PRECH_N is pulled high, and the cutoff control voltage CON is pulled down to the low level GND.
  • both the PMOS transistor 221 and the NMOS transistor 222 are in the off state, and all the bit lines are floating (floating) , the voltage on all bit lines remains at VDD-Vt.
  • Step 2 Set the bit line voltage according to the value of the latch in the page buffer, if the value on the latch corresponding to the bit line BL(i) is "1", then raise the bit line voltage to a high level Level VDD, and the value on the latch corresponding to the bit line BL(i-1) is "0", then keep the bit line voltage at the low level GND.
  • the voltage on the bit line BL(i) can be controlled, and the voltage on the bit line BL(i) will follow the cut-off control signal CON increases, and has a difference that depends in magnitude on the voltage drop between the cutoff control signal CON and the bit line, which in this embodiment is the threshold voltage of the NMOS transistor 222 Vt.
  • the voltage reduction value ⁇ V(1) on the latch node Q will be significantly reduced.
  • the precharge method provided in the present invention will have more headroom, because in this case, the bit line will be driven by the NMOS transistor 235 in the page buffer, which has a stronger driving ability.
  • the control signal TRAN is pulled up to VDD+Vt, and the NMOS transistor 231 is turned on.
  • the sensing node S0 corresponding to the cell with the value "0" on the latch will be pulled down to GND, and the latch The sensing node S0 corresponding to the cell whose value is “1” on , will still be VDD.
  • the cut-off control voltage CON is pulled up, but its voltage value is less than VDD, and at this time the NMOS transistor 222 corresponding to the bit line will be turned on, and the corresponding NMOS transistor 222 will be quickly turned on.
  • bit line BL(i-1) is pulled down to GND; and for the unit whose value on the latch is "1", the cut-off control voltage CON is still kept at a low level, and the NMOS transistor 222 corresponding to the bit line is still kept Turn off, its corresponding bit line BL(i) is still in a floating state, but because the voltage on its adjacent bit line is pulled down to GND, due to the parasitic capacitance between adjacent bit lines, the bit line The voltage is also pulled down rapidly.
  • the minimum value at which this voltage is pulled down is CON-Vt, because if it is less than this value, NMOS transistor 222 will turn on and pull BL(i) up to CON-Vt.
  • the cut-off control signal CON is a gradually increasing voltage, as shown in Figure 5(a) and Figure 5(b)
  • the gradually increasing voltage shown in where the voltage in Figure 5(a) is a step voltage, and the voltage in Figure 5(b) is an irregularly increasing voltage.
  • the waveform of the cutoff control signal CON is not limited.
  • the cut-off control signal CON is a gradually increasing voltage
  • the voltage on the bit line BL(i) is also a gradually increasing voltage, so that the voltage rise on the bit line BL(i-1) will be segmented and the amplitude is smaller, and thus the voltage reduction value ⁇ V(1) on the latch node Q will also decrease.
  • adopting the precharging method provided in the present invention will reduce the change of the voltage value on the latch node due to the coupling capacitance, and can effectively reduce the influence of the coupling capacitance between the bit lines on the memory device, so that the bit line
  • the memory device can also operate normally when there is a large capacitive load on it.

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Abstract

本发明提供一种预充电方法以及使用该方法的存储器装置。该预充电方法包含以下步骤：步骤1，对所有的位线进行预充电；步骤2，根据页面缓冲器中锁存器的值对位线电压进行设置，其中，当锁存器上的值为"1"时，将与该页面缓存器连接的位线电压升高到高电平；当锁存器上的值为"0"时，将与该页面缓存器连接的位线电压保持为低电平。采用本发明中提供的预充电方法，将会减小因为耦合电容而导致的锁存节点上的电压值的改变，可以有效地减少位线间耦合电容对存储器装置的影响，使得位线上有较大的容性负载时，存储器装置也能正常工作。

Description

一种预充电方法及使用该方法的存储器装置
本申请要求于2022年01月27日提交中国专利局、申请号为202210097610.2、发明名称为“一种预充电方法及使用该方法的存储器装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及一种快闪存储器领域，尤其涉及一种预充电方法以及使用该方法的存储器装置。
背景技术
NAND存储器是一种非易失性存储器，其具有访问速度快、功耗低、体积小等优点，这使其被广泛地用来作为移动设备、笔记本电脑和服务器中的固态硬盘以及其他数据处理系统中的储存介质。
一种已知类型的NAND快闪存储器器件包括存储单元阵列、列解码器和页面缓冲器，其中存储单元阵列包括按行延伸的多个字线、按列延伸的多个位线以及与位线对应的多个单元串。页面缓冲器与位线电性相连，用于在编程期间给位线提供适当的驱动电压。在存取页面数据的存储器操作中，需要对位线充电，如在页面编程算法中，耦接至页面中待编程的存储器单元的位线可被浮置或放电，而耦接至不进行编程存储器单元的位线可在施加编程脉冲之前进行预充电以禁止编程(program inhibit)。一般而言，位线的电压是通过页面缓冲器的锁存数据来定义。举例来说，当页面缓冲器中的锁存数据为0时，位线的电压为GND，当页面缓冲器中的锁存数据为1时，位线的电压为VDD。
在集成电路的发展过程中，小型化和集成化是发展的重要目标。因此，集成电路内部半导体元器件的密度会随之增加，从而使半导体尺寸之间的距离会随之减小，进而使得半导体元件中的用于传导电信号的传导部件之间的距离也相应地缩减，这将直接导致任意两个相邻的传导部件之间所产生的寄生电容增加。随着半导体尺寸的不断缩减，相邻传导部件之间所产生的寄生电容和由寄生电容所带来的干扰越来越严重。具体到NAND快闪存储器，因为存储器内部包括多条位线和多条字线，其中多条位线通常是形成在衬底上并沿着预定方 向平行排布。而随着半导体器件尺寸的不断缩小，相邻的位线之间的间距也逐渐缩短，从而导致相邻的位线之间极易产生较大的寄生电容，且容易出现电容耦合的现象，从而影响半导体存储器的性能。尤其是当位线上的电容负载超过页面缓冲器的锁存驱动能力时，页面缓冲器的锁存数据可能会崩溃。当负载过重的位线连接到页面缓冲器时，页面缓冲器的锁存数据可能会出现翻转，进而影响存储器的正常工作。
因此，亟需设计一种操作存储器装置的方法，可以有效地减少位线间耦合电容对存储器装置的影响，使得位线上有较大的容性负载时，存储器装置也能正常工作。
发明内容
为了解决上述技术问题，本发明提供一种预充电方法，所述预充电方法包括以下步骤：步骤1，对所有的位线进行预充电；步骤2，根据页面缓冲器中锁存器的值对位线电压进行设置，其中，当锁存器上的值为“1”时，将与该页面缓存器连接的位线电压升高到高电平；当锁存器上的值为“0”时，将与该页面缓存器连接的位线电压保持为低电平。
采用本发明中提供的预充电方法，将会减小因为耦合电容而导致的锁存节点上的电压值的改变，可以有效地减少位线间耦合电容对存储器装置的影响，使得位线上有较大的容性负载时，存储器装置也能正常工作。
优选地，在步骤2中对位线预充电到高电平时，通过切断控制电压CON对位线电压进行控制。
优选地，在步骤2中对位线预充电到高电平时，位线上的电压随着切断控制信号CON的增大而增大，切断控制信号CON与位线之间的电压差为晶体管的阈值电压。
优选地，切断控制信号CON的电压为逐渐增大的电压。当切断控制信号CON为逐渐增大的电压时，选择位线BL(i)上的电压也为逐渐增大的电压，这样其相邻的非选择位线BL(i-1)上的电压上升将会分段且幅值较小，进而锁存节点Q上的电压减小值ΔV(1)也会减小。
优选地，切断控制信号CON的电压为步阶式电压。
本发明的另一方面，还提供一种采用该预充电方法的存储器装置，其特征在于，所述存储器装置包括电压源、页面缓冲器、位线和存储单元，所述页面缓冲器电性连接至电压源，并且与存储器装置中的位线连接，通过位线连接至存储器装置中的存储单元；其中，所述页面缓冲器包括锁存器，当锁存器上的值为“1”时，将与该页面缓存器连接的位线预充电到高电平；当锁存器上的值为“0”时，将与该页面缓存器连接的位线保持为低电平。
优选地，所述页面缓冲器包括控制电路和位线驱动电路，所述控制电路用于产生控制信号，所述控制信号用于控制所述位线驱动电路，选择性地对存储器装置中的位线施加编程电压或者禁止编程电压。
优选地，所述位线驱动电路包括位线选择单元、预充电单元以及感测和锁存单元。
附图说明
图1为具有页面缓冲器的NAND存储器装置的示意图。
图2为页面缓冲器的位线驱动电路的电路图。
图3为现有技术中全位线编程操作时各个节点的波形图。其中，图3(a)为正常工作时的波形图；图3(b)为异常工作时的波形图。
图4为本发明提供的对位线进行预充电的波形图。
图5(a)和图5(b)为关断控制信号CON的示意图。
具体实施方式
以下配合图式及本发明的较佳实施例，进一步阐述本发明为达成预定发明目的所采取的技术手段。
请参照图1所示，图1为现有技术中具有页面缓冲器的NAND存储器装置的示意图。在图1中，NAND存储器装置示意图包括电压源VDD、页面缓冲器100、位线102，以及图1中未示出的字线、存储单元等。
页面缓冲器100电性连接至电压源VDD，页面缓冲器100还与存储器装置中的位线BL相连接，通过位线BL连接至存储器装置中的存储单元。页面缓冲器100包括控制电路，其响应于所要存储的数据特征产生该数据特征写入 时的控制信号，进而选择性地对存储器装置中的位线施加编程电压或者禁止编程电压。如在编程操作期间，通过控制电路产生的控制信号，控制位线驱动电路101，提高未被选取位线的位线电压，来增加存储器中被选取位线的操作裕度。页面缓冲器100至少还包括位线驱动电路101，位线驱动电路101根据控制电路产生的控制信号，对存储器装置中的位线施加编程电压或者禁止编程电压。位线驱动电路101包括锁存器电路，在读取操作期间，锁存器用于暂存从存储单元中读取的数据，在编程操作期间，将外部读取的数据存储在锁存器中，随后将这些数据传输至存储单元中。
位线102用于连接页面缓冲器100和存储单元。由于位线102为平行放置的金属线，因此位线之间存在较大的电容，在图1中，用电容103来表示位线之间的电容C BL，假设每个电容的电容值均为C。
在一个较佳的实施例中，位线102也可以通过一个位线钳位晶体管与页面缓冲器100连接，位线钳位晶体管通过位线控选择信号CON_BL控制其开闭，只要位线选择信号CON_BL大于临界电压(其大于充电中的位线的电压)，位线钳位晶体管将电流传递至对应的位线。
在全位线程序执行过程中，每个位线均由页面缓冲器驱动，当BL(i)上的电压为VDD，而BL(i-1)和BL(i+1)上的电压均为GND时，此时BL(i)上的有效电容将达到最大，为2C。在对位线BL(i)进行赋值的过程中，较大的电容值可能会对锁存器上的电压造成影响，甚至会使锁存器上的数据翻转。
图2为页面缓冲器100的位线驱动电路101的电路图。如图2中所示，页面缓冲器100的位线驱动电路101包括位线选择单元21、预充电单元22以及感测和锁存单元23。位线选择单元21用于选择所要感测的位线BL。预充电单元22用于在编程操作之前为被选位线BL预充电以及为感测节点S0预充电。NAND闪速存储器主要包含三个动作：读出、编程和擦除。感测节点S0设置在预充电单元21中并连接到感测和锁存单元23。感测和锁存单元23包括用于存储数据值的锁存器239，。一逻辑值呈现在锁存器239的节点Q上，当进行读出操作时，在锁存节点Q上呈现的逻辑值可根据在感测节点S0上呈现的电压的电平改变，而感测节点S0的电压电平随单元的编程或擦除状态而改变。也就是说，在单元被编程的情况下，感测节点S0保持高电压电平，而在单元 被擦除的情况下，感测节点S0被放电到低电压电平。锁存节点Q在正常读出操作期间输出在锁存节点Q上呈现的逻辑值，因此锁存节点Q可起到输出节点的作用。当锁存节点Q上呈现逻辑值“1”时，页面缓冲器100被设置为禁止编程(program inhibit)操作模式；当锁存节点Q上呈现逻辑值“0”时，页面缓冲器100被设置为编程操作模式。
位线选择单元21包括1个NMOS晶体管211，NMOS晶体管211响应于位线选择信号CON_BL而选择将在其上执行操作的位线，位线选择信号CON_BL施加到NMOS晶体管211的栅极，被选位线电连接到预充电单元21以及感测和锁存单元22。
预充电单元22包括PMOS晶体管221，NMOS晶体管222和223。PMOS晶体管221设置在电源电压VDD和感测节点S0之间，并且响应于预充电控制信号PRECH_N而导通或者截止。当PMOS晶体管221导通时，位线BL通过电源电压VDD而被预充电到预定电平。NMOS晶体管222设置于位线选择电路21和感测节点S0之间。NMOS晶体管222响应于切断控制信号CON而导通或者截止。NMOS晶体管222用于将位线BL和感测节点S0电隔离。NMOS晶体管223设置于位线选择电路21和电源VSS之间。NMOS晶体管223响应于放电控制信号DIS。当NMOS晶体管223导通时，位线BL通过被加压到VSS。
感测和锁存单元23包括用于存储在读取操作期间读取的数据和将被编程的数据的锁存器239。锁存器239包括两个反相器，他们输出互为相反的数据值。锁存节点Q和Q_N被分别设置在两个反相器的输出端口。反相器由NMOS晶体管和POMS晶体管组成，每个反相器中的NMOS晶体管和POMS晶体管栅极相连作为输入端，漏极相连作为输出端，NMOS晶体管的源级接地，PMOS晶体管的源级连接电源VDD。在锁存器239中，其包括由NMOS晶体管233和PMOS晶体管232组成的反相器，以及包括由NMOS晶体管235和PMOS晶体管234组成的反相器，锁存节点Q和Q_N被分别设置在两个反相器的输出端口。
NMOS晶体管231设置在锁存节点Q和感测节点S0之间，并且响应于控制信号TRAN，在编程操作期间，将锁存节点Q上的逻辑值(即存储在锁存器239中的数据)传输到被选位线BL。控制信号TRAN在编程操作期间被激 活，在这期间存储在锁存器239中的数据被传送到位线BL。如果在编程操作期间呈现在锁存节点Q上的逻辑值为“1”，则编程操作被禁止。因此，锁存器239被初始化，以便呈现在锁存节点Q上的逻辑值为“1”。
NMOS晶体管237的源级连接到锁存节点Q，并且NMOS晶体管236的源级连接到锁存节点Q_N。在读操作期间，NMOS晶体管237响应于控制信号RST而提供感测路径。在正常读操作的感测时段期间，控制信号RST被激活到逻辑高电平。响应于控制信号SET，NMOS晶体管236初始化锁存器239以便呈现在锁存节点Q和Q_N上的逻辑值分别为“1”和“0”。控制信号SET在页面缓冲器设置期间被激活到逻辑高电平以初始化锁存器239。
NMOS晶体管238连接到NMOS晶体管236和237的端子，其栅极连接到感测节点S0。NMOS晶体管238在感测时段期间选择性地导通。例如，如果在感测期间呈现在感测节点S0上的电压电平是逻辑高电平(即被选存储单元是已编程的)，则NMOS晶体管238导通。如果在感测时段期间在感测节点S0上呈现的电压电平是逻辑低电平(即被选存储单元是已擦除)，则NMOS晶体管238截止。
图3为现有技术中全位线编程操作时各个节点的波形图。在图3中，BL(1)表示电压需要设置为高电压的位线，BL(0)表示电压需要设置为低电压的位线；Q(1)表示锁存器上的值为“1”，Q(0)表示锁存器上的值为“0”。图3(a)为正常工作时的波形图。在编程操作时，若锁存器上的值为“1”，则将其对应的位线上的电压上升至VDD，用于禁止编程；若锁存器上的值为“0”，则将其对应位线上的电压设置为GND，用于编程操作。假设所有位线的初始电压均为GND，位线BL(i)对应的锁存器上的值为“1”，而位线BL(i-1)对应的锁存器上的值为“0”。因此，需要将位线BL(i)上的电压上升至VDD。首先对位线BL(i)进行充电，则位线BL(i)上的电压将从GND预充电至VDD，而与其相邻的位线BL(i-1)上的电压仍保持为GND。因为电容之间的耦合作用，BL(i-1)上的电压也会出现略微上升的现象。当锁存节点Q上的电压电平为高电平时，由于其电性连接至位线BL(i)，BL(i)具有较大的电容负载且其初始电压为GND，因此，在预充电期间，锁存节点Q上的电压将会减小，记其电压减小值为ΔV(1)。与之相对应，锁存节点Q_N上的电压值将会增大，记其电压增大值为ΔV(0)。由于锁存器中的PMOS晶体 管234和NMOS晶体管235面积大小较为接近，因而PMOS晶体管234的电流驱动能力较小。因此，锁存节点Q上的电压减小值ΔV(1)将比锁存节点Q_N上的电压减小值ΔV(0)大得多。在图3(a)中，锁存节点Q上的电压减小值ΔV(1)尚未使锁存节点Q上的逻辑值下降到逻辑阈值以下，因此，此时该存储装置仍然能正常工作。
图3(b)为异常工作时的波形图。在图3(b)中，显示了在驱动位线时，页面缓冲器中锁存值异常翻转时的波形。当位线BL(i)上的电容负载足够大，使得锁存节点Q上的电压减小值ΔV(1)使锁存节点Q上的逻辑值下降到逻辑阈值以下，则此时锁存节点Q上的电压电平翻转为低电平。这将导致位线BL(i)上的电压也变为GND，即使该存储单元应该被禁止编程。此时，该存储装置将会发生异常不能正常工作。
图4为本发明提供的对位线进行预充电方法的波形图。在图4中，BL(1)表示电压需要设置为高电压的位线，BL(0)表示电压需要设置为低电压的位线；Q(1)表示锁存器上的值为“1”，Q(0)表示锁存器上的值为“0”。本发明提供的预充电方法中，首先，对于所有的位线均进行预充电，即图4中的tPRECH阶段(即T1-T2时间段)。在此阶段中，无论锁存器节点Q上的值为0或者为1，均进行预充电。通过将所有的位线均充电到VDD-Vt，将使得所有位线的初始电压更改为更高的值。在T1时刻，预充电控制信号PRECH_N拉低至低电平GND，切断控制电压CON拉高至高电平VDD，此时，通过PMOS晶体管221将所有位线的感测节点S0均拉高至高电平VDD。因为此时位线之间的电压均相等，不存在位线间寄生电容的影响，因此，NMOS晶体管222可将所有位线的电压在短时间内拉高至VDD-Vt。在T2时刻，将预充电控制信号PRECH_N拉高，将切断控制电压CON拉低至低电平GND，此时PMOS晶体管221和NMOS晶体管222均处于关闭状态，所有的位线均浮置(floating)，所有位线上的电压仍然维持在VDD-Vt。
步骤二，根据页面缓冲器中锁存器的值对位线电压进行设置，位线BL(i)对应的锁存器上的值为“1”，则将其位线电压升高到高电平VDD，而位线BL(i-1)对应的锁存器上的值为“0”，则保持其位线电压为低电平GND。如图4中T3-T6时间段内，通过控制NMOS晶体管222上的切断控制电压CON，可以控制位线BL(i)上的电压，位线BL(i)上的电压将随着切断控制信号 CON的增大而增大，并且具有在大小上取决于切断控制信号CON与位线之间的电压降的差值，在该实施例中，该电压降的差值为NMOS晶体管222的阈值电压Vt。
与图3(a)中的现有技术相比，锁存节点Q上的电压减小值ΔV(1)将会显著减小。与之前的方法相比，本发明中提供的预充电方法将会有更多的余量，因为在这种情况下，位线将是由页面缓冲器中的NMOS晶体管235驱动，其具有更强的驱动能力。
在T3时刻，控制信号TRAN拉高至VDD+Vt，NMOS晶体管231打开，此时，锁存器上的值为“0”的单元对应的感应节点S0将被拉低至GND，而锁存器上的值为“1”的单元对应的感应节点S0将仍然为VDD。在T4时刻，对于锁存器上的值为“0”的单元，切断控制电压CON拉高，但是其电压值小于VDD，此时该位线对应的NMOS晶体管222将打开，迅速将其对应的位线BL(i-1)拉低至GND；而对于锁存器上的值为“1”的单元，切断控制电压CON仍保持低电平，此时该位线对应的NMOS晶体管222仍然保持关闭，其对应的位线BL(i)仍然处于浮置状态，但是因为其相邻的位线上的电压被拉低至GND，由于相邻的位线之间存在寄生电容，该位线上的电压也被迅速拉低。该电压被拉低的最小值为CON-Vt，因为若小于该值，则NMOS晶体管222将打开，并将BL(i)拉高至CON-Vt。
为了进一步地降低锁存节点Q上的电压减小值ΔV(1)，在T5-T6时间段内，切断控制信号CON为逐渐增大的电压，如图5(a)和图5(b)中所示的逐渐增大的电压，其中图5(a)中的电压为步阶式电压，图5(b)中的电压为非规则增大的电压。在本发明中，并不限制切断控制信号CON的波形。当切断控制信号CON为逐渐增大的电压时，位线BL(i)上的电压也为逐渐增大的电压，这样位线BL(i-1)上的电压上升将会分段且幅值较小，进而锁存节点Q上的电压减小值ΔV(1)也会减小。
因此，采用本发明中提供的预充电方法，将会减小因为耦合电容而导致的锁存节点上的电压值的改变，可以有效地减少位线间耦合电容对存储器装置的影响，使得位线上有较大的容性负载时，存储器装置也能正常工作。
以上所述仅是本发明的优选实施例而已，并非对本发明做任何形式上的限制，虽然本发明已以优选实施例揭露如上，然而并非用以限定本发明，任何熟 悉本专业的技术人员，在不脱离本发明技术方案的范围内，当可利用上述揭示的技术内容作出些许更动或修饰为等同变化的等效实施例，但凡是未脱离本发明技术方案的内容，依据本实用发明的技术实质对以上实施例所作的任何简单修改、等同变化与修饰，均仍属于本发明技术方案的范围内。

Claims (8)

  1. 一种预充电方法，其特征在于，所述预充电方法包括以下步骤：
    步骤1，对所有的位线进行预充电；
    步骤2，根据页面缓冲器中锁存器的值对位线电压进行设置，其中，当锁存器上的值为“1”时，将与该页面缓存器连接的位线电压升高到高电平；当锁存器上的值为“0”时，将与该页面缓存器连接的位线电压保持为低电平。
  2. 根据权利要求1中所述的预充电方法，其特征在于，在步骤2中对位线预充电到高电平时，通过切断控制电压CON对位线电压进行控制。
  3. 根据权利要求2中所述的预充电方法，其特征在于，在步骤2中对位线预充电到高电平时，位线上的电压随着切断控制信号CON的增大而增大，切断控制信号CON与位线之间的电压差为晶体管的阈值电压。
  4. 根据权利要求2或权利要求3中所述的预充电方法，其特征在于，切断控制信号CON的电压为逐渐增大的电压。
  5. 根据权利要求4中所述的预充电电压，其特征在于，切断控制信号CON的电压为步阶式电压。
  6. 一种采用权利要求1中所述预充电方法的存储器装置，其特征在于，所述存储器装置包括电压源、页面缓冲器、位线和存储单元，
    所述页面缓冲器电性连接至电压源，并且与存储器装置中的位线连接，通过位线连接至存储器装置中的存储单元；其中，所述页面缓冲器包括锁存器，当锁存器上的值为“1”时，将与该页面缓存器连接的位线预充电到高电平；当锁存器上的值为“0”时，将与该页面缓存器连接的位线保持为低电平。
  7. 根据权利要求6中所述的存储器装置，其特征在于，所述页面缓冲器包括控制电路和位线驱动电路，所述控制电路用于产生控制信号，所述控制信号用于控制所述位线驱动电路，选择性地对存储器装置中的位线施加编程电压或者禁止编程电压。
  8. 根据权利要求7中所述的存储装置，其特征在于，所述位线驱动电路包括位线选择单元、预充电单元以及感测和锁存单元。
PCT/CN2022/119200 2022-01-27 2022-09-16 一种预充电方法及使用该方法的存储器装置 WO2023142495A1 (zh)

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CN101149969A (zh) * 2006-08-10 2008-03-26 富士通株式会社 半导体存储器和存储器系统
CN101211660A (zh) * 2006-12-28 2008-07-02 海力士半导体有限公司 非易失性存储装置以及对其中的多级单元进行编程的方法
US20080205138A1 (en) * 2007-02-22 2008-08-28 Hynix Semiconductor Inc. Memory device and method of operating the same
CN114512162A (zh) * 2022-01-27 2022-05-17 东芯半导体股份有限公司 一种预充电方法及使用该方法的存储器装置

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CN101149969A (zh) * 2006-08-10 2008-03-26 富士通株式会社 半导体存储器和存储器系统
CN101211660A (zh) * 2006-12-28 2008-07-02 海力士半导体有限公司 非易失性存储装置以及对其中的多级单元进行编程的方法
US20080205138A1 (en) * 2007-02-22 2008-08-28 Hynix Semiconductor Inc. Memory device and method of operating the same
CN114512162A (zh) * 2022-01-27 2022-05-17 东芯半导体股份有限公司 一种预充电方法及使用该方法的存储器装置

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