WO2023137836A1 - 半导体结构的制作方法及半导体结构 - Google Patents

半导体结构的制作方法及半导体结构 Download PDF

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Publication number
WO2023137836A1
WO2023137836A1 PCT/CN2022/079329 CN2022079329W WO2023137836A1 WO 2023137836 A1 WO2023137836 A1 WO 2023137836A1 CN 2022079329 W CN2022079329 W CN 2022079329W WO 2023137836 A1 WO2023137836 A1 WO 2023137836A1
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layer
initial
region
gate structure
barrier layer
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PCT/CN2022/079329
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English (en)
French (fr)
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王蒙蒙
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长鑫存储技术有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/82345—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/20—DRAM devices comprising floating-body transistors, e.g. floating-body cells

Definitions

  • the present disclosure relates to but not limited to a method for fabricating a semiconductor structure and the semiconductor structure.
  • DRAM Dynamic Random Access Memory
  • MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor
  • transistors of different conductivity types are usually formed in the same process, and the process heights of transistors of different conductivity types are different. It is often the case that some structures are under-etched while other structures are over-etched, which reduces the electrical performance and reliability of the transistor.
  • the disclosure provides a method for manufacturing a semiconductor structure and the semiconductor structure.
  • a first aspect of the present disclosure provides a manufacturing method of a semiconductor structure, the manufacturing method comprising: providing a substrate, the substrate including a first region and a second region;
  • the first device including a first gate structure, the first gate structure including a first work function layer;
  • the second device including a second gate structure, the second gate structure including a second work function layer;
  • the top surface of the first gate structure is flush with the top surface of the second gate structure.
  • the manufacturing method includes:
  • the stack structure including a first stack portion located in the first area and a second stack portion located in the second area;
  • the first stacked portion and the second stacked portion are of equal height.
  • the forming a stack structure on the substrate includes:
  • An initial gate dielectric layer is respectively formed on the first region and the second region of the substrate, the initial gate dielectric layer includes an initial oxide layer and an initial high-K dielectric layer, and the initial high-K dielectric layer is formed on a top surface of the initial oxide layer.
  • the forming a stack structure on the substrate further includes:
  • an initial first barrier layer, an initial first work function layer, and an initial second barrier layer are sequentially stacked on the top surface of the initial high-K dielectric layer;
  • the forming a stack structure on the substrate further includes:
  • the etch barrier layer includes an oxide layer and a nitride layer
  • the etch stop layer formed above the second region is removed, leaving the etch stop layer formed above the first region.
  • the forming a stack structure on the substrate further includes:
  • initial second work function layer covering the top surface of the initial high-K dielectric layer and the top surface of the etch stop layer located above the second region;
  • the initial second work function layer, the initial third barrier layer and the etching barrier layer formed above the first region are removed, and the initial second work function layer and the initial third barrier layer formed above the second region remain.
  • the top surface of the initial second barrier layer is flush with the top surface of the initial third barrier layer.
  • the forming a stack structure on the substrate further includes:
  • An initial metal layer and an initial isolation layer are sequentially stacked on the top surface of the initial second barrier layer and the top surface of the initial third barrier layer.
  • the forming a stack structure on the substrate further includes:
  • An initial semiconductor layer and an initial fourth barrier layer are formed, the semiconductor layer and the initial fourth barrier layer are sequentially stacked between the initial second barrier layer and the initial metal layer above the first region, and sequentially stacked between the initial third barrier layer and the initial metal layer above the second region.
  • the manufacturing method further includes:
  • a mask layer is formed on the surface of the isolation layer, and the stack structure is etched through the mask layer to form the first gate structure and the second gate structure.
  • the manufacturing method further includes:
  • Ion implantation is performed on the second regions on both sides of the second gate structure to form a second source region and a second drain region.
  • a second aspect of the present disclosure provides a semiconductor structure comprising:
  • a substrate comprising a first region and a second region
  • the first device is disposed in the first region, the first device includes a first gate structure, and the first gate structure includes a first work function layer;
  • the second device is disposed in the second region, the second device includes a second gate structure, the second gate structure includes a second work function layer;
  • the top surfaces of the first gate structure and the second gate structure are flush.
  • the first gate structure includes a first gate dielectric layer, a first barrier layer, a first work function layer, a second barrier layer, a first metal layer, and a first isolation layer sequentially stacked on the first region;
  • the second gate structure includes a second gate dielectric layer, a second work function layer, a third barrier layer, a second metal layer, and a second isolation layer sequentially stacked on the second region;
  • the top surface of the second barrier layer is flush with the top surface of the third barrier layer.
  • the first gate structure further includes: a first semiconductor layer and a first and fourth barrier layer sequentially stacked between the second barrier layer and the first metal layer.
  • the second gate structure further includes: a second semiconductor layer and a second and fourth barrier layer sequentially stacked between the third barrier layer and the second metal layer.
  • the first device further includes: a first source region, a first drain region, and a first channel region, the first source region and the first drain region are respectively located on both sides of the first gate structure, and the first channel region is disposed below the first gate structure;
  • the second device further includes: a second source region, a second drain region and a second channel region, the second source region and the second drain region are respectively located on two sides of the second gate structure, and the second channel region is disposed below the second gate structure.
  • the first gate structure of the first device and the second gate structure of the second device are formed in the same etching process, and the process heights of the first gate structure and the second gate structure are equal, which reduces the process difficulty of forming the first gate structure and the second gate structure, and improves the yield and reliability of the semiconductor structure.
  • Fig. 1 is a flow chart of a method for fabricating a semiconductor structure according to an exemplary embodiment.
  • Fig. 2 is a flow chart of a method for fabricating a semiconductor structure according to an exemplary embodiment.
  • FIG. 3 is a schematic diagram of a substrate shown in accordance with an exemplary embodiment.
  • FIG. 4 is a schematic diagram of forming a gate dielectric layer according to an exemplary embodiment.
  • Fig. 5 is a schematic diagram of forming a first barrier layer, a first work function layer and a second barrier layer stacked in sequence on a high-K dielectric layer according to an exemplary embodiment.
  • FIG. 6 is a schematic diagram of forming a first photoresist mask according to an exemplary embodiment.
  • FIG. 7 is a schematic diagram of removing the first barrier layer, the first work function layer and the second barrier layer above the second region according to an exemplary embodiment.
  • FIG. 8 is a schematic diagram of forming an etch stop layer according to an exemplary embodiment.
  • FIG. 9 is a schematic diagram of forming a second photoresist mask on the etch stop layer above the first region according to an exemplary embodiment.
  • FIG. 10 is a schematic diagram of removing the etch stop layer above the second region according to an exemplary embodiment.
  • FIG. 11 is a schematic diagram of forming a second work function layer and a third work function layer according to an exemplary embodiment.
  • FIG. 12 is a schematic diagram of forming a third photoresist mask according to an exemplary embodiment.
  • FIG. 13 is a schematic diagram of forming a second work function layer and a third work function layer over the second region according to an exemplary embodiment.
  • FIG. 14 is a schematic diagram of removing the etch stop layer above the first region according to an exemplary embodiment.
  • FIG. 15 is a schematic diagram of forming a metal layer according to an exemplary embodiment.
  • FIG. 16 is a schematic diagram of a stack structure formed in accordance with an exemplary embodiment.
  • FIG. 17 is a schematic diagram of forming a mask layer on a stack structure according to an exemplary embodiment.
  • FIG. 18 is a schematic diagram of forming a fourth photoresist mask according to an exemplary embodiment.
  • FIG. 19 is a schematic diagram of forming a first gate structure and a second gate structure according to an exemplary embodiment.
  • FIG. 20 is a schematic diagram of forming a first device and a second device according to an exemplary embodiment.
  • FIG. 21 is a schematic diagram of a stack structure formed in accordance with an exemplary embodiment.
  • FIG. 22 is a schematic diagram of forming a mask layer on a stack structure according to an exemplary embodiment.
  • FIG. 23 is a schematic diagram of a first gate structure and a second gate structure formed in accordance with an exemplary embodiment.
  • FIG. 24 is a schematic diagram of a first device and a second device formed in accordance with an exemplary embodiment.
  • First light engraving film mask 20. Cutting the blocking layer; 21. Oxide layer; 22, nitride layer; 30, second light engraving glue mask; 40, third light engraving glue mask; 50, fourth light engraving glue mask; 100, substrate; 110, first region; 200, first components; 210, first grid structure; Extremely aggressive electrical layer; 2111, first oxide layer; 2112, the first high K medium layer; 213, the first blocking layer; 213, the first function function layer; 214, the second blocking layer; 215, the first metal layer; 216, the first isolated layer; 217, the first half of the conductor layer; 218, the fourth blocking layer; Dao District; 300, second device; 310, second grid structures; 311, second grid polar aggressive layers; 3111, second oxidation layer; 3112, second high K media layer; 312, secondary function layer; 313, third blocking layer; 314, secondary isolation layer; 316, second semiconductor layer; 32 fourth blocking layer; 0, the second source area; 330, the second leakage area; 340, the second channel area; 400, stacking structure;
  • An exemplary embodiment of the present disclosure provides a method for fabricating a semiconductor structure.
  • a stacked structure is formed above the two regions.
  • the heights of the stacked parts corresponding to the two regions in the stacked structure are equal, and the stacked parts corresponding to the two regions in the stacked structure include work function layers corresponding to the respective regions.
  • Etching the stacked structure forms a gate structure on the two regions. Yield and reliability of semiconductor structures.
  • This embodiment does not limit the semiconductor structure.
  • the following will introduce the semiconductor structure as a dynamic random access memory (DRAM) as an example, but this embodiment is not limited thereto.
  • the semiconductor structure in this embodiment may also be other structures.
  • 3-24 are schematic diagrams of the structures formed in various stages of the manufacturing method of the semiconductor structure. The manufacturing method of the semiconductor structure in this embodiment will be introduced below with reference to FIGS. 3-24 .
  • a method for fabricating a semiconductor structure includes the following steps:
  • Step S110 providing a substrate, the substrate includes a first region and a second region.
  • the substrate 100 may be a semiconductor substrate, and the semiconductor substrate may include a silicon substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, an SOI (Silicon-on-insulator, silicon-on-insulator) substrate or a GOI (Germanium-on-Insulator, germanium-on-insulator) substrate, etc.
  • the semiconductor substrate can be doped with ions, for example, the semiconductor substrate can be a P-type doped substrate, or an N-type doped substrate.
  • the substrate 100 is a silicon substrate.
  • At least one first region 110 is provided in the substrate 100, and the first region 110 is a P-type conductive doped region, and at least one second region 120 is provided in the substrate 100, and the second region 120 is an N-type conductive doped region.
  • the substrate 100 is a P-type doped substrate or an N-type doped substrate, the doping concentration of dopant ions in the first region 110 and the second region 120 is greater than that in the rest of the substrate 100 .
  • the substrate 100 is provided with a plurality of first regions 110 and a plurality of second regions 120 , wherein the numbers of the first regions 110 and the second regions 120 may be equal or different.
  • Step S120 forming a first device on the first region, forming a second device on the second region, the first device includes a first gate structure, the second device includes a second gate structure, and the top surface of the first gate structure is flush with the top surface of the second gate structure.
  • the first gate structure 210 of the first device 200 and the second gate structure 310 of the second device 300 are formed by etching the stacked structure 400 on the substrate 100 . Perform an etching process on the stacked structure 400 to form the first gate structure 210 and the second gate structure 310 at the same time. In this etching process, the height of the first gate structure 210 formed by etching the first stacked part 401 is equal to the height of the second gate structure 310 formed by etching the second stacked part 402.
  • the etching speed of the first gate structure 210 and the second gate structure 310 are equal, and the first gate structure 210 and the second gate structure 310 are formed simultaneously, and The first gate structure 210 and the second gate structure 310 are of the same height.
  • the first gate structure 210 includes a first work function layer 213
  • the second gate structure 310 includes a second work function layer 312
  • the first device 200 is a PMOS
  • the first work function layer 213 is a P-type work function layer formed according to the conductivity type of the first region 110
  • the second device 300 is NMOS
  • the second work function layer 312 is an N-type work function layer formed according to the conductivity type of the second region 120 .
  • the first gate structure 210 includes the first work function layer 213 but does not include the second work function layer 312, and the second gate structure 310 includes the second work function layer 312 but does not include the first work function layer 213.
  • the top surfaces of the first gate structure 210 and the second gate structure 310 are aligned.
  • the first gate structure 210 includes a first work function layer 213 and a second work function layer 312
  • the second gate structure 310 also includes a first work function layer 213 and a second work function layer 312, so that the first gate structure 210 and the second gate structure 310 have the same number of layers and the same thickness of each layer, ensuring that the top surfaces of the first gate structure 210 and the second gate structure 310 are flush.
  • the first gate structure and the second gate structure can be formed in the same etching process, the etching height for forming the first gate structure is equal to the process height for etching the second gate structure, the first gate structure and the second gate structure are formed simultaneously, and the formed first gate structure and the second gate structure have the same morphology.
  • the process heights of the first gate structure and the second gate structure are different, resulting in one of them being etched and formed, while the other is still in the etching process, and the etching time is difficult to control, resulting in the problem of under-etching or over-etching of the first gate structure and/or the second gate structure.
  • the forming method of this embodiment reduces the process difficulty of forming the first gate structure and the second gate structure, improves the control precision of etching to form the first gate structure and the second gate structure, and improves the yield and reliability of the formed semiconductor structure.
  • an exemplary embodiment of the present disclosure provides a method for manufacturing a semiconductor structure. As shown in FIG. 2, a method for fabricating a semiconductor structure provided by an exemplary embodiment of the present disclosure includes the following steps:
  • Step S210 providing a substrate, the substrate including a first region and a second region.
  • step S210 in this embodiment is the same as that of step S110 in the foregoing embodiment, and will not be repeated here.
  • Step S220 forming a stacked structure on the substrate, the stacked structure includes a first stacked portion located in the first area and a second stacked portion located in the second area, the first stacked portion and the second stacked portion have the same height.
  • the time for forming the first stacked part and the second stacked part is not specifically limited.
  • the first stacked part may be formed first, or the second stacked part may be formed first, or part of the first stacked part may be formed first, and then part of the structure in the second stacked part may be formed, and then the remaining structures in the first stacked part may be formed, and then the rest of the structures in the second stacked part may be formed.
  • step S220 may include the following steps:
  • Step S221 Form an initial gate dielectric layer on the first region and the second region of the substrate respectively, the initial gate dielectric layer includes an initial oxide layer and an initial high-K dielectric layer, and the initial high-K dielectric layer is formed on the top surface of the initial oxide layer.
  • an initial oxide layer 411 is formed on the surface of the substrate 100 by an in-situ steam generation (In-Situ Steam Generation, ISSG) process.
  • the material of the initial oxide layer 411 may include silicon oxide or silicon oxynitride.
  • the material of the initial oxide layer 411 is silicon oxide.
  • an initial high-K dielectric layer 412 is formed on the top surface of the initial oxide layer 411 by a deposition process, and the initial high-K dielectric layer 412 covers the initial oxide layer 411.
  • the material of the initial high-K dielectric layer 412 is a dielectric material with a high dielectric constant.
  • the material of the initial high-K dielectric layer 412 includes hafnium metal or hafnium compound.
  • the material of the initial high-K dielectric layer 412 may include one or more of hafnium oxide (HfO), hafnium silicon oxide (HfSiO), hafnium aluminum oxide (HfAlO) or hafnium tantalum oxide (HfTaO).
  • hafnium oxide HfO
  • hafnium silicon oxide HfSiO
  • hafnium aluminum oxide HfAlO
  • hafnium tantalum oxide hafnium tantalum oxide
  • the initial oxide layer 411 and the initial high-K dielectric layer 412 together constitute the initial gate dielectric layer 410 , and when the material of the initial oxide layer 411 is silicon oxide, its dielectric constant is 3.9. When the material of the initial high-K dielectric layer 412 is hafnium, its dielectric constant is about 25.
  • the thickness of the initial high-K dielectric layer formed in the semiconductor structure is thicker, increasing the thickness of the initial gate dielectric layer 410, reducing the tunneling problem of the first gate structure 210 and the second gate structure 310 formed subsequently, and reducing the leakage current of the first gate structure 210 and the second gate structure 310.
  • Step S222 forming an initial first barrier layer, an initial first work function layer, and an initial second barrier layer stacked in sequence above the first region.
  • an initial first barrier layer 420, an initial first work function layer 430, and an initial second barrier layer 440 are sequentially stacked on the top surface of the initial high-K dielectric layer 412 through any of the above deposition processes, wherein the material of the initial first barrier layer 420 may include titanium nitride, and the material of the initial second barrier layer 440 may include titanium nitride.
  • the first region 110 is a P-type doped region
  • the first device 200 is a PMOS
  • the initial first work function layer 430 is a P-type work function layer corresponding to the first region 110 .
  • the material of the initial first work function layer 430 includes aluminum or an aluminum compound, wherein the aluminum compound may be, for example, aluminum nitride. Since the material of the initial first work function layer 430 is soluble in the material of the initial high-K dielectric layer 412, and the material of the initial first work function layer 430 is also soluble in the metal material of the subsequently formed initial metal layer 470, in this embodiment, an initial first barrier layer 420 is formed on the bottom surface of the initial first work function layer 430 to prevent the materials in the initial first work function layer 430 from diffusing into the initial high-K dielectric layer 412, and on the top of the initial first work function layer 430 A second barrier layer 440 is formed on the surface to prevent the material in the initial first work function layer 430 from diffusing into the subsequently formed initial metal layer 470 .
  • a first photoresist mask 10 is formed on the top surface of the initial second barrier layer 440 , the first photoresist mask 10 covers the initial second barrier layer 440 above the first region 110 , and the first photoresist mask 10 exposes the initial second barrier layer 440 above the second region 120 . As shown in FIG. 6 , referring to FIG. 5 , a first photoresist mask 10 is formed on the top surface of the initial second barrier layer 440 , the first photoresist mask 10 covers the initial second barrier layer 440 above the first region 110 , and the first photoresist mask 10 exposes the initial second barrier layer 440 above the second region 120 . As shown in FIG.
  • the initial second barrier layer 440, the initial first work function layer 430 and the initial second barrier layer 440 are etched layer by layer, the initial first barrier layer 420, the initial first work function layer 430 and the initial second barrier layer 440 formed above the second region 120 are removed, and the initial first barrier layer 420, initial first work function layer 430 and initial second barrier layer 440 formed above the first region 110 are retained. That is, only the initial first barrier layer 420, initial first work function layer 430, and initial second barrier layer 440 above the first region 110 remain, and the initial first barrier layer 420, initial first work function layer 430, and initial second barrier layer 440 at other positions are all etched away.
  • Step S223 sequentially forming an initial second work function layer and an initial third barrier layer above the second region.
  • an etch stop layer 20 needs to be formed above the first region 110 .
  • an etch stop layer 20 is simultaneously formed on the top surface of the initial second barrier layer 440 above the first region 110 and on the top surface of the initial high-K dielectric layer 412 above the second region 120, wherein the etch stop layer 20 includes an oxide layer 21 and a nitride layer 22.
  • the etch stop layer 20 formed above the second region 120 is removed, and the etch stop layer 20 formed above the first region 110 remains.
  • an oxide layer 21 may be first formed by a chemical vapor deposition process or a physical vapor deposition process.
  • the oxide layer 21 covers the top surface of the initial second barrier layer 440 and the exposed top surface of the initial high-K dielectric layer 412, wherein the material of the oxide layer 21 includes silicon oxide or silicon oxynitride.
  • the material of the oxide layer 21 has a high etching selectivity ratio relative to the material of the initial second barrier layer 440, so that the oxide layer 21 is subsequently etched away from the initial second barrier layer 440, preventing the initial second barrier layer 440 from being removed by the etching process, and retaining the initial second barrier layer 440 to block the diffusion of the material of the initial first work function layer 430.
  • a nitride layer 22 may be formed on the top surface of the oxide layer 21 by a chemical vapor deposition process or a physical vapor deposition process, wherein the material of the nitride layer 22 includes silicon nitride.
  • a second photoresist mask 30 is formed on the top surface of the nitride layer 22 above the first region 110 .
  • the nitride layer 22 and the oxide layer 21 exposed outside the second photoresist mask 30 are sequentially removed through a dry etching or wet etching process, the nitride layer 22 and the oxide layer 21 above the first region 110 remain, and the etch stop layer 20 above the first region 110 remains.
  • an initial second work function layer 450 is then formed above the second region, and the initial second work function layer 450 covers the top surface of the initial high-K dielectric layer 412 above the second region 120 and the top surface of the etch stop layer 20.
  • an initial third barrier layer 460 is formed on the top surface of the initial second work function layer 450 , and the initial third barrier layer 460 covers the entire initial second work function layer 450 .
  • the initial second work function layer 450 and the initial third barrier layer 460 may be formed by chemical vapor deposition or atomic layer deposition.
  • a third photoresist mask 430 is formed on the top surface of the initial third barrier layer 460 located above the second region 120 .
  • the initial third barrier layer 460 and the initial second work function layer 450 formed above the first region 110 are sequentially removed layer by layer, and the initial second work function layer 450 and the initial third barrier layer 460 formed above the second region 120 remain.
  • all the etching stopper layer 20 is removed through a dry etching process or a wet etching process, exposing the top surface of the initial second barrier layer 440 .
  • an initial first barrier layer 420 , an initial first work function layer 430 , and an initial second barrier layer 440 are stacked above the first region 110
  • an initial second work function layer 450 and an initial third barrier layer 460 are sequentially stacked above the second region 120 .
  • the time for depositing the initial second work function layer 450 and the initial third barrier layer 460 can be adjusted so that the top surface of the initial third barrier layer 460 is flush with the top surface of the initial second barrier layer 440 .
  • the total thickness of the initial second work function layer 450 and the initial third barrier layer 460 formed on the second region 120 is equal to the total thickness of the initial first barrier layer 420, the initial first work function layer 430 and the initial second barrier layer 440 formed on the first region 110.
  • the second region 120 is an N-type conductive doped region
  • the second device 300 is an NMOS
  • the initial second work function layer 450 is an N-type work function layer corresponding to the second region 120 .
  • the material of the initial second work function layer 450 includes metal lanthanum (Lanthanum) or a lanthanum compound.
  • the lanthanum compound may be lanthanum hexaboride (Lanthanum boride).
  • an initial third barrier layer 460 is formed on the top surface of the initial second work function layer 450.
  • the initial third barrier layer 460 can prevent the material of the initial second work function layer 450 from dissolving into the initial metal layer 470 formed in the subsequent fabrication, so as to prevent the initial second work function layer from being dissolved in the subsequent process.
  • the material in the functional layer 450 diffuses into the initial metal layer 470 , causing the initial metal layer 470 to be polluted.
  • Step S224 sequentially stacking the top surface of the initial second barrier layer and the top surface of the initial third barrier layer to form an initial metal layer and an initial isolation layer.
  • an initial metal layer 470 may be formed by a chemical vapor deposition process or an atomic layer deposition process, and the initial metal layer 470 covers the top surface of the initial second barrier layer 440 and the top surface of the initial third barrier layer 460.
  • the material of the initial metal layer 470 includes tungsten or tungsten compound
  • the top surface of the initial first work function layer 430 is separated from the initial metal layer 470 by the initial second barrier layer 440
  • the top surface of the initial second work function layer 450 is separated from the initial metal layer 470 by the initial third barrier layer 460, so as to avoid mutual penetration between the material of the initial metal layer 470 and the material of the initial first work function layer 430, and at the same time, avoid mutual penetration between the materials of the initial metal layer 470 and the initial second work function layer 450, Avoid mutual contamination of adjacent layers due to material penetration, and ensure high reliability of the formed semiconductor structure.
  • an initial isolation layer 480 may be formed by a chemical vapor deposition process or an atomic layer deposition process.
  • the initial isolation layer 480 covers the top surface of the initial metal layer 470.
  • the material of the initial isolation layer 480 may include silicon oxide or silicon oxynitride.
  • the first stack part 401 includes an initial oxide layer 411 , an initial high-K dielectric layer 412 , an initial first barrier layer 420 , an initial first work function layer 430 , an initial second barrier layer 440 , an initial metal layer 470 and an initial isolation layer 480 formed above the first region 110 .
  • the second stack part 402 includes an initial oxide layer 411 , an initial high-K dielectric layer 412 , an initial second work function layer 450 , an initial third barrier layer 460 , an initial metal layer 470 and an initial isolation layer 480 formed above the second region 120 .
  • the top surfaces of the initial second barrier layer 440 of the first stacked part 401 and the initial third barrier layer 460 of the second stacked part 402 are flush;
  • the thickness is equal to the thickness of the initial metal layer 470 and the initial isolation layer 480 formed on the second region 120 . Based on the above two reasons, the heights of the first stacking part 401 and the second stacking part 402 are equal.
  • the etching height required to etch the first stack portion 401 to form the first gate structure 210 is equal to the etching height required to etch the second stack portion 402 to form the second gate structure 310, that is, the first stack portion 401 and the second stack portion 402 are etched in the same etching process to form the first gate structure 210 and the second gate structure 310 at the same time, and the first gate structure 210 and the second gate structure 310 are formed at the same time.
  • the problem of partial etching or over-etching caused by post-formation reduces the difficulty of subsequent formation of the first gate structure 210 and the second gate structure 310 , and improves the yield of the formed first gate structure 210 and the second gate structure 310 .
  • the following steps are further included:
  • an initial semiconductor layer 491 is first formed, and the initial semiconductor layer 491 covers the top surface of the initial second barrier layer 440 and the top surface of the initial third barrier layer 460, and then an initial fourth barrier layer 492 is formed, and the initial fourth barrier layer 492 covers the initial semiconductor layer 491.
  • the initial semiconductor layer 491 and the initial fourth barrier layer 492 are sequentially stacked between the initial second barrier layer 440 and the initial metal layer 470 above the first region 110 , and sequentially stacked between the initial third barrier layer 460 and the initial metal layer 470 above the second region 120 .
  • the initial semiconductor layer 491 can be formed by a chemical vapor deposition process or an atomic layer deposition process.
  • the initial semiconductor layer 491 covers both the top surface of the initial second barrier layer 440 and the top surface of the initial third barrier layer 460.
  • the initial semiconductor layer 491 also covers the exposed top surface of the initial high-K dielectric layer 412.
  • the material of the initial semiconductor layer 491 may be one or more of single crystal silicon or polycrystalline.
  • the material included in the initial semiconductor layer 491 may be an intrinsic semiconductor material or a doped semiconductor material. In this embodiment, the material of the initial semiconductor layer 491 includes polysilicon.
  • an initial fourth barrier layer 492 is formed by a chemical vapor deposition process or an atomic layer deposition process, and the initial fourth barrier layer 492 covers the initial semiconductor layer 491 .
  • the initial fourth barrier layer 492 can isolate the initial semiconductor layer 491 from the initial semiconductor layer 491 to prevent the material of the initial metal layer 470 from diffusing into the initial semiconductor layer 491 .
  • the material of the initial fourth barrier layer 492 may be titanium nitride, and the titanium nitride in the initial fourth barrier layer 492 may be doped with a small amount of sulfur (S) element.
  • the first stacked part 401 includes not only an initial oxide layer 411 , an initial high-K dielectric layer 412 , an initial first barrier layer 420 , an initial first work function layer 430 , an initial second barrier layer 440 , an initial metal layer 470 and an initial isolation layer 480 , but also an initial semiconductor layer 491 and an initial fourth barrier layer 492 formed between the initial second barrier layer 440 and the initial metal layer 470 .
  • the second stack part 402 includes an initial oxide layer 411, an initial high-K dielectric layer 412, an initial second work function layer 450, an initial third barrier layer 460, an initial metal layer 470, and an initial isolation layer 480, and also includes an initial semiconductor layer 491 and an initial fourth barrier layer 492 formed between the initial third barrier layer 460 and the initial metal layer 470.
  • the thicknesses of the initial semiconductor layer 491 and the initial fourth barrier layer 492 in the first stacked portion 401 are equal to the thicknesses of the initial semiconductor layer 491 and the initial fourth barrier layer 492 in the second stacked portion 402, so that the first stacked portion 40 formed in this embodiment 1 and the height of the second stacked part 402 are equal.
  • the process heights for forming the first gate structure 210 and the second gate structure 310 are equal.
  • Step S230 forming a mask layer on the surface of the initial isolation layer, and etching the stacked structure through the mask layer to form a first gate structure and a second gate structure.
  • a mask layer 500 may be formed by a chemical vapor deposition process or a physical vapor deposition process, and the mask layer 500 covers the initial isolation layer 480 .
  • the mask layer 500 may be a single-layer structure or a multi-layer structure.
  • the mask layer 500 is a multi-layer structure, and the mask layer 500 includes a silicon nitride layer 510 covering the initial isolation layer 480, and an amorphous carbon layer 520 covering the silicon nitride layer 510.
  • the material of the silicon nitride layer 510 has a higher etching selectivity than the material of the initial isolation layer 480 , so as to prevent the initial isolation layer 480 from being removed when the silicon nitride layer 510 is etched away, and ensure that the initial isolation layer 480 covers the top surface of the initial metal layer 470 .
  • a fourth photoresist mask 50 is formed on the mask layer 500.
  • the retained mask layer 500 exposes part of the initial isolation layer 480 , and according to the retained mask layer 500 , part of the stack structure 400 is etched away, that is, part of the first stack part 401 and part of the second stack part 402 are removed.
  • the reserved first stack part 401 forms the first gate structure 210
  • the reserved second stack part 402 forms the second gate structure 310
  • the first gate structure 210 and the second gate structure 310 formed in this step are equal in height.
  • the projection of the first gate structure 210 formed in this embodiment on the substrate 100 falls in the first region 110 , that is, after the first gate structure 210 is formed, the first region 110 still retains a part of the outer periphery of the first gate structure 210 that can be processed.
  • the projection of the second gate structure 310 formed in this embodiment on the substrate 100 falls in the second region 120 , and the exposed part of the second region 120 is a processable part.
  • Step S240 performing ion implantation on the first regions on both sides of the first gate structure to form a first source region and a first drain region respectively.
  • part of the structure of the first region 110 is exposed on both sides of the first gate structure 210 , and ion implantation may be performed on this part of the structure through an ion implantation process to form a first source region 220 and a first drain region 230 on both sides of the first gate structure 210 .
  • boron ions (B + ) are implanted in the left region of the exposed first region 110 to form the first source region 220; boron ions (B + ) are implanted in the right region of the exposed first region 110 to form the first drain region 230.
  • a first channel region 240 is formed in the region between the first source region 220 and the first drain region 230 under the first gate structure 210 .
  • the first gate structure 210 , the first source region 220 , the first drain region 230 and the first channel region 240 form the first device 200 .
  • Step S250 performing ion implantation on the second regions on both sides of the second gate structure to form a second source region and a second drain region.
  • part of the structure of the second region 120 is exposed on both sides of the second gate structure 310 , and ion implantation may be performed on this part of the structure through an ion implantation process to form a second source region 320 and a second drain region 330 on both sides of the second gate structure 310 .
  • phosphorus ions P 5+
  • phosphorus ions P 5+
  • phosphorus ions P 5+
  • a second channel region 340 is formed in the region between the second source region 320 and the second drain region 330 under the second gate structure 310 .
  • the second gate structure 310 , the second source region 320 , the second drain region 330 and the second channel region 340 form the second device 300 .
  • the heights of the formed first stacked part and the second stacked part are consistent, and the time for etching the first stacked part to form the first gate structure is basically the same as the time for etching the second stacked part to form the second gate structure.
  • an exemplary embodiment of the present disclosure provides a semiconductor structure, as shown in FIG. 20 and FIG. 24 , referring to FIG. 19 and FIG. 23 , the semiconductor structure includes a substrate 100, and at least one first device 200 disposed on the substrate 100 and at least one second device 300 disposed on the substrate 100.
  • the substrate 100 includes a first region 110 and a second region 120 .
  • the first device 200 is disposed on the first region 110 , the first device 200 includes a first gate structure 210 , and the first gate structure 210 includes a first work function layer 213 .
  • the second device 300 is disposed in the second region 120 , the second device 300 includes a second gate structure 310 , the second gate structure 310 includes a second work function layer 312 , and the top surfaces of the first gate structure 210 and the second gate structure 310 are flush.
  • the first region 110 includes dopant ions of the first conductivity type
  • the second region 120 includes dopant ions of the second conductivity type
  • the first conductivity type and the second conductivity type are different.
  • the first region 110 is a P-type conductive doped region
  • the first device 200 is a PMOS
  • the first work function layer 213 of the first gate structure 210 is a P-type work function layer
  • the second region 120 is an N-type conductive doped region
  • the second device 300 is an NMOS
  • the second work function layer 312 of the second gate structure 310 is an N-type work function layer.
  • the first gate structure 210 includes a first gate dielectric layer 211 , a first barrier layer 212 , a first work function layer 213 , a second barrier layer 214 , a first metal layer 215 and a first isolation layer 216 sequentially stacked above the first region 110 from bottom to top.
  • the first gate dielectric layer 211 of the first gate structure 210 includes a first oxide layer 2111 and a first high-K dielectric layer 2112 sequentially disposed on the first region 110 , and the first oxide layer 2111 is located below the first high-K dielectric layer 2112 .
  • the first gate structure 210 further includes a first semiconductor layer 217 and a first and fourth barrier layer 218 sequentially stacked between the second barrier layer 214 and the first metal layer 215 .
  • the second gate structure 310 includes a second gate dielectric layer 311 , a second work function layer 312 , a third barrier layer 313 , a second metal layer 314 and a second isolation layer 315 sequentially stacked on the second region 120 from bottom to top.
  • the second gate dielectric layer 311 of the second gate structure 310 includes a second oxide layer 3111 and a second high-K dielectric layer 3112 sequentially disposed on the first region 110 .
  • the top surface of the second barrier layer 214 is flush with the top surface of the third barrier layer 313 .
  • the second gate structure 310 further includes a second semiconductor layer 316 and a second and fourth barrier layer 317 sequentially stacked between the third barrier layer 313 and the second metal layer 314 .
  • the first device 200 further includes a first source region 220 , a first drain region 230 and a first channel region 240 , the first source region 220 and the first drain region 230 are respectively located on both sides of the first gate structure 210 , and the first channel region 240 is disposed below the first gate structure 210 .
  • the second device 300 further includes a second source region 320 , a second drain region 330 and a second channel region 340 , the second source region 320 and the second drain region 330 are respectively located on both sides of the second gate structure 310 , and the second channel region 340 is disposed below the second gate structure 310 .
  • a plurality of first devices and a plurality of second devices are arranged on the same substrate, and the heights of the first devices and the second devices are equal, the first devices and the second devices of the semiconductor structure have good electrical properties, and the yield and reliability of the semiconductor structure are higher.
  • orientations or positional relationships indicated by the terms “center”, “upper”, “lower”, “left”, “right”, “vertical”, “horizontal”, “inner”, “outer”, etc. are based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be construed as a limitation to the present disclosure.
  • the first gate structure of the first device and the second gate structure of the second device are formed in the same etching process, and the process heights of the first gate structure and the second gate structure are equal, which reduces the process difficulty of forming the first gate structure and the second gate structure, and improves the yield and reliability of the semiconductor structure.

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Abstract

本公开提供一种半导体结构的制作方法及半导体结构，涉及半导体技术领域，所述半导体结构的制作方法包括，提供衬底，衬底包括第一区域和第二区域；在第一区域上形成第一器件，第一器件包括第一栅极结构，第一栅极结构包括第一功函数层；在第二区域上形成第二器件，第二器件包括第二栅极结构，第二栅极结构包括第二功函数层；第一栅极结构的顶面与第二栅极结构的顶面平齐。

Description

半导体结构的制作方法及半导体结构
本公开基于申请号为202210058165.9、申请日为2022年01月19日、申请名称为“半导体结构的制作方法及半导体结构”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及但不限于一种半导体结构的制作方法及半导体结构。
背景技术
随着集成电路的发展，动态随机存取存储器(Dynamic Random Access Memory，简称DRAM)的结构尺寸微缩，金属-氧化物半导体场效应晶体管，简称金氧半场效晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor，MOSFET)的尺寸越来越小，为了改善晶体管的漏电和提高器件的可靠性，高介电常数介质金属栅极(High-K Metal Gate，简称HKMG)技术被广泛应用于半导体制程中。
在半导体制程中，通常在同一制程形成不同导电类型的晶体管，而不同导电类型的晶体管的制程高度不同，常会出现其中部分结构刻蚀不足而另一部分结构过刻蚀的情况，降低了晶体管的电性能和可靠性。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开提供了一种半导体结构的制作方法及半导体结构。
本公开的第一方面提供了一种半导体结构的制作方法，所述制作方法包括：提供衬底，所述衬底包括第一区域和第二区域；
在所述第一区域上形成第一器件，所述第一器件包括第一栅极结构，所述第一栅极结构包括第一功函数层；
在所述第二区域上形成第二器件，所述第二器件包括第二栅极结构，所述第二栅极结构包括第二功函数层；
所述第一栅极结构的顶面与所述第二栅极结构的顶面平齐。
根据本公开的一些实施例，所述制作方法，包括：
于所述衬底上形成堆叠结构，所述堆叠结构包括位于所述第一区域的第一堆叠部分以及位于所述第二区域的第二堆叠部分；
所述第一堆叠部分和所述第二堆叠部分等高。
根据本公开的一些实施例，所述于所述衬底上形成堆叠结构，包括：
在所述衬底的所述第一区域和所述第二区域上分别形成初始栅极介电层，所述初始栅极介电层包括初始氧化层和初始高K介质层，所述初始高K介质层形成在所述初始氧化层的顶面上。
根据本公开的一些实施例，所述于所述衬底上形成堆叠结构，还包括：
在所述初始高K介质层的顶面上依次堆叠形成初始第一阻挡层、初始第一功函数层和初始第二阻挡层；
去除形成于所述第二区域上方的所述初始第一阻挡层、所述初始第一功函数层和所述初始第二阻挡层，保留形成于所述第一区域上方的所述初始第一阻挡层、所述初始第一功函数层和所述初始第二阻挡层。
根据本公开的一些实施例，所述于所述衬底上形成堆叠结构，还包括：
于所述第一区域上方的所述初始第二阻挡层的顶面以及所述第二区域上方的所 述初始高K介质层的顶面上形成刻蚀阻挡层；所述刻蚀阻挡层包括氧化物层和氮化物层；
去除形成于所述第二区域上方的所述刻蚀阻挡层，保留形成于所述第一区域上方的所述刻蚀阻挡层。
根据本公开的一些实施例，所述于所述衬底上形成堆叠结构，还包括：
形成初始第二功函数层，所述初始第二功函数层覆盖位于所述第二区域上方的所述初始高K介质层的顶面以及所述刻蚀阻挡层的顶面；
形成初始第三阻挡层，所述初始第三阻挡层覆盖所述第二功函数层；
去除形成于所述第一区域上方的所述初始第二功函数层、所述初始第三阻挡层和所述刻蚀阻挡层，保留形成于所述第二区域上方的所述初始第二功函数层和所述初始第三阻挡层。
根据本公开的一些实施例，所述初始第二阻挡层的顶面和所述初始第三阻挡层的顶面平齐。
根据本公开的一些实施例，所述于所述衬底上形成堆叠结构，还包括：
于所述初始第二阻挡层的顶面和所述初始第三阻挡层的顶面依次堆叠形成初始金属层和初始隔离层。
根据本公开的一些实施例，所述于所述衬底上形成堆叠结构，还包括：
形成初始半导体层和初始第四阻挡层，所述半导体层和所述初始第四阻挡层依次堆叠于所述第一区域上方的所述初始第二阻挡层和所述初始金属层之间，以及依次堆叠于所述第二区域上方的所述初始第三阻挡层和所述初始金属层之间。
根据本公开的一些实施例，所述制作方法，还包括：
在所述隔离层的表面形成掩膜层，通过所述掩膜层刻蚀所述堆叠结构形成所述第一栅极结构和所述第二栅极结构。
根据本公开的一些实施例，所述制作方法，还包括：
对所述第一栅极结构两侧的所述第一区域进行离子注入，分别形成第一源区和第一漏区；
对所述第二栅极结构两侧的所述第二区域进行离子注入，形成第二源区和第二漏区。
本公开的第二方面提供了一种半导体结构，所述半导体结构包括：
衬底，所述衬底包括第一区域和第二区域；
至少一个第一器件，所述第一器件设置在所述第一区域，所述第一器件包括第一栅极结构，所述第一栅极结构包括第一功函数层；
至少一个第二器件，所述第二器件设置在所述第二区域，所述第二器件包括第二栅极结构，所述第二栅极结构包括第二功函数层；
所述第一栅极结构和所述第二栅极结构的顶面平齐。
根据本公开的一些实施例，所述第一栅极结构包括依次堆叠在所述第一区域上的第一栅极介电层、第一阻挡层、第一功函数层、第二阻挡层、第一金属层以及第一隔离层；
所述第二栅极结构包括依次堆叠在所述第二区域上的第二栅极介电层、第二功函数层、第三阻挡层、第二金属层以及第二隔离层；
所述第二阻挡层的顶面和所述第三阻挡层的顶面平齐。
根据本公开的一些实施例，所述第一栅极结构还包括：依次堆叠于所述第二阻挡层和所述第一金属层之间的第一半导体层和第一第四阻挡层。
根据本公开的一些实施例，所述第二栅极结构还包括：依次堆叠于所述第三阻挡层和所述第二金属层之间的第二半导体层和第二第四阻挡层。
根据本公开的一些实施例，所述第一器件还包括：第一源区、第一漏区和第一沟道区，所述第一源区和所述第一漏区分别位于所述第一栅极结构的两侧，所述第一沟道区设置在所述第一栅极结构的下方；
所述第二器件还包括：第二源区、第二漏区和第二沟道区，所述第二源区和所述第二漏区分别位于所述第二栅极结构的两侧，所述第二沟道区设置在所述第二栅极结构的下方。
本公开实施例所提供的半导体结构的制作方法及半导体结构中，第一器件的第一栅极结构和第二器件的第二栅极结构在同一刻蚀制程中形成，第一栅极结构和第二栅极结构的制程高度相等，降低了形成第一栅极结构和第二栅极结构的工艺难度，提高了半导体结构的成品率和可靠性。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
并入到说明书中并且构成说明书的一部分的附图示出了本公开的实施例，并且与描述一起用于解释本公开实施例的原理。在这些附图中，类似的附图标记用于表示类似的要素。下面描述中的附图是本公开的一些实施例，而不是全部实施例。对于本领域技术人员来讲，在不付出创造性劳动的前提下，可以根据这些附图获得其他的附图。
图1是根据一示例性实施例示出的半导体结构的制作方法的流程图。
图2是根据一示例性实施例示出的半导体结构的制作方法的流程图。
图3是根据一示例性实施例中所示的衬底的示意图。
图4是根据一示例性实施例中形成栅极介电层的示意图。
图5是根据一示例性实施例中在高K介质层上形成依次堆叠的第一阻挡层、第一功函数层和第二阻挡层的示意图。
图6是根据一示例性实施例中形成第一光刻胶掩膜的示意图。
图7是根据一示例性实施例中去除第二区域上方的第一阻挡层、第一功函数层和第二阻挡层的示意图。
图8是根据一示例性实施例中形成刻蚀阻挡层的示意图。
图9是根据一示例性实施例中在第一区域上方的刻蚀阻挡层上形成第二光刻胶掩膜的示意图。
图10是根据一示例性实施例中去除第二区域上方的刻蚀阻挡层的示意图。
图11是根据一示例性实施例中形成第二功函数层和第三功函数层的示意图。
图12是根据一示例性实施例中形成第三光刻胶掩膜的示意图。
图13是根据一示例性实施例中在第二区域上方形成第二功函数层和第三功函数层的示意图。
图14是根据一示例性实施例中去除第一区域上方的刻蚀阻挡层的示意图。
图15是根据一示例性实施例中形成金属层的示意图。
图16是根据一示例性实施例中形成的堆叠结构的示意图。
图17是根据一示例性实施例中在堆叠结构上形成掩膜层的示意图。
图18是根据一示例性实施例中形成第四光刻胶掩膜的示意图。
图19是根据一示例性实施例中形成第一栅极结构和第二栅极结构的示意图。
图20是根据一示例性实施例中形成第一器件和第二器件的示意图。
图21是根据一示例性实施例中形成的堆叠结构的示意图。
图22是根据一示例性实施例中在堆叠结构上形成掩膜层的示意图。
图23是根据一示例性实施例中形成的第一栅极结构和第二栅极结构的示意图。
图24是根据一示例性实施例中形成的第一器件和第二器件的示意图。
附图标记：
10、第一光刻胶掩膜；20、刻蚀阻挡层；21、氧化物层；22、氮化物层；30、第二光刻胶掩膜；40、第三光刻胶掩膜；50、第四光刻胶掩膜；100、衬底；110、第一区域；120、第二区域；200、第一器件；210、第一栅极结构；211、第一栅极介电层；2111、第一氧化层；2112、第一高K介质层；212、第一阻挡层；213、第一功函数层；214、第二阻挡层；215、第一金属层；216、第一隔离层；217、第一半导体层；218、第一第四阻挡层；220、第一源区；230、第一漏区；240、第一沟道区；300、第二器件；310、第二栅极结构；311、第二栅极介电层；3111、第二氧化层；3112、第二高K介质层；312、第二功函数层；313、第三阻挡层；314、第二金属层；315、第二隔离层；316、第二半导体层；317、第二第四阻挡层；320、第二源区；330、第二漏区；340、第二沟道区；400、堆叠结构；401、第一堆叠部分；402、第二堆叠部分；410、初始栅极介电层；411、初始氧化层；412、初始高K介质层；420、初始第一阻挡层；430、初始第一功函数层；440、初始第二阻挡层；450、初始第二功函数层；460、初始第三阻挡层；470、初始金属层；480、初始隔离层；491、初始半导体层；492、初始第四阻挡层；500、掩膜层；510、氮化硅层；520、非晶碳层。
具体实施方式
下面将结合本公开实施例中的附图，对公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
本公开示例性的实施例中提供了一种半导体结构的制作方法，在两个区域上形成器件时，在两个区域上方形成堆叠结构，堆叠结构中对应两个区域的堆叠部分的高度等高，且堆叠结构中对应两个区域的堆叠部分包括与各自区域对应的功函数层，刻蚀堆叠结构在两个区域上形成栅极结构，形成两个栅极结构的刻蚀高度相同，形成的两个栅极结构的顶面平齐，降低了形成第一栅极结构和第二栅极结构的工艺难度，提高了半导体结构的成品率和可靠性。
本实施例对半导体结构不作限制，下面将以半导体结构为动态随机存储器(DRAM)为例进行介绍，但本实施例并不以此为限，本实施例中的半导体结构还可以为其他的结构。图3-图24为半导体结构的制作方法的各个阶段形成的结构的示意图，下面结合图3-图24对本实施例中的半导体结构的制作方法进行介绍。
如图1所示，本公开一示例性的实施例提供的一种半导体结构的制作方法，包括如下的步骤：
步骤S110：提供衬底，衬底包括第一区域和第二区域。
如图3所示，衬底100可以为半导体衬底，半导体衬底可以包括硅衬底、锗(Ge)衬底、锗化硅(SiGe)衬底、SOI(Silicon-on-insulator，绝缘体上硅)衬底或GOI(Germanium-on-Insulator，绝缘体上锗)衬底等。半导体衬底中可以掺杂离子，例如，半导体衬底可以为P型掺杂衬底，也可以为N型掺杂衬底。在本实施例中，衬底100为硅晶衬底。
如图3所示，衬底100中设置有至少一个第一区域110，第一区域110为P型导电掺杂区域，衬底100中设置有至少一个第二区域120，第二区域120为N型导电掺杂区域。在衬底100为P型掺杂衬底或N型掺杂衬底时，第一区域110和第二区域120中掺杂离子的掺杂浓度大于衬底100的其余区域中掺杂离子的掺杂浓度。在本实施例中，衬底100中设置有多个第一区域110、多个第二区域120，其中，第一区域110和第二区域120的数量可以相等或不等。
步骤S120：在第一区域上形成第一器件，在第二区域上形成第二器件，第一器件包括第一栅极结构，第二器件包括第二栅极结构，第一栅极结构的顶面与第二栅极结构的顶面平齐。
如图20所示，参照图16、图17，第一器件200的第一栅极结构210和第二器件300的第二栅极结构310通过刻蚀位于衬底100上的堆叠结构400形成，堆叠结构400位于第一区域110上的第一堆叠部分401和位于第二区域120上的第二堆叠部分402的高度相等。对堆叠结构400进行一次刻蚀制程，同时形成第一栅极结构210和第二栅极结构310，在此刻蚀制程中，刻蚀第一堆叠部分401形成第一栅极结构210的高度和刻蚀第二堆叠部分402形成第二栅极结构310的高度相等，也即在刻蚀制程中，第一栅极结构210和第二栅极结构310的刻蚀速度相等，第一栅极结构210和第二栅极结构310同时形成，且第一栅极结构210和第二栅极结构310等高。
如图20所示，参照图19，在本实施例中，第一栅极结构210包括第一功函数层213，第二栅极结构310包括第二功函数层312。本实施例中，第一器件200为PMOS，第一功函数层213为根据第一区域110的导电类型形成的P型功函数层。第二器件300为NMOS，第二功函数层312为根据第二区域120的导电类型形成的N型功函数层。
需要说明的是，在保持第一栅极结构210的顶面与第二栅极结构310的顶面平齐时，可以采用不同的方式。在一个示例中，第一栅极结构210包括第一功函数层213但不包括第二功函数层312，第二栅极结构310包括第二功函数层312但不包括第一功函数层213，通过调整第一栅极结构210的层数和每层结构的厚度，以及调整第二栅极结构310中的层数和每层结构的厚度，以使第一栅极结构210和第二栅极结构310的顶面平齐。在另一个示例中，第一栅极结构210包括第一功函数层213和第二功函数层312，第二栅极结构310也包括第一功函数层213和第二功函数层312，以使第一栅极结构210和第二栅极结构310的层数相同且每层的厚度相同，确保第一栅极结构210和第二栅极结构310的顶面平齐。
本实施例的半导体结构的形成方法，第一栅极结构和第二栅极结构可在同一刻蚀制程中形成，刻蚀形成第一栅极结构的刻蚀高度和刻蚀形成第二栅极结构的制程高度相等，第一栅极结构和第二栅极结构同时形成且形成的第一栅极结构和第二栅极结构具有相同形貌。本实施例的形成方法不会出现第一栅极结构或第二栅极结构的制程高度不同，导致其中之一已被刻蚀形成，而另一还处于刻蚀过程中，刻蚀时间难以控制，导致第一栅极结构和/或第二栅极结构刻蚀不足或过刻蚀的问题。本实施例的形成方法，降低了形成第一栅极结构和第二栅结构的工艺难度，提高了刻蚀形成第一栅极结构和第二栅极结构的控制精度，提高了形成的半导体结构的成品率和可靠性。
根据一个示例性实施例，本公开一示例性的实施例提供的一种半导体结构的制作方法。如图2所示，本公开一示例性的实施例提供的一种半导体结构的制作方法，包括如下的步骤：
步骤S210：提供衬底，衬底包括第一区域和第二区域。
本实施例的步骤S210和上述实施例的步骤S110的实现方法相同，在此，不再赘述。
步骤S220：于衬底上形成堆叠结构，堆叠结构包括位于第一区域的第一堆叠部分以及位于第二区域的第二堆叠部分，第一堆叠部分和第二堆叠部分等高。
在实现该步骤时，形成第一堆叠部分和第二堆叠部分的时间没有具体限定，可以先形成第一堆叠部分，也可以先形成第二堆叠部分，还可以先形成第一堆叠部分中的部分，然后再形成第二堆叠部分中的部分结构，然后再接着形成第一堆叠部分中的其余结构，然后再形成第二堆叠部分中的其余结构。
在一种可能的实施方式中，步骤S220在实施过程中，可以包括以下步骤：
步骤S221：在衬底的第一区域和第二区域上分别形成初始栅极介电层，初始栅极介电层包括初始氧化层和初始高K介质层，初始高K介质层形成在初始氧化层的顶面上。
如图4所示，参照图3，通过原位水气生成(In-Situ Steam Generation，ISSG)工艺在衬底100表面形成初始氧化层411。其中，初始氧化层411的材料可以包括氧化硅或氮氧化硅。本实施例中，初始氧化层411的材料为氧化硅。
通过化学气相沉积工艺(Chemical Vapor Deposition，CVD)、物理气相沉积工艺(Physical Vapor Deposition，PVD)、原子层沉积工艺(Atomic Layer Deposition，ALD)或溅射工艺(sputtering)中的任一种，在初始氧化层411的顶面上沉积工艺形成初始高K介质层412，初始高K介质层412覆盖初始氧化层411。初始高K介质层412的材料选用具有高介电常数的介电材料，在本实施例中，初始高K介质层412的材料包括金属铪(hafnium)或铪化合物等铪材料。例如，初始高K介质层412的材料可以包括氧化铪(HfO)、氧化铪硅(HfSiO)、氧化铪铝(HfAlO)或氧化铪钽(HfTaO)中的一种或多种。
如图4所示，初始氧化层411和初始高K介质层412共同构成初始栅极介电层410，当初始氧化层411的材料为氧化硅时，其介电常数为3.9。初始高K介质层412的材料为铪材料时，其介电常数约为25。由于初始高K介质层412的介电常数大于初始氧化层411的介电常数，因此，在同样条件下，在半导体结构中形成的初始高K介质层的厚度更厚，增加了初始栅极介电层410的厚度，减小了后续形成的第一栅极结构210和第二栅极结构310的隧穿问题，减小了第一栅极结构210和第二栅极结构310的漏电流。
步骤S222：于第一区域上方形成依次堆叠的初始第一阻挡层、初始第一功函数层和初始第二阻挡层。
如图5所示，通过上述任一沉积工艺在初始高K介质层412的顶面上形成依次堆叠的初始第一阻挡层420、初始第一功函数层430和初始第二阻挡层440，其中，初始第一阻挡层420的材料可以包括氮化钛，初始第二阻挡层440的材料可以包括氮化钛。本实施例中，由于第一区域110为P型掺杂区域，第一器件200为PMOS，初始第一功函数层430为与第一区域110对应的P型功函数层。初始第一功函数层430的材料包括铝或铝化合物，其中，铝化合物比如可以是氮化铝。由于初始第一功函数层430的材料在初始高K介质层412的材料中具有可溶解性，并且初始第一功函数层430的材料在后续形成的初始金属层470的金属材料中也具有可溶解性，本实施例中，在初始第一功函数层430的底面形成有初始第一阻挡层420，以防止初始第一功函数层430中的材料向初始高K介质层412中扩散，在初始第一功函数层430的顶面形成有第二阻挡层440，以防止初始第一功函数层430中的材料向后续形成的初始金属层470中扩散。
如图6所示，参照图5，在初始第二阻挡层440的顶面上形成第一光刻胶掩膜10，第一光刻胶掩膜10覆盖位于第一区域110上方的初始第二阻挡层440，且第一光刻胶掩膜10暴露出位于第二区域120上方的初始第二阻挡层440。如图7所示，根据第一光刻胶掩膜10定义的图形，逐层刻蚀初始第二阻挡层440、初始第一功函数层430和初始第二阻挡层440，去除形成于第二区域120上方的初始第一阻挡层420、初始第一功函数层430和初始第二阻挡层440，保留形成于第一区域110上方的初始第一阻挡层420、初始第一功函数层430和初始第二阻挡层440。也即，仅保留第一区域110上方的初始第一阻挡层420、初始第一功函数层430和初始第二阻挡层440，其余位置处的初始第一阻挡层420、初始第一功函数层430和初始第二阻挡层440全部被刻蚀去除。
步骤S223：于第二区域上方依次形成初始第二功函数层和初始第三阻挡层。
该步骤中，在形成初始第二功函数层之前，首先需要在第一区域110的上方形成刻蚀阻挡层20。如图8所示，参照图7，在实施过程中，于第一区域110上方的初始第二阻挡层440的顶面，以及于第二区域120上方的初始高K介质层412的顶面，同时形成刻蚀阻挡层20，其中，刻蚀阻挡层20包括氧化物层21和氮化物层22。如图10所示，去除形成于第二区域120上方的刻蚀阻挡层20，保留形成于第一区域110上方的刻蚀阻挡层20。
如图8所示，参照图7，在形成刻蚀阻挡层20时，可以首先通过化学气相沉积工艺或物理气相沉积工艺形成氧化物层21，氧化物层21覆盖初始第二阻挡层440的顶面以及暴露的初始高K介质层412的顶面，其中，氧化物层21的材料包括氧化硅或氮氧化硅。氧化物层21的材料相对于初始第二阻挡层440的材料具有高刻蚀选择比，以便后续将氧化物层21从初始第二阻挡层440上刻蚀去除，避免初始第二阻挡层440被刻蚀工艺去除，保留初始第二阻挡层440阻挡初始第一功函数层430的材料扩散。在形成氧化物层21后，可以通过化学气相沉积工艺或物理气相沉积工艺，在氧化物层21的顶面形成氮化物层22，其中，氮化物层22的材料包括氮化硅。
如图9所示，在位于第一区域110上方的氮化物层22的顶面形成第二光刻胶掩膜30。如图10所示，通过干法刻蚀或湿法刻蚀工艺，依次去除暴露在第二光刻胶掩膜30之外的氮化物层22和氧化物层21，保留位于第一区域110上方的氮化物层22和氧化物层21，保留位于第一区域110上方的刻蚀阻挡层20。
如图11所示，参照图10，在第一区域110的上方形成刻蚀阻挡层20之后，接着在第二区域的上方形成初始第二功函数层450，初始第二功函数层450覆盖位于第二区域120上方的初始高K介质层412的顶面，以及刻蚀阻挡层20的顶面。接着，在初始第二功函数层450的顶面形成初始第三阻挡层460，初始第三阻挡层460覆盖整个初始第二功函数层450。本实施例中，可以通过化学气相沉积或原子层沉积形成初始第二功函数层450和初始第三阻挡层460。
如图12所示，参照图11，接着，在位于第二区域120上方的初始第三阻挡层460的顶面形成第三光刻胶掩膜430。如图13所示，通过干法刻蚀工艺或湿法刻蚀工艺，依次逐层去除形成于第一区域110上方的初始第三阻挡层460、初始第二功函数层450，保留形成于第二区域120上方的初始第二功函数层450和初始第三阻挡层460。
然后，如图14所示，参照图13，通过干法刻蚀工艺或湿法刻蚀工艺，去除全部的刻蚀阻挡层20，暴露出初始第二阻挡层440的顶面。此时，第一区域110上方堆叠了初始第一阻挡层420、初始第一功函数层430和初始第二阻挡层440，第二区域120上方依次堆叠的初始第二功函数层450和初始第三阻挡层460。本实施例中，可以通过调整沉积初始第二功函数层450和初始第三阻挡层460的时间，以使初始第三阻挡层460的顶面和初始第二阻挡层440的顶面平齐。也即，本实施例中，形成于第二区域120上的初始第二功函数层450和初始第三阻挡层460的总厚度，与形成于第一区域110上的初始第一阻挡层420、初始第一功函数层430和初始第二阻挡层440的总厚度相等。
本实施例中，第二区域120为N型导电掺杂区域，第二器件300为NMOS，初始第二功函数层450为与第二区域120对应的N型功函数层。初始第二功函数层450的材料包括金属镧(Lanthanum)或镧化合物，示例性的，镧化合物可以为六硼化镧(Lanthanum boride)。
当初始高K介质层412的材料为铪材料时，镧或镧化合物不溶于初始高K介质层412，但会溶解在后续制成中形成的初始金属层470的金属材料，因此，本实施例在初始第二功函数层450的顶面形成初始第三阻挡层460，初始第三阻挡层460能够 阻挡初始第二功函数层450的材料向后续制成中形成的初始金属层470中溶解，以免在后续制程中，初始第二功函数层450中的材料扩散到初始金属层470中，造成初始金属层470被污染。
步骤S224：于初始第二阻挡层的顶面和初始第三阻挡层的顶面依次堆叠形成初始金属层和初始隔离层。
如图15所示，参照图14，在执行步骤S224时，可以通过化学气相沉积工艺或原子层沉积工艺形成初始金属层470，初始金属层470覆盖初始第二阻挡层440的顶面和初始第三阻挡层460的顶面。其中，初始金属层470的材料包括钨或钨化合物，初始第一功函数层430的顶面与初始金属层470被初始第二阻挡层440隔开，初始第二功函数层450的顶面与初始金属层470被初始第三阻挡层460隔开，避免初始金属层470的材料与初始第一功函数层430的材料之间互相渗透，同时，避免初始金属层470与初始第二功函数层450的材料之间互相渗透，避免相邻层由于材料渗透造成相互污染，确保形成的半导体结构具有高可靠性。
如图16所示，该步骤中，可以通过化学气相沉积工艺或原子层沉积工艺形成初始隔离层480，初始隔离层480覆盖在初始金属层470的顶面，初始隔离层480的材料可以包括氧化硅或氮氧化硅。通过设置初始隔离层480，能够避免初始金属层470的材料暴露在制程环境中，初始金属层470的材料与制程环境中的气体发生反应。
在本实施例中，如图16所示，参照图17，第一堆叠部分401包括形成于第一区域110上方的初始氧化层411、初始高K介质层412、初始第一阻挡层420、初始第一功函数层430、初始第二阻挡层440、初始金属层470和初始隔离层480。第二堆叠部分402包括形成于第二区域120上方的初始氧化层411、初始高K介质层412、初始第二功函数层450、初始第三阻挡层460、初始金属层470和初始隔离层480。
一方面，第一堆叠部分401的初始第二阻挡层440和第二堆叠部分402的初始第三阻挡层460的顶面平齐；另一方面，形成于第一区域110上方的初始金属层470和初始隔离层480，与形成于第二区域120上的初始金属层470和初始隔离层480均是在同一沉积工艺中形成的，因此，形成于第一区域110上方的初始金属层470和初始隔离层480的厚度，与形成于第二区域120上的初始金属层470和初始隔离层480的厚度相等。基于上述两方面原因，第一堆叠部分401和第二堆叠部分402的高度相等。以使刻蚀第一堆叠部分401形成第一栅极结构210所需的刻蚀高度，和刻蚀第二堆叠部分402形成第二栅极结构310的刻蚀高度相等，也即在同一刻蚀制程中刻蚀第一堆叠部分401和第二堆叠部分402，形成第一栅极结构210和第二栅极结构310的时间相等，第一栅极结构210和第二栅极结构310同时形成，不会出现刻蚀进度不一致导致其中之一先形成，另一后形成造成刻蚀部分或过刻蚀的问题，降低了后续形成第一栅极结构210和第二栅极结构310的难度，提高了形成的第一栅极结构210和第二栅极结构310的合格率。
在一些实施例中，在形成初始金属层470和初始隔离层480之前，还包括以下步骤：
参照图21，先形成初始半导体层491，初始半导体层491覆盖初始第二阻挡层440的顶面和初始第三阻挡层460的顶面，再形成初始第四阻挡层492，初始第四阻挡层492覆盖初始半导体层491。初始半导体层491和初始第四阻挡层492依次堆叠于第一区域110上方的初始第二阻挡层440和初始金属层470之间，以及依次堆叠于第二区域120上方的初始第三阻挡层460和初始金属层470之间。
参照图14、图21，可以通过化学气相沉积工艺或原子层沉积工艺形成初始半导体层491，初始半导体层491同时覆盖初始第二阻挡层440的顶面和初始第三阻挡层460的顶面，另外，初始半导体层491还会覆盖初始高K介质层412暴露的顶面。初 始半导体层491的材料可以单晶硅或多晶中的一种或多种。初始半导体层491包括的材料可以为本征半导体材料或掺杂半导体材料。在本实施例中，初始半导体层491的材料包括多晶硅。
参照图14、图21，通过化学气相沉积工艺或原子层沉积工艺形成初始第四阻挡层492，初始第四阻挡层492覆盖初始半导体层491。通过设置初始第四阻挡层492，初始第四阻挡层492可以隔离初始半导体层491和初始半导体层491，以免初始金属层470的材料扩散到初始半导体层491中。本实施例中，初始第四阻挡层492的材料可以为氮化钛，初始第四阻挡层492中的氮化钛中可以掺杂有少量硫(S)元素。
如图21所示，参照图22，本实施例形成堆叠结构400，第一堆叠部分401除了包括初始氧化层411、初始高K介质层412、初始第一阻挡层420、初始第一功函数层430、初始第二阻挡层440、初始金属层470和初始隔离层480，还包括形成于初始第二阻挡层440和初始金属层470之间的初始半导体层491和初始第四阻挡层492。第二堆叠部分402除了包括初始氧化层411、初始高K介质层412、初始第二功函数层450、初始第三阻挡层460、初始金属层470和初始隔离层480，还包括形成于初始第三阻挡层460和初始金属层470之间的初始半导体层491和初始第四阻挡层492。由于，第一堆叠部分401中的初始半导体层491和初始第四阻挡层492，与第二堆叠部分402中的初始半导体层491和初始第四阻挡层492同时形成，因此，第一堆叠部分401中的初始半导体层491和初始第四阻挡层492的厚度，与第二堆叠部分402中的初始半导体层491和初始第四阻挡层492的厚度相等，从而使得本实施例形成的第一堆叠部分401和第二堆叠部分402的高度相等。以确保在后续制程中，形成第一栅极结构210和第二栅极结构310的制程高度相等。
步骤S230：在初始隔离层的表面形成掩膜层，通过掩膜层刻蚀堆叠结构形成第一栅极结构和第二栅极结构。
如图17所示，在执行该步骤时，可以通过化学气相沉积工艺或物理气相沉积工艺形成掩膜层500，掩膜层500覆盖初始隔离层480。其中，掩膜层500可以为单层结构或多层结构，在本实施例中，掩膜层500为多层结构，掩膜层500包括覆盖在初始隔离层480上的氮化硅层510，以及覆盖在氮化硅层510上的非晶碳层520。其中，氮化硅层510的材料相对于初始隔离层480的材料具有高刻蚀选择比，以免刻蚀去除氮化硅层510时将初始隔离层480去除，确保初始隔离层480覆盖在初始金属层470的顶面。
如图18所示，在掩膜层500上形成第四光刻胶掩膜50，如图19所示，参照图18、图20，根据第四光刻胶掩膜50定义的图案刻蚀掩膜层500，将第四光刻胶掩膜50的图案延伸到掩膜层500中。被保留的掩膜层500暴露出部分初始隔离层480，根据被保留的掩膜层500，刻蚀去除部分堆叠结构400，也即，去除部分第一堆叠部分401，并去除部分第二堆叠部分402。被保留的第一堆叠部分401形成第一栅极结构210，被保留的第二堆叠部分402形成第二栅极结构310，本步骤形成的第一栅极结构210和第二栅极结构310等高。
本实施例形成的第一栅极结构210在衬底100上的投影落在第一区域110中，也即，形成第一栅极结构210之后，第一区域110在第一栅极结构210的外周仍保留部分可加工的部分。同样的，本实施例形成的第二栅极结构310在衬底100上的投影落在第二区域120中，第二区域120被暴露出的部分为可加工部分。
步骤S240：对第一栅极结构两侧的第一区域进行离子注入，分别形成第一源区和第一漏区。
如图20所示，第一栅极结构210两侧的暴露出第一区域110的部分结构，可以通过离子注入工艺对这部分结构进行离子注入，以在第一栅极结构210两侧分别形成 第一源区220和第一漏区230。在一个示例中，以图20中示出的方位为准，在暴露出的第一区域110的左侧区域注入硼离子(B +)，形成第一源区220；在暴露出的第一区域110的右侧区域注入硼离子(B +)，形成第一漏区230。
继续参照图20，形成第一源区220和第一漏区230之后，在第一栅极结构210下方，第一源区220和第一漏区230之间的区域形成了第一沟道区240。第一栅极结构210、第一源区220、第一漏区230和第一沟道区240形成第一器件200。
步骤S250：对第二栅极结构两侧的第二区域进行离子注入，形成第二源区和第二漏区。
如图20所示，第二栅极结构310两侧的暴露出第二区域120的部分结构，可以通过离子注入工艺对这部分结构进行离子注入，以在第二栅极结构310两侧分别形成第二源区320和第二漏区330。在一个示例中，以图20中示出的方位为准，在暴露出的第二区域120的左侧区域注入磷离子(P 5+)，形成第二源区320；在暴露出的第二区域120的右侧区域注入磷离子(P 5+)，形成第二漏区330。
如图20所示，形成第二源区320和第二漏区330之后，在第二栅极结构310下方，第二源区320和第二漏区330之间的区域形成第二沟道区340。第二栅极结构310、第二源区320、第二漏区330和第二沟道区340形成第二器件300。
本实施例的制作方法，形成的第一堆叠部分和第二堆叠部分的高度一致，刻蚀第一堆叠部分形成第一栅极结构的时间，与刻蚀第二堆叠部分形成第二栅极结构的时间基本相等，不会出现第一栅极结构和/或第二栅极结构出现刻蚀不足或过刻蚀的问题，不仅降低了形成第一栅极结构和第二栅极结构的刻蚀难度，还提高了形成的半导体结构的良品率。
根据一个示例性实施例，本公开一示例性的实施例提供了一种半导体结构，如图20、图24所示，参照图19、图23，半导体结构包括衬底100，以及设置在衬底100上的至少一个第一器件200和设置在衬底100上的至少一个第二器件300。衬底100包括第一区域110和第二区域120。第一器件200设置在第一区域110上，第一器件200包括第一栅极结构210，第一栅极结构210包括第一功函数层213。第二器件300设置在第二区域120，第二器件300包括第二栅极结构310，第二栅极结构310包括第二功函数层312，第一栅极结构210和第二栅极结构310的顶面平齐。
其中，第一区域110包括第一导电类型的掺杂离子，第二区域120包括第二导电类型的掺杂离子，第一导电类型和第二导电类型不同。在本实施例中，第一区域110为P型导电掺杂区域，第一器件200为PMOS，第一栅极结构210的第一功函数层213为P型功函数层。第二区域120为N型导电掺杂区域，第二器件300为NMOS，第二栅极结构310的第二功函数层312为N型功函数层。
在一些实施例中，如图19所示，第一栅极结构210包括由下至上依次堆叠在第一区域110上方的第一栅极介电层211、第一阻挡层212、第一功函数层213、第二阻挡层214、第一金属层215以及第一隔离层216。其中，第一栅极结构210的第一栅极介电层211包括依次设置在第一区域110上的第一氧化层2111和第一高K介质层2112，第一氧化层2111位于第一高K介质层2112的下方。
在一些实施例中，如图23所示，第一栅极结构210还包括依次堆叠于第二阻挡层214和第一金属层215之间的第一半导体层217和第一第四阻挡层218。
如图19所示，第二栅极结构310包括由下至上依次堆叠在第二区域120上的第二栅极介电层311、第二功函数层312、第三阻挡层313、第二金属层314以及第二隔离层315。其中，第二栅极结构310的第二栅极介电层311包括依次设置在第一区域110上的第二氧化层3111和第二高K介质层3112。第二阻挡层214的顶面和第三阻挡层313的顶面平齐。
如图23所示，第二栅极结构310还包括依次堆叠于第三阻挡层313和第二金属层314之间的第二半导体层316和第二第四阻挡层317。
在一些实施例中，如图20、图24所示，第一器件200还包括第一源区220、第一漏区230和第一沟道区240，第一源区220和第一漏区230分别位于第一栅极结构210的两侧，第一沟道区240设置在第一栅极结构210的下方。
在一些实施例中，如图20、图24所示，第二器件300还包括第二源区320、第二漏区330和第二沟道区340，第二源区320和第二漏区330分别位于第二栅极结构310的两侧，第二沟道区340设置在第二栅极结构310的下方。
本实施例的半导体结构，多个第一器件和多个第二器件设置在同一衬底上，且第一器件和第二器件的高度相等，半导体结构的第一器件和第二器件均具有良好的电性能，半导体结构的成品率和可靠性更高。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“实施例”、“示例性的实施例”、“一些实施方式”、“示意性实施方式”、“示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
在本公开的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
可以理解的是，本公开所使用的术语“第一”、“第二”等可在本公开中用于描述各种结构，但这些结构不受这些术语的限制。这些术语仅用于将第一个结构与另一个结构区分。
在一个或多个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的多个部分没有按比例绘制。此外，可能未示出某些公知的部分。为了简明起见，可以在一幅图中描述经过数个步骤后获得的结构。在下文中描述了本公开的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本公开。但正如本领域技术人员能够理解的那样，可以不按照这些特定的细节来实现本公开。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。
工业实用性
本公开实施例所提供的半导体结构的制备方法及半导体结构中，第一器件的第一栅极结构和第二器件的第二栅极结构在同一刻蚀制程中形成，第一栅极结构和第二栅极结构的制程高度相等，降低了形成第一栅极结构和第二栅极结构的工艺难度，提高了半导体结构的成品率和可靠性。

Claims (16)

  1. 一种半导体结构的制作方法，所述方法包括：
    提供衬底，所述衬底包括第一区域和第二区域；
    在所述第一区域上形成第一器件，所述第一器件包括第一栅极结构，所述第一栅极结构包括第一功函数层；
    在所述第二区域上形成第二器件，所述第二器件包括第二栅极结构，所述第二栅极结构包括第二功函数层；
    所述第一栅极结构的顶面与所述第二栅极结构的顶面平齐。
  2. 根据权利要求1所述的半导体结构的制作方法，其中，所述制作方法，包括：
    于所述衬底上形成堆叠结构，所述堆叠结构包括位于所述第一区域的第一堆叠部分以及位于所述第二区域的第二堆叠部分；
    所述第一堆叠部分和所述第二堆叠部分等高。
  3. 根据权利要求2所述的半导体结构的制作方法，其中，于所述衬底上形成堆叠结构，包括：
    在所述衬底的所述第一区域和所述第二区域上分别形成初始栅极介电层，所述初始栅极介电层包括初始氧化层和初始高K介质层，所述初始高K介质层形成在所述初始氧化层的顶面上。
  4. 根据权利要求3所述的半导体结构的制作方法，其中，于所述衬底上形成堆叠结构，还包括：
    在所述初始高K介质层的顶面上依次堆叠形成初始第一阻挡层、初始第一功函数层和初始第二阻挡层；
    去除形成于所述第二区域上方的所述初始第一阻挡层、所述初始第一功函数层和所述初始第二阻挡层，保留形成于所述第一区域上方的所述初始第一阻挡层、所述初始第一功函数层和所述初始第二阻挡层。
  5. 根据权利要求4所述的半导体结构的制作方法，其中，于所述衬底上形成堆叠结构，还包括：
    于所述第一区域上方的所述初始第二阻挡层的顶面以及所述第二区域上方的所述初始高K介质层的顶面上形成刻蚀阻挡层；所述刻蚀阻挡层包括氧化物层和氮化物层；
    去除形成于所述第二区域上方的所述刻蚀阻挡层，保留形成于所述第一区域上方的所述刻蚀阻挡层。
  6. 根据权利要求5所述的半导体结构的制作方法，其中，于所述衬底上形成堆叠结构，还包括：
    形成初始第二功函数层，所述初始第二功函数层覆盖位于所述第二区域上方的所述初始高K介质层的顶面以及所述刻蚀阻挡层的顶面；
    形成初始第三阻挡层，所述初始第三阻挡层覆盖所述第二功函数层；
    去除形成于所述第一区域上方的所述初始第二功函数层、所述初始第三阻挡层和所述刻蚀阻挡层，保留形成于所述第二区域上方的所述初始第二功函数层和所述初始第三阻挡层。
  7. 根据权利要求6所述的半导体结构的制作方法，其中，所述初始第二阻挡层的顶面和所述初始第三阻挡层的顶面平齐。
  8. 根据权利要求6所述的半导体结构的制作方法，其中，于所述衬底上形成堆叠结构，还包括：
    于所述初始第二阻挡层的顶面和所述初始第三阻挡层的顶面依次堆叠形成初始金属层和初始隔离层。
  9. 根据权利要求8所述的半导体结构的制作方法，其中，于所述衬底上形成堆叠结构，还包括：
    形成初始半导体层和初始第四阻挡层，所述半导体层和所述初始第四阻挡层依次堆叠于所述第一区域上方的所述初始第二阻挡层和所述初始金属层之间，以及依次堆叠于所述第二区域上方的所述初始第三阻挡层和所述初始金属层之间。
  10. 根据权利要求8所述的半导体结构的制作方法，其中，所述制作方法，还包括：
    在所述隔离层的表面形成掩膜层，通过所述掩膜层刻蚀所述堆叠结构形成所述第一栅极结构和所述第二栅极结构。
  11. 根据权利要求10所述的半导体结构的制作方法，其中，所述制作方法，还包括：
    对所述第一栅极结构两侧的所述第一区域进行离子注入，分别形成第一源区和第一漏区；
    对所述第二栅极结构两侧的所述第二区域进行离子注入，形成第二源区和第二漏区。
  12. 一种半导体结构，所述半导体结构包括：
    衬底，所述衬底包括第一区域和第二区域；
    至少一个第一器件，所述第一器件设置在所述第一区域，所述第一器件包括第一栅极结构，所述第一栅极结构包括第一功函数层；
    至少一个第二器件，所述第二器件设置在所述第二区域，所述第二器件包括第二栅极结构，所述第二栅极结构包括第二功函数层；
    所述第一栅极结构和所述第二栅极结构的顶面平齐。
  13. 根据权利要求12所述的半导体结构，其中，
    所述第一栅极结构包括依次堆叠在所述第一区域上的第一栅极介电层、第一阻挡层、第一功函数层、第二阻挡层、第一金属层以及第一隔离层；
    所述第二栅极结构包括依次堆叠在所述第二区域上的第二栅极介电层、第二功函数层、第三阻挡层、第二金属层以及第二隔离层；
    所述第二阻挡层的顶面和所述第三阻挡层的顶面平齐。
  14. 根据权利要求13所述的半导体结构，其中，所述第一栅极结构还包括：依次堆叠于所述第二阻挡层和所述第一金属层之间的第一半导体层和第一第四阻挡层。
  15. 根据权利要求13所述的半导体结构，其中，所述第二栅极结构还包括：依次堆叠于所述第三阻挡层和所述第二金属层之间的第二半导体层和第二第四阻挡层。
  16. 根据权利要求12所述的半导体结构，其中，所述第一器件还包括：第一源区、第一漏区和第一沟道区，所述第一源区和所述第一漏区分别位于所述第一栅极结构的两侧，所述第一沟道区设置在所述第一栅极结构的下方；
    所述第二器件还包括：第二源区、第二漏区和第二沟道区，所述第二源区和所述第二漏区分别位于所述第二栅极结构的两侧，所述第二沟道区设置在所述第二栅极结构的下方。
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