WO2023137696A1 - Unité de stockage d'opération logique, réseau de stockage et mémoire d'opération logique - Google Patents

Unité de stockage d'opération logique, réseau de stockage et mémoire d'opération logique Download PDF

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WO2023137696A1
WO2023137696A1 PCT/CN2022/073145 CN2022073145W WO2023137696A1 WO 2023137696 A1 WO2023137696 A1 WO 2023137696A1 CN 2022073145 W CN2022073145 W CN 2022073145W WO 2023137696 A1 WO2023137696 A1 WO 2023137696A1
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transistor
pole
node
data
circuit
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PCT/CN2022/073145
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English (en)
Chinese (zh)
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崔小乐
张孙睿
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北京大学深圳研究生院
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Priority to PCT/CN2022/073145 priority Critical patent/WO2023137696A1/fr
Publication of WO2023137696A1 publication Critical patent/WO2023137696A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/501—Half or full adders, i.e. basic adder cells for one denomination

Definitions

  • the invention relates to the technical field of storage devices, in particular to a logical operation storage unit, a storage array and a logical operation memory.
  • the current computer architecture is the traditional von Neumann architecture. This architecture separates the computing unit from the storage unit, and the data needs to be read from the storage unit first, and then placed in the computing unit for calculation.
  • This architecture separates the computing unit from the storage unit, and the data needs to be read from the storage unit first, and then placed in the computing unit for calculation.
  • semiconductor technology the channel for data transmission between storage and computing units has become the bottleneck of the overall performance and power consumption of the computer.
  • a computing paradigm called in-memory computing has emerged.
  • SRAM As the main component of cache memory, SRAM has become a key research object for researchers based on Compute-in Memory, including the method of implementing logic operations on SRAM arrays.
  • the existing Static Random Access Memory (SRAM) is mainly based on a 6-tube structure or an 8-tube structure.
  • FIG 1 is a schematic diagram of the memory cell circuit structure of a 6T SRAM.
  • An 8T SRAM refers to a memory cell composed of six transistors. Each bit in the SRAM is stored in two cross-coupled inverters composed of four field effect transistors (M1, M2, M3, and M4). The other two field effect transistors (M5 and M6) are the control switches of the bit line (Bit Line) used by the memory cell for reading and writing.
  • the basic storage unit of a SRAM has two stable states of 0 and 1. It is composed of two CMOS inverters.
  • the input and output of the two inverters are cross-connected, that is, the output of the first inverter is connected to the input of the second inverter, and the output of the second inverter is connected to the input of the first inverter.
  • This realizes the locking and saving of the output states of the two inverters, that is, the state of 1 bit is stored.
  • the word line (Word Line) is high, so that the two control switch transistors M5 and M6 of each basic unit are turned on, and the basic unit is connected to the bit line (Bit Line).
  • the bit lines are used to read or write the saved state of the elementary cell.
  • two inverted bit lines are not necessary, such inverted bit lines help improve noise margins.
  • other SRAMs also have eight-tube, ten-tube or even more transistors per bit.
  • Figure 2 is a schematic diagram of a calculation method based on bit lines.
  • This type of calculation method can be implemented using traditional 6T SRAM cells, or 8T and 10T cells.
  • the bit lines BL and BLB of a certain column in the SRAM array are precharged to a high level first. Afterwards, word lines of multiple SRAM cells in the same column are activated simultaneously, their transmission transistors will be turned on simultaneously, and the voltage of the bit lines will change according to the logic values stored inside the two SRAM cells. When no less than one activated SRAM cell stores a logic value of 0, the voltage on the bit line will drop to a low level; otherwise, the bit line will remain high.
  • Figure 3 is a schematic diagram of a calculation method based on a look-up table (LUT).
  • LUT look-up table
  • bit-line-based computing methods can implement very limited types of logic operations in SRAM arrays, which adds many restrictions to the further implementation of arithmetic operations in storage arrays, so that a large number of operations that can be completed inside the storage array can only be realized through dedicated operation logic near the array.
  • dedicated operation logic does not have general versatility. For scenarios that require different operations, it is necessary to design completely different operational logic circuits around the array, which increases the design cost.
  • the calculation method based on the lookup table can meet the requirements of realizing any logic function, the solution based on the lookup table has a very large area overhead.
  • An n-input lookup table must store all 2 n calculation results, and these results must consume additional computing resources to obtain. However, only a few results of each operation are used, which wastes a lot of external computing resources and storage space.
  • the technical problem pre-solved in this application is how to implement memory logic operation based on SRAM.
  • a logic operation storage unit including a logic operation control circuit, a result storage circuit, a WBL connection terminal, a WBLB connection terminal, and N data storage circuits; wherein, N is an integer greater than 1;
  • the WBL connection end and the WBLB connection end are used to input data signals to be logically operated;
  • the data storage circuit is connected to the WBL connection end and the WBLB connection end, and is used to store the data signal to be logically operated;
  • the logical operation control circuit is connected to the result storage circuit and each of the data storage circuits, and is used to perform logical operation on the data signal to be logically operated stored in the data storage circuit, and store the calculation result data signal obtained by the logical operation in the result storage circuit;
  • Each of the data storage circuits includes a node Q, a node QB, an RBL connection end and an RBLB connection end;
  • the node Q is connected to the WBL connection end, and the node QB is connected to the WBLB connection end, and the node Q and the node QB are used to obtain the data signal to be logically operated from the WBL connection end and the WBLB connection end, and write the data signal to be logically operated into the data storage circuit;
  • the RBL connection end and the RBLB connection end are connected to the logic operation control circuit for reading the data signal to be logically operated from the data storage circuit , and sending the acquired logic operation data signal to the logic operation control circuit;
  • the logic operation control circuit includes a first data reading end, a second data reading end and a result output end; the first data reading end is connected to the RBL connection end of each of the data storage circuits, the second data reading end is connected to the RBLB connection end of each of the data storage circuits, and the first data reading end and the second data reading end are used to read the data signal to be logically operated from the data storage circuit; The data signal is sent to the result storage circuit through the result output terminal;
  • the result storage circuit includes a NORIN connection end and a first common line end, the first common line end is connected to the RBL connection end of each of the data storage circuits, the NORIN connection end is connected to the result output end, and the result storage circuit is used to store the calculation result data signal.
  • a storage array including M logical operation storage units as described in the first aspect; wherein, M is an integer greater than 0.
  • a logic operation memory comprising the storage array and the array logic calculation circuit as described in the second aspect; the array logic calculation circuit is connected to the RBL connection end of each of the logic operation storage units in the storage array, and the array logic calculation circuit obtains the calculation result data signal stored in the result storage circuit through the RBL connection end of each logic operation storage unit, and performs a logic operation on each of the obtained calculation result data signals to obtain an array logic operation result signal.
  • the logic operation storage unit includes a logic operation control circuit, a result storage circuit, a WBL connection terminal, a WBLB connection terminal and N data storage circuits.
  • the WBL connection end and the WBLB connection end are used to input the data signal to be logically operated
  • the data storage circuit is used to store the data signal to be logically operated
  • the logical operation control circuit is used to perform logical operation on the data signal to be logically operated stored in the data storage circuit, and store the calculation result data signal obtained by the logical operation in the result storage circuit.
  • the structure of the logic operation storage unit is to directly map the logic function to be implemented into the storage unit, the specific logic values of the N logic variables in the logic function are determined according to the input, so that all logic functions can be realized while retaining the original read-write and storage characteristics of the storage array.
  • Figure 1 is a schematic diagram of the memory cell circuit structure of 6T SRAM
  • FIG. 2 is a schematic diagram of a calculation method based on bit lines
  • Fig. 3 is a schematic diagram of a calculation method based on a lookup table
  • Fig. 4 is a schematic circuit diagram of a logical operation storage unit in an embodiment
  • Fig. 5 is a schematic circuit diagram of a result storage circuit in an embodiment
  • FIG. 6 is a schematic circuit diagram of a data storage circuit in an embodiment
  • Fig. 7 is a schematic structural diagram of a logical operation memory in another embodiment.
  • connection All include direct and indirect connection (connection).
  • Transistors in this application may be transistors of any structure, such as bipolar junction transistors (BJTs) or field effect transistors (FETs).
  • BJTs bipolar junction transistors
  • FETs field effect transistors
  • the transistor is a bipolar transistor
  • its control pole refers to the gate of the bipolar transistor
  • the first pole can be the collector or emitter of the bipolar transistor
  • the corresponding second pole can be the emitter or collector of the bipolar transistor.
  • the "emitter” and “collector” can be interchanged according to the signal flow direction
  • source” and “drain” can be interchanged according to the direction of signal flow.
  • node Q, node U, node QB and node UB are introduced in this application document to identify the relevant parts of the circuit structure, and they cannot be identified as additional terminals introduced in the circuit.
  • the potential is represented by V DD
  • the unit ground is GND
  • the actual ground is represented by GND
  • the virtual ground is represented by V SS .
  • the present invention proposes an N-input lookup table for realizing arbitrary logic functions based on an in-memory calculation method.
  • the look-up table based on the in-memory calculation method does not require external computing resources to program and deploy the look-up table in advance. It can complete operations only according to instructions like a processor, and at the same time retains the storage characteristics of the SRAM array itself, which can be stored, read and written normally.
  • the present invention enhances the flexibility of the use of the lookup table to a certain extent, improves the use efficiency of the storage space, and reduces the complexity of peripheral special operation logic.
  • the logic operation storage unit in the embodiment of the present application includes a logic operation control circuit, a result storage circuit, a WBL connection terminal, a WBLB connection terminal and N data storage circuits.
  • the WBL connection end and the WBLB connection end are used to input the data signal to be logically operated
  • the data storage circuit is used to store the data signal to be logically operated
  • the logical operation control circuit is used to perform logical operation on the data signal to be logically operated stored in the data storage circuit, and store the calculation result data signal obtained by the logical operation in the result storage circuit.
  • the structure of the logic operation storage unit is to directly map the logic function to be implemented into the storage unit, the specific logic values of the N logic variables in the logic function are determined according to the input, so that all logic functions can be realized while retaining the original read-write and storage characteristics of the storage array.
  • FIG. 4 is a schematic circuit diagram of a logic operation storage unit in an embodiment.
  • the logic operation storage unit includes a logic operation control circuit 1, a result storage circuit 2, a WBL connection end, a WBLB connection end and N data storage circuits 3, wherein N is an integer greater than 1.
  • the WBL connection end and the WBLB connection end are used for inputting data signals to be logically operated.
  • the data storage circuit 3 is connected to the WBL connection terminal and the WBLB connection terminal, and is used for storing data signals to be logically operated.
  • the logical operation control circuit 1 is connected with the result storage circuit 2 and each of the data storage circuits 3, and is used to perform logical operations on the data signals to be logically operated stored in the data storage circuit 3, and store the calculation result data signals obtained by the logical operations in the result storage circuits 2.
  • Each data storage circuit 3 includes a node Q, a node QB, an RBL connection end and an RBLB connection end, the node Q is connected to the WBL connection end, the node QB is connected to the WBLB connection end, and the node Q and the node QB are used to obtain the data signal to be logically operated from the WBL connection end and the WBLB connection end, and write the data signal to be logically operated into the data storage circuit 3.
  • the RBL connection end and the RBLB connection end are connected to the logic operation control circuit 1 for reading the data signal to be logical operation from the data storage circuit 3 and sending the read acquired data signal to the logic operation control circuit 1 .
  • the logical operation control circuit 1 includes a first data reading end, a second data reading end and a result output end, the first data reading end is connected to the RBL connection end of each data storage circuit 3, the second data reading end is connected to the RBLB connection end of each data storage circuit 3, and the first data reading end and the second data reading end are used to read the data signal to be logically operated from the data storage circuit 3.
  • the result output terminal is connected to the result storage circuit 2, and the logical operation control circuit 1 is used to perform logical operation on the read data signal to be logically operated, and send the calculation result data signal obtained by the logical operation to the result storage circuit 2 through the result output terminal.
  • the result storage circuit 2 includes a NORIN connection end and a first common line end, the first common line end is connected to the RBL connection end of each data storage circuit 3, the NORIN connection end is connected to the result output end, and the result storage circuit 2 is used for storing calculation result data signals.
  • the result storage circuit further includes a result input circuit 22, a result reading circuit 23, a first latch 21, a CWL connection terminal, a RWLL connection terminal, a RWLR connection terminal, a node U and a node UB.
  • the CWL connection end is used to input the write control signal CWL
  • the RWLL connection end and the RWLR connection end are used to respectively input the read control signal RWLL and the read control signal RWLR.
  • the first latch 21 includes a transistor P21, a transistor P22, a transistor N21 and a transistor N22, and the first latch 21 is used for storing the calculation result data signal.
  • each transistor includes a first pole, a second pole and a control pole.
  • the control electrode of the transistor P21 is connected to the node UB, the first electrode of the transistor P21 is used for inputting the working voltage signal V DD , and the second electrode of the transistor P21 is connected to the node U.
  • the control electrode of the transistor P22 is connected to the node U, the first electrode of the transistor P22 is used for inputting the working voltage signal V DD , and the second electrode of the transistor P22 is connected to the node UB.
  • the control electrode of the transistor N21 is connected to the node UB, the first electrode of the transistor N21 is connected to the node U, and the second electrode of the transistor N21 is grounded.
  • the control electrode of the transistor N22 is connected to the node U, the first electrode of the transistor N22 is connected to the node UB, and the second electrode of the transistor N22 is grounded.
  • the result input circuit 22 includes a transistor N23, a transistor N24 and a transistor N25.
  • the control electrode of the transistor N23 is connected to the NORIN terminal, the first electrode of the transistor N23 is connected to the first electrode of the transistor N24, and the second electrode of the transistor N23 is connected to the node UB.
  • the control electrode of the transistor N24 is connected to the CWL connection terminal, and the second electrode of the transistor N24 is grounded.
  • the control electrode of the transistor N25 is connected to the CWL connection terminal, the first electrode of the transistor N25 is connected to the NORIN connection terminal, and the second electrode of the transistor N25 is connected to the node U.
  • the result reading circuit 23 includes a transistor N26, a transistor N27, a transistor N28, and a transistor N29.
  • the control electrode of the transistor N26 is connected to the RWLL connection terminal, the first electrode of the transistor N26 is connected to the first electrode of the transistor N27, and the second electrode of the transistor N26 is connected to the RBL connection terminal.
  • the control electrode of the transistor N27 is connected to the node U, and the second electrode of the transistor N27 is grounded.
  • the control electrode of the transistor N28 is connected to the node UB, the first electrode of the transistor N28 is connected to the first electrode of the transistor N29, and the second electrode of the transistor N29 is grounded.
  • the control electrode of the transistor N29 is connected to the RWLR connection terminal, and the second electrode of the transistor N29 is connected to the RBL connection terminal.
  • the data storage circuit includes a data write circuit 33, a second latch 31, a data read circuit 32, an RWL connection end, an RWLB connection end, a WWL connection end, a node Q, and a node QB.
  • the WWL connection end is used to input the write control signal WWL
  • the RWL connection end and the RWLB connection end are used to respectively input the read control signal RWL and the read control signal RWLB.
  • the second latch 31 includes a transistor P31 , a transistor P32 , a transistor N31 and a transistor N32 , and the second latch 31 is used for storing data signals to be logically operated.
  • each transistor includes a first pole, a second pole and a control pole.
  • the control electrode of the transistor P31 is connected to the node QB, the first electrode of the transistor P31 is used for inputting the working voltage signal V DD , and the second electrode of the transistor P31 is connected to the node Q.
  • the control electrode of the transistor P32 is connected to the node Q, the first electrode of the transistor P32 is used for inputting the working voltage signal V DD , and the second electrode of the transistor P32 is connected to the node QB.
  • the control electrode of the transistor N31 is connected to the node QB, the first electrode of the transistor N31 is connected to the node Q, and the second electrode of the transistor N31 is grounded.
  • the control electrode of the transistor N32 is connected to the node Q, the first electrode of the transistor N32 is connected to the node QB, and the second electrode of the transistor N32 is grounded.
  • the data writing circuit 32 includes a transistor N33 and a transistor N34.
  • the control electrode of the transistor N33 is connected to the WWL terminal, the first electrode of the transistor N33 is connected to the WBLB terminal, and the second electrode of the transistor N33 is connected to the node QB.
  • the control electrode of the transistor N34 is connected to the WWL connection terminal, the first electrode of the transistor N34 is connected to the WBL connection terminal, and the second electrode of the transistor N33 is connected to the node Q.
  • the data reading circuit 33 includes a transistor N35, a transistor N36, a transistor N37, and a transistor N38.
  • the control electrode of the transistor N35 is connected to the node QB, the first electrode of the transistor N35 is connected to the first electrode of the transistor N36, and the second electrode of the transistor N35 is grounded.
  • the control electrode of the transistor N36 is connected to the RWL connection terminal, and the second electrode of the transistor N36 is connected to the RBL connection terminal.
  • the control electrode of the transistor N37 is connected to the node Q, the first electrode of the transistor N37 is connected to the first electrode of the transistor N38, and the second electrode of the transistor N37 is grounded.
  • the control electrode of the transistor N38 is connected to the RWLB connection terminal, and the second electrode of the transistor N38 is connected to the RBLB connection terminal.
  • the logical operation control 1 circuit also includes a first driver, a second driver and a NOR gate circuit.
  • the two input terminals of the NOR gate circuit are respectively connected with the first data reading terminal and the second data reading terminal, and the output terminal of the NOR gate circuit is connected with the NORIN connection terminal.
  • the output end of the first driver is connected to the first data reading end, and the output end of the second driver is connected to the second data reading end.
  • the first driver is used for inputting logic operation control signals to the first data reading end.
  • the second driver is used for inputting logic operation control signals to the second data reading end.
  • the application discloses a logic operation storage unit, which includes a logic operation control circuit, a result storage circuit, a WBL connection terminal, a WBLB connection terminal and N data storage circuits.
  • the WBL connection end and the WBLB connection end are used to input the data signal to be logically operated
  • the data storage circuit is used to store the data signal to be logically operated
  • the logical operation control circuit is used to perform logical operation on the data signal to be logically operated stored in the data storage circuit, and store the calculation result data signal obtained by the logical operation in the result storage circuit.
  • the structure of the logic operation storage unit is to directly map the logic function to be implemented into the storage unit, the specific logic values of the N logic variables in the logic function are determined according to the input, so that all logic functions can be realized while retaining the original read-write and storage characteristics of the storage array.
  • FIG. 7 is a schematic structural diagram of a logic operation memory in another embodiment.
  • a storage array is disclosed.
  • the storage array 100 includes M logic operation storage units disclosed in Embodiment 1, where M is an integer greater than 0. In one embodiment, M ⁇ 2 N-2 .
  • the present application discloses a logic operation memory, which includes the storage array 100 and the array logic calculation circuit 200 as described above.
  • the array logic calculation circuit 200 is connected to the RBL connection end of each logic operation storage unit 110 in the storage array 100, the array logic calculation circuit 200 obtains the calculation result data signal stored in the result storage circuit through the RBL connection end of each logic operation storage unit 110, and performs logic operation on each obtained calculation result data signal to obtain the array logic operation result signal.
  • the array logic calculation circuit 200 includes a TWL connection terminal, M array data acquisition circuits 210 and an array logic operation result output circuit 220 .
  • the TWL connection end is used for inputting the logic operation control signal TWL.
  • Each array data acquisition circuit 210 corresponds to one logical operation storage unit 110 .
  • the array data acquisition circuit 210 includes a transistor N41 and a transistor N42.
  • the control pole of the transistor N41 is connected to the RBL connection terminal of the logic operation storage unit 110 corresponding to the array data acquisition circuit 210, the first pole of the transistor N41 is connected to the array logic operation result output circuit 220, the second pole of the transistor N41 is connected to the first pole of the transistor N42, the control pole of the transistor N42 is connected to the TWL connection terminal, and the second pole of the transistor N42 is grounded.
  • the array logic operation result output circuit 220 includes a signal amplifier SA, the input terminal of the signal amplifier SA is connected to the first pole of the transistor N41 of each array data acquisition circuit 210, and the output terminal of the signal amplifier SA is used to output the array logic operation result signal.
  • the signal amplifier SA includes a first output terminal and a second output terminal, the first output terminal of the signal amplifier SA is used to output the array logic operation result signal, and the second output terminal of the signal amplifier SA is used to output the inversion signal of the array logic operation result signal.
  • a look-up table (LUT) consists of three SRAM cells sharing a bit line, a NOR gate, and write drivers for two bit lines.
  • N 2 as an example.
  • a look-up table (LUT) consists of three SRAM cells sharing a bit line, a NOR gate, and write drivers for two bit lines.
  • the three SRAM cells sharing a bit line there are two data storage circuits (10T unit for short) as shown in FIG. 5 and one result storage circuit (11T unit for short) as shown in FIG. 6 .
  • the write word line WWL in Figure 6 is the write word line of the 10T SRAM unit, that is, the control signal of the write port.
  • RWL and RWLB are the read word lines of the 10T unit, that is, the control signals of the read port.
  • a total of 4 word lines input to 2 10T cells in the LUT are independent of each other.
  • the two variables of the logic function will be mapped one by one to the two 10T units contained in the 2-input LUT during calculation.
  • the 2-input LUT can generate a total of 16 logic functions, covering all possible truth tables of 2-variable logic functions. The logic operations required by these functions can be roughly divided into the following three parts:
  • the precharged bit line will decide whether to discharge according to the data stored in the 10T cell.
  • the two storage nodes of the first 10T unit as shown in Figure 4 are Q1 and QB1 respectively
  • the Q1 node stores the logical variable A
  • the QB1 stores
  • the two storage nodes of the second 10T unit are Q2 and QB2 respectively
  • the Q2 node stores the logic variable B
  • the logical value A stored by Q1 is read to the RBL, and the logical value stored by QB1 Read to RBLB. so that we can get The result of two logical operations; similarly, by opening the read port of the read port RWLR of the 11T unit, it can be obtained the result of. If the read ports on the same side of the two 10T units in the LUT unit are activated at the same time, the RBL/RBLB will discharge according to the data stored in the two cells.
  • the logical operation memory in the embodiment of the present application includes a storage array with a size of M columns (M ⁇ 2 N-2 ) and N rows, where each column is based on a 2-input LUT with N-2 10T units added.
  • These additional 10T cells have a row-shared double word line RWLL/RWLR, where RWLL is shared by the left read port (connected to the RBL of each column) of all 10T cells in the same row, and RWLR is shared by the right read port (connected to the RBLB of each column) of all 10T SRAM cells.
  • RWLL/RWLR row-shared double word line
  • RWLL is shared by the left read port (connected to the RBL of each column) of all 10T cells in the same row
  • RWLR is shared by the right read port (connected to the RBLB of each column) of all 10T SRAM cells.
  • TBL bottom lateral bit line
  • the transpose read port is controlled by a shared word line TWL.
  • a single-ended sense amplifier is connected to the end of the transverse bit line TBL for rapidly reading out the calculation result.
  • Such an array can implement all N-variable logic functions, that is, the array is an N-variable LUT.
  • mapping rules are as follows: first write the logic function into the simplest "and or” formula, and then map each "and” item of the "and or” formula to the 10T unit of each column in the array.
  • the 11T unit is only used as a result operation unit, and it is not allowed to map logic variables when implementing logic functions.
  • there is no difference between the two 10T units contained in the 2-input LUT and the other 10T units in the column in the variable mapping that is, the position in the column where the variable contained in the "AND" item is mapped does not affect the final calculation result.
  • the read bit lines RBL/RBLB of all columns are precharged first, and then the 2-input LUT part performs an "AND” operation according to the aforementioned operation flow.
  • the left read port word line RWLL of all other 10T cells is activated at the same time, and the RBL will discharge according to the data stored in all 10T cells, which is equivalent to completing the "AND” operation of all logic variables in the "AND” item, and the operation result is retained on the RBL.
  • the RBL of each column in the array is loaded with the results of each "AND” item. Subsequently, the transposed bit line TBL starts precharging. After the TBL is precharged to a high level, the TWL is activated, and the TBL will be discharged according to the voltage on each column RBL (that is, the calculation result of each "AND” item). When one or more RBLs are high, the TBL will discharge. This is equivalent to "NOR" the data loaded on each RBL.
  • the N-input LUT can be regarded as a complete SRAM array as a whole, and the array still has normal read and write functions that a general SRAM array has.
  • the read bit line RBL/RBLB corresponding to the column where the cell is located is firstly precharged. If the unit to be read is a unit in a 2-input LUT, then the two independent word lines of the unit are activated at the same time, and the value stored in the unit is read to the bit line; if the unit to be read is another 10T unit, the two word lines RWLL/RWLR of the row where the unit is located are activated at the same time, and the value stored in the unit is read to the bit line. Subsequently, TBL is precharged, TWL is activated, and the sense amplifier connected to TBL outputs the value read.
  • the cell to be written When writing to a certain cell in the array, if the cell to be written is a 10T cell, first load the data to be written to the write bit line WBL/WBLB of the column where the cell is located. Then activate the word line WWL of the write port, and write the data to the storage node of the unit through the transmission tube; if the unit to be written is an 11T SRAM unit, it can be divided into two situations according to the written logic value: when it is necessary to write "0", charge the read bit line RBL/RBLB to high level, turn on the write word line CWL in the 11T unit, and then write "0" into the 11T unit. When it is necessary to write "1”, the read bit lines RBL/RBLB are all loaded with "0", and the CWL is turned on, and "1" can be written into the 11T unit.
  • This application proposes a two-input look-up table that realizes all two-variable logic functions (sixteen types in total) based on an in-memory calculation method instead of a traditional memory access method.
  • an N-input look-up table that can realize logic functions with any number of variables is developed. What the traditional N-input lookup table stores are all 2 N possible results corresponding to a certain certain N variable logic function, and the lookup table structure proposed by the application directly maps the logic function itself to be realized in the storage unit, and the specific logic values of the N logic variables in the logic function are determined according to the input.
  • the look-up table proposed in this application retains the original read-write and storage characteristics of the storage array while realizing all logic functions.

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  • General Engineering & Computer Science (AREA)
  • Static Random-Access Memory (AREA)

Abstract

La présente demande divulgue une unité de stockage d'opération logique, un réseau de stockage et une mémoire d'opération logique. L'unité de stockage d'opération logique comprend un circuit de commande d'opération logique, un circuit de stockage de résultat, une extrémité de connexion de WBL, une extrémité de connexion de WBLB et N circuits de stockage de données. L'extrémité de connexion de WBL et l'extrémité de connexion de WBLB sont utilisées pour entrer des signaux de données à soumettre à une opération logique, les circuits de stockage de données sont utilisés pour stocker lesdits signaux de données et le circuit de commande d'opération logique est utilisé pour effectuer une opération logique sur lesdits signaux de données stockés dans les circuits de stockage de données, et pour stocker, dans le circuit de stockage de résultat, un signal de données de résultat de calcul acquis au moyen d'une opération logique. La structure de l'unité de stockage d'opération logique consiste à mapper directement, à l'unité de stockage, une fonction logique qui doit être réalisée, et des valeurs logiques spécifiques de N variables logiques dans la fonction logique sont déterminées en fonction de l'entrée de telle sorte que toutes les fonctions logiques soient réalisées et que les caractéristiques de lecture-écriture et de stockage d'origine du réseau de stockage puissent également être conservées.
PCT/CN2022/073145 2022-01-21 2022-01-21 Unité de stockage d'opération logique, réseau de stockage et mémoire d'opération logique WO2023137696A1 (fr)

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US20160189769A1 (en) * 2014-12-30 2016-06-30 The Regents Of The University Of Michigan A storage device supporting logical operations, methods and storage medium
CN110364203A (zh) * 2019-06-20 2019-10-22 中山大学 一种支撑存储内计算的存储系统及计算方法
CN111863071A (zh) * 2020-07-22 2020-10-30 上海高性能集成电路设计中心 一种基于sram实现存内运算的电路结构
CN112116937A (zh) * 2020-09-25 2020-12-22 安徽大学 一种在存储器中实现乘法和或逻辑运算的sram电路结构
CN112133339A (zh) * 2020-08-12 2020-12-25 清华大学 基于铁电晶体管的存内按位逻辑计算电路结构
CN112214197A (zh) * 2020-10-16 2021-01-12 苏州兆芯半导体科技有限公司 Sram全加器及多比特sram全加器

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US20160189769A1 (en) * 2014-12-30 2016-06-30 The Regents Of The University Of Michigan A storage device supporting logical operations, methods and storage medium
CN110364203A (zh) * 2019-06-20 2019-10-22 中山大学 一种支撑存储内计算的存储系统及计算方法
CN111863071A (zh) * 2020-07-22 2020-10-30 上海高性能集成电路设计中心 一种基于sram实现存内运算的电路结构
CN112133339A (zh) * 2020-08-12 2020-12-25 清华大学 基于铁电晶体管的存内按位逻辑计算电路结构
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117708042A (zh) * 2023-12-28 2024-03-15 中科南京智能技术研究院 一种单边控制的存内计算电路及存储器

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