WO2023137696A1

WO2023137696A1 - Logical operation storage unit, storage array and logical operation memory

Info

Publication number: WO2023137696A1
Application number: PCT/CN2022/073145
Authority: WO
Inventors: 崔小乐; 张孙睿
Original assignee: 北京大学深圳研究生院
Priority date: 2022-01-21
Filing date: 2022-01-21
Publication date: 2023-07-27

Abstract

Disclosed in the present application are a logical operation storage unit, a storage array and a logical operation memory. The logical operation storage unit comprises a logical operation control circuit, a result storage circuit, a WBL connecting end, a WBLB connecting end and N data storage circuits. The WBL connecting end and the WBLB connecting end are used for inputting data signals to be subjected to logical operation, the data storage circuits are used for storing said data signals, and the logical operation control circuit is used for performing a logical operation on said data signals stored in the data storage circuits, and storing, in the result storage circuit, a calculation result data signal acquired by means of logical operation. The structure of the logical operation storage unit involves directly mapping, to the storage unit, a logical function that needs to be realized, and specific logical values of N logical variables in the logical function are determined according to the input, such that all logical functions are realized, and the original read-write and storage characteristics of the storage array can also be retained.

Description

A logical operation storage unit, a storage array and a logical operation memory

technical field

The invention relates to the technical field of storage devices, in particular to a logical operation storage unit, a storage array and a logical operation memory.

Background technique

The current computer architecture is the traditional von Neumann architecture. This architecture separates the computing unit from the storage unit, and the data needs to be read from the storage unit first, and then placed in the computing unit for calculation. With the development of semiconductor technology, the channel for data transmission between storage and computing units has become the bottleneck of the overall performance and power consumption of the computer. In order to break this bottleneck, a computing paradigm called in-memory computing has emerged. As the main component of cache memory, SRAM has become a key research object for researchers based on Compute-in Memory, including the method of implementing logic operations on SRAM arrays. The existing Static Random Access Memory (SRAM) is mainly based on a 6-tube structure or an 8-tube structure. Please refer to Figure 1, which is a schematic diagram of the memory cell circuit structure of a 6T SRAM. An 8T SRAM refers to a memory cell composed of six transistors. Each bit in the SRAM is stored in two cross-coupled inverters composed of four field effect transistors (M1, M2, M3, and M4). The other two field effect transistors (M5 and M6) are the control switches of the bit line (Bit Line) used by the memory cell for reading and writing. The basic storage unit of a SRAM has two stable states of 0 and 1. It is composed of two CMOS inverters. The input and output of the two inverters are cross-connected, that is, the output of the first inverter is connected to the input of the second inverter, and the output of the second inverter is connected to the input of the first inverter. This realizes the locking and saving of the output states of the two inverters, that is, the state of 1 bit is stored. When accessing the SRAM, the word line (Word Line) is high, so that the two control switch transistors M5 and M6 of each basic unit are turned on, and the basic unit is connected to the bit line (Bit Line). The bit lines are used to read or write the saved state of the elementary cell. Although two inverted bit lines are not necessary, such inverted bit lines help improve noise margins. In addition to six-tube SRAM, other SRAMs also have eight-tube, ten-tube or even more transistors per bit.

At present, there are mainly two methods for implementing logic operations on the SRAM array, namely, a calculation method based on bit lines and a calculation method based on a look-up table (LUT).

Please refer to Figure 2, which is a schematic diagram of a calculation method based on bit lines. This type of calculation method can be implemented using traditional 6T SRAM cells, or 8T and 10T cells. The bit lines BL and BLB of a certain column in the SRAM array are precharged to a high level first. Afterwards, word lines of multiple SRAM cells in the same column are activated simultaneously, their transmission transistors will be turned on simultaneously, and the voltage of the bit lines will change according to the logic values stored inside the two SRAM cells. When no less than one activated SRAM cell stores a logic value of 0, the voltage on the bit line will drop to a low level; otherwise, the bit line will remain high. The relationship between the voltage on the stabilized BL and the logic value stored in the SRAM is "AND", while the relationship between the voltage on the BLB and the logic value stored in the SRAM is "NOR". If a single-ended sense amplifier is connected to the ends of BL and BLB, we can quickly obtain the results of the two logical operations of "AND" and "NOR" of any unit in this column. These two logic functions are realized by using 8T SRAM cells, and logical operations such as "AND", "XOR" and "implication" are realized by means of design techniques such as word line activation pulse and asymmetric inverter. Using some combinational logic and sequential logic circuits integrated near the storage array, such as XOR gates, ripple carry adders, shift registers, etc., some simple arithmetic operations, such as addition and multiplication, are realized based on bit serial/parallel.

Please refer to Figure 3, which is a schematic diagram of a calculation method based on a look-up table (LUT). What is stored in the RAM array is not the original input data, but all possible results that can be obtained by the target operation. The input data is now regarded as an address signal and used to address the corresponding results. The results read from the LUTs can be fed into dedicated logic circuits on the periphery of the array for further processing. Because the calculation method based on the LUT does not produce the result in the SRAM array, but simply reads and writes the calculated result, it has lower power consumption and area overhead than the calculation method based on the bit line.

There are some problems in the above two methods of implementing logic operations based on the SRAM array. For example, bit-line-based computing methods can implement very limited types of logic operations in SRAM arrays, which adds many restrictions to the further implementation of arithmetic operations in storage arrays, so that a large number of operations that can be completed inside the storage array can only be realized through dedicated operation logic near the array. Although these special operation logics are fast, they seriously increase the area of peripheral circuits. In addition, dedicated operation logic does not have general versatility. For scenarios that require different operations, it is necessary to design completely different operational logic circuits around the array, which increases the design cost. For example, although the calculation method based on the lookup table can meet the requirements of realizing any logic function, the solution based on the lookup table has a very large area overhead. An n-input lookup table must store all 2 ⁿ calculation results, and these results must consume additional computing resources to obtain. However, only a few results of each operation are used, which wastes a lot of external computing resources and storage space.

Contents of the invention

The technical problem pre-solved in this application is how to implement memory logic operation based on SRAM.

According to the first aspect, there is provided a logic operation storage unit, including a logic operation control circuit, a result storage circuit, a WBL connection terminal, a WBLB connection terminal, and N data storage circuits; wherein, N is an integer greater than 1;

The WBL connection end and the WBLB connection end are used to input data signals to be logically operated;

The data storage circuit is connected to the WBL connection end and the WBLB connection end, and is used to store the data signal to be logically operated;

The logical operation control circuit is connected to the result storage circuit and each of the data storage circuits, and is used to perform logical operation on the data signal to be logically operated stored in the data storage circuit, and store the calculation result data signal obtained by the logical operation in the result storage circuit;

Each of the data storage circuits includes a node Q, a node QB, an RBL connection end and an RBLB connection end; the node Q is connected to the WBL connection end, and the node QB is connected to the WBLB connection end, and the node Q and the node QB are used to obtain the data signal to be logically operated from the WBL connection end and the WBLB connection end, and write the data signal to be logically operated into the data storage circuit; the RBL connection end and the RBLB connection end are connected to the logic operation control circuit for reading the data signal to be logically operated from the data storage circuit , and sending the acquired logic operation data signal to the logic operation control circuit;

The logic operation control circuit includes a first data reading end, a second data reading end and a result output end; the first data reading end is connected to the RBL connection end of each of the data storage circuits, the second data reading end is connected to the RBLB connection end of each of the data storage circuits, and the first data reading end and the second data reading end are used to read the data signal to be logically operated from the data storage circuit; The data signal is sent to the result storage circuit through the result output terminal;

The result storage circuit includes a NORIN connection end and a first common line end, the first common line end is connected to the RBL connection end of each of the data storage circuits, the NORIN connection end is connected to the result output end, and the result storage circuit is used to store the calculation result data signal.

According to the second aspect, there is provided a storage array, including M logical operation storage units as described in the first aspect; wherein, M is an integer greater than 0.

According to a third aspect, there is provided a logic operation memory, comprising the storage array and the array logic calculation circuit as described in the second aspect; the array logic calculation circuit is connected to the RBL connection end of each of the logic operation storage units in the storage array, and the array logic calculation circuit obtains the calculation result data signal stored in the result storage circuit through the RBL connection end of each logic operation storage unit, and performs a logic operation on each of the obtained calculation result data signals to obtain an array logic operation result signal.

The logic operation storage unit according to the above embodiment includes a logic operation control circuit, a result storage circuit, a WBL connection terminal, a WBLB connection terminal and N data storage circuits. The WBL connection end and the WBLB connection end are used to input the data signal to be logically operated, the data storage circuit is used to store the data signal to be logically operated, and the logical operation control circuit is used to perform logical operation on the data signal to be logically operated stored in the data storage circuit, and store the calculation result data signal obtained by the logical operation in the result storage circuit. Since the structure of the logic operation storage unit is to directly map the logic function to be implemented into the storage unit, the specific logic values of the N logic variables in the logic function are determined according to the input, so that all logic functions can be realized while retaining the original read-write and storage characteristics of the storage array.

Description of drawings

Figure 1 is a schematic diagram of the memory cell circuit structure of 6T SRAM;

FIG. 2 is a schematic diagram of a calculation method based on bit lines;

Fig. 3 is a schematic diagram of a calculation method based on a lookup table;

Fig. 4 is a schematic circuit diagram of a logical operation storage unit in an embodiment;

Fig. 5 is a schematic circuit diagram of a result storage circuit in an embodiment;

6 is a schematic circuit diagram of a data storage circuit in an embodiment;

Fig. 7 is a schematic structural diagram of a logical operation memory in another embodiment.

Detailed ways

The present invention will be further described in detail below through specific embodiments in conjunction with the accompanying drawings. Wherein, similar elements in different implementations adopt associated similar element numbers. In the following implementation manners, many details are described for better understanding of the present application. However, those skilled in the art can readily recognize that some of the features can be omitted in different situations, or can be replaced by other elements, materials, and methods. In some cases, some operations related to the present application are not shown or described in the description. This is to avoid the core part of the present application from being overwhelmed by too many descriptions. For those skilled in the art, it is not necessary to describe these related operations in detail. They can fully understand the related operations according to the description in the description and general technical knowledge in the field.

In addition, the characteristics, operations or characteristics described in the specification can be combined in any appropriate manner to form various embodiments. At the same time, the steps or actions in the method description can also be exchanged or adjusted in a manner obvious to those skilled in the art. Therefore, the various sequences in the specification and drawings are only for clearly describing a certain embodiment, and do not mean a necessary sequence, unless otherwise stated that a certain sequence must be followed.

The serial numbers assigned to components in this document, such as "first", "second", etc., are only used to distinguish the described objects, and do not have any sequence or technical meaning. And the application said "connection", "connection", if not specified, all include direct and indirect connection (connection).

Firstly, some terms involved in this application will be explained below.

Transistors in this application may be transistors of any structure, such as bipolar junction transistors (BJTs) or field effect transistors (FETs). When the transistor is a bipolar transistor, its control pole refers to the gate of the bipolar transistor, the first pole can be the collector or emitter of the bipolar transistor, and the corresponding second pole can be the emitter or collector of the bipolar transistor. In practical applications, the "emitter" and "collector" can be interchanged according to the signal flow direction; In practical applications, "source" and "drain" can be interchanged according to the direction of signal flow. It should be noted that, for the convenience of description and for those skilled in the art to understand the technical solution of this application more clearly, the node Q, node U, node QB and node UB are introduced in this application document to identify the relevant parts of the circuit structure, and they cannot be identified as additional terminals introduced in the circuit. For the convenience of description, the potential is represented by V _DD , the unit ground is GND, the actual ground is represented by GND, and the virtual ground is represented by V _SS .

In order to expand the logic functions that can be realized by the SRAM array, the present invention proposes an N-input lookup table for realizing arbitrary logic functions based on an in-memory calculation method. The look-up table based on the in-memory calculation method does not require external computing resources to program and deploy the look-up table in advance. It can complete operations only according to instructions like a processor, and at the same time retains the storage characteristics of the SRAM array itself, which can be stored, read and written normally. Compared with the existing SRAM logic operation scheme, the present invention enhances the flexibility of the use of the lookup table to a certain extent, improves the use efficiency of the storage space, and reduces the complexity of peripheral special operation logic.

The logic operation storage unit in the embodiment of the present application includes a logic operation control circuit, a result storage circuit, a WBL connection terminal, a WBLB connection terminal and N data storage circuits. The WBL connection end and the WBLB connection end are used to input the data signal to be logically operated, the data storage circuit is used to store the data signal to be logically operated, and the logical operation control circuit is used to perform logical operation on the data signal to be logically operated stored in the data storage circuit, and store the calculation result data signal obtained by the logical operation in the result storage circuit. Since the structure of the logic operation storage unit is to directly map the logic function to be implemented into the storage unit, the specific logic values of the N logic variables in the logic function are determined according to the input, so that all logic functions can be realized while retaining the original read-write and storage characteristics of the storage array.

Example 1:

Please refer to FIG. 4 , which is a schematic circuit diagram of a logic operation storage unit in an embodiment. The logic operation storage unit includes a logic operation control circuit 1, a result storage circuit 2, a WBL connection end, a WBLB connection end and N data storage circuits 3, wherein N is an integer greater than 1. The WBL connection end and the WBLB connection end are used for inputting data signals to be logically operated. The data storage circuit 3 is connected to the WBL connection terminal and the WBLB connection terminal, and is used for storing data signals to be logically operated. The logical operation control circuit 1 is connected with the result storage circuit 2 and each of the data storage circuits 3, and is used to perform logical operations on the data signals to be logically operated stored in the data storage circuit 3, and store the calculation result data signals obtained by the logical operations in the result storage circuits 2. Each data storage circuit 3 includes a node Q, a node QB, an RBL connection end and an RBLB connection end, the node Q is connected to the WBL connection end, the node QB is connected to the WBLB connection end, and the node Q and the node QB are used to obtain the data signal to be logically operated from the WBL connection end and the WBLB connection end, and write the data signal to be logically operated into the data storage circuit 3. The RBL connection end and the RBLB connection end are connected to the logic operation control circuit 1 for reading the data signal to be logical operation from the data storage circuit 3 and sending the read acquired data signal to the logic operation control circuit 1 . The logical operation control circuit 1 includes a first data reading end, a second data reading end and a result output end, the first data reading end is connected to the RBL connection end of each data storage circuit 3, the second data reading end is connected to the RBLB connection end of each data storage circuit 3, and the first data reading end and the second data reading end are used to read the data signal to be logically operated from the data storage circuit 3. The result output terminal is connected to the result storage circuit 2, and the logical operation control circuit 1 is used to perform logical operation on the read data signal to be logically operated, and send the calculation result data signal obtained by the logical operation to the result storage circuit 2 through the result output terminal. The result storage circuit 2 includes a NORIN connection end and a first common line end, the first common line end is connected to the RBL connection end of each data storage circuit 3, the NORIN connection end is connected to the result output end, and the result storage circuit 2 is used for storing calculation result data signals.

Please refer to FIG. 5 , which is a schematic circuit diagram of the result storage circuit in an embodiment. In one embodiment, the result storage circuit further includes a result input circuit 22, a result reading circuit 23, a first latch 21, a CWL connection terminal, a RWLL connection terminal, a RWLR connection terminal, a node U and a node UB. The CWL connection end is used to input the write control signal CWL, and the RWLL connection end and the RWLR connection end are used to respectively input the read control signal RWLL and the read control signal RWLR. The first latch 21 includes a transistor P21, a transistor P22, a transistor N21 and a transistor N22, and the first latch 21 is used for storing the calculation result data signal. Wherein, each transistor includes a first pole, a second pole and a control pole. The control electrode of the transistor P21 is connected to the node UB, the first electrode of the transistor P21 is used for inputting the working voltage signal V _DD , and the second electrode of the transistor P21 is connected to the node U. The control electrode of the transistor P22 is connected to the node U, the first electrode of the transistor P22 is used for inputting the working voltage signal V _DD , and the second electrode of the transistor P22 is connected to the node UB. The control electrode of the transistor N21 is connected to the node UB, the first electrode of the transistor N21 is connected to the node U, and the second electrode of the transistor N21 is grounded. The control electrode of the transistor N22 is connected to the node U, the first electrode of the transistor N22 is connected to the node UB, and the second electrode of the transistor N22 is grounded. The result input circuit 22 includes a transistor N23, a transistor N24 and a transistor N25. The control electrode of the transistor N23 is connected to the NORIN terminal, the first electrode of the transistor N23 is connected to the first electrode of the transistor N24, and the second electrode of the transistor N23 is connected to the node UB. The control electrode of the transistor N24 is connected to the CWL connection terminal, and the second electrode of the transistor N24 is grounded. The control electrode of the transistor N25 is connected to the CWL connection terminal, the first electrode of the transistor N25 is connected to the NORIN connection terminal, and the second electrode of the transistor N25 is connected to the node U. The result reading circuit 23 includes a transistor N26, a transistor N27, a transistor N28, and a transistor N29. The control electrode of the transistor N26 is connected to the RWLL connection terminal, the first electrode of the transistor N26 is connected to the first electrode of the transistor N27, and the second electrode of the transistor N26 is connected to the RBL connection terminal. The control electrode of the transistor N27 is connected to the node U, and the second electrode of the transistor N27 is grounded. The control electrode of the transistor N28 is connected to the node UB, the first electrode of the transistor N28 is connected to the first electrode of the transistor N29, and the second electrode of the transistor N29 is grounded. The control electrode of the transistor N29 is connected to the RWLR connection terminal, and the second electrode of the transistor N29 is connected to the RBL connection terminal.

Please refer to FIG. 6, which is a schematic circuit diagram of a data storage circuit in an embodiment. In one embodiment, the data storage circuit includes a data write circuit 33, a second latch 31, a data read circuit 32, an RWL connection end, an RWLB connection end, a WWL connection end, a node Q, and a node QB. The WWL connection end is used to input the write control signal WWL, and the RWL connection end and the RWLB connection end are used to respectively input the read control signal RWL and the read control signal RWLB. The second latch 31 includes a transistor P31 , a transistor P32 , a transistor N31 and a transistor N32 , and the second latch 31 is used for storing data signals to be logically operated. Wherein, each transistor includes a first pole, a second pole and a control pole. The control electrode of the transistor P31 is connected to the node QB, the first electrode of the transistor P31 is used for inputting the working voltage signal V _DD , and the second electrode of the transistor P31 is connected to the node Q. The control electrode of the transistor P32 is connected to the node Q, the first electrode of the transistor P32 is used for inputting the working voltage signal V _DD , and the second electrode of the transistor P32 is connected to the node QB. The control electrode of the transistor N31 is connected to the node QB, the first electrode of the transistor N31 is connected to the node Q, and the second electrode of the transistor N31 is grounded. The control electrode of the transistor N32 is connected to the node Q, the first electrode of the transistor N32 is connected to the node QB, and the second electrode of the transistor N32 is grounded. The data writing circuit 32 includes a transistor N33 and a transistor N34. The control electrode of the transistor N33 is connected to the WWL terminal, the first electrode of the transistor N33 is connected to the WBLB terminal, and the second electrode of the transistor N33 is connected to the node QB. The control electrode of the transistor N34 is connected to the WWL connection terminal, the first electrode of the transistor N34 is connected to the WBL connection terminal, and the second electrode of the transistor N33 is connected to the node Q. The data reading circuit 33 includes a transistor N35, a transistor N36, a transistor N37, and a transistor N38. The control electrode of the transistor N35 is connected to the node QB, the first electrode of the transistor N35 is connected to the first electrode of the transistor N36, and the second electrode of the transistor N35 is grounded. The control electrode of the transistor N36 is connected to the RWL connection terminal, and the second electrode of the transistor N36 is connected to the RBL connection terminal. The control electrode of the transistor N37 is connected to the node Q, the first electrode of the transistor N37 is connected to the first electrode of the transistor N38, and the second electrode of the transistor N37 is grounded. The control electrode of the transistor N38 is connected to the RWLB connection terminal, and the second electrode of the transistor N38 is connected to the RBLB connection terminal.

As shown in Figure 4, the logical operation control 1 circuit also includes a first driver, a second driver and a NOR gate circuit. The two input terminals of the NOR gate circuit are respectively connected with the first data reading terminal and the second data reading terminal, and the output terminal of the NOR gate circuit is connected with the NORIN connection terminal. The output end of the first driver is connected to the first data reading end, and the output end of the second driver is connected to the second data reading end. The first driver is used for inputting logic operation control signals to the first data reading end. The second driver is used for inputting logic operation control signals to the second data reading end.

The application discloses a logic operation storage unit, which includes a logic operation control circuit, a result storage circuit, a WBL connection terminal, a WBLB connection terminal and N data storage circuits. The WBL connection end and the WBLB connection end are used to input the data signal to be logically operated, the data storage circuit is used to store the data signal to be logically operated, and the logical operation control circuit is used to perform logical operation on the data signal to be logically operated stored in the data storage circuit, and store the calculation result data signal obtained by the logical operation in the result storage circuit. Since the structure of the logic operation storage unit is to directly map the logic function to be implemented into the storage unit, the specific logic values of the N logic variables in the logic function are determined according to the input, so that all logic functions can be realized while retaining the original read-write and storage characteristics of the storage array.

Example 2:

Please refer to FIG. 7 , which is a schematic structural diagram of a logic operation memory in another embodiment. In one embodiment, a storage array is disclosed. The storage array 100 includes M logic operation storage units disclosed in Embodiment 1, where M is an integer greater than 0. In one embodiment, M≤2 ^N-2 .

In one embodiment, the present application discloses a logic operation memory, which includes the storage array 100 and the array logic calculation circuit 200 as described above. The array logic calculation circuit 200 is connected to the RBL connection end of each logic operation storage unit 110 in the storage array 100, the array logic calculation circuit 200 obtains the calculation result data signal stored in the result storage circuit through the RBL connection end of each logic operation storage unit 110, and performs logic operation on each obtained calculation result data signal to obtain the array logic operation result signal.

In one embodiment, the array logic calculation circuit 200 includes a TWL connection terminal, M array data acquisition circuits 210 and an array logic operation result output circuit 220 . The TWL connection end is used for inputting the logic operation control signal TWL. Each array data acquisition circuit 210 corresponds to one logical operation storage unit 110 . The array data acquisition circuit 210 includes a transistor N41 and a transistor N42. The control pole of the transistor N41 is connected to the RBL connection terminal of the logic operation storage unit 110 corresponding to the array data acquisition circuit 210, the first pole of the transistor N41 is connected to the array logic operation result output circuit 220, the second pole of the transistor N41 is connected to the first pole of the transistor N42, the control pole of the transistor N42 is connected to the TWL connection terminal, and the second pole of the transistor N42 is grounded.

In one embodiment, the array logic operation result output circuit 220 includes a signal amplifier SA, the input terminal of the signal amplifier SA is connected to the first pole of the transistor N41 of each array data acquisition circuit 210, and the output terminal of the signal amplifier SA is used to output the array logic operation result signal. In one embodiment, the signal amplifier SA includes a first output terminal and a second output terminal, the first output terminal of the signal amplifier SA is used to output the array logic operation result signal, and the second output terminal of the signal amplifier SA is used to output the inversion signal of the array logic operation result signal.

As shown in FIG. 4 , it is the logical operation storage unit disclosed in the embodiment of the present application. The working flow of the logical operation storage unit will be described below by taking N=2 as an example. A look-up table (LUT) consists of three SRAM cells sharing a bit line, a NOR gate, and write drivers for two bit lines. Among the three SRAM cells sharing a bit line, there are two data storage circuits (10T unit for short) as shown in FIG. 5 and one result storage circuit (11T unit for short) as shown in FIG. 6 . The write bit line WBL and the write bit line WBLB in FIG. 4 are a pair of write bit lines, which are used to write the data to be calculated into two 10T units, and the read bit line RBL and the read bit line RBLB in FIG. The write word line WWL in Figure 6 is the write word line of the 10T SRAM unit, that is, the control signal of the write port. RWL and RWLB are the read word lines of the 10T unit, that is, the control signals of the read port. A total of 4 word lines input to 2 10T cells in the LUT are independent of each other. The two variables of the logic function will be mapped one by one to the two 10T units contained in the 2-input LUT during calculation. The 2-input LUT can generate a total of 16 logic functions, covering all possible truth tables of 2-variable logic functions. The logic operations required by these functions can be roughly divided into the following three parts:

① When the read port on one side of the 10T cell is turned on, the precharged bit line will decide whether to discharge according to the data stored in the 10T cell. Assume that the two storage nodes of the first 10T unit as shown in Figure 4 are Q1 and QB1 respectively, the Q1 node stores the logical variable A, and the QB1 stores

The two storage nodes of the second 10T unit are Q2 and QB2 respectively, the Q2 node stores the logic variable B, and the QB2 node stores

Assuming A=1, B=0, when the read port RWLL of the 11T unit is turned on, the voltage of RBL will be maintained at V _DD , and RBLB will be discharged to GND. In this way, the logical value A stored by Q1 is read to the RBL, and the logical value stored by QB1

Read to RBLB. so that we can get

The result of two logical operations; similarly, by opening the read port of the read port RWLR of the 11T unit, it can be obtained

the result of. If the read ports on the same side of the two 10T units in the LUT unit are activated at the same time, the RBL/RBLB will discharge according to the data stored in the two cells. If both Q1 node and Q2 node have a storage "1", then RBL will be discharged to GND when RWLR is activated, which will

Mapped to RBLB, similarly, if QB1 node and QB2 node have a storage "1", RBL will be discharged to 0 when RWLL is activated, thus mapping AB to RBL. To sum up, by activating different numbers of read ports on the same side, six logic operations can be realized, namely A, B,

and AB.

②Based on the operation described in ①, we can use the NOR gate and 11T unit inside the LUT to obtain the inverse of the results of these logical operations. Because the results of the six operations described in ① will only be loaded to one bit line in RBL/RBLB, if the driver DR is turned on to write a logic value "0" to another free bit line while loading the operation results, then the NOR gate will output the inverse value of the operation result in ①. Activate CWL, the node U of the 11T unit will get the result of the operation in ①, and the node UB will get their inverse. Using this method, the 6 logic functions implemented in ① and A+B,

The results of these 2 new logic operations.

③Based on the operation described in ①, use the NOR gate and 11T unit contained in the LUT to complete the operation in the process of writing to the 11T unit, and the result is stored on the two storage nodes of the 11T unit. Assume that the Q1 node of a 10T unit in FIG. 4 stores "1", which is the logical value of the logical variable A, and the node Q2 of another 10T unit also stores "1", which is the logical value of the logical variable B. The read bit lines RBL/RBLB are precharged to V _DD first. When the read port of Q1 connected to RBLB and the read port of QB2 connected to RBL are turned on, RBLB will be discharged to 0, that is, the data on RBLB is

The RBL will remain at 1, that is, the data stored on the RBL is B. At this time, the output of the NOR gate is "0". When the write control signal CWL of the 11T unit is turned on, the output of the NOR gate will be directly written into the node U, and then the node UB will be reversed to the opposite logic value. Thus we can get 0 at node U, ie

, and get 1 at node UB, ie

the result of. Similarly, a similar operation on the read port of the Q2/QB1 connection can be obtained at node U

logical value of , while at node UB one gets

The logic value of the logic value of ; while performing similar operations on the read ports connected to Q1/QB1 and Q2/QB2, the logic values of logic operations "0" and "1" can be obtained at node U and node UB respectively. If you open the read ports on both sides of the two 10T units, you can get AB and RBLB respectively on RBL/RBLB

The value of , at this time activate CWL, node U will get

And node UB will get A⊙B. In this way, we can get

0, 1,

The operation result of A⊙B. So far, all 2-variable logic operations have been proven to be performed in this 2-input LUT.

As shown in FIG. 7 , the logical operation memory in the embodiment of the present application includes a storage array with a size of M columns (M≤2 ^N-2 ) and N rows, where each column is based on a 2-input LUT with N-2 10T units added. These additional 10T cells have a row-shared double word line RWLL/RWLR, where RWLL is shared by the left read port (connected to the RBL of each column) of all 10T cells in the same row, and RWLR is shared by the right read port (connected to the RBLB of each column) of all 10T SRAM cells. At the bottom of each column there is a transposed read port consisting of two transistors that can read logic values onto the bottom lateral bit line TBL. The transpose read port is controlled by a shared word line TWL. A single-ended sense amplifier is connected to the end of the transverse bit line TBL for rapidly reading out the calculation result. Such an array can implement all N-variable logic functions, that is, the array is an N-variable LUT.

When using an N-input LUT to implement an arbitrary N-variable logic function, it is necessary to map the variables in the logic function into the aforementioned SRAM array. The specific mapping rules are as follows: first write the logic function into the simplest "and or" formula, and then map each "and" item of the "and or" formula to the 10T unit of each column in the array. The 11T unit is only used as a result operation unit, and it is not allowed to map logic variables when implementing logic functions. On the same column, there is no difference between the two 10T units contained in the 2-input LUT and the other 10T units in the column in the variable mapping, that is, the position in the column where the variable contained in the "AND" item is mapped does not affect the final calculation result. If the number of logical variables contained in an "AND" item is less than the number of rows in the array, "1" should be mapped in the vacant cells of the column during mapping to ensure the correct result. When performing operations, the read bit lines RBL/RBLB of all columns are precharged first, and then the 2-input LUT part performs an "AND" operation according to the aforementioned operation flow. At the same time, the left read port word line RWLL of all other 10T cells is activated at the same time, and the RBL will discharge according to the data stored in all 10T cells, which is equivalent to completing the "AND" operation of all logic variables in the "AND" item, and the operation result is retained on the RBL.

After the "AND" operation of each column is completed, the RBL of each column in the array is loaded with the results of each "AND" item. Subsequently, the transposed bit line TBL starts precharging. After the TBL is precharged to a high level, the TWL is activated, and the TBL will be discharged according to the voltage on each column RBL (that is, the calculation result of each "AND" item). When one or more RBLs are high, the TBL will discharge. This is equivalent to "NOR" the data loaded on each RBL. The voltage change on the TBL will be quickly captured by the single-ended sense amplifier connected to its end, and the "NOR" result and "OR" result of the logic values on each column RBL will be obtained from the differential output port of the sense amplifier, where the "OR" result is the final calculation result of the input logic function.

The N-input LUT can be regarded as a complete SRAM array as a whole, and the array still has normal read and write functions that a general SRAM array has. When reading a certain cell in the array, the read bit line RBL/RBLB corresponding to the column where the cell is located is firstly precharged. If the unit to be read is a unit in a 2-input LUT, then the two independent word lines of the unit are activated at the same time, and the value stored in the unit is read to the bit line; if the unit to be read is another 10T unit, the two word lines RWLL/RWLR of the row where the unit is located are activated at the same time, and the value stored in the unit is read to the bit line. Subsequently, TBL is precharged, TWL is activated, and the sense amplifier connected to TBL outputs the value read.

When writing to a certain cell in the array, if the cell to be written is a 10T cell, first load the data to be written to the write bit line WBL/WBLB of the column where the cell is located. Then activate the word line WWL of the write port, and write the data to the storage node of the unit through the transmission tube; if the unit to be written is an 11T SRAM unit, it can be divided into two situations according to the written logic value: when it is necessary to write "0", charge the read bit line RBL/RBLB to high level, turn on the write word line CWL in the 11T unit, and then write "0" into the 11T unit. When it is necessary to write "1", the read bit lines RBL/RBLB are all loaded with "0", and the CWL is turned on, and "1" can be written into the 11T unit.

This application proposes a two-input look-up table that realizes all two-variable logic functions (sixteen types in total) based on an in-memory calculation method instead of a traditional memory access method. On the basis of the two-input look-up table, an N-input look-up table that can realize logic functions with any number of variables is developed. What the traditional N-input lookup table stores are all 2 ^N possible results corresponding to a certain certain N variable logic function, and the lookup table structure proposed by the application directly maps the logic function itself to be realized in the storage unit, and the specific logic values of the N logic variables in the logic function are determined according to the input. The look-up table proposed in this application retains the original read-write and storage characteristics of the storage array while realizing all logic functions.

This document is described with reference to various exemplary embodiments. However, those skilled in the art will recognize that changes and modifications can be made to the exemplary embodiments without departing from the scope herein. For example, the various operational steps, and the components used to perform the operational steps, may be implemented in different ways (e.g., one or more steps may be deleted, modified, or combined into other steps) depending on the particular application or considering any number of cost functions associated with the operation of the system.

While the principles herein have been shown in various embodiments, many modifications in structure, arrangement, proportions, elements, materials and components, particularly suited to particular circumstances and operational requirements, may be employed without departing from the principles and scope of this disclosure. The above modifications and other changes or amendments are intended to be included within the scope of this document.

The foregoing detailed description has been described with reference to various embodiments. However, those skilled in the art will recognize that various modifications and changes can be made without departing from the scope of the present disclosure. Accordingly, the disclosure is to be considered in an illustrative rather than a restrictive sense, and all such modifications are intended to be embraced within its scope. Also, advantages, other advantages and solutions to problems have been described above with respect to various embodiments. However, neither benefits, advantages, solutions to problems, nor any elements that lead to these, or make the solutions more definite, should be construed as critical, required, or necessary. The term "comprising" and any other variations thereof, as used herein, are non-exclusive inclusions, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements, but also other elements that are not expressly listed or not part of the process, method, system, article, or apparatus. Additionally, the term "coupled" and any other variations thereof, as used herein, refers to a physical connection, an electrical connection, a magnetic connection, an optical connection, a communicative connection, a functional connection, and/or any other connection.

Those skilled in the art will recognize that many changes may be made to the details of the above-described embodiments without departing from the underlying principles of the invention. Accordingly, the scope of the invention should be determined from the following claims.

Claims

A logic operation storage unit, characterized in that it includes a logic operation control circuit, a result storage circuit, a WBL connection end, a WBLB connection end, and N data storage circuits; wherein, N is an integer greater than 1;

The WBL connection end and the WBLB connection end are used to input data signals to be logically operated;

The data storage circuit is connected to the WBL connection end and the WBLB connection end, and is used to store the data signal to be logically operated;

The logical operation control circuit is connected to the result storage circuit and each of the data storage circuits, and is used to perform logical operation on the data signal to be logically operated stored in the data storage circuit, and store the calculation result data signal obtained by the logical operation in the result storage circuit;

Each of the data storage circuits includes a node Q, a node QB, an RBL connection end and an RBLB connection end; the node Q is connected to the WBL connection end, and the node QB is connected to the WBLB connection end, and the node Q and the node QB are used to obtain the data signal to be logically operated from the WBL connection end and the WBLB connection end, and write the data signal to be logically operated into the data storage circuit; the RBL connection end and the RBLB connection end are connected to the logic operation control circuit for reading the data signal to be logically operated from the data storage circuit , and sending the acquired logic operation data signal to the logic operation control circuit;

The logic operation control circuit includes a first data reading end, a second data reading end and a result output end; the first data reading end is connected to the RBL connection end of each of the data storage circuits, the second data reading end is connected to the RBLB connection end of each of the data storage circuits, and the first data reading end and the second data reading end are used to read the data signal to be logically operated from the data storage circuit; The data signal is sent to the result storage circuit through the result output terminal;

The result storage circuit includes a NORIN connection end and a first common line end, the first common line end is connected to the RBL connection end of each of the data storage circuits, the NORIN connection end is connected to the result output end, and the result storage circuit is used to store the calculation result data signal.
The logical operation storage unit according to claim 1, wherein the result storage circuit further comprises a result input circuit, a result reading circuit, a first latch, a CWL connection end, a RWLL connection end, an RWLR connection end, a node U and a node UB; the CWL connection end is used for inputting a write control signal CWL, and the RWLL connection end and the RWLR connection end are used for respectively inputting a read control signal RWLL and a read control signal RWLR;

The first latch includes a transistor P21, a transistor P22, a transistor N21, and a transistor N22, and the first latch is used to store the calculation result data signal; wherein each transistor includes a first pole, a second pole, and a control pole;

The control pole of the transistor P21 is connected to the node UB, the first pole of the transistor P21 is used for the input of the working voltage signal VDD , and the second pole of the transistor P21 is connected to the node U;

The control pole of the transistor P22 is connected to the node U, the first pole of the transistor P22 is used for the input of the working voltage signal VDD , and the second pole of the transistor P22 is connected to the node UB;

The control pole of the transistor N21 is connected to the node UB, the first pole of the transistor N21 is connected to the node U, and the second pole of the transistor N21 is grounded;

The control pole of the transistor N22 is connected to the node U, the first pole of the transistor N22 is connected to the node UB, and the second pole of the transistor N22 is grounded;

The result input circuit includes a transistor N23, a transistor N24 and a transistor N25, the control pole of the transistor N23 is connected to the NORIN connection terminal, the first pole of the transistor N23 is connected to the first pole of the transistor N24, and the second pole of the transistor N23 is connected to the node UB; the control pole of the transistor N24 is connected to the CWL connection terminal, and the second pole of the transistor N24 is grounded; the control pole of the transistor N25 is connected to the CWL connection terminal, and the first pole of the transistor N25 is connected to the NORIN connection terminal connected, the second pole of the transistor N25 is connected to the node U;

Described result reading circuit comprises transistor N26, transistor N27, transistor N28 and transistor N29;

The control pole of the transistor N26 is connected to the RWLL connection terminal, the first pole of the transistor N26 is connected to the first pole of the transistor N27, the second pole of the transistor N26 is connected to the RBL connection terminal; the control pole of the transistor N27 is connected to the node U, and the second pole of the transistor N27 is grounded; the control pole of the transistor N28 is connected to the node UB, the first pole of the transistor N28 is connected to the first pole of the transistor N29, and the second pole of the transistor N29 is grounded; connected to the connection terminal, and the second pole of the transistor N29 is connected to the RBL connection terminal.
The logical operation storage unit according to claim 1, wherein the data storage circuit comprises a data write circuit, a second latch, a data read circuit, a RWL connection end, a RWLB connection end, a WWL connection end, a node Q and a node QB; the WWL connection end is used for inputting a write control signal WWL, and the RWL connection end and the RWLB connection end are used for respectively inputting a read control signal RWL and a read control signal RWLB;

The second latch includes a transistor P31, a transistor P32, a transistor N31, and a transistor N32, and the second latch is used to store the data signal to be logically operated; wherein each transistor includes a first pole, a second pole, and a control pole;

The control pole of the transistor P31 is connected to the node QB, the first pole of the transistor P31 is used for the input of the working voltage signal VDD , and the second pole of the transistor P31 is connected to the node Q;

The control pole of the transistor P32 is connected to the node Q, the first pole of the transistor P32 is used for the input of the working voltage signal VDD , and the second pole of the transistor P32 is connected to the node QB;

The control pole of the transistor N31 is connected to the node QB, the first pole of the transistor N31 is connected to the node Q, and the second pole of the transistor N31 is grounded;

The control electrode of the transistor N32 is connected to the node Q, the first electrode of the transistor N32 is connected to the node QB, and the second electrode of the transistor N32 is grounded;

The data writing circuit includes a transistor N33 and a transistor N34, the control pole of the transistor N33 is connected to the WWL connection terminal, the first pole of the transistor N33 is connected to the WBLB connection terminal, the second pole of the transistor N33 is connected to the node QB; the control pole of the transistor N34 is connected to the WWL connection terminal, the first pole of the transistor N34 is connected to the WBL connection terminal, and the second pole of the transistor N33 is connected to the node Q;

The data reading circuit includes a transistor N35, a transistor N36, a transistor N37 and a transistor N38;

The control pole of the transistor N35 is connected to the node QB, the first pole of the transistor N35 is connected to the first pole of the transistor N36, and the second pole of the transistor N35 is grounded; the control pole of the transistor N36 is connected to the RWL connection end, and the second pole of the transistor N36 is connected to the RBL connection end; The connection terminal is connected, and the second pole of the transistor N38 is connected to the RBLB connection terminal.
The logical operation storage unit according to claim 1, wherein the logical operation control circuit further comprises a first driver, a second driver and a NOR gate circuit; two input terminals of the NOR gate circuit are respectively connected with the first data read terminal and the second data read terminal, and the output terminal of the NOR gate circuit is connected with the NORIN connection terminal; the output terminal of the first driver is connected with the first data read terminal, and the output terminal of the second driver is connected with the second data read terminal; the first driver is used to input a logical operation control signal to the first data read terminal ; The second driver is used to input a logic operation control signal to the second data reading end.
A storage array, characterized by comprising M logical operation storage units according to any one of claims 1 to 4; wherein, M is an integer greater than 0.
A logic operation memory, characterized in that it comprises a storage array and an array logic calculation circuit according to claim 5; the array logic calculation circuit is connected to the RBL connection end of each of the logic operation storage units in the storage array, and the array logic calculation circuit obtains the calculation result data signal stored in the result storage circuit through the RBL connection end of each of the logic operation storage units, and performs a logic operation on each of the acquired calculation result data signals to obtain an array logic operation result signal.
The logic operation memory according to claim 6, wherein the array logic calculation circuit comprises a TWL connection end, M array data acquisition circuits and an array logic operation result output circuit; the TWL connection end is used to input the logic operation control signal TWL;

Each array data acquisition circuit corresponds to one logic operation storage unit; the array data acquisition circuit includes a transistor N41 and a transistor N42; the control pole of the transistor N41 is connected to the RBL connection end of the logic operation storage unit corresponding to the array data acquisition circuit, the first pole of the transistor N41 is connected to the array logic operation result output circuit, the second pole of the transistor N41 is connected to the first pole of the transistor N42; the control pole of the transistor N42 is connected to the TWL connection terminal, and the second pole of the transistor N42 is grounded.
The logic operation memory according to claim 7, wherein the array logic operation result output circuit comprises a signal amplifier SA, the input terminal of the signal amplifier SA is connected to the first pole of each transistor N41 of the array data acquisition circuit, and the output terminal of the signal amplifier SA is used to output the array logic operation result signal.
The logic operation memory according to claim 8, wherein the signal amplifier SA includes a first output terminal and a second output terminal, the first output terminal of the signal amplifier SA is used to output the array logic operation result signal, and the second output terminal of the signal amplifier SA is used to output the inversion signal of the array logic operation result signal.
The logical operation memory according to claim 6, characterized in that M≤2 N-2 .