WO2022183314A1 - Memory - Google Patents

Abstract

A memory. The memory comprises: a cell array comprising multiple storage cells; and multiple circuit units respectively connected to at least one storage cell; wherein each circuit unit is used for: receiving a first bit value of externally inputted bit addressing data; reading a second bit value in a target storage cell pointed to by the bit addressing data; and updating the second bit value in the target storage cell to be the first bit value when the first bit value is different from the second bit value. When a processor needs to perform a Bloom filter operation, the memory only needs to receive addressing data from the processor, and the rest of addressing and writing update processes can be completed in the memory by the circuit units according to the addressing data, without the involvement of the processor. Therefore, excessive data migration does not occur on a bus between the memory and the processor, avoiding bus conflicts, shortening system response time, and improving the efficiency of a Bloom filter.

Description

a memory technical field

The present application relates to the field of computer technology, and in particular, to a memory.

Background technique

In computer systems, in order to quickly detect whether an element is in a target set, people invented the Bloom filter (Bloom Filter). The principle of Bloom filter is: when an element is added to the set, the element is mapped to K positions in a bit array Vector through K hash values, and the value of these K positions is set to 1 . When retrieving, it is only necessary to check whether the values of the K positions are all 1 to determine whether the target set contains this element probabilistically, that is, if the value of the K positions has any 0, the detected element must not be Exist in the target set; if the values of these K positions are all 1, the detected element is likely to exist in the target set.

At present, when a von Neumann-based computer performs the Bloom filter function, the processor needs to address the memory of the target Vector and the four target locations of the target Vector, and then the processor also needs to access the memory from each target. The position reads the data for judgment, and then writes the updated data to the target position. As a result, each addressing and writing update process of the Bloom filter needs to consume multiple instruction cycles, resulting in a long delay in addressing and writing updates, and the data needs to be passed multiple times and frequently. The bus is moved between the processor and memory, resulting in significant power consumption for addressing and write updates. In addition, because the bandwidth of the bus between the processor and the memory is usually limited, the addressing and writing update process of the Bloom filter requires a large amount of parallel computation, which will lead to bus conflicts, which in turn increases the system response time and reduces the distribution time. Efficiency of the Long Filter.

SUMMARY OF THE INVENTION

In order to solve the problems of time extension, high power consumption, bus conflict, etc. existing in the traditional von Neumann computer-based Bloom filter solution, and improve the efficiency of the Bloom filter, an embodiment of the present application provides a memory.

In a first aspect, an embodiment of the present application provides a memory, the memory includes: a cell array, the cell array includes a plurality of storage cells; a plurality of circuit units, the plurality of circuit units are respectively connected with at least one storage unit; wherein, the circuit unit Used for: receiving the first bit value of the bit-addressed data input from the outside; reading the second bit value in the target storage unit pointed to by the bit-addressing data; when the first bit value is different from the second bit value, the target The memory cell is updated to the first bit value.

According to the memory provided by the embodiment of the present application, when the processor needs to perform the Bloom filter operation, it only needs to input the bit addressing data to the circuit unit, and the rest of the addressing and writing update processes can be performed by the circuit unit according to the bit search process. The address data is completed in the memory and does not require the participation of the processor, so there will not be too much data migration on the bus between the memory and the processor, avoiding bus conflicts, shortening the system response time, and improving the bloom filter. efficiency.

In an implementation manner, a plurality of the memory cells are distributed into multiple rows and columns, the memory cells in each row are connected by a word line, the memory cells in each column are connected by a bit line, and the memory cells in each row are connected by a word line. For storing a bit array, each of the bit lines is connected with one of the circuit units; the first bit values received by different circuit units correspond to different bits of the bit addressing data.

In one implementation, the circuit unit includes a filter circuit and an update circuit; the filter circuit includes a bit-addressable input terminal, a data input terminal, and a filter output terminal; the bit-addressable input terminal is used to receive the first A bit value, the data input terminal is connected to the storage unit for reading the second bit value; the filter circuit is configured to, when the first bit value is different from the second bit value, A first enable signal is output at the filter output terminal; the update circuit includes a data output terminal, the data output terminal is connected to the storage unit; the update circuit is used for outputting the first enable signal at the filter circuit When the signal is enabled, the target storage unit is updated to the first bit value.

In an implementation manner, the filter circuit includes a first field effect transistor, a second field effect transistor and a third field effect transistor; the source of the first field effect transistor is grounded, and the gate of the first field effect transistor is For the bit addressing input terminal, the drain of the first field effect transistor is connected to the source of the second field effect transistor; the gate of the second field effect transistor is the data input terminal, and the first field effect transistor is the data input terminal. The drain of the second field effect transistor is connected to the source of the third field effect transistor; the gate of the third field effect transistor is the input end of the filter enable signal, and the drain of the third field effect transistor is the filter output. In this way, three field effect transistors are connected in series to form a three-stage filtering structure, wherein the first field effect transistor is used for receiving the first bit value of the bit addressing data, and the second field effect transistor is used for receiving the second bit value stored in the memory unit.

In an implementation manner, the filtering circuit is specifically configured to receive a second enable signal at the filter enable signal input terminal, and when the first bit value is different from the second bit value, The filter output terminal outputs the first enable signal. In this way, when the gate of the third field effect transistor receives the second enable signal, the filter circuit can activate the update unit when the first bit value is different from the second bit value, so as to realize the filtering function of the Bloom filter.

In an implementation manner, the first field effect transistor, the second field effect transistor and the third field effect transistor are all N-type field effect transistors.

In an implementation manner, the update circuit includes a tri-state buffer, an inverse tri-state buffer, a first data selector and a second data selector; the first input of the first data selector is a write an enable signal input terminal, the second input terminal of the first data selector is used for receiving the inversion signal of the first enable signal, the output terminal of the first data selector is connected to the tri-state buffer The enable terminal of the second data selector is connected to the enable terminal of the inverse tri-state buffer; the second input terminal of the second data selector is connected to the bit addressing input terminal or high potential, and the second data selector The output end of the buffer is connected to the input end of the tri-state buffer and the input end of the inverse tri-state buffer; the output end of the tri-state buffer and the output end of the inverse tri-state buffer are the data output. In this way, the update circuit can enable the tri-state buffer and the inverse tri-state buffer by filtering the low signal at the output terminal, so as to write update data to the storage unit, so as to realize the update function of the Bloom filter.

In an implementation manner, the first enable signal is a high-level signal, and the update circuit is specifically configured to, when the value of the first bit is 1 and the value of the second bit is 0, The target storage unit is updated to the first bit value. In this way, the update circuit can implement the update function of the Bloom filter and write 1 to the mapping value of the new element.

In an implementation manner, the update circuit includes an AND gate unit, a tri-state buffer, an inverse tri-state buffer, a first data selector and a second data selector; the first input terminal of the AND gate unit Connected with the filter output end, used for receiving the inversion signal of the first enable signal; the second input end of the AND gate unit is the write enable signal input end; the output end of the AND gate unit is the same as the The second input end of the first data selector is connected; the first input end of the first data selector is connected to the write enable signal input end, and the output end of the first data selector is connected to the The enable terminal of the tri-state buffer is connected to the enable terminal of the inverse tri-state buffer; the second input terminal of the second data selector is connected to the bit addressing input terminal or high potential, the The output end of the second data selector is connected to the input end of the tri-state buffer and the input end of the inverse tri-state buffer; the output end of the tri-state buffer and the inverse tri-state buffer The output terminal is the data output terminal. In this way, the update circuit can enable the tri-state buffer and the reverse tri-state buffer by filtering the low signal at the output end and the write enable signal, so as to write update data to the storage unit, and realize the update function of the Bloom filter.

In an implementation manner, the first enable signal is a high level signal, the update circuit is specifically configured to input a high level at the input end of the write enable signal, and the first bit value is 1 . When the second bit value is 0, the target storage unit is updated to the first bit value. In this way, the update circuit can implement the update function of the Bloom filter and write 1 to the mapping value of the new element.

In one implementation, the bit line includes a first bit line and a second bit line, the output end of the tri-state buffer is connected to the first bit line, and the output end of the inverse tri-state buffer is connected to the second bit line; When the first bit line is high and the second bit line is low, the bit value in the memory cell is 1; when the first bit line is low and the second bit line is high, the bit value in the memory cell is 1. The bit value is 0. In this way, after the update circuit is activated, the tri-state buffer can output a high level on the first bit line, and the reverse tri-state buffer can output a low level on the second bit line, so that the bit value of the storage unit can be updated to 1.

In an implementation manner, the data selection terminal of the first data selector and the data selection terminal of the second data selector are used to receive the working mode selection signal; when the working mode selection signal is at a low level, the first data selector The output terminal and the output terminal of the second data selector both output the signal of the respective first input terminal; when the working mode selection signal is at a high level, the output terminal of the first data selector and the output terminal of the second data selector both output the respective signals of the first input terminal. signal at the second input. In this way, the memory can be switched between the traditional read-write mode and the Bloom filter mode through different working mode selection signals.

In an implementation manner, the data input end is connected to the bit line through a sense amplifier; the sense amplifier includes two input ends, which are respectively connected to the first bit line and the second bit line; the sense amplifier further includes an output end, which is connected to the data input end When the first bit line is high level and the second bit line is low level, the sense amplifier outputs low level; when the first bit line is low level and the second bit line is high level, The sense amplifier outputs a high level. In this way, when the bit value in the storage unit is 0, the sense amplifier can input a high level to the data input terminal of the filter circuit, so that the filter circuit can activate the update circuit.

In an implementation manner, the filter circuit further includes a fourth field effect transistor, the source of the fourth field effect transistor is coupled to a high potential, the drain of the fourth field effect transistor is connected to the filter output end, and the gate of the fourth field effect transistor Extremely precharge signal input terminal; wherein, when the precharge signal input terminal is input with a low level, the fourth field effect transistor is turned on to pull the filter output terminal to a high level to realize the initialization and reset of the circuit unit.

In an implementation manner, the fourth field effect transistor is a P-type field effect transistor.

In an implementation manner, multiple circuit units share the same filter enable signal input terminal.

In an implementation manner, multiple circuit units share the same write enable signal input terminal.

In one implementation, multiple circuit units share the same filter output.

In this way, by sharing the filter enable signal input end, the write enable signal input end and the filter output end by multiple circuit units, the circuit structure can be simplified and the circuit area can be saved.

In an implementation manner, the latch further includes a control signal input terminal for receiving an external control signal, wherein when the external control signal is at a low level, the latch is used for receiving and latching the one-hot encoded data, and when the external control signal is at a low level When the control signal is at a high level, the latch is used to input the bit values of different bits of the one-hot encoded data to the addressing input terminals of each circuit unit in a one-to-one correspondence. In this way, the Bloom filter can receive the addressing data in the Hash Value format, convert it into one-hot encoded data in the form of one-hot encoding, and then input it to each circuit unit.

In one implementation, the bit-addressable data is a binary array. In this way, the processor can directly input the binary value of each bit of the bit-addressable data into each circuit unit, and there is no need to set a latch, so there is no need to add a latch in the system circuit composed of memory and processing. The related circuit simplifies the system circuit structure and reduces the circuit area.

In a second aspect, the present application also provides a computer storage medium. The computer storage medium computer instructions, when executed on a computer, cause the computer to perform the methods in the above-described aspects and implementations thereof.

In a third aspect, the present application also provides a computer program product comprising instructions, which, when run on a computer, cause the computer to perform the methods in the above aspects and implementations thereof.

Description of drawings

Figure 1 is the architecture diagram of the current von Neumann computer;

Fig. 2 is a schematic diagram of a Bloom filter addressing and updating process based on a von Neumann-type computer;

3 is a schematic diagram of an in-memory computing architecture provided by an embodiment of the present application;

4 is a schematic structural diagram of an SRAM shown in an embodiment of the present application;

5 is a schematic structural diagram of a Bloom filter functional circuit shown in an embodiment of the present application;

6 is a schematic diagram of a circuit connection between a circuit unit and a storage unit provided by an embodiment of the present application;

7 is a schematic structural diagram of a filter circuit provided by an embodiment of the present application;

8 is a schematic structural diagram of an update circuit provided by an embodiment of the present application;

9 is a specific circuit diagram of the connection between a circuit unit and a storage unit provided by an embodiment of the present application;

10 is a sequence diagram of a circuit control method provided by an embodiment of the present application;

11 is a schematic structural diagram of another update circuit provided by an embodiment of the present application;

12 is a specific circuit diagram of another circuit unit connected to a storage unit provided by an embodiment of the present application;

13 is a sequence diagram of another circuit control method provided by an embodiment of the present application;

FIG. 14 is a schematic structural diagram of another functional circuit of a bloom filter provided by an embodiment of the present application.

Detailed ways

In computer systems, in order to quickly detect whether an element is in a target set, people invented the Bloom filter (Bloom Filter). The principle of Bloom filter is: when an element is added to the set, the element is mapped to K positions in a bit array Vector through K hash values, and the value of these K positions is set to 1 . When retrieving, it is only necessary to check whether the values of the K positions are all 1 to determine whether the target set contains this element probabilistically, that is, if the value of the K positions has any 0, the detected element must not be Exist in the target set; if the values of these K positions are all 1, the detected element is likely to exist in the target set.

The Bloom filter function is widely used in many applications of computer systems (eg, network applications). The following is a brief description of the implementation scheme of the Bloom filter based on the widely used traditional von Neumann computer. FIG. 1 is an architecture diagram of a current von Neumann computer. As shown in FIG. 1 , the processor 10 and the memory 20 of the von Neumann computer are set separately, and communication between the processor 10 and the memory 20 can be performed through a bus 30 For data exchange, the processor 10 may further include a cache 11 , which may be used to temporarily store data read from the memory 20 or data to be written into the memory 20 .

Based on the von Neumann-type computer architecture shown in FIG. 1, in order to realize the function of the Bloom filter, a hash value can be used to pair the data stored in the memory 20, such as static random access memory (SRAM), by means of a hash value. Bit array Vector for addressing and mapping.

Figure 2 is a schematic diagram of a Bloom filter addressing and updating process based on a von Neumann-type computer implementation. As shown in FIG. 2 , the SRAM may include an M-level SRAM array array, where M is a positive integer, and each level of the array array may include a plurality of bit arrays Vector, and the length of each Vector is, for example, 16 bytes. The hash value Hash Value can include the high-order segment HSB and the low-order segment LSB. Taking the current common hash value Hash Value with a length of 64 bits as an example, the length of the high-order segment HSB can be, for example, 44 bits, and the length of the low-order segment can be, for example, is 20 bits. The high-order segment HSB part is used to address the specific bit array Vector in the SRAM array; the low-order segment LSB can be divided into four groups of arrays, which are respectively used to address four positions in the bit array Vector.

Further as shown in Figure 2, the addressing and write update functions of the Bloom filter can be implemented in the following four steps:

Step 1: The processor finds the target Vector by addressing the high-order segment HSB of the Hash Value in the SRAM array.

Step 2: The processor divides the target Vector into 4 groups, each group is marked as Vector', and the length of each Vector' is 4 bytes, that is, 32 bits.

Step 3: The processor divides the LSB of the Hash Value into 4 groups, each group of LSB data corresponds to a Vector', and the length of each group of LSB data is 5 bits, which can form 2 ⁵ =32 values, so each group The LSB data can just be bit-wise addressed to its corresponding 32-bit Vector'. In this way, the processor can mark the four target positions of the target Vector through the LSB of the Hash Value.

Step 4: The processor reads the data of the four target positions in the target Vector respectively, and judges whether the values of the four target positions are all 1; if the values of the four target positions are all 1, it means that the detected element has It may be included in the target set; if at least one of the values of the four target positions is 0, it means that the detected element must not exist in the target set and belongs to a new data stream. At this time, the target position with a value of 0 is updated. is 1.

Through the above steps, the addressing and writing update of the Bloom filter are completed.

Combining with Fig. 1 and Fig. 2, it can be seen that the Bloom filter scheme based on von Neumann computer needs to address the memory of the target Vector and the four elements of the target Vector when performing addressing and writing update each time. The addressing of the target location, and then the processor also needs to read data from each target location for judgment, and then write updated data to the target location. As a result, each addressing and writing update process of the Bloom filter needs to consume multiple instruction cycles, resulting in a long delay in addressing and writing updates, and the data needs to be passed multiple times and frequently. The bus is moved between the processor and memory, resulting in significant power consumption for addressing and write updates. In addition, because the bandwidth of the bus between the processor and the memory is usually limited, the addressing and writing update process of the Bloom filter requires a large amount of parallel computation, which will lead to bus conflicts, which in turn increases the system response time and reduces the distribution time. Efficiency of the Long Filter.

In order to solve the problems of time extension, high power consumption, bus conflict, etc. existing in the traditional von Neumann computer-based bloom filter solution, and improve the efficiency of the bloom filter, the embodiment of the present application provides a bloom filter device function circuit.

Different from the traditional von Neumann computer-based Bloom filter solution, the Bloom filter function circuit provided by the embodiment of the present application can be applied to a non-von Neumann computer architecture, and specifically can be applied to a computer with internal memory. In computers of direct computing (in-memory computing) architecture. FIG. 3 is a schematic diagram of an in-memory computing architecture provided by an embodiment of the present application. As shown in FIG. 3, the in-memory computing architecture includes a processor 100 and a memory 200. Communication and data exchange can be performed between the processor 100 and the memory 200 through a bus 300. The processor 100 can also include a cache 110, which can be used for temporary To store data read from the memory 200 or data to be written into the memory 200, the memory 200 not only stores data (for example, the SRAM array 210), but also includes an in-memory computing circuit 220, and the in-memory computing circuit 220 can be used to store data in the memory 200. The processing of the data is completed in the memory 200 .

In an implementation manner, the in-memory computing circuit 220 may include, for example, the bloom filter function circuit provided by the embodiment of the present application, so that the bloom filter function circuit of the embodiment of the present application implements the bloom filter function in the memory , such as addressing and write updates.

In order to facilitate those skilled in the art to understand the technical solutions of the embodiments of the present application, before the structure of the bloom filter circuit provided by the embodiments of the present application is described in detail, first take SRAM as an example to describe an achievable structure of the memory. Simple instructions.

FIG. 4 is a schematic structural diagram of an SRAM shown in an embodiment of the present application. As shown in FIG. 4 , the SRAM includes an SRAM cell array (SRAM array), and the SRAM cell array may include a plurality of memory cells, and the plurality of memory cells are distributed into multiple rows and columns. Each row of memory cells in the SRAM array can be used to store a Vector, and each row of memory cells is connected by a word line (WL). Each column of memory cells in the SRAM array corresponds to the same bit of a different Vector and is connected by a bit line (bit line, BL). Wherein, the processor or other devices can word address the SRAM cell array through the word line WL to find the target Vector, and can read and write each memory cell used to store the target Vector through each bit line BL.

Further as shown in FIG. 4 , in an example, the bit width of the SRAM array may be 16 bytes, that is, 128 bits, so each word line WL may include 128 memory cells, and each memory cell stores 1 of the Vector. bits, so that the memory cells on each word line WL of the SRAM array can store a Vector with a length of 16 bytes.

Correspondingly, the SRAM array may include 128 bit lines BL in total. For ease of description, FIG. 4 divides the 128 bit lines BL into four groups according to the correspondence between the 128 bit lines BL and the 128 bits of the Vector, and each group of 32 bit lines BL corresponds to the 0th bit of the Vector. ~31 bits, 32nd to 63rd bits, 64th to 95th bits, and 96th to 127th bits, so each group of bit lines BL corresponds to a Vector' with a length of 4 bytes. Among them, when an element is mapped to the four target positions in the Vector, the bits on each group of BLs include one target position.

It needs to be supplemented here that the above-mentioned features of the SRAM array shown in the embodiments of the present application are 16 bytes in bit width, 16 bytes in length of Vector, and 128 bit lines BL are included in the SRAM array. Example, does not constitute a specific limitation to SRAM array and Vector, those skilled in the art can reasonably set the above-mentioned features according to the specific software and hardware environment and use requirements when implementing the solutions of the embodiments of the present application. The protection scope of the application examples.

FIG. 5 is a schematic structural diagram of a circuit including a Bloom filter function according to an embodiment of the present application. As shown in FIG. 5 , the bloom filter function circuit 50 can be arranged in a memory, and the memory with the bloom filter circuit 50 can be regarded as a new type of memory. The bloom filter function circuit 50 may specifically include: a cell array 230 and a plurality of circuit units 400 having the same number as the plurality of bit lines BL of the cell array 230 . In this embodiment of the present application, the cell array 230 may be, for example, the above-mentioned SRAM array as shown in FIG. 4 , or an array structure including storage cells formed in other memories, including but not limited to dynamic random access memories (dynamic random access memories). random access memory, DRAM), electrically erasable programmable read-only memory (electrically-erasable programmable read-only memory, EEPROM), flash memory (flash memory), etc., which are not limited in this application.

Further as shown in FIG. 5 , a plurality of circuit units 400 are connected to a plurality of bit lines BL of the cell array 230 in one-to-one correspondence; each circuit unit 400 further includes a bit addressing input terminal 410, and the bit addressing input terminal 410 is used for Receives addressed data from outside the Bloom filter function circuit. In addition, each circuit unit 400 further includes a filter enable signal input terminal Filter_En, a filter output terminal Filter_Done and a write enable signal input terminal WR_EN, wherein the filter enable signal input terminal Filter_En, the filter output terminal Filter_Done and the write enable signal input terminal The specific function of WR_EN will be explained in detail in the following content.

In an implementation manner, all circuit units 400 may share a filter enable signal input terminal Filter_En, that is, the Bloom filter function circuit includes a filter enable signal input terminal Filter_En bus, and all circuit units 400 may share a filter enable signal input terminal Filter_En. The output terminal Filter_Done, that is, the Bloom filter function circuit includes a filter output terminal Filter_Done bus, and all circuit units 400 can share a write enable signal input terminal WR_EN, that is, the Bloom filter function circuit includes a write enable signal input terminal. WR_EN bus.

Based on the functional circuit structure of the bloom filter shown in FIG. 5, when the processor or other external device needs to perform the addressing and writing update functions of the bloom filter, the target Vector mapped in the cell array can be mapped according to the detected element. The corresponding addressing data is generated at the position of , and the addressing data may include, for example, word-addressed data and word-bit-addressed data. Among them, the word addressing data is used to address the word line WL to find the word line WL where the target Vector is located; the bit addressing data is used to address the bit line BL to find the detected element to map in the target Vector The target bit is addressed, and operations such as writing and updating are performed on the target bit.

In one implementation, the addressed data will be input to each word line WL or each circuit cell in the form of 0 or 1 bit values. Among them, the bit value input to the word line WL where the target Vector is located is 1 to activate the word line WL where the target Vector is located, and the bit value input to the word line WL where the remaining Vectors are located is 0, so that the word lines WL where the remaining Vectors are located will not be activated. ; The bit value input to the circuit unit on the bit line BL where the target bit is located is 1, and the bit value input to other circuit units is 0 to select the target bit, so that the circuit unit performs subsequent addressing and writing to the target bit. update, etc.

In an implementation manner, the addressing data may initially be, for example, a Hash Value, and the low-order segment LSB of the LSB may generate a 0 or 1-bit value for input to each word line WL or each circuit unit by encoding.

For example, a 0 or 1-bit value can be obtained by one-hot encoding the low-order segment LSB of the Hash Value.

In an example, assuming that the length of the target Vector is 128 bits, and the detected element is mapped with 4 target bits in the target Vector, the target Vector may include 4 groups, each group includes 32 bits, and each group has 32 bits. A target bit is included in the bits. Then, in order to address the 4 target bits, the LSB of the low-order segment of the Hash Value can obtain 4 groups of One-hot arrays after One-hot encoding, and the 4 groups of One-hot arrays correspond to the 4 groups of the target Vector one-to-one. , each One-hot array has the same length as the target Vector group, both of which are 32 bits. The One-hot value of only one bit in each One-hot array is 1, which corresponds to one target bit of the target Vector, and the remaining bits The One-hot value of 0 is 0.

In the embodiment of the present application, the operation of obtaining a One-hot array by performing One-hot encoding on the LSB of the low-order segment of the Hash Value may be implemented by a processor or other external device set outside the memory, or may be implemented by a processor set outside the memory. It is realized by a computing device in the memory, for example: a main control chip of a memory, a microcontroller unit (MCU), etc., which is not limited in this embodiment of the present application.

Next, a method for obtaining a One-hot array by one-hot encoding of the LSB of the low-order segment of the Hash Value is exemplarily described.

As shown in Figure 5, corresponding to the four 32-bit groups of Vector, the low-order segment LSB of Hash Value can also include 4 groups of data, and each group of data is binary coded with a length of 5 bits, so the total LSB The length can be 20 bits. Each group of LSB data can form 32 values through binary encoding, so each value can be encoded into a One-hot array with a length of 32 bits. An exemplary One-hot encoding method is shown in Table 1.

binary	One-hot encoding
00000	00000000000000000000000000000001
00001	00000000000000000000000000000010
00010	00000000000000000000000000000100
00011	00000000000000000000000000001000
00100	00000000000000000000000000010000
00101	00000000000000000000000000100000
00110	00000000000000000000000001000000
00111	00000000000000000000000010000000
…	…

Table 1

It should be supplemented here that in the Hash Value shown in FIG. 5 , the length of the high-order segment HSB is 64 bits, while in the Hash Value shown in FIG. 2 , the length of the high-order segment HSB is 44 bits. Therefore, it can be seen that in different designs, the length of the high-order segment HSB can be changed. Specifically, it can be determined according to the number of word lines WL of the SRAM array that needs word addressing. For example, the length of the high-order segment HSB can be formed. The number of binary codes is greater than or equal to the number of word lines WL of the SRAM array that needs word addressing, which is not specifically limited in this embodiment of the present application.

In an implementation manner, as shown in FIG. 5 , the bloom filter function circuit may also be provided with a latch 500 . The input terminal of the latch 500 is used for receiving the One-hot value of each bit of the One-hot array, and latching the One-hot value of each bit of the One-hot array. The latch 500 may have the same number of output terminals as the multiple circuit units 400 of the Bloom filter functional circuit provided in the embodiment of the present application, and the multiple output terminals of the latch are related to the bit search of the multiple circuit units 400 . The address input terminals 410 are connected in one-to-one correspondence, so the latch 500 can input the one-hot value of each bit of the one-hot array latched into each circuit unit 400 in a one-to-one correspondence. The latch 500 may further include a control signal input terminal, such as the one_hot_latch_EN terminal in FIG. 5 , the control signal input terminal is used to receive an external control signal, so as to latch the one-bit of each bit of the One-hot array according to the external control signal. The -hot values are input into the respective circuit units 400 in a one-to-one correspondence.

Based on the above structure, each circuit unit in the Bloom filter functional circuit can perform a bitwise logical operation on the bits of the target Vector on the bit line BL where it is located according to the received One-hot value. If the One-hot value received by a certain circuit unit is 1, it means that a target bit mapped by the detected element is located on the bit line BL where the circuit unit is located. Further, if the One-hot value received by a certain circuit unit is 1, and the value of the target bit on the bit line BL where the circuit unit is located is also 1, it means that the detected element may exist in the target set; if The One-hot value received by the circuit unit is 1, and the value of the target bit on the bit line BL where the circuit unit is located is 0, which means that the detected element must not exist in the target set, indicating that the detected element is a new one. , then the circuit unit can write 1 to the target bit to update the value of the target bit to 1. The above bitwise logical operations can be performed simultaneously in each circuit unit, so that the Bloom filter function circuit simultaneously detects the four target bits of the detected element in the target Vector.

In an implementation manner, each circuit unit may include two functional circuit modules, such as a filter circuit and an update circuit, in order to implement the above-mentioned bitwise logic operation. Among them, the filter circuit is used to receive the One-hot value from the latch, and when receiving the One-hot value of 1, judge whether the value of the corresponding target bit is also 1, and if the value of the target bit is judged to be no If it is 1, the value of the target bit is updated to 1 by the update circuit.

FIG. 6 is a schematic diagram of a circuit connection between a circuit unit and a storage unit provided by an embodiment of the present application. As shown in FIG. 6 , the filter circuit 420 and the update circuit 430 of the circuit unit 400 are respectively connected to the memory unit 211 through bit lines (eg, BL and BL#). The read selector YSR and the sense amplifier SA are arranged on the bit line between the filter circuit 420 and the storage unit 211 , and the write selector YSW is arranged on the bit line between the update circuit 430 and the storage unit 211 . When the filter circuit 420 needs to read data from the storage unit 211, the read selector YSR is closed and the write selector YSW is opened, so that the filter circuit 420 reads the bit value from the storage unit 211. When data is updated, the read selector YSR is opened and the write selector YSW is closed, so that the update circuit 430 writes a new bit value into the storage unit 211 .

In an implementation manner, the storage unit 211, the filter circuit 4204 and the update circuit 430 can be connected by two bit lines. For the convenience of description, the two bit lines are marked as bit line BL and bit line BL# here. The bit value in the storage unit 211 can be determined according to the levels of the bit line BL and the bit line BL#. For example, when the bit line BL is at a high level and the bit line BL# is at a low level, the corresponding bit value in the storage unit 211 If it is 1, when the bit line BL is at a low level and the bit line BL# is at a high level, the bit value corresponding to the memory cell 211 is 0.

Further as shown in FIG. 6 , the filter circuit 420 includes a data input terminal Q#, the bit line BL and the bit line BL# are respectively connected with two input terminals of the sense amplifier SA, and the output of the sense amplifier SA is connected with the filter circuit 420. The data input terminal Q# is connected so that the filter circuit 420 can read data from the storage unit 211 . The update circuit 430 includes two output terminals Y2 and Y3, which are respectively connected to the bit line BL and the bit line BL#, so that the update circuit 430 can output different voltages through the two output terminals Y2 and Y3. The storage unit 211 is updated by writing.

As further shown in FIG. 6 , the filter circuit 420 further includes a bit-addressable input terminal Translated Hash Value, which is used for receiving the bit value of the bit-addressable data input from the outside.

FIG. 7 is a schematic structural diagram of a filter circuit provided by an embodiment of the present application. As shown in FIG. 7 , each filter circuit may include three N-channel field-effect transistors (NFETs). For ease of description, the three N-type field-effect transistors are referred to as the first N-type FETs, respectively. Field effect transistor NFET1, second N-type field effect transistor NFET2 and third N-type field effect transistor NFET3. Among them, the source S of the first N-type field effect transistor NFET1 is grounded to GND; the gate G of the first N-type field effect transistor NFET1 is used as the bit addressing input terminal of the circuit unit. Translated Hash Value can be connected to the output terminal of the latch The drain D of the first N-type field effect transistor NFET1 is connected with the source S of the second N-type field effect transistor NFET2; the gate G of the second N-type field effect transistor NFET2 is used as the data input terminal Q# of the filter circuit, It is connected to the output end of the sense amplifier SA; the drain D of the second N-type field effect transistor NFET2 is connected to the source S of the third N-type field effect transistor NFET3, and the gate G of the third N-type field effect transistor NFET3 is used as a filter. The filter enable signal input terminal Filter_En of the circuit, and the drain D of the third N-type field effect transistor NFET3 is used as the filter output terminal Filter_Done of the filter circuit.

In the embodiment of the present application, the filter circuits of all circuit units can share a filter output terminal Filter_Done bus, and the filter output terminal Filter_Done bus is also connected with a P-type field effect transistor PFET shared by the filter circuits of all circuit units, The P-type field effect transistor PFET can be regarded as a part of the filter circuit. Among them, the source S of the P-type field effect transistor PFET is coupled to the high potential VDD, the drain D of the P-type field effect transistor PFET is connected to the filter output terminal Filter_Done bus, and the gate G of the P-type field effect transistor PFET is used as the gate of each circuit unit. Pre-charge signal input terminal Pre_Ch.

FIG. 8 is a schematic structural diagram of an update circuit provided by an embodiment of the present application. As shown in FIG. 8, each update circuit may include at least one AND gate AND unit AND1, one tri-state buffer TSB1, one inverse tri-state buffer TSB2, and two data selectors DS1 and DS2.

Among them, the AND gate unit AND1 includes two input terminals A1 and B1, and an output terminal Y1; the input terminal A1 of the AND gate unit AND1 is connected to the filter output terminal Filter_Done, and is used to receive the inversion signal of the filter output terminal Filter_Done; AND gate The input terminal B1 of the unit AND1 is used as the write enable signal input terminal WR_EN of the update circuit to receive the write enable signal; the output terminal Y1 of the AND gate unit AND1 is connected to the second input terminal B2 of the data selector DS1.

The first input terminal A2 of the data selector DS1 is connected to the write enable signal input terminal WR_EN for receiving the write enable signal; the data selection terminal S1 of the data selector DS1 is connected to the operating mode selection port CIN_MODE of the circuit unit for use in Receive a working mode selection signal, wherein the working mode of the circuit unit may include a traditional mode and an in-memory operation mode; the output terminal Z1 of the data selector DS1 is respectively connected with the enabling terminal E1 of the tri-state buffer TSB1 and the reverse tri-state buffer TSB2 The enable terminal E2 is connected.

The first input end A3 of the data selector DS2 is connected to the data input end D_in of the circuit unit, and is used to receive the data to be written in the storage unit in the conventional mode; the second input end B3 of the data selector DS2 is connected to a high potential or The bit addressing input terminal Translated Hash Value of the circuit unit is connected; the data selection terminal S2 of the data selector DS2 is connected with the working mode selection port CIN_MODE of the circuit unit for receiving the working mode selection signal; the output terminal Z2 of the data selector DS2 is respectively It is connected to the input terminal A4 of the tri-state buffer TSB1 and the input terminal A5 of the reverse tri-state buffer TSB2. Among them, when the input signal of the working mode selection port CIN_MODE is low level, the circuit unit works in the traditional mode, and performs the conventional SRAM write function, that is, receives data from the data input terminal D_in, and passes through the data selector DS2 and tri-state The registers TSB1 and TSB2 are written into the storage unit. When the input signal of the working mode selection port CIN_MODE is at a high level, the circuit unit works in the memory calculation mode and performs the function of the Bloom filter.

The output terminal Y2 of the tri-state buffer TSB1 is connected to the bit line BL; when the enable terminal E1 of the tri-state buffer TSB1 inputs a low signal 0, the tri-state buffer TSB1 is in a high-impedance state and cannot perform data transmission. When the high signal 1 is input to the enable terminal E1 of the buffer TSB1, its output value is equal to the input value.

The output terminal Y3 of the reverse three-state buffer TSB2 is connected to the bit line BL#; when the enable terminal E2 of the reverse three-state buffer TSB2 inputs a low signal 0, the reverse three-state buffer TSB2 is in a high-impedance state and cannot be For data transmission, when the enable terminal E2 of the reverse tri-state buffer TSB2 inputs a high signal 1, its output value is equal to the inversion of the input value.

Based on the filter circuit structure shown in FIG. 7 and the update circuit structure shown in FIG. 8 , FIG. 9 is a specific circuit diagram of the connection between the circuit unit 400 and the storage unit 211 provided by the embodiment of the present application. It can also be seen in conjunction with FIG. 9 that each memory unit 211 may include two inverted tri-state buffers arranged in opposite directions, and two field effect transistor FETs arranged at both ends of the two inverted tri-state buffers. The gates G of the FETs are connected to the word line WL, the drain D/source S of one FET is connected to the bit line BL, and the source S/drain D of the other FET is connected to bit line BL#. It should be added that the circuit structure of the storage unit 211 belongs to the prior art in the art, so the structure of the storage unit 211 shown in the figure is only an example, and does not constitute a specific limitation to the technical solutions of the embodiments of the present application.

For the circuit unit shown in FIG. 9 , an embodiment of the present application further provides a circuit control method. The circuit control method can be used for the circuit unit shown in FIG. 9 , so that the circuit unit can realize the function of bloom filter.

FIG. 10 is a sequence diagram of a circuit control method provided by an embodiment of the present application. In Figure 10, one_hot_latch_EN represents the signal of the control signal input terminal of the latch, CLK represents the clock signal, Pre_Ch represents the signal of the pre-charge signal input terminal Pre_Ch, Filter_Done represents the signal of the filter output terminal Filter_Done of the circuit unit, Filter_En represents the signal of the circuit unit's filter output terminal The signal of the filter enable signal input terminal Filter_En, WR_EN represents the signal of the write enable signal input terminal WR_EN of the circuit unit.

Among them, when Pre_Ch is low, it means that a valid precharge command is received, and the P-type field effect transistor PFET is turned on; when Pre_Ch is high, it means that no valid precharge command has been received, and the P-type The FET PFET is turned off. When Filter_En is high, it means that a valid filtering addressing command is received, and the third N-type field effect transistor NFET3 is turned on; when Filter_En is low, it means that no valid filtering addressing command has been received, at this time The third N-type field effect transistor NFET3 is turned off.

In the embodiments of the present application, each circuit unit of the Bloom filter functional circuit can complete the addressing and writing update functions of the Bloom filter within one clock cycle by executing the circuit control method provided by the embodiments of the present application. One clock cycle of the control method of the embodiment of the present application is exemplarily described below with reference to the timing diagram shown in FIG. 10 . Wherein, when the circuit unit performs the function of Bloom filter, the input signal of the working mode selection port CIN_MODE is a high level signal.

Before the rising edge of the CLK signal comes, the pre-charge signal input terminal Pre_Ch is high level, the P-type field effect transistor PFET is in the off state, so that the filter output terminal Filter_Done is low level, in addition, the filter enable signal input terminal Filter_En It is high level, and the write enable signal input terminal WR_EN is high level. During this period, one_hot_latch_EN is first low level, and the One-hot array obtained by Hash Value after One-hot encoding is sent to the latch; then, one_hot_latch_EN is flipped from low level to high level, then latch The controller inputs each bit of the One-hot array it latches into the bit-addressable input terminal Translated Hash Value of each circuit unit.

When the rising edge of the CLK signal arrives, Pre_Ch is flipped from high level to low level, and the level of Filter_Done bus is pulled up to high level, thus completing the precharging of Filter_Done bus. At the same time, Filter_En is changed from high level to high level. Flip to low level, WR_EN flips from high level to low level, the initialization phase ends, and the circuit unit enters the working phase. At this time, the output terminal Y1 of the AND gate unit AND1 outputs a low level according to the Filter_Done signal and the WR_EN signal, and the data selector DS1 outputs a low level to the enable terminals E1 and E2 of the tri-state buffer TSB1 and the reverse tri-state buffer TSB2 level, so that the tri-state buffer TSB1 and the reverse tri-state buffer TSB2 are in a high-impedance state, and no data transmission is performed.

When the falling edge of the CLK signal arrives, Pre_Ch flips from low level to high level, Filter_En flips from low level to high level, and WR_EN flips from low level to high level. At this time, the filter circuit starts to perform bitwise logic operations. The bitwise logic operation specifically includes: when the bit value in the storage unit is 1, the bit line BL outputs a high level, the bit line BL# outputs a low level, and the sense amplifier SA outputs a low level; When the value is 0, the bit line BL outputs a low level, the bit line BL# outputs a high level, and the sense amplifier SA outputs a high level. If the data input terminal Q# of the filter circuit receives a high level signal from the sense amplifier SA, and the bit addressing input terminal Translated Hash Value of the filter circuit (the gate G of the first N-type field effect transistor NFET1) receives a high level signal level signal, then the three NFETs (ie the first N-type field effect transistor NFET1, the second N-type field effect transistor NFET2 and the third N-type field effect transistor NFET3) will be turned on, thereby pulling Filter_Done down to a low level level; otherwise, the three NFETs will not be turned on and Filter_Done will remain high.

Based on the above configuration, when Filter_Done is pulled down to a low level, it means that the bit value in the storage unit is 0, and the One-hot value input by the bit-addressable input terminal Translated Hash Value of the filter circuit is 1, indicating that this storage unit corresponds to A target bit mapped by the detected element, and the detected element is not in the target Vector, it belongs to a new element, so the bit value in the storage unit needs to be updated, at this time, the update circuit will be activated.

After the update circuit is activated, the write update operation starts. The write update operation may specifically include: on the one hand, the output terminal Y1 of the AND gate unit AND1 outputs a high level according to the Filter_Done signal and the WR_EN signal, so that the data selector DS1 sends the tri-state buffer TSB1 and the reverse tri-state buffer TSB2 The enable terminals E1 and E2 output high level, set the tri-state buffer TSB1 and the reverse tri-state buffer TSB2 to the data output state; on the other hand, the data selector DS2 sends the tri-state buffer TSB1 and the reverse three-state buffer The input terminals A4 and A5 of the state buffer TSB2 input high level or the signal of the Translated Hash Value of the bit addressing input terminal (corresponding to the One-hot value of 1, which is also high level), so that the output terminal of the three-state buffer TSB1 Y2 outputs a high level to the bit line BL, and the output terminal Y3 of the tri-state buffer TSB2 outputs a low level (ie, the inverted signal of the high level) to the bit line BL#, thereby updating the bit value of the memory cell to 1.

So far, the circuit unit has completed the addressing and writing update process of the Bloom filter.

In addition, when the falling edge of the CLK signal arrives, one_hot_latch_EN can be flipped from a high level to a low level. At this time, the latch releases the one-hot data it has already described and waits for new one-hot data to be input.

It can be seen from the above technical solutions that the bloom filter circuit provided in the embodiment of the present application can be provided in the memory, and when the processor needs to perform the bloom filter operation, the bloom filter circuit only needs to receive addressing data from the processor, The rest of the addressing and writing update processes can be completed in the memory by the Bloom filter circuit according to the addressing data, without the involvement of the processor, so there will not be too much data migration on the bus between the memory and the processor. , to avoid bus conflicts. In addition, the bloom filter circuit provided by the embodiment of the present application can also realize the addressing and writing update process of the bloom filter in one instruction cycle cycle, which shortens the system response time and improves the Bloom filter efficiency.

FIG. 11 is a schematic structural diagram of another update circuit provided by an embodiment of the present application. As shown in FIG. 11, each update circuit may include at least one tri-state buffer TSB1, an inverse tri-state buffer TSB2, and two data selectors DS1 and DS2. The difference between the update circuit shown in FIG. 11 and the update circuit shown in FIG. 8 is that the AND gate AND unit AND1 is not included. Wherein, the second input end B2 of the data selector DS1 is connected to the filter output end Filter_Done for directly receiving the inversion signal of the filter output end Filter_Done; the first input end A2 of the data selector DS1 is used as the write enable signal of the update circuit The input terminal WR_EN is used to receive the write enable signal. The rest of the implementation manners of the update circuit shown in FIG. 11 are the same as those of the update circuit shown in FIG. 8 , which will not be repeated here.

Based on the filter circuit structure shown in FIG. 7 and the update circuit structure shown in FIG. 11 , FIG. 12 is a specific circuit diagram of the connection between the circuit unit 400 and the storage unit 211 provided by the embodiment of the present application. The connection mode shown in FIG. 12 is similar to the connection mode shown in FIG. 9 , each storage unit 211 may include two reverse tri-state buffers, and two reverse tri-state buffers arranged at both ends of the two reverse tri-state buffers Two FETs, the gate G of the two FETs is connected to the word line WL, the drain D/source S of one FET is connected to the bit line BL, and the other FET's The source S/drain D is connected to the bit line BL#. It should be added that the circuit structure of the storage unit 211 belongs to the prior art in the art, so the structure of the storage unit 211 shown in the figure is only an example, and does not constitute a specific limitation to the technical solutions of the embodiments of the present application.

For the circuit unit shown in FIG. 12 , an embodiment of the present application further provides a circuit control method. This circuit control method can be used for the circuit unit shown in FIG. 12 , so that the circuit unit can realize the function of bloom filter.

FIG. 13 is a sequence diagram of a circuit control method provided by an embodiment of the present application. In FIG. 13, one_hot_latch_EN represents the signal of the control signal input terminal of the latch, CLK represents the clock signal, Pre_Ch represents the signal of the precharge signal input terminal Pre_Ch, Filter_Done represents the signal of the filter output terminal Filter_Done of the circuit unit, Filter_En represents the signal of the circuit unit Filter enable signal input Filter_En signal.

In the embodiments of the present application, each circuit unit of the Bloom filter functional circuit can complete the addressing and writing update functions of the Bloom filter within one clock cycle by executing the circuit control method provided by the embodiments of the present application. One clock cycle of the control method of the embodiment of the present application is exemplarily described below with reference to the timing diagram shown in FIG. 13 . Wherein, when the circuit unit performs the function of Bloom filter, the input signal of the working mode selection port CIN_MODE is a high level signal.

Before the rising edge of the CLK signal comes, the pre-charge signal input terminal Pre_Ch is high level, the P-type field effect transistor PFET is in the off state, so that the filter output terminal Filter_Done is low level, in addition, the filter enable signal input terminal Filter_En to high level. During this period, one_hot_latch_EN is first low level, and the One-hot array obtained by Hash Value after One-hot encoding is sent to the latch; then, one_hot_latch_EN is flipped from low level to high level, then latch The controller inputs each bit of the One-hot array it latches into the bit-addressable input terminal Translated Hash Value of each circuit unit.

When the rising edge of the CLK signal arrives, Pre_Ch is flipped from high level to low level, and the level of Filter_Done bus is pulled up to high level, thus completing the precharging of Filter_Done bus. At the same time, Filter_En is changed from high level to high level. Inverted to low level, the initialization phase ends, and the circuit unit enters the working phase. At this time, the data selector DS1 outputs a low level to the enable terminals E1 and E2 of the tri-state buffer TSB1 and the inverse tri-state buffer TSB2, so that the tri-state buffer TSB1 and the inverse tri-state buffer TSB2 are in high impedance status, no data transfer is performed.

When the falling edge of the CLK signal arrives, Pre_Ch is flipped from low level to high level, and Filter_En is flipped from low level to high level. At this time, the filter circuit starts to perform bitwise logic operations. The bitwise logic operation specifically includes: when the bit value in the storage unit is 1, the bit line BL outputs a high level, the bit line BL# outputs a low level, and the sense amplifier SA outputs a low level; When the value is 0, the bit line BL outputs a low level, the bit line BL# outputs a high level, and the sense amplifier SA outputs a high level. If the data input terminal Q# of the filter circuit receives a high level signal from the sense amplifier SA, and the bit addressing input terminal Translated Hash Value of the filter circuit (the gate G of the first N-type field effect transistor NFET1) receives a high level signal level signal, then the three NFETs (ie the first N-type field effect transistor NFET1, the second N-type field effect transistor NFET2 and the third N-type field effect transistor NFET3) will be turned on, thereby pulling Filter_Done down to a low level level; otherwise, the three NFETs will not be turned on and Filter_Done will remain high.

Based on the above configuration, when Filter_Done is pulled down to a low level, it means that the bit value in the storage unit is 0, and the One-hot value input by the bit-addressable input terminal Translated Hash Value of the filter circuit is 1, indicating that this storage unit corresponds to A target bit mapped by the detected element, and the detected element is not in the target Vector, but belongs to a new element. Therefore, the bit value in the storage unit needs to be updated. At this time, the update circuit will be activated.

After the update circuit is activated, the write update operation starts. The write update operation may specifically include: because the Filter_Done signal is at a low level, the data selector DS1 outputs a high level to the enabling terminals E1 and E2 of the tri-state buffer TSB1 and the reverse tri-state buffer TSB2, and the three The state buffer TSB1 and the reverse three-state buffer TSB2 are set to the data output state; on the other hand, the data selector DS2 inputs a high level to the input terminals A4 and A5 of the three-state buffer TSB1 and the reverse three-state buffer TSB2 Or the signal of the Translated Hash Value of the bit addressing input terminal (corresponding to the One-hot value of 1, which is also a high level), makes the output terminal Y2 of the tri-state buffer TSB1 output a high level to the bit line BL, and the tri-state buffer outputs a high level to the bit line BL. The output terminal Y3 of the device TSB2 outputs a low level (ie, an inversion signal of a high level) to the bit line BL#, thereby updating the bit value of the memory cell to 1.

So far, the circuit unit has completed the addressing and writing update process of the Bloom filter.

In addition, when the falling edge of the CLK signal arrives, one_hot_latch_EN can be flipped from a high level to a low level. At this time, the latch releases the one-hot data it has already described and waits for new one-hot data to be input.

It can be seen from the above technical solutions that the bloom filter circuit provided in the embodiment of the present application can be provided in the memory, and when the processor needs to perform the bloom filter operation, the bloom filter circuit only needs to receive addressing data from the processor, The rest of the addressing and writing update processes can be completed in the memory by the Bloom filter circuit according to the addressing data, without the involvement of the processor, so there will not be too much data migration on the bus between the memory and the processor. , to avoid bus conflicts. In addition, the bloom filter circuit provided by the embodiment of the present application can also realize the addressing and writing update process of the bloom filter in one instruction cycle cycle, which shortens the system response time and improves the Bloom filter efficiency. Comparing the structures of FIGS. 9 and 11 , and the timing diagrams of FIGS. 11 and 13 , it can be seen that for the structures of FIGS. 9 and 11 , the difference between the circuit control methods is: in the circuit control method for FIG. 9 , the three-state The working states of the buffer TSB1 and the reverse tri-state buffer TSB2 are controlled by the Filter_Done signal and the WR_EN signal, while in the circuit control method for FIG. Controlled by the Filter_Done signal. Among them, for the circuit control method of FIG. 9, due to the dual control scheme of the Filter_Done signal and the WR_EN signal, an additional function of preventing writing and updating can be realized. Keep the WR_EN signal at a low level, so that when the update circuit is activated, since the WR_EN signal is at a low level, the data selector DS1 sends the enable terminals E1 and E1 of the tri-state buffer TSB1 and the reverse tri-state buffer TSB2 to E2 outputs a low level, so that the tri-state buffer TSB1 and the reverse tri-state buffer TSB2 are in a high-impedance state, and no data transmission is performed to prevent writing and updating.

In the above-mentioned embodiment of the present application, the addressing data is designed as Hash Value, wherein the LSB of the low-order segment of Hash Value is one-hot encoded to obtain a One-hot array, and then input to the latch, and then the latch will The One-hot values of each bit of the One-hot array are input into each circuit unit in a one-to-one correspondence, so as to implement a bitwise logical operation on the bits of the target Vector on the bit line BL where each circuit unit is located. It can be understood that it takes a certain amount of time for the processor to perform One-hot encoding on the above Hash Value, resulting in a certain delay, and at the same time, the latch and the like need to be implemented by a corresponding circuit.

In order to further eliminate the delay caused by One-hot encoding, simplify the circuit structure of the system, and reduce the circuit area, the bit-addressable data can also be implemented by other encoding forms.

FIG. 11 is a schematic structural diagram of another functional circuit of a bloom filter provided by an embodiment of the present application. In some embodiments, as shown in FIG. 11 , the bit-addressable data may be a binary array with the same length (bit width) as the Vector, or a binary array larger than the Vector’s length, preferably the length of the Vector is the same as the bit-addressable data. same length. For example, when the length of the Vector is 32 bits, the length of the bit-addressable data may be 32 bits; when the length of the Vector is 64 bits, the length of the bit-addressable data may be 64 bits; when the length of the Vector is 128 bits , the length of bit-addressable data can be 128 bits; and so on.

When the bit-addressable data is a binary array with the same length (bit width) as the Vector, the addressed data (including word-addressable data and bit-addressable data) are also generated by the processor. Among them, the word addressing data can be the same as the high-order segment of the Hash Value, that is, the bit value used for input to the word line WL where the target Vector is located is 1, which is used to activate the word line WL where the target Vector is located, and input to the word lines where the other Vectors are located. The bit value of WL is 0, so that the word line WL where the rest of the Vectors are located will not be activated; each bit value of the bit addressing data is used to be input to the bit addressing input terminal 410 of each circuit unit 400 in a one-to-one correspondence, wherein the bit addressing Each bit value of the address data can be 0 or 1, and the bit value of 1 of the bit addressing data points to the target bit of the target Vector. For example, when the detected element is mapped to 4 target bits in the target Vector, the bit addressing In the 128-bit binary array of data, correspondingly, 4 bits have the value of 1, and the rest are 0. In this way, each circuit unit 400 in the Bloom filter function circuit 50 can perform a bitwise logical operation on the bits of the target Vector on the bit line BL where it is located according to the bit value it receives. If the bit value received by a certain circuit unit 400 is 1, it means that a target bit mapped by the detected element is located on the bit line BL where the circuit unit 400 is located.

Based on the scheme shown in Figure 14, the processor can directly generate a binary array with the same length (bit width) as the Vector as bit-addressable data, and then directly input each bit value of the bit-addressable data to each circuit in a one-to-one correspondence The bit-addressable input terminal 410 of the unit 400 is used for each circuit unit 400 to perform bit-wise logical operations, so as to realize the direct bit-wise addressing of the processor, thereby eliminating the delay caused by One-hot encoding, and in addition, the bit-addressable data is not Then it needs to be sent into the latch for latching, so that the related circuit of the latch does not need to be added in the system circuit composed of the memory and the processor, which simplifies the system circuit structure and reduces the circuit area.

The present application also provides a computer storage medium. The computer storage medium computer instructions, when executed on a computer, cause the computer to perform the methods in the above-described aspects and implementations thereof.

The present application also provides a computer program product comprising instructions which, when run on a computer, cause the computer to perform the methods of the above aspects and implementations thereof.

The above contents are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto, and any changes or substitutions within the technical scope disclosed in the present application should be covered within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (21)

1. A memory, characterized in that, comprising:

   a cell array, the cell array including a plurality of memory cells;

   A plurality of circuit units, the plurality of circuit units are respectively connected with at least one of the storage units; wherein, the circuit units are used for:

   Receive the first bit value of the externally input bit-addressable data;

   reading the second bit value in the target storage unit pointed to by the bit-addressable data;

   When the first bit value is different from the second bit value, the target storage unit is updated to the first bit value.
2. The memory of claim 1, wherein

   A plurality of the storage cells are distributed into multiple rows and columns, the storage cells in each row are connected by a word line, the storage cells in each column are connected by a bit line, and the storage cells in each row are used to store a bit array, and each row is used to store a bit array. One of the bit lines is connected with one of the circuit units;

   The first bit values received by the different circuit units correspond to different bits of the bit-addressed data.
3. The memory of claim 2, wherein:

   The circuit unit includes a filter circuit and an update circuit;

   The filtering circuit includes a bit addressing input terminal, a data input terminal and a filtering output terminal;

   The bit addressing input terminal is used for receiving the first bit value, and the data input terminal is connected to the storage unit for reading the second bit value;

   The filtering circuit is configured to output a first enable signal at the filtering output end when the first bit value is different from the second bit value;

   The update circuit includes a data output terminal, and the data output terminal is connected with the storage unit;

   The update circuit is configured to update the target storage unit to a first bit value when the filter circuit outputs the first enable signal.
4. The memory of claim 3, wherein:

   The filtering circuit includes a first field effect transistor, a second field effect transistor and a third field effect transistor;

   The source of the first field effect transistor is grounded, the gate of the first field effect transistor is the bit addressing input terminal, the drain of the first field effect transistor and the source of the second field effect transistor pole connection;

   The gate of the second field effect transistor is the data input terminal, and the drain electrode of the second field effect transistor is connected to the source electrode of the third field effect transistor;

   The gate of the third field effect transistor is the filter enable signal input terminal, and the drain of the third field effect transistor is the filter output terminal.
5. The memory of claim 4, wherein:

   The filtering circuit is specifically configured to output the filtering output terminal when a second enabling signal is received at the filtering enabling signal input terminal and the first bit value is different from the second bit value. first enable signal.
6. The memory according to claim 4 or 5, wherein the first field effect transistor, the second field effect transistor and the third field effect transistor are all N-type field effect transistors.
7. The memory according to any one of claims 2-6, wherein,

   The update circuit includes a tri-state buffer, an inverse tri-state buffer, a first data selector and a second data selector;

   The first input terminal of the first data selector is a write enable signal input terminal, the second input terminal of the first data selector is used to receive the inversion signal of the first enable signal, and the first The output end of a data selector is connected with the enabling end of the tri-state buffer and the enabling end of the inverse tri-state buffer;

   The second input terminal of the second data selector is connected to the bit addressing input terminal or a high potential, and the output terminal of the second data selector is connected to the input terminal of the tri-state buffer and the reverse The input terminal of the three-state buffer is connected;

   The output end of the tri-state buffer and the output end of the inverse tri-state buffer are the data output ends.
8. The memory according to claim 7, wherein the first enable signal is a high-level signal, and the update circuit is specifically configured to set the value of the first bit to 1 and the value of the second bit to When it is 0, the target storage unit is updated to the first bit value.
9. The memory according to any one of claims 2-6, characterized in that

   The update circuit includes an AND gate unit, a tri-state buffer, an inverse tri-state buffer, a first data selector and a second data selector;

   The first input end of the AND gate unit is connected to the filter output end, and is used for receiving the inversion signal of the first enable signal; the second input end of the AND gate unit is the write enable signal input end ; The output end of the AND gate unit is connected with the second input end of the first data selector;

   The first input terminal of the first data selector is connected to the input terminal of the write enable signal, and the output terminal of the first data selector is connected to the enable terminal of the three-state buffer and the inverse three-state buffer. enable connection of the state buffer;

   The second input terminal of the second data selector is connected to the bit addressing input terminal or a high potential, and the output terminal of the second data selector is connected to the input terminal of the tri-state buffer and the reverse The input terminal of the three-state buffer is connected;

   The output end of the tri-state buffer and the output end of the inverse tri-state buffer are the data output ends.
10. The memory according to claim 9, wherein the first enable signal is a high level signal, the update circuit is specifically configured to input a high level at the write enable signal input terminal, and the When the first bit value is 1 and the second bit value is 0, the target storage unit is updated to the first bit value.
11. The memory according to any one of claims 7-10, wherein,

    The bit line includes a first bit line and a second bit line, the output end of the tri-state buffer is connected to the first bit line, and the output end of the inverse tri-state register is connected to the second bit line. line connection;

    When the first bit line is at a high level and the second bit line is at a low level, the bit value in the memory cell is 1; when the first bit line is at a low level, the second bit line is at a low level. When the bit line is at a high level, the bit value in the memory cell is 0.
12. The memory according to any one of claims 7-10, wherein,

    The data selection terminal of the first data selector and the data selection terminal of the second data selector are used to receive a working mode selection signal; when the working mode selection signal is at a low level, the first data selector The output end of the first data selector and the output end of the second data selector both output the signal of the respective first input end; when the working mode selection signal is high level, the output end of the first data selector and the second data selector The output terminals of the data selectors all output the signals of the respective second input terminals.
13. The memory of claim 11, wherein:

    the data input terminal is connected to the bit line through a sense amplifier;

    The sense amplifier includes two input terminals, which are respectively connected with the first bit line and the second bit line;

    The sense amplifier further includes an output terminal connected to the data input terminal;

    Wherein, when the first bit line is at a high level and the second bit line is at a low level, the sense amplifier outputs a low level; when the first bit line is at a low level, the second bit line is at a low level When the bit line is at a high level, the sense amplifier outputs a high level.
14. The memory according to claim 8 or 10, characterized in that,

    The filtering circuit further includes a fourth field effect transistor, the source of the fourth field effect transistor is coupled to a high potential, the drain of the fourth field effect transistor is connected to the filtering output end, and the fourth field effect transistor is connected to the filter output. The gate of the tube is a precharge signal input terminal; wherein, when the precharge signal input terminal is input with a low level, the fourth field effect transistor is turned on to pull the filter output terminal to a high level.
15. The memory according to claim 14, wherein the fourth field effect transistor is a P-type field effect transistor.
16. The memory according to claim 4 or 5, wherein a plurality of the circuit units share the same input terminal of the filter enable signal.
17. The memory according to any one of claims 7-15, wherein a plurality of the circuit units share the same input terminal of the write enable signal.
18. The memory according to any one of claims 3-17, wherein a plurality of the circuit units share the same filter output end.
19. The memory according to any one of claims 3-18, further comprising:

    a latch; an input end of the latch is used to receive the bit-addressed data, and the bit-addressed data is one-hot encoded One-hot data; an output end of the latch is connected to each of the circuits The addressing input terminals of the unit are connected, and are used for inputting the bit values of different bits of the one-hot encoded data to the addressing input terminals of each of the circuit units in a one-to-one correspondence.
20. The memory according to claim 19, wherein the latch further comprises a control signal input terminal for receiving an external control signal, wherein when the external control signal is at a low level, the latch uses For receiving and latching the one-hot encoded data, when the external control signal is at a high level, the latch is used to input the bit values of different bits of the one-hot encoded data into each of the one-hot encoded data. the addressing input of the circuit unit.
21. The memory according to any one of claims 1-20, wherein the bit-addressable data is a binary array.

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