JP4854277B2 - Orthogonal transformation circuit - Google Patents

Description

  The present invention relates to a circuit for converting a data array between a bit serial and word parallel data string and a word serial and bit parallel data string, and in particular, a memory and an arithmetic circuit are integrated on the same semiconductor substrate. The present invention relates to an orthogonal transform circuit for efficiently transferring data between a system bus for transferring external data and the memory in a signal processing device.

  With the development of mobile communication technology, mobile terminal devices such as mobile phones can transmit and receive large amounts of data such as voice and images. The importance of high-speed digital signal processing is increasing. For such digital signal processing, a DSP (digital signal processor) is generally used as a dedicated semiconductor device. In digital signal processing for audio and image data, data processing such as filter processing is performed, and in such processing, there are many arithmetic processes that repeat product-sum operations. Therefore, in general, in the configuration of the DSP, a multiplication circuit, an addition circuit, and an accumulation register are provided. If such a dedicated DSP is used, the product-sum operation can be executed in one machine cycle, and high-speed operation processing is possible.

  Japanese Patent Laid-Open No. 6-324862 discloses a configuration in which a register file is used when performing such product-sum operation. In Patent Document 1, binary operand data stored in a register file is read and added by an arithmetic unit, and then the addition result is written into the register file via a write data register.

  In the configuration disclosed in Patent Document 1, a write address and a read address are simultaneously given to a register file, and data writing and data reading are performed in parallel. By executing the writing and reading in parallel, the processing time is shortened as compared with a configuration in which a data writing cycle and a data reading cycle are separately provided for arithmetic processing.

  Also, a signal processing apparatus that aims to perform processing such as DCT transformation (discrete cosine transformation) of image data at high speed is disclosed in Japanese Patent Laid-Open No. 10-74141. In the configuration disclosed in Patent Document 2, since image data is input in a bit parallel and word serial sequence, that is, in units of words (pixel data), the serial / parallel conversion circuit is used to perform word parallel and bit serial. Convert to data string and write to memory array. In the memory array, data constituting the same block on the screen is stored aligned in the column direction. That is, in each memory array block, pixel data constituting the corresponding image block is stored in units of words for each row of the memory array. An arithmetic unit is provided for each memory array block.

In the configuration disclosed in Patent Document 2, data is transferred in units of words (data corresponding to one pixel) between a memory array block and a corresponding arithmetic unit. By executing the same processing on the words transferred by the corresponding arithmetic unit for each block individually, it is possible to execute the filtering processing by DCT conversion at high speed. The result of the arithmetic processing is written again into the memory array, and again parallel / serial conversion is performed to convert bit serial and word parallel data into bit parallel and word serial data, and pixel data for each line is sequentially output. To do. In normal processing, bit position conversion of data is not performed, and normal arithmetic processing is performed in parallel on a plurality of data in an arithmetic unit.
JP-A-6-324862 Japanese Patent Laid-Open No. 10-74141

  When the amount of data to be processed is very large, it is difficult to dramatically improve the performance even if a dedicated DSP is used. For example, if there are 10,000 sets of calculation target data, even if the calculation for each piece of data can be executed in one machine cycle, at least 110,000 cycles are required for the calculation. Therefore, in the configuration in which the multiply-accumulate operation is performed using the register file as shown in Patent Document 1, although each processing is performed at a high speed, the data processing is performed in series, so that the data amount is large. Then, the processing time becomes longer in proportion to this, and high-speed processing cannot be realized.

  In addition, when a dedicated DSP is used, the processing performance greatly depends on the operating frequency. Therefore, when high-speed processing is prioritized, power consumption increases.

  Further, when using a register file and an arithmetic unit as disclosed in Patent Document 1, it is often designed specifically for a certain application, and the arithmetic bit width and the configuration of the arithmetic circuit are fixed. Therefore, when diverting to other uses, it is necessary to redesign the bit width and the configuration of the arithmetic circuit, and there arises a problem that it becomes impossible to flexibly cope with a plurality of arithmetic processing uses.

  Further, in the configuration shown in Patent Document 2, a plurality of images are arranged in which pixel data of one line of the screen is stored in one row of memory cells and aligned in the row direction in order to speed up processing such as DCT conversion of image data. Perform processing on blocks in parallel. However, this image block is, for example, a block of 8 pixels × 8 pixels, and one pixel is 8-bit data as an example. Pixel data is sequentially transferred pixel by bit in bit parallel and word serial, the array is converted by 8 pixels, converted to a word parallel and bit serial data string, and stored in a memory array. Therefore, when the number of pixels is increased for higher definition of the image, the number of operation-symmetric blocks increases, and the number of macroblocks included in the line of the operation target block generally called a macroblock increases. Therefore, even when arithmetic processing is performed for each macroblock line, the number of pixels increases. Accordingly, it takes a long time to transfer pixel data to and from the memory cell array, and high-speed processing is performed. Can not be.

  Further, Patent Document 2 discloses a configuration in which arithmetic circuits are arranged corresponding to blocks of a memory cell array and product-sum arithmetic processing is executed. However, the arithmetic mode is a word serial and bit parallel mode. If the data bit width is changed and the data bit width is changed, the bit width of the arithmetic unit needs to be changed, and the circuit configuration needs to be designed. Therefore, when the bit width of the pixel data is fixed as in processing of pixel data of a specific format, the pixel data storage area of the memory cell array and the arithmetic processing bit width of the arithmetic unit are fixedly set. Arithmetic processing can be executed. However, when the bit widths of pixel data are different in a plurality of types of formats, the configuration disclosed in Patent Document 2 cannot flexibly cope with the problem, and the application is fixedly set and versatile. Occurs.

  Further, when the bus width for transferring the operation target data is 32 bits, for example, when the data to be processed is 8 bit data in a certain application, four 8-bit data words are arranged in parallel for efficient data transfer. It is possible to transfer. When the data array conversion method disclosed in Patent Document 2 described above is applied, data array conversion is performed in units of 4 word data transferred in one bus access cycle. Therefore, when A0-A3, B0-B3, C0-C3 and D0-D3 are each 8-bit data, 4 word data A0-A3 is transferred at the first transfer, and then data B0-B3 is transferred. Next, data C0-C3 is transferred, and when 4-word data D0-D3 is transferred, the data array is converted. The bit width of one transfer data before and after conversion is the same. Therefore, in this case, the data array of the entire 4-word data is converted. In the converted data string, the data A0, B0, C0 and D0 are transferred in parallel in a bit-serial manner, and the data string A0-A3 is converted into bits. The data cannot be transferred in parallel in a serial manner, and the desired arithmetic processing cannot be realized.

  SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an orthogonal transform circuit that can efficiently perform data array conversion regardless of the bit width of data to be calculated.

  Another object of the present invention is to provide an orthogonal transform circuit suitable for a signal processing apparatus capable of executing arithmetic processing at high speed without causing data transfer to be overhead regardless of the data bit width.

According to the orthogonal transform circuit device of the present invention, a memory having a plurality of entries each extending in a first direction and including a plurality of memory cells, and bit width information of data transferred on the first bus , Setting a data transfer path between the first bus and the memory, transferring a data according to the set path, and a second direction of the second bus and the plurality of memory entries And a data transfer circuit for transferring data in parallel with the aligned bits.
The data transfer path setting circuit, when the effective bit width information indicates that the bit width of the unit data transferred on the first bus is smaller than the bit width of the first bus, A data transfer path is set to transfer data to and from the same area of a plurality of entries.
When the bit width information indicates that the bit width of the data transferred through the first bus is smaller than the bit width of the first bus, the data transfer circuit expands the number of entries to increase the number of entries. And the second bus.

  The data transfer path setting circuit switches the data transfer path to and from the memory according to the bit width of the data transferred on the first bus, and transfers the data to and from the memory entry. Therefore, when the bus width of the first bus is the same as the bit width of the transfer data, data transfer is sequentially performed with the memory entries, and the bit width of the transfer data is smaller than the bus width of the first bus. Sometimes, a plurality of data is transferred in parallel on the first bus, and the transfer is transferred between a plurality of entries in the memory. Data transfer can be performed by fully utilizing the bus line of the first bus, the data transfer capability of the first bus can be fully utilized, and efficient regardless of the bit width of the transfer data. Data transfer can be realized.

  The data transfer circuit transfers data at the same position in a plurality of memory entries, and the data transferred from the first bus is transferred in a word parallel and bit serial manner regardless of the bit width. The Therefore, the arrangement of data transferred through the first bus and the second bus can be efficiently converted regardless of the bit width.

  By mounting this orthogonal transform circuit in a signal processing device in which a memory (arithmetic memory) and an arithmetic unit are integrated, data can be transferred between the orthogonal transform circuit and the arithmetic memory in an entry parallel and bit serial manner. It is possible to transfer data efficiently in a signal processing device, and it is possible to avoid data transfer from becoming a bottleneck for high-speed arithmetic processing, and to realize high-speed arithmetic processing Can do.

[Embodiment 1]
FIG. 1 is a diagram schematically showing an overall configuration of a signal processing system to which an orthogonal transform circuit according to the present invention is applied. In FIG. 1, the signal processing system 1 includes a system LSI 2 that realizes an arithmetic function for executing various processes, and an external memory connected to the system LSI 2 via an external system bus 3. The external memory includes a large-capacity memory 4, a high-speed memory 5, and a read-only memory (read-only memory: ROM) 6 that stores fixed information such as instructions at the time of system startup. The large-capacity memory 4 is composed of, for example, a clock synchronous dynamic random access memory (SDRAM), and the high-speed memory 5 is composed of, for example, a static random access memory (SRAM).

  The system LSI 2 includes basic arithmetic blocks FB1 to FBh coupled in parallel to the internal system bus 7, a host CPU 8 coupled to the internal system bus 7 and controlling processing operations of these basic arithmetic blocks FB1 to FBh, and signal processing. An input port 9 that converts an input signal IN from the outside of the system 1 into data for internal processing, and an output port 10 that receives the output data given from the internal system bus 7 and generates an output signal OUT that is transferred to the outside of the system including. These input port 9 and output port 10 are constituted by, for example, a library IP (Intellectual Property) block, and realize functions necessary for data / signal input / output.

  The system LSI 2 further receives an interrupt signal from the basic operation blocks FB1 to FBh, notifies the host CPU 8 of the interrupt, and a CPU peripheral that performs a control operation necessary for each processing of the host CPU 8. 12, a DMA (direct memory access) controller 13 for transferring data to the external memory in accordance with a transfer request from the basic operation blocks FB1-FBh, and an external system bus 3 in accordance with an instruction from the host CPU 8 or the DMA controller 13. The external bus controller 14 that performs access control to the memory 4-6 and the dedicated logic 15 that assists the data processing of the host CPU 8 are included.

  The CPU peripheral 12 has functions necessary for program and debugging purposes in the host CPU 8 such as a timer and serial IO (input / output). The dedicated logic 15 is configured by, for example, an IP block, and implements a necessary processing function using an existing function block. These functional blocks 9-15 are connected to the internal system bus 7 in parallel. The DMA controller 13 is given a DMA request signal from the basic operation blocks FB1-FBh.

  Since basic operation blocks FB1-FBh have the same configuration, FIG. 1 representatively shows the configuration of basic operation block FB1.

  The basic arithmetic block FB1 is in accordance with a main arithmetic circuit 20 that performs arithmetic processing of actual data, a microinstruction memory 21 that stores microinstructions that specify arithmetic processing in the main arithmetic circuit 20, and a microinstruction from the microinstruction memory 21. Data between the controller 22 that controls the arithmetic processing of the main arithmetic circuit 20, the work data memory 23 that stores intermediate processing data or work data of the controller 22, and the internal arithmetic bus FB1 and the internal system bus 7 A system bus interface (I / F) 24 that performs signal transfer is included.

  The main arithmetic circuit 20 has a memory cell mat 30 in which a plurality of memory cells are arranged in a matrix and divided into a plurality of entries, and is arranged corresponding to each entry of the memory cell mat 30, and performs a specified arithmetic processing. An arithmetic unit (ALU) 31 to perform and an inter-ALU interconnection switch circuit 32 for setting a data transfer path between the arithmetic units 31 are included.

  Basically, each row of the memory cell mat 30 constitutes one entry, and each bit of multi-bit data is stored in one entry.

  An arithmetic unit (hereinafter referred to as ALU as appropriate) 31 receives the data from the corresponding entry in bit serial and performs arithmetic processing, and the processing result is assigned to a specified entry (for example, corresponding entry) in the memory cell mat 30. Stored in a predetermined position.

  The connection path of the ALU 31 is switched by the inter-ALU interconnection switch circuit 32, so that data of different entries can be calculated. By storing different data in each entry and performing parallel arithmetic processing by the ALU 31, data processing can be performed at high speed.

  The controller 22 performs an operation in accordance with the microprogram method in accordance with the microinstruction stored in the microinstruction memory 21. Work data necessary for the microprogram operation is stored in the work data memory 23.

  The system bus I / F 24 allows the host CPU 8 or the DMA controller 13 to access the memory cell mat 30, the dedicated register in the controller 22, the microinstruction memory 21 and the work data memory 23.

  An orthogonal transform circuit 85 that rearranges a given data string between the system bus I / F 24 and the main arithmetic circuit 20, and between one of the system bus I / F 24 and the orthogonal transform circuit 85 and the main arithmetic circuit 20. Is provided with a switching circuit (MUX) 87.

  This orthogonal transform circuit 85 transfers data transferred from the system bus I / F 24 in a bit parallel and word serial manner in a word parallel and bit serial manner, and a different data word is assigned to each entry of the memory cell mat 30. Are written in bit parallel at the same position. Further, the orthogonal transform circuit 85 transposes a data string transferred in word parallel and bit serial from the memory cell mat 30 of the main arithmetic circuit 20 and transfers it in a bit parallel and word serial manner. Thereby, the consistency of data transfer between the system bus I / F 24 and the memory cell mat 30 is established.

  Here, the bit serial indicates a mode in which bits constituting one data word are sequentially transferred or processed, and the bit parallel indicates a mode in which bits constituting one data word are transferred or processed in parallel. The entry (or word) parallel indicates a mode in which a plurality of entries (or words) are transferred or processed in parallel, and the entry (or word) serial indicates that a plurality of entries (or words) are sequentially transferred or processed. An embodiment is shown.

  Conversion between a bit serial and word parallel data sequence and a bit parallel and word serial data sequence is defined as “orthogonal transformation”.

  The switching circuit 87 may be configured to select work data from the controller 22 and transfer it to the main arithmetic circuit 20. In this case, the work data memory 23 becomes unnecessary. Further, when it is not necessary to transpose the operation target data string by orthogonal transformation, the switching circuit 87 selects the system bus I / F 24 and connects it to the main arithmetic circuit 20.

  Regarding the processing operation of the entire signal processing system and the configuration and processing operation of the main arithmetic circuit 20, the same applicant has already filed as Japanese Patent Application Nos. 2004-358719 and 2004-282014. However, in order to fully understand the operation and effect of the orthogonal transform circuit according to the present invention, the configuration and operation of the main arithmetic circuit 20 will be briefly described below.

  FIG. 2 schematically shows an arrangement of memory cell mat 30 and arithmetic unit (ALU) 31 of main arithmetic circuit 20 shown in FIG. In memory cell mat 30, memory cells MC are arranged in a matrix and divided into M entries ERY. The entry ERY has a bit width of N bits. In this memory cell mat 30, a word line WL is provided in common to M entries ERY, a bit line pair BLP is arranged for one entry ERY, and a bit line BL of this bit line pair BLP is arranged. And / BL are used as data transfer lines.

  An arithmetic unit (ALU) 31 is provided corresponding to each entry ERY and constitutes an arithmetic processing unit 35. The computing unit 31 can perform operations such as addition, logical product, coincidence detection (EXOR), and inversion (NOT). Data is loaded and stored between each entry ERY and the corresponding arithmetic unit 31 to execute arithmetic processing. The calculation contents of the calculator 31 are set by the controller 22 shown in FIG.

  Each entry ERY stores data to be subjected to arithmetic processing, and the arithmetic unit 31 executes arithmetic processing in a bit serial manner. Therefore, the arithmetic processing unit 35 executes data arithmetic processing in a bit serial and entry parallel manner.

  By executing arithmetic processing in a bit serial manner in the arithmetic processing unit 35, the number of arithmetic cycles is simply changed according to the bit width of the data word even when the bit width of the data to be calculated differs depending on the application. However, the processing content is not changed, and it is possible to easily cope with data processing with different word configurations.

  Further, data of a plurality of entries ERY can be processed in parallel in the arithmetic processing unit 35, and a large amount of data can be arithmetically processed at once by increasing the number of entries M. As an example, the number of entries M is 1024, and the bit width N of one entry ERY is 512 bits.

  Memory cell MC is formed of an SRAM (Static Random Access Memory) cell and can perform data transfer by performing high speed access. Further, it is not necessary to periodically refresh the data, and the control of the arithmetic processing for the data in the memory cell mat 30 can be simplified.

  When the main arithmetic circuit 20 performs an operation, first, operation symmetric data is stored in each entry ERY. Next, a certain digit of the stored data is read in parallel for all the entries ERY and transferred (loaded) to the corresponding arithmetic unit 31. That is, by driving the word line WL to the selected state, the data of the memory cell MC connected to the selected word line is read onto the corresponding bit line pair BLP, and the read data is transferred to the corresponding arithmetic unit 31. Transferred.

  When performing a binary operation, in each entry ERY, data of a set of binary operations is stored, and after a bit of one data word is transferred, a similar transfer operation is performed on the bit of another data word. Do. Thereafter, each arithmetic unit 31 performs a binary operation, and the arithmetic processing result is rewritten (stored) from the arithmetic unit 31 to a predetermined area in the corresponding entry ERY.

  FIG. 3 is a diagram showing an example of the arithmetic operation in the main arithmetic circuit 20 shown in FIG. In FIG. 3, data words a and b having a 2-bit width are added to generate data word c. In each entry ERY, data words a and b forming a set to be calculated are stored.

  In FIG. 3, the calculator 31 for the entry ERY in the first row adds 10B + 01B, and the calculator 31 for the entry ERY in the second row calculates 00B + 11B. Here, “B” indicates a binary number. The calculator 31 for the entry ERY in the third row adds 11B + 10B. Thereafter, similarly, an addition operation of the data words a and b stored in each entry ERY is executed.

  The calculation is performed in a bit serial manner in order from the lower bit. First, the lower bit a [0] of the data word a is transferred to the corresponding arithmetic unit (ALU) 31 in each entry ERY. Next, the lower bit [0] of the data word b is transferred to the corresponding computing unit 31. Each of the arithmetic units 31 performs an addition operation using the given 2-bit data. This addition operation result a [0] + b [0] is written (stored) at the position of the lower bit c [0] of the data word c. For example, in the entry ERY in the first row, bit “1” is written at the position of c [0].

  This addition process is also performed for the upper bits a [1] and b [1], and the addition result a [1] + b [1] is written at the position of bit c [1].

  Depending on the addition operation, a carry may occur, and the carry value is written in the position of bit c [2]. Thereby, the addition of the data words a and b is completed in all the entries ERY, and the result is stored as data c in each entry ERY. When 1024 entries are provided, the addition of 1024 sets of data can be performed in parallel.

  FIG. 4 is a diagram schematically showing the flow of data bits during the binary addition operation. FIG. 4 shows the flow of data bits during an arithmetic operation on the i-th and (i + 1) -th bits. As shown in FIG. 4, in memory cell mat 30, first, bits a [i] and b [i] are read (Read) in the k-th cycle and (k + 1) -th cycle, respectively, and an arithmetic unit (ALU) 31 is read. Forwarded to

  In the next (k + 1) cycle, the operation shifts to the addition operation (ADD) of the calculator 31 and the calculation result c [i] is written in the next cycle (k + 3) (Write). Next, in the next cycle (k + 4) to (k + 7), sequential reading of bits a [i + 1] and b [i + 1], addition operation, and writing of the addition result c [i + 1] are executed.

  As shown in FIG. 4, one machine cycle is required for each data bit transfer between the memory cell mat 30 and the computing unit 31, and the computing unit 31 requires one machine cycle. In the case of the configuration, 4 machine cycles are required to add 2-bit data and store the addition result. That is, 4 machine cycles are required for each digit of the arithmetic processing data.

  However, the memory cell mat 30 is divided into a plurality of entries ERY, a set of data to be calculated is stored in each entry ERY, and a calculation process is performed in a bit-serial manner in a corresponding arithmetic unit (ALU) 31. The following features are realized. In other words, each data operation requires a relatively large number of machine cycles, but if the amount of data to be processed is very large, high-speed data processing is achieved by increasing the parallelism of the operations. Can be realized. In addition, since the arithmetic processing is performed in the bit serial mode and the bit width of the processed data is not fixed, it can be easily adapted to applications having various data configurations.

  FIG. 5 is a diagram illustrating an example of a specific configuration of the main arithmetic circuit 20. In the main arithmetic circuit 20, the memory cells MC arranged in the memory cell mat 30 are single port SRAM cells. A word line WL is arranged corresponding to each memory cell aligned in the vertical direction in the figure, and a bit line pair BLP is arranged corresponding to each entry. Memory cell MC is arranged corresponding to the intersection of bit line pair BLP and word line WL. One word line WL is connected to memory cells MC arranged at the same position in entries ERY0 to ERY (M−1). In bit line pairs BLP0-BLP (M-1) arranged for entries ERY0-ERY (M-1), the memory cells of the corresponding entries are connected.

  A row decoder 74 is provided for driving the word line WL to which the operation target data bit is connected to the selected state in accordance with an address signal from the controller 22 or the orthogonal transform circuit 85 for the word line WL of the memory cell mat 30. . The row decoder 74 selects the data bits at the same position in the entries ERY0 to ERY (M-1) in parallel.

  In the arithmetic processing unit 35, an arithmetic unit (ALU) 31 is arranged corresponding to the bit line pair BLP0-BLP (M-1).

  A read / write circuit for loading / storing data is provided between arithmetic processing unit 35 and memory cell mat 30. Read / write circuit 38 includes a sense amplifier unit 70 and a write driver group 72 each including a sense amplifier and a write driver provided corresponding to each of bit line pairs BLP0 to BLP (M-1).

  An input / output circuit 76 for transmitting / receiving data to / from the read / write circuit 38 via the orthogonal transform circuit 85 and the internal memory bus 77 is provided. The input / output circuit 76 transfers data between the memory cell mat 30 and the internal memory bus 77. The input / output bit width of data of the input / output circuit 76 is set to a value equal to or larger than the bit width of data transferred by the system bus I / F 24.

  A column decoder 78 is provided to adjust the data bit width in the input / output circuit 76 and the bit width (M) of an entry connected to one word line WL. By the column selection line CL from the column decoder 78, the orthogonal transformation circuit 85 selects the number of bit line pairs (sense amplifier or write driver) corresponding to the transfer data bit width. The column decoder 78 is given an entry address from the controller 22 or the orthogonal transform circuit 85. The number of bits of the address given to the column decoder 78 is appropriately determined according to the bit width of the data transferred to and from the orthogonal transform circuit 85.

  The entry selected by the column selection line CL is connected to the input / output circuit 76, and data is transferred to and from the orthogonal transformation circuit 85 via the internal memory bus.

  As shown in FIG. 5, the entries ERY0-ERY (M-1) are selected by the row decoder 74, and data writing is executed in parallel for a predetermined number of entries of the selected entries. Therefore, it is necessary to transfer data stored in different entries from the input / output circuit 76. On the other hand, data transferred via the system bus I / F 24 is data in units of data words, and is data included in one entry ERY. Therefore, word serial and bit parallel data of transfer data (transfer data on internal system bus 7) is converted to bit serial and word parallel data suitable for writing to memory cell mat 30. Convert. As described above, this function is called an orthogonal transformation function, and the orthogonal transformation circuit 85 performs data array transformation.

  FIG. 6 is a diagram showing a data flow by the data array conversion operation in the orthogonal transform circuit 85 shown in FIG. In FIG. 6, the operation in the case where 4-bit data is transferred from an external large-capacity memory (SDRAM) 4 and 4-bit data is transferred from the orthogonal transformation circuit 85 to the memory cell mat 30 in the main arithmetic circuit 20 is shown. Shown as an example.

  The SDRAM 4 stores 4-bit data a (bits a0 to a3) to i (bits i3 to i0). Each bit of 4-bit data DTE (data i; bits i3-i0) is transferred in parallel from the SDRAM 4 via the internal system bus (7). The data DTE from the SDRAM 4 is entry unit data stored in the same entry ERY of the memory cell mat. In the orthogonal transform circuit 85, each bit of the transferred 4-bit data is stored in alignment in the Y direction. Is done. In the memory of the orthogonal transform circuit 85, the transfer data is sequentially stored in the X direction.

  At the time of data transfer from the orthogonal transformation circuit 85 to the memory cell mat 30, bits aligned in the X direction are read in parallel, and data transfer is performed by sequentially updating the selected bit position along the Y direction. Therefore, data DTA composed of bits e 1, f 1, g 1 and h 1 is stored in parallel in 4 entries of memory cell mat 30. This address unit data DTA is data that is stored when one address is specified in the memory cell mat, and is stored in the position indicated by the entry position information and write bit position information of the memory cell mat 30. By repeating this operation sequentially for all transfer data, a plurality of data bits are written in parallel to a plurality of entries (4 entry units) in the memory cell mat 30, and each entry is entered in the entry ERY. The data DTE is stored. When data is transferred from the memory cell mat 30 to the outside via the internal system bus (7), data flows in the opposite direction, and data DTA in address units is sequentially stored in the orthogonal transform circuit 85 along the Y direction. Then, the data DTE of the entry unit aligned in the X direction is read from the orthogonal transform circuit 85 and transferred via the system bus I / F (24). When data is transferred from the memory cell mat 30 to the SDRAM 4 via the system bus, only the data flow shown in FIG.

  Therefore, basically, data is transferred in bit parallel and word serial between the internal system bus and the orthogonal transform circuit 85, and data in bit serial and word parallel is transferred between the orthogonal transform circuit 85 and the memory cell mat. Transferred.

  FIG. 7 schematically shows a configuration of orthogonal transform circuit 85 shown in FIG. In FIG. 7, the orthogonal transform circuit 85 includes two orthogonal memories 90a and 90b. Each of these orthogonal memories 90a and 90b is composed of a dual port SRAM (this configuration will be described in detail later), and each has K entries each having a width of L bits. The entries extend in the Y direction, and data DTE for each entry is stored in each of these K entries. On the other hand, address unit data DTA is stored at bit positions aligned along the X direction.

  The orthogonal transform circuit 85 further includes a system bus orthogonal memory I / F (interface) 91 that provides an interface between the orthogonal memories 90 a and 90 b and the system bus I / F 24, an orthogonal memory 90 a and 90 b, and an internal memory bus 77. A memory cell mat orthogonal memory I / F 92 coupled to the input / output circuit 76 and serving as an interface between the orthogonal memories 90a and 90b and the internal memory bus 77 when data is transferred to and from the memory cell mat (30). The control register group 94 that stores information necessary for the internal operation of the orthogonal transform circuit 85, the internal register group 93 that stores address information at the time of data transfer between the memory cell mats, and the internal register group 93 are stored. Based on the information, the access target address for the memory cell mat (30) is calculated. A memory cell mat address calculation unit 95 to provide to the main processing circuit (20).

  An L-bit internal data bus 96 is provided between the system bus I / F 24 and the system bus orthogonal memory I / F 91, and an L bit between the system bus orthogonal memory I / F and the orthogonal memories 90a and 90b. A width internal data bus 97 is provided. An internal data bus 98 having a K-bit width is provided between the orthogonal memories 90a and 90b and the memory cell mat orthogonal memory I / F 92. The internal memory bus 77 has a bit width of J bits and L ≦ K ≦ J.

  Bus 96 corresponds to the first bus, and bus 77 corresponds to the second bus. Orthogonal memories 90a and 90b convert the array of data strings between these buses.

  The internal register group 93 includes a system bus access number counter 93a that stores count information of the number of accesses to the internal system bus 7, and a memory cell mat access number counter 93b that stores count information of the number of accesses to the memory cell mat. . These counters 93a and 93b are alternately used by the orthogonal memories 90a and 90b.

  The control register group 94 includes an entry position register 94a for storing entry position information for the memory cell mat 30, a bit position register 94b for storing bit position information for the memory cell mat 30, and activation / inactivation of the orthogonal transformation circuit 85. And an enable register 94c for storing a control bit (enable bit) for determining data, and a read / write direction register 94b for storing information for setting a data transfer direction between the memory cell mat 30 and the system bus 7. Entry position register 94a and bit position register 94b include an A register and a B register respectively provided for orthogonal memories 90a and 90b. The entry position register 94a and the bit position register 94b can be shared and used alternately by the orthogonal memories 90a and 90b, respectively, but here, the orthogonal memories 90a and 90b are used for simplicity of control. These registers 94a and 94b are provided for each.

  In entry position register 94a and bit position register 94b, entry position information and bit position information in memory cell mat 30 are designated. At the time of data transfer to the memory cell mat 30, the contents of the designated area in the memory cell mat 30 are held in the orthogonal memories 90a and 90b, and the orthogonal transform circuit 85 has a function of rearranging data. / Functions as a write buffer circuit.

  Further, the data storage status in the orthogonal memories 90a and 90b is indicated by the count values of the counter registers 93a and 93b in the internal register group 93.

  The system bus orthogonal memory I / F 91 has a function of controlling data transfer between the orthogonal transform circuit 85 and the internal system bus 7, and data transfer from the orthogonal transform circuit 85 to the memory cell mat (memory internal bus) 77. In some cases, wait control of a bus request for requesting data transfer between the internal system bus 7 and the orthogonal memory 90a or 90b is performed.

  The memory cell mat address calculation unit 95 calculates the address of the memory cell mat to be transferred based on the information stored in the entry position register 94a and the bit position register 94b during data transfer to the memory cell mat. The data is transferred to the main arithmetic circuit (transferred to the row decoder 74 and the column decoder 78 shown in FIG. 5).

  In the system bus orthogonal memory I / F 91, valid data (entry data) of data transferred via the internal system bus 7 is not limited to L bits, and data in units of entries having an m-bit width is transferred. The bit width of entry data transferred during one bus access is referred to as an effective bit width. Further, data having an effective bit width is hereinafter referred to as unit data. Further, both the effective bit width and the effective bit width information for specifying the effective bit width are indicated by a symbol m.

  The effective bit width m of the data transferred on the internal system bus 7 is stored in the effective bit width register 94e. According to the effective bit width information m stored in the effective bit width register 94e, the system bus orthogonal memory I / F 91, when a plurality of data is transferred in parallel via the internal system bus 7, in the orthogonal memories 90a and 90b. The data transfer path is set so that each unit data is stored in a different entry.

  On the other hand, memory cell mat orthogonal memory I / F 92 receives data bits of K entries read in parallel from orthogonal memories 90a and 90b via internal data bus 98 during data transfer to memory cell mat 30. Transfer is performed via the internal memory bus 77. When the bit width J of the internal memory bus 77 is larger than the number K of entries included in the orthogonal memories 90a and 90b, the memory cell mat orthogonal memory I / F 92 stores the valid data on the internal memory bus 77. Selects a bus line to be transferred, and transfers an extension bit (invalid data bit) on an unselected bus line.

  In the system bus orthogonal memory I / F 91, a data transfer path is set, and in the orthogonal memories 90a and 90b according to the set path, an entry selection sequence (entry write / read sequence) according to the effective bit width of the unit data. To change. Thus, even when the bit width of data transferred via internal system bus 7 is different from 32 bits, 16 bits, and 8 bits, for example, in system bus orthogonal memory I / F 91 according to each word configuration A data transfer path is set, unit data is transferred according to the set path, and data is transferred using all bus lines of the internal system bus 7 by adjusting the entry selection mode in the orthogonal memory. And efficient data transfer can be realized.

  FIG. 8 is a diagram showing an example of the configuration of memory cells included in orthogonal memories 90a and 90b shown in FIG. The memory cells included in the orthogonal memories 90a and 90b are constituted by dual port SRAM cells. In FIG. 8, the orthogonal memory cell includes cross-coupled load P-channel MOS PQ1 and PQ2, and cross-coupled drive N-channel MOS transistors NQ1 and NQ2 for data storage. Similar to a normal SRAM cell, this orthogonal memory cell includes an inverter latch (flip-flop element) as a data storage element, and the flip-flop element stores complementary data in storage nodes SN1 and SN2.

  The orthogonal memory cell further includes N channel MOS transistors NQA1 and NQA2 coupling storage nodes SN1 and SN2 to bit lines BLA and / BLA, respectively, in response to a signal potential on word line WLA, and a signal potential on word line WLB. In response, N channel MOS transistors NQB1 and NQB2 coupling storage nodes SN1 and SN2 to bit lines BLB and / BLB are included.

  Word lines WLA and WLB are arranged orthogonally, bit lines BLA and / BLA are arranged orthogonally to bit lines BLB and BLB.

  A first port (transistors NQA1, NQA2) composed of the word line WLA and the bit lines BLA and / BLA and a second port (transistors NQB1, NQB2) composed of the word line WLB and the bit lines BLB and / BLB Each is coupled to a separate orthogonal memory I / F. For example, the first port is used as a port for interfacing with the internal system bus, and the second port is used as a port for accessing the memory bus. Thereby, row and column conversion can be performed in the orthogonal memory, data access can be performed, and the data array can be converted.

  FIG. 9 is a flowchart showing the operation of the orthogonal transform circuit shown in FIG. 7 at the time of data transfer from the internal system bus 7 to the memory cell mat 30. The operation of the orthogonal transform circuit 85 shown in FIG. 7 will be described below with reference to FIG. However, in the following description, data is first stored in the orthogonal memory 90a, the stored data is transferred to the memory cell mat, and the orthogonal memory is transferred in parallel with the data transfer from the orthogonal memory 90a to the memory cell mat. A data transfer operation when data is stored in 90b will be described.

Phase 1:
At the start of data transfer, information indicating the first bit position or entry position to be written is first sent from the host CPU or DMA controller or from the controller in the main arithmetic circuit to the bit position register 94b and the entry position register 94a, respectively. Set. This bit position corresponds to the word line address of the memory cell mat of the main arithmetic circuit, and the entry position corresponds to the bit line address of the memory cell mat 30. In the bit position register 94b, bit position information about data held in the orthogonal memory 90a is stored, and in the B register of the bit position register 94b, hit position information of data held in the orthogonal memory 90b is stored. . Therefore, the number of entries K of these orthogonal memories 90a and 90b is smaller than the number of entries M of the memory cell mat 30, and between the number of entries M of the memory cell mat 30 and the number of entries K of these orthogonal memories 90a and 90b. , M = 2 · K · I (I is an arbitrary integer), the bit position information for the transfer data of the orthogonal memory 90b is a bit obtained by incrementing the bit position information for the orthogonal memory 90a by K. Stored in the B register of the position register 94b.

  In addition, information indicating the bit width (effective bit width) m of unit data (data in memory cell mat entry unit) transferred on the internal system bus 7 is stored in the effective bit width register 94a of the control register group 94. The In this case, information indicating the number of unit data transferred in parallel on the internal system bus 7 may be stored. Further, a bit indicating data transfer from the internal system bus 7 to the memory cell mat 30, that is, writing is set in the read / write direction register 94d.

  Thereafter, an enable bit (control bit) is set in the enable register 94c to enable the orthogonal transform circuit 85. By asserting the enable bit of the enable register 94c, the count values of the counters 93a and 93b included in the internal register group 93 are initialized to 0 (step ST1).

Phase 2:
Transfer data is written from the system bus I / F 24 to the orthogonal memory 90a via the system bus orthogonal memory I / F 91. The write data to the orthogonal memory 90a includes one or a plurality of entry unit data (unit data) DTE according to the effective bit width information m, and sequentially in the X direction according to the effective bit width information m. The unit data is stored in the entry of the orthogonal memory 90a. When the transfer data includes a plurality of entry unit data (hereinafter referred to as unit data) DTE, the unit data sequentially transferred in parallel is stored in different entries of the orthogonal memory 90a.

  Each time data is written to the orthogonal memory 90a (every data transferred from the system bus 7 is written), the count value of the system bus access number counter register 93a is incremented (step ST2). The increment unit of the system bus access number counter register 93a is set according to the effective bit width information m. For example, when the internal system bus 7 is a 32-bit bus and the unit data DTE for each entry is 8 bits, four entries of data are written to the orthogonal memory by one system bus access. The count value of the access number counter 93a is incremented by 4. The increment amount of the count value of this system bus access number counter can be generally expressed by L / m.

Phase 3:
Until the stored contents of the orthogonal memory 90a become full (full state), that is, until the count value of the system bus access number counter register 93a reaches the number K of entries in the orthogonal memory 90a, the system bus orthogonal memory I / F 91 The data is written via (step ST3). While the transfer data from the internal system bus 7 is written to the orthogonal memory 90a, the orthogonal memory 90b is in a wait state (step ST11).

Phase 4:
When K unit data DTE are written to the orthogonal memory 90a from the internal system bus 7 via the system bus I / F 24 and the system bus orthogonal memory I / F 91, the count value of the system bus access number counter 93a is the initial value. Of 0. By returning the system bus access number counter 93a to the initial value, the orthogonal memory 90b is enabled, and data can be written to the orthogonal memory 90b. In parallel with this, the orthogonal memory 90a is set to the read mode, and is ready to transfer data to the memory cell mat 30 (step ST4).

Phase 5:
By switching between the orthogonal memories 90a and 90b, the system bus orthogonal memory I / F 91 sequentially stores the data supplied from the internal system bus 7 via the system bus I / F 24 in the orthogonal memory 90b. The count value of system bus access counter 93a is incremented in the same manner as when data is written to orthogonal memory 90a (step ST12).

  In parallel with the writing to the orthogonal memory 90 b, the data DTA in the address unit aligned in the X direction is read through the memory cell mat orthogonal memory I / F 92, and in the main arithmetic circuit via the internal memory bus 77. To the input / output circuit 76 and stored in K entries of the memory cell mat 30.

  At the time of data transfer to the memory cell mat 30, the memory cell mat address calculation unit 95 stores the stored values of the A register of the entry position register 94a and the A register of the bit position register 94b and the stored value of the memory cell mat access count counter register 93b. Based on the value, the address of the memory cell mat 30 to be transferred is calculated, and the address (bit position and entry position address) for the memory cell mat is output in accordance with the data transmission from the memory cell mat orthogonal memory I / F 92. To do. Further, in accordance with the data transmission to the memory cell mat 30, the count value of the memory cell mat access frequency counter 93b is incremented under the control of the memory cell mat orthogonal memory I / F 92. The increment value of the count value of the memory cell mat access count counter 93b is incremented by 1 regardless of the value of the effective bit width information m (step ST5).

Phase 6:
The data stored in the orthogonal memory 90a is transferred to the memory cell mat 30, and in parallel with the data transfer to the memory cell mat 30, the internal system bus is used until the stored content becomes full in the orthogonal memory 90b. 7 is executed (steps ST6 and ST13).

  When the orthogonal memory 90b is full (when the count value of the system bus access count counter 93a reaches K) and when the orthogonal memory 90a is empty (empty) (the count value of the memory cell mat access count counter 93b is When the effective bit width m is reached, it is determined whether all necessary data has been transferred from the system bus 7 (step ST7).

  When all the write data for the memory cell mat has not yet been transferred from internal system bus 7, orthogonal memory 90a is set to the write mode, and orthogonal memory 90b is set to the read mode indicating data reading (counter). According to the count up of 93a and 93b).

  Further, the count values of the system bus access frequency counter 93a and the memory cell mat access frequency counter 93b are initialized to 0 (step ST8).

Phase 7:
If transfer data remains, the stored value of the A register of the entry position register 94a is incremented by 2 · K, or is set to a value obtained by adding 1 to the stored value of the B register of the entry position register 94a. Is done. The stored value of the A register of the bit position register 94b is incremented by L or set to a value obtained by adding 1 to the value of the B register (step ST9). Even when the effective bit width is m bits and smaller than L bits, the L bit width is secured as a unit data storage area in the memory cell mat.

  In the orthogonal memory 90a, the process from step ST2 is executed again, and data transferred from the internal system bus 7 is sequentially stored from the head position of the orthogonal memory 90a.

  On the other hand, in orthogonal memory 90b, the read mode is set, and the stored data is transferred to memory cell mat 30 (step ST14). At the time of data transfer from the orthogonal memory 90b to the memory cell, the same processing as the data transfer from the orthogonal memory 90a to the memory cell mat 30 is performed, and the data is transferred until the data held in the orthogonal memory 90b becomes empty. (Step ST15). When all the data stored in the orthogonal memory 90b is transferred and the transfer of necessary data is completed, the processing of the orthogonal memory 90b is completed.

  On the other hand, if necessary transfer data remains, the entry position information of the B register of the entry position register 94a is updated 2 · K again, and the stored value of the B register of the bit position register 94b is updated to L again. Is done.

  The determination of the storage status of the orthogonal memories 90a and 90b at the time of transfer is made when the count value of the memory cell mat access count counter 93b becomes equal to the effective bit width m, all the stored data in the orthogonal memory 90a or 90b is stored in the memory cell mat 30. Is determined to have been transferred. When the stored value of the entry position register 94a exceeds the entry M of the memory cell mat, the stored values of the A register and B register of the bit position register 94b are incremented by 1, and the word line at the next position is transferred to the memory cell. The selected state is set in the mat 30 and the stored values of the A register and the B register of the entry position register 94a are set to 0 and K, respectively.

  In the orthogonal memory 90b, the processing shifts from step ST17 to step ST4 and waits for the next transfer data.

  The operations from phase 2 to phase 7 described above are repeatedly executed to write / read data to / from the orthogonal memories 90a and 90b in an interleaved manner to transfer the data. When it is determined that the transfer of all necessary data has been completed (the transfer request from the system bus I / F 24 is inverted by deassertion), the data transfer is completed and the enable bit of the enable register 94c is deasserted. Is done. Thereby, the unit data DTE is transferred using all the bus lines of the internal system bus 7 regardless of the effective bit width, and is converted into bit serial and word parallel data in the orthogonal conversion circuit 85 to be converted into the memory cell mat 30. Can be transferred to.

  FIG. 10 is a diagram schematically showing a data flow for transferring data from the SDRAM 4 to the memory cell mat 30 via the internal system bus 7. In FIG. 10, the bit width L of the internal system bus is 32 bits, the effective bit width information m indicates 8 bits, and four pieces of entry unit data, that is, unit data DTE are transferred in parallel via the system bus. Shows the flow of data.

  The SDRAM 4 stores 8-bit data A0... A39. In one access, four data aligned in the horizontal direction in FIG. 10 are read from the SDRAM 4 in parallel. First, transfer data from the SDRAM 4 is stored in the orthogonal memory 90a. In the orthogonal memory 90a, the unit data DTE is stored in different entries according to the effective bit width information m. FIG. 10 shows a state in which data A0 to A31 are stored in K entries (32 bits each) in the orthogonal memory 90a. In this state, in the orthogonal memory 90a, the unit data is stored in all K entries, and the transfer data A32-A35 from the next SDRAM 4 is stored in the orthogonal memory 90b.

  In parallel with storing the transfer data (A32-A35) in the orthogonal memory 90B, data is sequentially output from the orthogonal memory 90a in entry parallel and bit serial. That is, the same digit bits of unit data A0-A31 are selected and transferred in parallel, and stored in the corresponding entries of memory cell mat 30, respectively. Therefore, when data is transferred from the orthogonal memory 90a to the memory cell mat 30, data is transferred from the orthogonal memory 90a to the memory cell mat 30 eight times, whereby the data A0 to A31 are respectively stored in the memory cell mat 30. Stored in different entries.

  Further, when K unit data DTE are stored in the orthogonal memory 90b, the orthogonal memory 90b is brought into a full state, and the data A32-A63 are transferred from the orthogonal memory 90b to the corresponding entry of the memory cell mat 30 in the entry parallel. And it is transferred and stored in a bit-serial manner. At the time of data transfer from the orthogonal memory 90b to the memory cell mat 30, data is transferred from the SDRAM 4 to the orthogonal memory 90a (when transfer data remains).

  As described above, in the system bus, data is transferred using the entire bus width L (32 bits), and when data is transferred from the orthogonal memory 90a to the memory cell mat 30, data is transferred from the SDRAM 4 to the orthogonal memory 90b. Is done. When the bit width (effective bit width) m of the unit data DTE is 8 bits and the bus width of the system bus is 32 bits, the number of data transfer cycles for the full state from the SDRAM 4 to the orthogonal memory 90a or 90b is 8 cycles. In addition, the cycle time required for data transfer from the orthogonal memory 90a or 90b to the memory cell mat 30 is 8 cycles. Therefore, efficient data transfer can be realized without causing an idle (idle) period in data transfer on the internal system bus. The memory cells of the orthogonal memories 90a and 90b and the memory cell mat 30 are high-speed SRAM cells, and transfer data between the orthogonal transformation circuit 85 and the memory cell mat 30 with sufficient time according to the clock cycle of the SDRAM 4. Can be performed.

  When data is transferred from the memory cell mat 30 to the system bus 7, a bit indicating data reading is set in the read / write direction register 49d, which is the reverse of the transfer operation when the write bit is set. Data flows in the direction. In the orthogonal memories 90a and 90b, although the write / read operation is the reverse of the description of the transfer operation described above, the same control is performed for address control, and data is transferred.

  FIG. 11 is a diagram more specifically showing a configuration of a portion related to data transfer of orthogonal transform circuit 85 shown in FIG. In FIG. 11, the orthogonal transform circuit 85 transfers the transfer direction according to the enable bit EN stored in the enable register 94c and the data transfer direction instruction bit (write / read instruction bit) R / W stored in the read / write direction register 94d. An access sequence control circuit that generates control signal TRD, sets the activation sequence of system bus access count counter 93a and memory cell mat access count counter 93b, and monitors the bus occupation status of internal memory bus 77 and internal data bus 96 100 and an H address generation circuit 102 for generating an H address HRA for selecting the word line WLH in the H direction according to the count value from the system bus access number counter 93a and the effective bit width information m stored in the effective bit width register 94e. When Including V address generation circuit 104 for generating a V address VRA for selecting the V direction word line WLV for memory cell mat transfer accordance with the count value of the memory cell mat access number counter 93 b.

  When the enable bit EN of the enable register 94c is asserted, the access sequence control circuit 100 determines the system bus access count counter 93a and the memory cell mat access count according to the transfer direction instruction bit R / W stored in the read / write direction register 94d. In addition to setting which of the counters 93b is to be activated first, the orthogonal memories 90a and 90b generate a transfer direction control signal TRD for controlling which direction data transfer is to be executed first.

  An H (horizontal) direction word line WLH is arranged corresponding to each entry in the orthogonal memories 90a and 90b, and a V (vertical) direction word line WLV is arranged commonly to a plurality of entries. At the time of data transfer with the internal system bus 77, the horizontal word line WLH is selected, and at the time of data transfer with the memory cell mat 30, the vertical direction word line WLV is selected.

  The H address generation circuit 102 uses the count value of the system bus access frequency counter 93a as an initial address, and the number of times determined by the effective width bit information m from the initial value according to the effective bit width information m from the effective bit width register 94e, that is, The H address designating the horizontal word line (entry) is incremented L / m times. One unit data is stored for each selected entry.

  Since the orthogonal memories 90a and 90b have the same configuration, FIG. 11 representatively shows the configuration of the orthogonal memory 90a. The orthogonal memory 90 a includes an orthogonal memory cell array 110 in which orthogonal memory cells are arranged in a matrix, an H word line selection circuit 111 that selects a horizontal word line WLH of the orthogonal memory cell array 110, and a vertical direction of the orthogonal memory cell array 110. Data transfer between the V word line selection circuit 112 that selects the word line WLV and the orthogonal memory cells on the horizontal word line WLH selected in accordance with the effective bit width information m and the internal data bus 97 is effective bit width. H input / output circuit 113 executed in units, V input / output circuit 114 for transferring data between internal data bus 98 and memory cells connected to selected vertical word line WLV, H address HRA, H word line selection circuit 111 and H input / output circuit according to effective bit width information m and transfer direction control signal TRD And H control circuit 115 for controlling the operation of 13, according to V address VRA and the transfer direction control signal TRD, including V system control circuit 116 for controlling the operation of the V word line selection circuit 112 and the V output circuit 114.

  The H-system control circuit 115 controls the input / output of data in the effective bit width unit in the H input / output circuit 113 according to the effective bit width information m, and controls the H word line selection circuit 111 once. The horizontal word line WLH is driven to the selected state a number of times corresponding to the number of unit data DTE included in the bus access cycle.

  The V-system control circuit 112 controls the V word line selection circuit 112 to select the vertical direction word line by the number of times indicated by the effective bit width information m. The V input / output circuit 114 transfers data to / from memory cells connected to the selected vertical word line WLV under the control of the V-system control circuit 116.

  These H system control circuit 115 and V system control circuit 116 are activated according to the most significant bits of addresses HRA and VRA of H address generation circuit 102 and V address generation circuit 104, respectively. That is, the most significant bits of H address HRA and V address VRA are used as activation signals for orthogonal memories 90a and 90b. Therefore, the H address generation circuit 102 and the V address generation circuit 104 respectively select the orthogonal memory corresponding to the chip selection signal at the most significant bit position of the count values of the system bus access number counter 93a and the memory cell mat access number counter 93b. A bit is added to generate an H address HRA and a V address VRA.

  Further, these H-system control circuit 115 and V-system control circuit 116 control their operations when the respective address signals HRA and VRA reach the final values, and hand over the next operation control right to the other party. That is, when the H word line selection circuit 111 selects the final horizontal word line and completes the transfer of the unit data, the H system control circuit 115 stops its own operation, and then the V system control circuit 116 is enabled. As a result, in the orthogonal memories 90a and 90b, it is possible to prevent a conflict between writing and reading with respect to data at the same position.

  The occupied state of the buses of the orthogonal memories 90a and 90b is also monitored by the access sequence control circuit 100 based on a count-up signal indicating whether the counters 93a and 93b are initialized. Access sequence control circuit 100 stops the next counting operation until both counters 93a and 93b complete counting up. This prevents one of the orthogonal memories 90a and 90b from starting another horizontal transfer of data when one is performing data transfer (horizontal data transfer) with the system bus. .

  In the orthogonal memories 90a and 90b, the H-direction control circuit 115 and the V-system control circuit 116 control the handshake mode, and after the necessary number of word lines are selected internally, the horizontal direction and the vertical direction The word line selection operation is switched.

  The system bus orthogonal memory I / F 91 includes a path control circuit 120 that generates a path control signal according to the address timing control signal HRAF output from the H address generation circuit 102 and the effective bit width information m from the effective bit width register 94e. A path setting circuit 122 that sets a data transfer path between the data buses 96 and 97 in accordance with a path control signal from the path control circuit 120 and transfers data according to the set path is included.

  The address timing control signal HRAF generated from the H address generation circuit 102 is a signal activated at a timing earlier than the change of the H address HRA. The path control circuit 120 sets a data transfer path in the path setting circuit 122 according to the address timing control signal HRAF. Thus, in the orthogonal memories 90a and 90b, when the horizontal word line is selected, the connection path between the H input / output circuit 113 and the data bus 96 is set at an earlier timing than the word line selection.

  K-bit internal data bus 98 is coupled to internal memory bus 77 via memory cell mat orthogonal memory I / F 92. When bit widths K and J of internal data bus 98 and internal memory bus 77 are equal, memory cell mat orthogonal memory I / F 92 connects internal data bus 98 to internal memory bus 77 and performs data transfer. Functions as a circuit for adjusting timing.

  In accordance with transfer direction control signal TRD from access sequence control circuit 100, it is determined which of input circuit (write circuit) and output circuit (read circuit) is activated in H input / output circuit 113 and V input / output circuit 114. The

  12 schematically shows a configuration of path setting circuit 122 and H input / output circuit 113 of orthogonal memories 90a and 90b included in system bus orthogonal memory I / F shown in FIG. In FIG. 12, since the H input / output circuit 113 of the orthogonal memories 90a and 90b has the same configuration, the H input / output circuit 113 of one orthogonal memory is representatively shown.

  In FIG. 12, the system bus is 32 bits wide, the minimum effective bit width m is 8 bits, and the bit width candidates for transfer unit data are 8 bits, 16 bits, and 32 bits. . Depending on the relationship between the valid bit width information m and the bus width L of the internal system bus, this configuration is appropriately changed or expanded.

  Internal data bus 96 includes sub-data buses 96a-96d each having an 8-bit width, and internal data bus 97 also includes sub-data buses 97a-97d each having an 8-bit width. The bit width of the data buses of the internal data buses 96 and 97 is determined by the minimum value of the effective bit width m specified by the effective bit width information m.

  H input / output circuit 113 includes read / write circuits 113a-113d provided for sub data buses 97a-97d. The read / write circuit 113a is activated according to the activation signal ENA, and the read / write circuit 113b is activated according to the activation signal 16/32 · ENA. The activation signal 16/32 · ENA is activated in parallel with the activation signal ENA when the effective bit width information m indicates 16 bits or 32 bits. Read / write circuits 113c and 113d are activated in accordance with activation signal 32 · ENA, respectively. The activation signal 32 • ENA is activated in parallel with the activation signal ENA when the effective bit width information m indicates 32 bits. These activation signals are supplied from the H-system control circuit 115 shown in FIG.

  In these read / write circuits 113a to 113d, which one of the read circuit constituted by, for example, a sense amplifier and the write circuit constituted by, for example, a write driver is activated is shown in FIG. Is determined in accordance with the transfer direction control signal TRD.

  In this H input / output circuit 113, read / write circuits 113a-113d can be selectively activated in units of 8 bits, and input / output of 8-bit data and input / output of 16-bit data to / from the orthogonal memory cell array 110. And 32-bit data can be input / output. When transferring 8-bit data and 16-bit data, unit data transferred in one bus access cycle is stored at the same position in different entries.

  The path setting circuit 122 is configured to connect the sub data buses 96a to 96d to the sub data buses 97a to 97d according to the 32-bit data transfer control signal m32 and the 16-bit data transfer control signals m16a and m16b, respectively. 16-bit data transfer unit 122b connecting sub-data buses 96a and 96b to sub-data buses 97a and 97b and coupling sub-data buses 96c and 96d to sub-data buses 97a and 97b, respectively, and 8-bit data transfer control signal m8a In accordance with -m8d, an 8-bit data transfer unit 122c that sequentially couples sub data buses 96a-96d to sub data bus 97a is included.

  32-bit data transfer unit 122a includes 8-bit transfer gates TX1-TX4 that are provided for sub-data buses 96a-96d and are selectively turned on in accordance with 32-bit data transfer control signal m32. This 32-bit data transfer control signal m32 is activated once in one system bus access cycle.

  16-bit data transfer unit 122b, according to 16-bit data transfer control signal m16a, 8-bit transfer gates TX5 and TX6 coupling sub-data buses 96a and 96b to sub-data buses 97a and 97b, respectively, and 16-bit data transfer control signal According to m16b, sub-data buses 96c and 96d include 8-bit transfer gates TX7 and TX8 that couple to sub-data buses 97a and 97b, respectively. These 16-bit transfer control signals m16a and m16b are sequentially activated once in one system bus access cycle.

  The 8-bit data transfer unit 122c connects the sub-data bus 96a to the sub-data bus 97a according to the 8-bit data transfer control signal m8a, and the sub-data bus 96b to the sub-data according to the 8-bit data transfer control signal m8b. An 8-bit transfer gate TX10 coupled to the bus 97a, an 8-bit transfer control signal m8c, an 8-bit transfer gate TX11 connected to the sub-data bus 97a of the sub-data bus 96c, and an 8-bit transfer control signal m8d. 96d includes an 8-bit transfer gate TX12 that couples to sub-data bus 97a. These 8-bit data transfer control signals m8a-m8d are sequentially activated once in one system bus access cycle.

  These data transfer control signals m32, m16a, m16b and m8a-8d are generated from the path control circuit 120 shown in FIG.

  Therefore, when effective bit width information m indicates 32 bits, sub data buses 96a-96d of internal data bus 96 are coupled to sub data buses 97a-97d, respectively, and 8-bit data is transmitted to each. Read / write circuits 113a-113d are all activated. Therefore, when horizontal word line WLH is selected in orthogonal memory cell array 110, data A is transferred (written or read) in parallel to one entry of 32-bit memory cells connected to horizontal word line WLH. ) Is performed.

  When valid bit width information m indicates 16 bits, first, sub data buses 96a and 96b are connected to sub data buses 97a and 97b, respectively. Read / write circuits 113a and 113b are activated in parallel, while read / write circuits 113c and 113d are in an inactive state. Therefore, in the data write mode, 16-bit data transmitted to sub data buses 97a and 97b is stored in orthogonal memory cell array 110. After this data storage, transfer control signal m16b is then activated, and sub data buses 96c and 96d are coupled to sub data buses 97a and 97b. At this time, another horizontal word line is selected in the orthogonal memory cell array 110, and the read / write circuits 113a and 113b write the transfer data to the memory cells connected to the selected horizontal word line. Therefore, 16-bit data A and B are sequentially stored in different entries in direct memory cell array 10 (data is read in the read mode).

  When the effective bit width information m indicates 8 bits, first, the sub data bus 96a is coupled to the sub data 97a by the transfer control signal m8a. At this time, the read / write circuit 113a is activated, and the read / write circuits 113b to 113d are maintained in an inactive state. In the orthogonal memory cell array 110, when the horizontal word line is driven to the selected state, the first 8-bit data A is transferred to and from the selected memory cell. Thereafter, when transfer control signals m8b-m8d are sequentially activated, sub data buses 96b-96d are sequentially coupled to sub data bus 97a. In accordance with the connection of the sub data buses, different horizontal word lines are sequentially selected in the orthogonal memory cell array 110, and 8-bit data B, C, and D are sequentially transferred to and from memory cells connected to different horizontal word lines. Transferred.

  In the SDRAM, data of a plurality of entries is transferred by one bus access, and unit data is sequentially stored in different entries in the orthogonal transform circuit 85. In this case, in the orthogonal transform circuit 85, L / m horizontal word line selection operations are required. However, the orthogonal memory in the orthogonal transform circuit is an SRAM, and can select an orthogonal memory cell and perform internal data transfer (write / read) at a high speed, and unit data for each entry with an external SDRAM. Compared to the sequential transfer, it is possible to realize high-speed data transfer.

  In this system bus orthogonal memory I / F 91, even if a buffer memory is provided to buffer the difference between the transfer speed of the memory cell data in the multiple selection of the horizontal word line and the transfer speed with the external SDRAM. Good. For example, when the system bus is a 32-bit bus and the unit data is 8 bits, it is necessary to drive the horizontal word line to the selected state four times in the orthogonal transformation circuit. By providing up to four stages of FIFO type 23-bit width buffer memory, even when one access cycle time of the orthogonal memory and one data transfer cycle (bus access cycle) time of the system bus are the same, this buffer memory should be used. Thus, it is possible to select different entries in the orthogonal transform circuit a plurality of times and transfer data without affecting the system bus transfer cycle.

[Example of change]
FIGS. 13A and 13B are diagrams schematically showing a configuration of a main part of orthogonal transform circuit 85 according to a modification of the first embodiment of the present invention. In FIG. 13A, a bus width conversion circuit 130 is provided in a memory cell mat orthogonal memory I / F 92 having an interface between the orthogonal memories 90 a and 90 b and the internal memory bus 77. The bus width conversion circuit 130 switches the connection path between the internal data bus 98 and the internal memory bus 77 according to the count value CNT from the memory cell mat access frequency counter 93b and the effective bit width information m. The internal data bus 98 is K bits, the bit width of the internal memory bus 77 is J, and the bit width J of the internal memory bus 77 is larger than the bit width K of the internal data bus 98.

  FIG. 13B is a diagram more specifically showing the configuration of bus width conversion circuit 130 shown in FIG. In FIG. 13B, internal memory bus 77 is divided into sub-buses 77S0-77Sk each having a K-bit bus width. Corresponding to each of these sub-buses 77S0 to 77Sk, bus drive circuits BDK0 to BDKk each having a K-bit width are provided. Bus drive circuits BDK0-BDKk are commonly coupled to internal data bus 98. In order to control the activation / inactivation of these bus drive circuits BDK0 to BDKk, a connection control circuit 132 is provided. The connection control circuit 132 activates the bus driver activation signals ACT0 to ACTk and the complementary bus driver in accordance with the count value CNT and effective bit width information m from the memory cell mat access frequency counter 93b shown in FIG. Signals ZACT0-ZACTk are generated.

  Since bus drive circuits BDK0 to BDKk have the same configuration and only different activation signals are applied, the same reference numerals are assigned to the components in bus drive circuits BDK0 to BDKk.

  Each of bus drive circuits BDK0-BDKk is activated when a corresponding bus driver activation signal ACT0-ACTk is activated, and is a bus driver for transferring data between internal data bus 98 and corresponding sub data buses 77S0-77Sk. 133, resistance element 134 coupled to corresponding sub data buses 77S0-77Sk, and selectively conductive according to corresponding complementary bus driver activation signals ZACT0-ZACTk, coupling corresponding resistance element 134 to the ground node. A switching element 135 is included.

  A series body of resistance element 134 and switching element 135 couples each bus line of corresponding sub-bus 77S0-77Sk to the ground node when switching element 135 is conductive.

  The connection control circuit 132 sequentially activates the activation signals ACT0 to ACTk every time the count value CNT of the memory cell mat access count counter matches the valid bit width information m. When bus driver 133 is activated, corresponding switching element 135 is in a non-conductive state, and valid data is transferred when data is transferred from internal data bus 98 to corresponding sub data buses 77S0-77Sk. In the non-selected sub data bus, switching element 135 is conductive and is coupled to the ground node via resistance element 134.

  FIG. 14 is a diagram schematically showing a state of data transfer in the internal memory bus 77 by the bus width conversion circuit 130 shown in FIGS. 13 (A) and 13 (B). In FIG. 14, valid data is transferred to the sub-bus 77Si, and data “0” is transferred to the remaining sub-buses 77S0 ... 77S (i-1), 77S (i + 1) ... 77Sk. Thus, when data is transferred between the orthogonal memories 90a and 90b and the memory cell mat, even when the internal data bus 98 and the internal memory bus 77 have different bus widths, the bus width is converted and K-bit valid data is transferred. However, it can be stored in the corresponding entry in the memory cell mat.

  By configuring the bus driver 133 as a bidirectional bus driver, data can be transferred from the memory cell mat to the orthogonal memory in units of K bits even when data is transferred from the memory cell mat to the orthogonal memory. However, an activation signal for the bus driver activated first is set according to the entry position information.

  As described above, according to the first embodiment of the present invention, at the time of data transfer between the internal system bus and the memory cell mat, an orthogonal transformation circuit is selected according to the bit width of data in entry units of the memory cell mat. The data is stored in one or more entries of the orthogonal memory and is accurately converted into an entry parallel and bit serial data string in the orthogonal memory regardless of the bit width of the unit data of the transfer data on the system bus. And vice versa. Therefore, even when the effective bit width of the transfer data is smaller than the bus width of the system bus, a plurality of unit data can be transferred in parallel during one system bus access, and the number of system bus accesses can be reduced. Can do.

  Compared with the case where the data transferred to the memory cell mat in one access cycle is transferred bit-serially and the transfer data is rearranged in the memory cell mat, the data transfer to and from the memory cell mat is performed. The number of cycles required can be reduced, the data transfer cycle time can be prevented from becoming a bottleneck for improving the processing capability, and high-speed processing can be realized.

[Embodiment 2]
FIG. 15 schematically shows a configuration of orthogonal transform circuit 85 according to the second embodiment of the present invention. Also in FIG. 15, since the orthogonal memories 90a and 90b have the same configuration, the configuration of the orthogonal memory 90a is representatively shown.

  The orthogonal transform circuit 85 shown in FIG. 15 differs from the orthogonal transform circuit according to the first embodiment shown in FIG. 11 in the following points.

  That is, in the orthogonal memory 90a, the orthogonal memory cell array 210 is divided into a plurality of memory blocks BKa-BKd along the entry extending direction. The number of divided blocks is determined according to the minimum bit width of the effective bit width information m, and each of the memory blocks BKa to BKd has a bit width equal to the minimum effective bit width.

  The H input / output circuit 213 includes input / output circuits provided corresponding to the memory blocks BK0 to BK3, and the activation / deactivation of each memory block is controlled according to the valid bit width information.

  The V word line selection circuit 212 for selecting the vertical word line VWL is enabled by the V-system control circuit 216, and each memory block unit according to the vertical word line address VRA and the vertical block address VBK from the V address generation circuit 204. Thus, the selection operation of the vertical word line VWL is selectively activated.

  V input / output circuit 214 selectively couples the global IO line provided for each of selected blocks BK0 to BL3 to internal data bus 198 in accordance with vertical block selection signal VDK. The internal data bus 198 has a bit width of K · K / m (min). Here, m (min) represents the minimum value of the effective bit width m.

  The V address generation circuit 204 generates a vertical word line address VRA and a vertical block address VBK according to the count value CNT from the memory cell mat access frequency counter 93b and the effective bit width information m from the effective bit width register 94e.

  The system bus orthogonal memory I / F 222 generates a control signal for establishing a connection path of the path setting circuit 222 according to the address timing control signal HRAF from the H address generation circuit 102 and the effective bit width information m. The path setting circuit 222 dynamically switches the connection path between the internal data bus 97 and the internal data bus 96 under the control of the path control circuit 220. When writing data, for example, when the bit width K of the data bus 96 is 32 bits and the effective bit width information m indicates 8-bit data, 8-bit unit data is sequentially stored in the memory block BK0 in the orthogonal memory cell array 210. After that, the unit data transferred to the next memory block BK1 is sequentially written. When the data writing to the block BK3 is finally completed, it is determined that the orthogonal memory 90a is full, and the V word line selection circuit 212 selects the vertical word line VWL. . In this case, when the effective bit width information m indicates 8-bit information, the vertical word line at the same position in each of the memory blocks BK0 to BK3 so as to read the data bits from the memory blocks BK0 to BK3. VWL is driven to the selected state.

  In the memory cell mat orthogonal memory I / F 192, the number of bus lines used for the internal data bus 198 differs depending on the bit width indicated by the effective bit width information m. A sub bus for transferring valid data in data bus 198 is coupled to internal memory bus 77.

  The other configuration of the orthogonal transform circuit 85 shown in FIG. 15 is the same as that of the orthogonal transform circuit shown in FIG. 11, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  FIG. 16 is a diagram more specifically showing the configuration of orthogonal memories 90a and 90b and system bus orthogonal memory I / F 91 shown in FIG. Since the orthogonal memories 90a and 90b have the same configuration, FIG. 16 representatively shows the configuration of the orthogonal memory 90a.

  In the system bus orthogonal memory I / F 91, the path control circuit 220 includes the sub data buses 96a to 96d of the internal data bus 96 and the sub data bus 97a of the internal data bus 97 according to the effective bit width information m and the address timing control signal HRAF. A control signal for setting a connection path of −97d is generated.

  The path setting circuit 222 includes a switch matrix, and sets a connection path between the sub data buses 96a to 96d and the sub data buses 97a to 97d according to a path control signal from the path control circuit 220.

  In the orthogonal memory 90a, the H input / output circuit 213 includes read / write circuits 213a-213d provided corresponding to the memory blocks BKa-BKd, respectively. These read / write circuits 213a to 213d are activated in units of 8 bits, 16 bits, and 32 bits according to the effective bit width information m (the effective bit width information m is 8 bits, 16 bits, and 32 bits). When specifying bits).

  Corresponding to each of memory blocks BKa-BKd, local input / output circuits LIOKa-LIOKd are provided. These local input / output circuits LIOKa to LIOKd transfer data to and from V input / output circuit 214 via internal global data buses VIOa to VIOD, respectively. Each of these global data buses VIOa to VIOd has a K-bit width (for example, a 32-bit width), and transfers data in parallel with all entries of the corresponding memory block.

  In V input / output circuit 214, main input / output circuits 214a-214d are provided corresponding to each of these global data buses VIOa-VIod, and main input / output circuits 214a-214d and sub data buses of internal data bus 198 are provided. A path switching circuit 214e for setting a connection path between 198a and 198d is provided. The path switching circuit 214e establishes a connection path between the main input / output circuits 214a to 214d and the sub data buses 198a to 198d according to the effective bit width information m.

  The main input / output circuits 214a to 214d are selectively activated according to the vertical block address VBK and transfer 32-bit data when activated.

  V word line selection circuit 212 includes V decode / word line drivers 212a to 212d provided corresponding to memory blocks BKa to BKd, respectively. These V decode / word line drivers 212a-212d select vertical word lines WLV according to vertical block address VBK and word line address VRA from V address generation circuit 204 shown in FIG.

  The vertical block address VBK is selectively degenerated according to the effective bit width information m, and the selection of the vertical word line WLV is performed in one memory block unit, two memory block units, or four memory block units. Therefore, V decode / word line drivers 212a-212d are activated when vertical block address VBK designates a corresponding memory block, and execute a word line selection operation according to vertical word line address VRA.

  An H word line selection circuit 111 is provided in common to these memory blocks BKa-BKd, and a horizontal word line WLH provided in common to these memory blocks BKa-BKd is driven to a selected state in accordance with a horizontal word line address HRA. To do. However, H word line selection circuit 111 is also divided into local H word line selection circuits provided corresponding to memory blocks BKa to BKd, and the horizontal word line is driven to the selected state in units of memory blocks. May be used.

  FIGS. 17A to 17C are diagrams schematically showing an operation at the time of storing 8-bit data from the internal system bus in the orthogonal transformation circuit shown in FIGS. 15 and 16. Hereinafter, referring to FIGS. 15, 16 and 17, data from the system bus to the orthogonal memory when the number of entries K in the orthogonal memories 90a and 90b is 32 bits and the effective bit width information m indicates 8 bits. The transfer operation will be described.

  The path setting circuit 222 shown in FIG. 16 sequentially couples the sub data buses 96a to 96d to the sub data bus 97a in accordance with a control signal from the path control circuit 220. In the H input / output circuit 213, the read / write circuit 213a is activated under the control of the H-system control circuit 215 shown in FIG. 15, and the H word line selection circuit 111 selects the horizontal word line WLH four times. Then, different horizontal word lines are driven to the selected state. Thereby, as shown in FIG. 17A, 8-bit data A0 to A3 are sequentially stored in the memory block BKa. This storing operation is the same as in the case of the first embodiment.

  When the 32-entry unit data DTE (A0-A31) is stored in the memory block BKa, the path control circuit 220 controls the path setting circuit 222 to sequentially connect the sub data buses 96a to 96d to the sub data buses 96a to 96d. Coupled to data bus 97b. The H-system control circuit 215 (see FIG. 15) activates the read / write circuit 213b provided for the memory block BKb according to each unit data. Also in this case, the H word line selection circuit 111 sequentially drives the horizontal word lines WLH from the head position to the selected state, and the next 32-entry 8-bit data A32-A63 is sequentially stored in the memory block BK1. (FIG. 17B).

  This operation is also performed on the read / write circuit 213c, and when 32 entries of 8-bit data are stored in the memory block BKc, the path setting circuit 222 ends up with these sub data buses 96a- 96d is sequentially coupled to the sub data bus 97d, and data writing to the memory block BKe is executed. Also in this case, the H word line selection circuit 111 sequentially activates the horizontal word line WLH four times for each bus access cycle from the head position, and the next 32 entries of 8-bit data A96 to A127 are sequentially stored. . Thereby, 128 pieces of 8-bit data A0 to A127 are stored in the memory blocks BKa to BKd. When the orthogonal memory 90a is full, the same operation is then performed in the orthogonal memory 90b.

  Therefore, in this data writing operation, each of read / write circuits 213a-213d sequentially shifts its activation state after writing data K times (32 times). Therefore, the path control circuit 220 sequentially shifts the connection destination of the path setting circuit 222 every time the address generated from the H address generation circuit 102 is generated 32 times.

  In the orthogonal memory 90a, when transfer data is stored, data in the vertical direction is then read out. In this case, the unit data is 8-bit data, and the vertical block address VBK is degenerated to designate all the memory blocks BKa to BKd in the selected state. This is realized, for example, by setting all the bits of the 2-bit vertical block address to the selected state according to the effective bit width information m. In this state, all the V decode / word line drivers 212a to 212d are activated in parallel, and the vertical word line WLV is selected according to the vertical word line address VRA. The local input / output circuits LIOKa to LIOKd are also block addresses. Activated in accordance with VBK, data is read, and 32-bit data is transferred to global data buses VIOa-VIOd, respectively.

  Next, the main input / output circuits 214a to 214b are all enabled in accordance with the vertical block address VBK, amplify the 32-bit data appearing on the global data buses VIOa to VIOD, and the amplified internal data to the path switching circuit 214e. Give to. The path switching circuit 214e transmits the output signals of the main input / output circuits 214a to 214d to the sub data buses 198a to 198d according to the effective bit width information m. Therefore, as shown in FIG. 18, 32-bit data read from each of memory blocks BK0 to BK3, that is, a total of 128-bit data is transmitted in parallel to sub data buses 198a to 198d.

  By driving the vertical word line WLV to the selected state eight times in each memory block and reading the data, all the data stored in the orthogonal memory 90a is entered via the internal memory bus in an entry parallel and bit serial manner. Transferred to memory cell mat.

  When data is written, horizontal word line WLH is selected also in the non-selected memory block. However, the orthogonal memory cell is an SRAM cell, and the memory cell data is simply read in the non-selected memory block, and the stored data is not destroyed.

  FIGS. 19A and 19B are diagrams schematically showing a data flow when 16-bit data is written to the orthogonal memory. At the time of writing the 16-bit data, the path setting circuit 222 shown in FIG. 16 switches the connection of the sub data buses in units of 16 bits. Specifically, path setting circuit 222 first connects sub data buses 96a and 96b to internal sub data buses 97a and 97b, respectively. In this state, read / write circuits 213a and 213b are activated, horizontal word line WLH is selected by H word line selection circuit 111, and 16-bit data B0 is stored in memory blocks BKa and BKb. Next, the path setting circuit 222 connects the sub data buses 96c and 96d to the internal sub data buses 97a and 97b, respectively, activates the read / write circuits 213a and 213B again, and the H word line selection circuit 111. The next horizontal word line is selected. As a result, the 16-bit data B1 is stored in the next entry in the memory blocks BKa and BKb.

  At the eighth system bus access, 16-bit data B30 and B31 are transferred in parallel. Also in this case, path setting circuit 222 connects sub data buses 96a and 96b to internal sub data buses 96a and 97b, activates read / write circuits 213a and 213b, and stores 16 bits in memory blocks BKa and BKb. Write data B30.

  Next, the sub data buses 96c and 96d are connected to the internal sub data buses 97a and 97b via the path setting circuit 222, respectively, and the H word line selection circuit 111 drives the last horizontal word line to the selected state. Write bit data B31.

  When this system bus access is performed eight times, the path control circuit 220 switches the connection mode of the path setting circuit 222. In this case, as shown in FIG. 19B, when 16-bit data B32 and B33 are first transferred in parallel via internal data bus 96, first, sub data buses 96a and 96b are connected to internal sub data buses. 97c and 97d are connected respectively. Read / write circuits 213c and 213d are activated, and 16-bit data B31 and B33 are sequentially stored in memory blocks BKc and BKd (H word line selection circuit 111 selects the different word lines).

  When the system bus access is performed eight times, the last 16-bit data B62 and B63 are transferred via the internal data bus 96, and the read / write circuits 213c and 213d are activated again, and the memory blocks BKc and BKd have 16 Bit data B62 and B63 are sequentially stored.

  Therefore, at the time of storing 16-bit data in the orthogonal memory, the H-system control circuit 215 shown in FIG. 15 is activated when the H address (horizontal word line address) HRA is generated 32 times. Switch the circuit. This switching simply counts the number of occurrences of horizontal word line address HRA, and writes data to memory blocks BKa and BKb, or writes data to memory blocks BKc and BKd based on the count value. This can be realized by determining.

  In the path switching in the path setting circuit 222, when the address timing control signal HRAF is generated 32 times, the connection path to the read / write circuit is switched in the switch matrix, and data is sequentially read in 16-bit units. This is realized by transferring data to and from the write circuit.

  When this orthogonal memory 90a or 90b is full, data writing to another orthogonal memory is executed in the same sequence.

  When data is transferred from the orthogonal memory 90a to the memory cell mat, the path switching sequence shown in FIGS. 20 and 21 is executed.

  First, as shown in FIG. 20, for example, the lower one bit of the vertical block address VBK is set in a degenerated state, and the memory blocks BKa and BKc are designated in a selected state. In this state, the vertical word line WLV at the same position is selected by the V decode / word line drivers 212a and 212c. Local input / output circuits LIOKa and LIOKc are activated to transfer 32-bit data via global data buses VIOa and VIOc, respectively. The main input / output circuits 214a and 214c are activated by the vertical block address VBK, while the main input / output circuits 214b and 214d are inactive. Therefore, 32-bit data is read in parallel from main input / output circuits 214a and 214c. In path switching circuit 214e, main input / output circuit 214a is coupled to sub data bus 198a and main input / output circuit 214c is coupled to sub data bus 198b according to effective bit width information m. As a result, 64-bit data B0-B63 are read in parallel on sub data buses 198a and 198b. This operation is repeated 8 times in memory blocks BKa and BKc, and the lower or upper 8 bits of 16-bit data B0-B63 are read and transferred.

  Next, when the 64-bit data read operation described above is repeated eight times, vertical block address BVK is set to a state designating memory blocks BKb and BKd. In this state, V decode / word line drivers 212b and 212d are activated, and 32-bit data is shown in parallel on global data lines VIOb and VIOd from memory blocks BKb and BKd, respectively.

  Main input / output circuits 214b and 214d are activated by block address VBK, while main input / output circuits 214a and 214c are inactive. The path switching circuit 214e couples the main input / output circuits 214b and 214d to the sub data buses 198a and 198b, respectively, after executing the above-described eight data transfers according to the effective bit width information m. Thereby, the remaining 8 bits of 16-bit data B0-B63 are sequentially read from memory blocks BKb and BKd. As a result, in the case of 16-bit data, 64-entry data is transferred in bit serial and entry parallel.

  Thereafter, the transfer path of 16-bit data B0-B63 is adjusted on the internal memory bus 77 by the memory cell orthogonal mat I / F 192 shown in FIG. 15, and the internal position at the position corresponding to the entry in the memory cell mat is adjusted. Data is transferred via the bus line of the memory bus.

  FIG. 22 is a diagram schematically showing a data storage state in the orthogonal memory at the time of transferring 32-bit data C (C0-C32). In the 32-bit data transfer, the path setting circuit 222 shown in FIG. 16 connects the sub data buses 96a to 96d to the internal sub data buses 97a to 97d, respectively. Read / write circuits 213a-213d are activated in parallel under the control of H-system control circuit 215 (see FIG. 15), and data is written in parallel to memory blocks BKa-BKd, respectively.

  The H word line selection circuit 211 drives one horizontal word line WLH to a selected state every bus access cycle. As a result, by performing bus access 32 times, 32-bit data C0-C32 is stored in memory blocks BKa-BKd in units of 8 bits.

  When data stored in the orthogonal memory cell array is read in the vertical direction and transferred to the memory cell mat, first, all the bits of the block address BVK are made valid, and the data of each memory block BKa-BKd is stored. Reading is performed. That is, as shown in FIG. 23, first, the memory block BKa is activated, and the corresponding V decode / word line driver 212a sequentially selects the vertical word lines WLV. The local input / output circuit LIOKa is in an active state, and 32-bit data is transferred onto the global data bus VIOa. In accordance with the vertical block address VBK, the main input / output circuit 214a is activated and the main input / output circuits 214b to 214d are inactive.

  In path switching circuit 214e, main input / output circuit 214a is coupled to internal sub data bus 198a, and 32-bit data from main input / output circuit 214a is transferred onto sub data bus 198a. In this memory block BKa, the vertical word line WLV is driven to the selected state eight times to read data, whereby the upper or lower 8-bit data of 32-bit data C0-C31 is sequentially read and transferred.

  After data reading is performed eight times in memory block BKa, vertical block address VBK is then switched, and memory block BKb is activated. Thus, V decode / word line driver 212b and local input / output circuit LIOKb shown in FIG. 16 are activated, and data is read by main input / output circuit 214b. In this case, the main input / output circuit 214b is coupled to the sub data bus 198a as indicated by numeral 2 in FIG. 23, and 32-bit data from the main input / output circuit 214b is transferred onto the internal sub data bus 198a. Is done.

  When the vertical word line is selected eight times in memory block BKb, vertical block address VBK is switched again, memory block BKc is activated, and 32-bit data is read onto global data bus VIOc. In this case, the main input / output circuit 214c is activated.

  In path switching circuit 214e, the output of main input / output circuit 214c is coupled to internal sub data bus 198a (indicated by numeral 3), and 32-bit data from memory block BKc is sequentially transferred to internal sub data bus 198a. .

  When data reading from memory block BKc is performed eight times, then, as shown in FIG. 24, memory block BKd is activated, the vertical word line is selected, and 32-bit data is transferred onto global data bus VIOd. Is read out. In this case, the main input / output circuit 214d is activated, and the main input / output circuits 214a-214c are inactive. The path switching circuit 214e couples the main input / output circuit 214d to the internal sub-bus 198a, and the remaining 8-bit data of each of these data C0 to C31 is sequentially read onto the internal sub-bus 198a.

  Accordingly, the memory blocks BKa-BKd are sequentially activated in units of blocks, and the main input / output circuits 214a-214d are also sequentially activated in units of blocks, so that 32-bit data can be converted into bits by using the internal sub data bus 198a. It can be transferred in a serial and entry parallel manner.

  When effective bit width information m indicates a 32-bit width, path switching circuit 214e sequentially connects main input / output circuits 214a-214d to internal sub data bus 198a every time data is transferred eight times. When the main input / output circuits 214a-214d are set to the output high impedance state when inactive, the path switching circuit 214e performs parallel operation of these main input / output circuits 214a-214d according to the effective bit width information m. It may be coupled to the internal sub data bus 198a.

  The V address generation circuit 204 (see FIG. 15) generates a vertical address (vertical word line address) VRA 32 times when the effective bit width information m indicates a 32-bit width, and also generates a vertical block address VBK. The value is switched every time eight vertical word line addresses are generated.

  FIG. 25 shows an example of the configuration of memory cell mat orthogonal memory I / F 192 shown in FIG. In FIG. 25, memory cell mat orthogonal memory I / F 192 includes a path shift circuit 192a that performs a connection path shift operation in a link form in accordance with effective bit width information m. The path shift circuit 192a sequentially switches transfer paths between the internal sub data buses 198a to 198d and the sub buses 77a to 77d of the internal memory bus 77. In other words, when effective bit width information m indicates 8-bit data, path shift circuit 192a does not perform a shift operation because effective data is transferred to sub data buses 198a to 198d. And internal memory sub-bus 77a-77d.

  When effective bit width information m indicates a 16-bit width, path shift circuit 192a receives data applied to sub data buses 198a and 198b, transfers the data onto internal memory sub buses 77a and 77b, When the data transfer is completed twice, path shift circuit 192a shifts the connection path by 64 bits to couple sub data buses 198a and 198b to internal memory sub buses 77c and 77d. When data transfer is performed 16 times again, path shift circuit 192a shifts the connection path by 64 bits, and couples sub data buses 198a and 198b to internal memory sub buses 77a and 77b, respectively. This operation is repeated every 16 data transfers to switch the transfer path. In the memory cell mat, in response to the entry being shifted after completion of unit data transfer, the bus line for transferring valid data is shifted in the internal memory bus. When invalid data is transferred on the memory internal data bus, the bit width expansion operation is executed as shown in the modification of the first embodiment.

  When the effective bit width information m indicates 32 bits, the path shift circuit 192a shifts the connection path of the sub-bus 198a by 32 bits for every 32 times of data transfer to the memory sub-buses 77a, 77b, 77c and 77d. Join sequentially. This connection path shift operation is performed every 32 data transfers.

  In the configuration shown in FIG. 25, the internal data bus 198 and the internal memory bus 77 have the same bit width. When the bit width of the internal memory bus 77 is larger than the bit width of the internal data bus 198, the path shift circuit 192a sends effective bit width information m to each sub-bus (32-bit width) of the internal memory bus 77. The connection is shifted for each bit width indicated by. In this case, fixed data (for example, “0”) is transferred on the internal memory bus to which valid data is not transferred in order to extend the bit width (see the modification of the first embodiment).

  In the case of transferring data from the memory cell mat to the system bus, the same operation control and data transfer path switching are executed although the data flow is reversed.

  As described above, when data is transferred using all the memory cells of the memory cell array of the orthogonal memory, and the effective data bit width is smaller than the bus width of the system bus, the memory cell mat is The number of transfer data entries can be increased, the number of data transfers can be reduced, and the memory cell array of the orthogonal memory can be used effectively.

[Example of change]
FIG. 26 schematically shows a structure of a main part of an orthogonal transform circuit according to a modification of the second embodiment of the present invention. Since the orthogonal memories 90a and 90b have the same configuration, FIG. 26 also shows the configuration of the main part of the orthogonal memory 90a. The orthogonal memory 90a includes an orthogonal memory cell array 300, a V word line selection circuit 320 that selects a vertical word line WLV of the orthogonal memory cell array 300, and a vertical word line WLV selected by the V word line selection circuit 320. A V input / output circuit 305 for inputting / outputting data to / from a K-bit memory cell connected thereto, and a V system for controlling operations of these V word line selection circuit 320 and V input / output circuit 305 in accordance with effective bit width information m A control circuit 310 is included.

  In the orthogonal memory cell array 300, vertical word lines are not divided into blocks, and 32 bits (K bits) of data can be input / output by selecting one vertical word line WLV during vertical data transfer. Done.

  An internal data bus 98 is provided in common for the orthogonal memories 90a and 90b. Internal data bus 98 is coupled to registers RGa-RGb via 32-bit transfer gates TFa-TFb, respectively. Registers RGa-RGb each have a 32-bit width and are coupled to internal sub data buses 198a-198d, respectively. These internal sub data buses 198a-198d are coupled to memory cell mat orthogonal memory I / F 192.

  The 32-bit transfer gate TFa is turned on according to the activation signal ENX and transfers 32-bit data. Transfer gate TFb is turned on according to activation signal 8 / 16ENX, 32-bit transfer gate TFc is selectively turned on according to activation signal • ENXA, and 32-bit transfer gate TFb is selectively turned on according to activation signal 8 · ENXB. Conducted to.

  When the effective bit width information m indicates 32-bit data, only the activation signal ENX is activated. When the effective bit width information m indicates 16-bit data, the activation signals ENX and 8/16 · ENX are sequentially activated. When the effective bit width information m indicates 8-bit data, the activation signals ENX, 8/16 • ENX, 8 • ENXA, and 8 • ENXB are sequentially activated. These activation signals are generated by the V-system control circuit 310 of the orthogonal memories 90a and 90b.

  Each of registers RGa-RGd is formed of a latch circuit and latches given data. The latch operations of these registers RGa-RGd may be controlled by activation signals for the corresponding 32-bit transfer gates TFa-TFb.

  In the orthogonal transformation circuit shown in FIG. 26, the mode in which data is written by selecting horizontal word line WLH is the same as the operation described with reference to FIGS. Data is written to or read from the orthogonal memory cell array 300 in units of 16 bits or 32 bits.

  When the effective bit width information m indicates 32-bit data, the V word line selection circuit 320 selects one vertical word line WLV according to a vertical word line address (VRA) from a V address generation circuit (not shown). At this time, the V input / output circuit 305 is activated by the V-system control circuit 310, reads data of the selected memory cell of K bits (32 bits), and transfers it onto the data bus 98.

  Activation signal ENX is activated, and data read from orthogonal memory 90a is stored in register RGa by 32-bit transfer gate TFa. Memory cell mat orthogonal memory I / F 192 operates in the same manner as the I / F shown in FIGS. 15, 16 and 25, and performs path setting to transfer data.

  When the effective bit width information m indicates 16-bit data, the V word line selection circuit 320 selects one vertical word line WLV according to the given vertical word line address. In accordance with the first selection of vertical word line WLV, activation signal ENX is activated, and the data read by V input / output circuit 305 is stored in register RGa. Next, according to the effective bit width information m, a V address generation circuit (not shown) increments the vertical word line address by +16. The V word line selection circuit 320 is activated again under the control of the V system control circuit 310 and selects the vertical word line WLV at the corresponding position. In the second vertical word line selection, activation signal 8/16 • ENX is activated, and data read by V input / output circuit 305 is stored in register RGb through 32-bit transfer gate TFb. When 32-bit data is stored in registers RGa and RGb, memory cell mat orthogonal memory I / F 192 transfers the 64 entry data bits stored in registers RGa and Rgb in parallel.

  This operation is repeated 16 times, the vertical word line is selected 32 times (L times), and all the data stored in the memory cell array 300 of the orthogonal memory is transferred to the memory cell mat.

  Next, when the effective bit width information m indicates 8-bit data, the V word line selection circuit 320 first performs the first vertical direction according to the vertical word line address under the control of the V-system control circuit 310. A word line WLV is selected. The 32-bit transfer gate TFa is turned on by the activation signal ENX, and K-bit (32-bit) data from the V input / output circuit 305 is transferred to and stored in the register RGa.

  Next, according to the valid bit information m, the V address generation circuit increments the vertical word line address by +8, and the V word line selection circuit 320 is activated again under the control of the V-system control circuit 310 to cause the vertical direction. The vertical word line WLV at the position obtained by incrementing the word line address by +8 is selected, and the V input / output circuit 305 is activated again to output data. At this time, activation signal 8/16 • ENX is activated, and the data amplified by V input / output circuit 305 is stored in register RGb.

  After this data reading is completed, the vertical word line address is incremented by 8 again, and the V word line selection circuit 320 selects a vertical word line that is 16 word line addresses away from the original position, and V input Output circuit 305 reads 32-bit data. At this time, activation signal 8 • ENXA is activated, and the read 32-bit data is stored in register RGc by 32-bit transfer gate TFc.

  Again, the V-system control circuit 310 activates the V word line selection circuit 320 and selects the vertical word line V at the position of the vertical word line address incremented by +24 by the V address generation circuit. Again, V input / output circuit 35 is activated to read 32-bit data. In this case, activation signal 8 · ENXB is activated, and 32-bit data read through 32-bit transfer gate TFe is stored in register RGd.

  When memory cell mat orthogonal memory I / F 192 stores 32-bit data in each of registers RGa-RGd, it performs data transfer operation and transfers 128-bit data to memory cell mat via internal memory bus 77. To do.

  The V address generation circuit designates the vertical word line by sequentially incrementing the vertical word line address by the effective bit width according to the effective bit width information m. In this case, after the data is transferred to the memory cell mat, the vertical word line address does not need to be reset to the initial value. The effective bit width information m is simply incremented sequentially from the head vertical word line address 0, and the modulo By performing 31 operations, for example, when the effective bit width m is 8 bits, after selecting the vertical word line incremented by 24, the vertical word line address is incremented by 8 and performing the modulo 31 operation, A vertical word line whose vertical word line address is +1 can be selected.

  The V-system control circuit 310 determines the number of times of activation of the V word line selection circuit 320 per one data transfer according to the effective bit width information m (activates L / m times).

  The activation signals ENX, 8/16 · ENX, 8 · ENXA and 8 · ENXB are activated by sequentially transferring the activation signals from the transfer gate TFa to the transfer gate TFd L / m times. Is done. These activation signals ENX, 8/16 · ENX, 8 · ENXA and 8 · ENXB are generated based on the synthesis of control signals from the V-system control circuit included in the orthogonal memories 90a and 90b (the OR circuit Use).

  Even when data is transferred from the memory cell mat to the system bus, although the data flow is reversed, the same vertical word line selection and register selection sequence is executed.

  At the time of data transfer to the memory cell mat, the vertical word line is selected a plurality of times according to the valid bit width information. However, the number of times is L / m per transfer cycle, which is the same as the number of horizontal word line selections per bus access cycle, and one of the orthogonal memories 90a and 90b transfers data to and from the system bus. While performing, the other orthogonal memory can perform data transfer with the memory cell mat with a sufficient time margin.

  In the configuration shown in FIG. 26, in the orthogonal memory cell array 300, only a 32-bit internal data line (global data line) is provided for data transfer with the memory cell mat, and the wiring layout is simplified. It becomes. The vertical word line address is generated by arranging the previous vertical block address and the vertical word line address in parallel, updating the part corresponding to the block address according to the effective bit width information, and With the configuration in which the line address is incremented by 1 for each data transfer cycle with the memory cell mat, the configuration in which the modulo 31 is added can be easily realized.

  Data transfer control in the memory cell mat orthogonal memory I / F 192 is the same as the operation described with reference to FIG.

  In the configuration shown in FIG. 1, the orthogonal transform circuit 85 is provided for each basic operation block, and it is possible to perform orthogonal transform of a data string for each basic operation block. However, this orthogonal transform circuit may be provided in common for a plurality of basic arithmetic blocks.

  As described above, according to the second embodiment of the present invention, after the transfer data is stored in all the memory cells in the orthogonal memory according to the effective bit width information, the entry extension according to the effective bit width information is performed. Thus, data transfer is performed to improve data transfer efficiency with the memory cell mat. Further, the utilization efficiency of the memory cell of the orthogonal memory can be improved. Further, the number of data transfers between the memory cell mat and the orthogonal transform circuit is reduced, the number of arithmetic processing cycles of the main arithmetic circuit can be increased, and the processing capacity of the entire system can be improved. In addition, the same effects as those of the first embodiment are also obtained.

  By applying the orthogonal transform circuit according to the present invention to a signal processing device in which an arithmetic unit is provided for each entry of the arithmetic memory array, data transfer can be performed efficiently and processing performance can be further improved. Can do.

  Further, the present invention is not limited to such a semiconductor signal processing device. For example, in a circuit device that performs matrix multiplication, data can be transmitted at high speed by using an orthogonal transformation circuit according to the present invention for a circuit portion that transposes a matrix. To generate a transposed matrix and perform matrix multiplication.

  Further, the present invention is not limited to such matrix multiplication and the like, and by using the orthogonal transform circuit according to the present invention for a circuit portion that requires matrix transposition operation, efficient orthogonal transform can be performed. A circuit device that can efficiently execute multiplication processing and the like can be realized.

It is a figure which shows roughly the structure of the signal processing system to which the orthogonal transformation circuit according to this invention is applied. FIG. 2 is a diagram schematically showing a configuration of a memory cell mat and an arithmetic processing unit of the main arithmetic circuit shown in FIG. 1. It is a figure which shows an example of the arithmetic operation performed within the main arithmetic circuit shown in FIG. It is a timing chart which shows the arithmetic processing operation | movement shown in FIG. It is a figure which shows more specifically the structure of the main arithmetic circuit shown in FIG. FIG. 2 is a diagram schematically showing a data flow during data transfer from an external memory to a memory cell mat of a main arithmetic circuit in the signal processing system shown in FIG. 1. It is a figure which shows roughly the structure of the orthogonal transformation circuit according to Embodiment 1 of this invention. FIG. 8 is a diagram illustrating an example of a configuration of orthogonal memory cells included in the orthogonal memory illustrated in FIG. 7. FIG. 8 is a flowchart showing a data transfer operation of the orthogonal transform circuit shown in FIG. 7. It is a figure which shows typically the flow of the data at the time of the other data transfer of the flowchart shown in FIG. It is a figure which shows more specifically the structure of the orthogonal transformation circuit according to Embodiment 1 of invention. FIG. 12 schematically shows a configuration of a main part of the orthogonal transform circuit shown in FIG. 11. (A) schematically shows the configuration of the memory cell mat orthogonal memory I / F shown in FIG. 11, and (B) shows more specifically the configuration of the bus width conversion circuit shown in FIG. 13 (A). FIG. It is a figure which shows an example of the arrangement | sequence of the transfer data by the bus width conversion circuit shown in FIG.13 (B). It is a figure which shows roughly the structure of the orthogonal transformation circuit according to Embodiment 2 of this invention. FIG. 16 is a diagram specifically showing the configuration of the orthogonal memory shown in FIG. 15. (A)-(C) is a figure which shows roughly the acquisition sequence to the orthogonal memory when the entry unit data is 8 bits wide. It is a figure which shows typically the data flow at the time of transfer to the memory cell mat from orthogonal memory when entry data are 8-bit data. (A) and (B) are diagrams schematically showing a data storage sequence in the orthogonal memory when the entry data is 16-bit data. It is a figure which shows typically the flow of the transfer data at the time of the data transfer to the memory cell mat from the orthogonal memory when entry unit data is 16 bit data. It is a figure which shows typically the flow of the data transfer from orthogonal memory to memory cell mat when entry unit data is 16 bit data. It is a figure which shows typically the data storage sequence to orthogonal memory when entry unit data is 32 bits. It is a figure which shows typically the data flow at the time of the data transfer from orthogonal memory to memory cell mat when entry unit data is 32 bits. It is a figure which shows typically the flow of the transfer data at the time of the data transfer from an orthogonal memory to a memory cell mat when entry data is 32 bits wide. FIG. 16 schematically shows a configuration of a memory cell mat orthogonal memory I / F shown in FIG. 15. It is a figure which shows schematically the structure of the principal part of the orthogonal transformation circuit according to the modification of Embodiment 2 of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Signal processing system, 2 Semiconductor signal processing apparatus, 20 Main arithmetic circuit, 7 Internal system bus, 24 System bus I / F, 85 Orthogonal transformation circuit, 90a, 90b Orthogonal memory, 93 Internal register group, 93a System bus access frequency counter 93b Memory cell mat access count counter, 94 control register group, 94a entry position register, 94b bit position register, 94c enable register, 94d read / write direction register, 94e effective bit width register, 95 memory cell mat address calculation unit, 92 Memory cell mat orthogonal memory I / F, 77 internal memory bus, 96, 97, 98 internal data bus, 91 system bus orthogonal memory I / F, 21 system bus memory I / F, 110 orthogonal memory cell array, 111 H word line selection circuit, 112 V word line selection circuit, 113 H input / output circuit, 114 V input / output circuit, 102 H address generation circuit, 104 V address generation circuit, 120 path control circuit, 122 path setting circuit, 113a- 113d read / write circuit, 122a transfer path setting unit, 130 bus width conversion circuit, 133 bus driver, 202 orthogonal memory cell array, 212 V word line selection circuit, 213 H input / output circuit, 214 V input / output circuit, 220 path control circuit 222 path setting circuit, 204 V address generation circuit, 192 memory cell mat orthogonal memory I / F, 198 internal data bus, 212a-212d V decode / word line driver, 214a-214d main input / output circuit, 214e path switching circuit, TFa-TF 32-bit transfer gates, RGa-RGb registers, 320 V word line selection circuit, 305 V input and output circuit, 310 V system control circuit.

Claims (5)

A memory comprising a plurality of entries, each extending in a first direction and having a plurality of memory cells;
A data transfer path between the first bus and the memory is set according to the effective bit width information indicating the bit width of the unit data of data transferred on the first bus, and the data is transferred according to the set path. A data transfer path setting circuit for transferring, and a data transfer circuit for transferring data in parallel between a second bus and bits aligned in a second direction of the plurality of entries of the memory ,
The data transfer path setting circuit, when the effective bit width information indicates that the bit width of the unit data transferred on the first bus is smaller than the bit width of the first bus, Set the data transfer path to transfer data to and from the same area of multiple entries,
When the bit width information indicates that the bit width of the data transferred through the first bus is smaller than the bit width of the first bus, the data transfer circuit expands the number of entries to increase the number of entries. And an orthogonal transformation circuit for transferring data between the second bus and the second bus . The data transfer path setting circuit further, in accordance with the effective bit width information, upon completion of unit data transfer with the plurality of entries in the same area, each entry in a different area from the same area of the memory. transferring unit data between the orthogonal transform circuit according to claim 1, wherein.   2. The orthogonal transform circuit according to claim 1, wherein the memory includes a write / read circuit that sequentially transfers unit data between the transfer path setting circuit and one or a plurality of entries in accordance with the effective bit width information.   When the effective bit width information indicates a bit width smaller than the first bus width, the memory completes data transfer in units of memory cells aligned in the second direction for unit data of each entry, The next unit data is transferred from each entry in memory cell units aligned in the second direction, the number of entries in the second direction is expanded from the memory, and the transfer circuit is connected to the transfer circuit in the expanded entry unit. The orthogonal transform circuit according to claim 1, further comprising an entry extension circuit that transfers data between the two. The memory comprises first and second orthogonal memories each having the same number of entries;
The data transfer path setting circuit includes first and second data transfer path setting circuits provided corresponding to the first and second orthogonal memories, respectively.
The data transfer circuit includes first and second data transfer circuits provided corresponding to the first and second orthogonal memories, respectively.
When one of the first and second data transfer path setting circuits, the first and second data transfer circuits, and the first and second orthogonal memories transfers the first bus data, the other is the second. The orthogonal transform circuit according to claim 1, wherein the orthogonal transform circuit operates alternately in an interleaved manner so as to transfer the bus and data.

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