JP5145581B2 - Orthogonal transformation circuit - Google Patents

Description

  The present invention relates to an orthogonal transform circuit that orthogonally transforms a data array, and more particularly to an orthogonal transform circuit that performs conversion between a word serial / bit parallel data string and a word parallel / bit serial data string in a parallel processing unit.

  With the development of mobile communication technology, mobile terminal devices such as mobile phones can transmit and receive large amounts of data such as voice and images. For this reason, the importance of digital signal processing for processing a large amount of data such as sound and images at high speed is increasing. For such digital signal processing, a DSP (digital signal processor) is generally used as a dedicated semiconductor device in many cases. In digital signal processing for audio and image data, data processing such as filter processing is performed, and in such processing, there are many arithmetic processes that repeat product-sum operations. Therefore, in general, in the configuration of the DSP, a multiplication circuit, an addition circuit, and an accumulation register are provided. If such a dedicated DSP is used, the product-sum operation can be executed in one machine cycle, and high-speed operation processing is possible.

  However, when such a dedicated DSP is used, there is a problem that the bit width of the data to be processed is fixed, so that the versatility is lacking. An example of a highly versatile arithmetic processing apparatus that performs arithmetic processing at high speed regardless of the bit width of data is disclosed in Japanese Patent Application Laid-Open No. 2007-140750.

  In the configuration disclosed in Patent Document 1, a memory cell mat that is divided into a plurality of entries and an arithmetic unit that is arranged corresponding to each entry are provided in the arithmetic processing unit. Data to be calculated is stored in each entry. In a plurality of entries, arithmetic processing is executed in a corresponding arithmetic unit in a bit serial manner in parallel, and the execution result is rewritten in the corresponding entry.

  In the configuration of the parallel arithmetic processing device shown in Patent Document 1, since the arithmetic processing is executed in a bit serial manner in which each bit is processed, the arithmetic processing is repeated by the bit width of the data to be calculated. The calculation processing of the target data can be executed. Therefore, the arithmetic processing can be executed with the same configuration without being limited by the bit width of the data to be arithmetic processed. Moreover, a plurality of types of arithmetic processing can be executed by setting the arithmetic processing contents of the arithmetic unit by program instructions.

  Data stored in this entry is transferred in bit serial. On the other hand, external data is transferred in word serial and bit parallel. Here, word serial and bit parallel indicate a mode in which data bits constituting a word are transferred in parallel via the data bus for each word. On the other hand, in the parallel arithmetic processing unit, arithmetic processing is executed in parallel for a plurality of entries. Therefore, it is necessary to transfer and store data in each entry in a bit serial manner. For this reason, it is necessary to convert the array between external data (data processed by an external processor or the like) and data in the parallel processing unit. In the above-mentioned Patent Document 1, data array conversion is performed using an orthogonal transform memory having two ports. As this orthogonal transformation memory, a 2-port SRAM is used. Two orthogonal transformation memories are prepared, and these orthogonal transformation memories are accessed in an interleaved manner. When data is written to one orthogonal transformation memory, data is read from the other orthogonal transformation memory.

In Patent Document 1, when the bit width of data transferred through an external data bus (system bus) is different, the data bit storage area of the orthogonal transformation memory is adjusted. As a result, even when the bit widths of the data to be processed are different, it is possible to efficiently transfer data without changing the bus configuration.
JP 2007-140750 A

  In Patent Document 1 described above, two orthogonal transformation memories are accessed in an interleaved manner. In one embodiment, this patent document 1 switches a data transfer path between a system bus and an orthogonal transformation memory according to a bit width of data (external data) transferred on the system bus. That is, when the external data is 8-bit data, the 8-bit area of the orthogonal transformation memory is accessed, and the remaining areas are not accessed. Therefore, the utilization efficiency of the orthogonal transformation memory is lowered.

  In another embodiment, Patent Document 1 switches the connection between a system bus and an input / output circuit of an orthogonal transformation memory in accordance with a data bit width. The orthogonal transform memory is divided into a plurality of memory blocks having the minimum data bit width of the external data. The access path between the system bus and the orthogonal transformation memory is switched according to the data bit width. For example, when the external data is 8 bits, after the access to one memory block is completed, the bus connection is switched, and data transfer is performed between the next memory block and the system bus. Therefore, although data can be transferred using all bits of the system bus during data transfer, a circuit for switching the bus connection between the orthogonal transformation memory and the system bus is required. There is room to further devise in order to reduce this.

  SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an orthogonal transformation circuit capable of performing orthogonal transformation and transferring data of various bit widths while suppressing an increase in circuit scale and a decrease in bus utilization efficiency. .

  The orthogonal transformation circuit according to the present invention couples a plurality of 2-port orthogonal transformation memories to first and second data buses orthogonal to each other. The bit width of the first data bus is made smaller than the bit width of the external system data bus. A bus connection control signal, an address signal, and a transfer control signal for controlling activation are individually generated for a plurality of orthogonal transformation memories according to the transfer data bit width, and the bus connection and activation of these two-port orthogonal transformation memories are performed. Set individually. A buffer memory for adjusting the arrangement of data transfer is provided between the second data bus and the plurality of orthogonal transformation memories. Using this buffer memory, the transfer path between the second data bus and the buffer and the path between the second data bus, the buffer and the interface are selectively set to adjust the data transfer order. The connection between the orthogonal transformation memory and the second data bus, the signal for controlling the activation of the orthogonal transformation memory and the address signal data bit width information are generated and the bus connection and the activation are individually controlled for the orthogonal transformation memory. .

  A plurality of 2-port orthogonal transformation memories adjust the bus connection according to the bit width of the transfer data, and selectively activate the data to execute data writing. Therefore, data having various bit widths can be transferred between the orthogonal transformation memory and the system side so as to use the entire memory area without changing the bus configuration. Further, by setting the connection between the second data bus and the orthogonal transformation memory and the activation of the orthogonal transformation memory in accordance with the bit width of the transfer data, data of various bit widths can be transmitted between the orthogonal transformation memory and the second transformation memory. Can be accurately transferred to and from the data bus.

  In addition, by using the buffer memory, the data transfer order is adjusted according to the bit width of the transfer data, so that data of various bit widths can be obtained in a bit serial manner using all the bits of the second data bus. Can be transferred.

[Embodiment 1]
FIG. 1 is a diagram schematically showing an overall configuration of a signal processing system to which an orthogonal transform circuit according to the present invention is applied. In FIG. 1, the signal processing system 1 includes a system LSI 2 that realizes an arithmetic function for executing various processes, and an external memory connected to the system LSI 2 via an external system bus 3. The external memory includes a large-capacity memory 4, a high-speed memory 5, and a read-only memory (ROM) 6. The large-capacity memory 4 is composed of, for example, a clock synchronous dynamic random access memory (SDRAM), and is simply referred to as SDRAM hereinafter. The high-speed memory 5 is composed of, for example, a static random access memory (SRAM). The read-only memory 6 is composed of a non-volatile memory such as a mask ROM, and stores fixed information such as an instruction at the time of system startup.

  The system LSI 2 includes basic operation blocks FB1 to FBh coupled in parallel to the internal system bus 7, a host CPU 8 that controls processing operations of these basic operation blocks FB1 to FBh, and input signals from the outside of the signal processing system 1. It includes an input port 9 that converts IN to internal processing data, and an output port 10 that receives output data supplied from the internal system bus 7 and generates an output signal / data OUT transferred to the outside of the system.

  Host CPU 8, input port 9 and output port 10 are commonly coupled to internal system bus 7. The input port 9 and the output port 10 are composed of, for example, an IP block (intellectual property block: a functional block prepared as a library), and realize functions necessary for data / signal input / output.

  The system LSI 2 further includes an interrupt controller 11, a CPU peripheral 12, a DMA (direct memory access) controller 13, an external bus controller 14, and dedicated logic 15 coupled to the internal system bus 7 in parallel. The interrupt controller 11 receives an interrupt signal from the basic operation blocks FB1 to FBh and notifies the host CPU 8 of the interrupt.

  The CPU peripheral 12 executes control operations necessary for each processing of the host CPU 8, and also has functions necessary for a program and debugging use in the host CPU 8, such as a timer and serial IO (input / output). The DMA controller 13 executes data transfer control with respect to the external memory in accordance with a DMA request signal indicating a transfer request from the basic operation blocks FB1 to FBh. The external bus controller 14 executes access control to the memory 4-6 connected to the external system bus 3 in accordance with an instruction from the host CPU 8 or the DMA controller 13. The dedicated logic 15 is configured by, for example, an IP block, and a necessary processing function is realized using an existing functional block, and assists data processing of the host CPU 8.

  The basic calculation blocks FB1-FBh execute specified calculation processes, respectively. Since these basic arithmetic blocks FB1-FBh have the same configuration, FIG. 1 representatively shows the configuration of the basic arithmetic block FB1.

  The basic arithmetic block FB1 includes a main arithmetic circuit 20 that executes arithmetic processing of actual data, a microinstruction memory 21 that stores microinstructions that specify arithmetic processing in the main arithmetic circuit 20, and a microinstruction from the microinstruction memory 21. And a controller 22 that controls arithmetic processing of the main arithmetic circuit 20 in accordance with an instruction. The main arithmetic circuit 20 has a memory cell mat 30 in which a plurality of memory cells are arranged in a matrix and divided into a plurality of entries, and is arranged corresponding to each entry of the memory cell mat 30, and performs a specified arithmetic processing. An arithmetic unit (ALU) 31 to be executed and an ALU interconnection switch circuit 32 for setting a data transfer path between the arithmetic units 31 are included. Basically, each row of the memory cell mat 30 constitutes one entry, and each bit of multi-bit data is stored in one entry.

  An arithmetic unit (hereinafter referred to as ALU as appropriate) 31 receives data from a corresponding entry in a bit serial manner and executes arithmetic processing, and the processing result is assigned to a specified entry (for example, a corresponding one of the corresponding memory cell mats 30). Entry) at a predetermined position.

  The connection path of the ALU 31 is switched by the inter-ALU interconnection switch circuit 32, and calculation for data of different entries becomes possible.

  The controller 22 executes an operation according to the microprogram method in accordance with the microinstruction stored in the microinstruction memory 21. Work data necessary for this microprogram operation is stored in the work data memory 23.

  The basic operation block 1 further includes a system bus interface (I / F) 24 for executing data / signal transfer between the inside of the basic operation block FB1 and the internal system bus 7, and the internal system bus 7 and the main operation circuit. An orthogonal transform circuit 40 that converts a data array with 20 memory cell mats 30 and a multiplexer (MUX) that selectively couples the main arithmetic circuit 20 to one of the system bus I / F 24 and the orthogonal transform circuit 40 42.

  The system bus I / F 24 enables the host CPU 8 or the DMA controller 13 to access the memory cell mat 30, the dedicated register in the controller 22, the microinstruction memory 21, and the work data memory 23.

  The orthogonal transform circuit 40 is configured according to the present invention, and is transferred in bit parallel and word serial form via the system bus I / F 24 and word parallel and bit serial transferred from the main arithmetic circuit 20 via the multiplexer 42. The data array to be transferred is converted to establish data transfer consistency. That is, the orthogonal transform circuit 40 transfers data transferred from the system bus I / F 24 in a bit parallel and word serial manner in a word parallel and bit serial manner, and stores different data in each entry of the memory cell mat 30. Write bits in the same position of the word in parallel. Conversely, the orthogonal transform circuit 40 transposes a data string transferred in a word parallel and bit serial manner from the memory cell mat 30 of the main arithmetic circuit 20, and the system bus I / F 24 in a bit parallel and word serial manner. Forward to.

  Here, in this specification, “bit serial” indicates a mode in which the bits constituting one data word are sequentially transferred or processed, and “bit parallel” indicates that the bits constituting one data word are parallel. Shows the mode of transfer or processing. Entry (or word) parallel indicates a mode in which a plurality of entries (or words) are transferred or processed in parallel, and “entry (or word) serial” indicates that a plurality of entries (or words) are sequentially transferred or The aspect processed is shown. Here, conversion between a bit serial and word parallel data sequence and a bit parallel and word serial data sequence is defined as “orthogonal transformation”.

  The orthogonal transform circuit 40 according to the present invention has a data arrangement so that data of different bit widths can be transferred using the entire bit width of the internal memory data bus with respect to the internal system bus 7 and the memory cell mat 30. Perform orthogonal transformation. Even when the data bit widths are different, the data transfer sequence between the internal system bus 7 and the internal memory data bus is the same. The configuration and operation of the orthogonal transform circuit 40 will be described in detail later.

  The multiplexer 42 may be configured to select work data from the controller 22 and transfer it to the main arithmetic circuit 20. When it is not necessary to transpose the operation target data string by orthogonal transformation, the multiplexer 42 selects the system bus I / F 24 and connects it to the main arithmetic circuit 20.

  In the system LSI 2 shown in FIG. 1, the orthogonal transform circuit 40 is shown to be provided in each of the basic operation blocks FB1 to FBh. This is because the operation processing contents are individually set by the microinstruction program set in the microinstruction memory 21 in each of the basic operation blocks FB1 to FBh. However, the orthogonal transform circuit 40 may be provided in common for these basic operation blocks FB1 to FBh.

  Although the processing operation of the entire signal processing system and the configuration and processing operation of the main arithmetic circuit 20 are also disclosed in the above-mentioned Patent Document 1, the operation and effect of the orthogonal transform circuit according to the present invention will be sufficiently described below. In the following, the configuration and operation of the main arithmetic circuit 20 will be briefly described.

  FIG. 2 schematically shows an arrangement of memory cell mat 30 and arithmetic unit (ALU) 31 of main arithmetic circuit 20 shown in FIG. In memory cell mat 30, memory cells MC are arranged in a matrix and are divided into M entries ERY along the row direction (X direction). The entry ERY has a bit width of N bits. In memory cell mat 30, word line WL is arranged in common for M entries ERY, and bit line pair BLP is arranged for one entry ERY. Bit lines BL and / BL of bit line pair BLP are used as data transfer lines.

  An arithmetic unit (ALU) 31 is provided corresponding to each entry ERY and constitutes an arithmetic processing unit 35. The computing unit 31 can perform operations such as addition, logical product, coincidence detection (EXOR), and inversion (NOT). Data is loaded and stored in bit units between each entry ERY and the corresponding arithmetic unit 31 to execute arithmetic processing. The calculation contents of the calculator 31 are set by the controller 22 shown in FIG.

  Each entry ERY stores data to be subjected to arithmetic processing, and the arithmetic unit 31 executes arithmetic processing in a bit serial manner. Accordingly, in the arithmetic processing unit 35 constituted by the arithmetic unit 31, data arithmetic processing is executed in a bit serial and entry parallel manner.

  By executing the arithmetic processing in the bit serial manner in the arithmetic processing unit 35, the following effects can be obtained. Even when the bit width of the data to be calculated varies depending on the application, the number of operation cycles is simply changed according to the bit width of the data word. The content of the arithmetic processing is not changed, and it is possible to easily cope with data processing with different word configurations.

  In addition, data of a plurality of entries ERY can be processed in parallel in the arithmetic processing unit 35. Therefore, by increasing the number of entries M, a large amount of data can be collectively processed. As an example, the number of entries M is 1024, and the bit width N of one entry ERY is 512 bits.

  Memory cell MC is formed of an SRAM cell and can transfer data by performing high-speed access. Further, it is not necessary to periodically refresh the data, and the control of the arithmetic processing for the data in the memory cell mat 30 can be simplified.

  When the main arithmetic circuit 20 performs an operation, first, operation target data is stored in each entry ERY. Next, for all entries ERY, a certain digit of the stored data is read in parallel and transferred (loaded) to the corresponding arithmetic unit 31. That is, by driving the word line WL at a certain bit position to the selected state, the data of the memory cell MC connected to the selected word line is read onto the corresponding bit line pair BLP, and the read data is The data is transferred to the corresponding calculator 31 via the bit line pair.

  Note that a sense amplifier that reads memory cell data and a write driver that writes data to the memory cell are provided between the memory cell mat 30 and the arithmetic unit 31. In FIG. 2, the drawing is simplified. It is not shown to make it.

  When performing a binary operation, data of a set of binary operations is stored in each entry ERY. In each entry ERY, after the bits of one data word are transferred to the calculator, the bits of another data word are transferred to the corresponding calculator. Thereafter, the arithmetic unit 31 performs a binary operation on the data bits transferred by each of the arithmetic units 31, and the arithmetic processing result is rewritten (stored) from the arithmetic unit 31 to a predetermined area in the corresponding entry ERY. Is done.

  For memory cell mat 30, data to be calculated is written / read from the direction of bit lines BL and / BL. This write / read data is transferred to / from the orthogonal transform circuit 40. Data transferred by the orthogonal transformation circuit 40 is stored in memory cells connected to a common word line in the memory cell mat 30. In memory cell mat 30, different external data is stored in each entry ERY. For this reason, in the orthogonal transformation circuit 40, it is necessary to orthogonally transform the data array during data transfer with an external memory (for example, a large capacity memory (SDRAM 4)).

  FIG. 3 is a diagram schematically showing the flow of data through the data array conversion operation in the orthogonal transform circuit 40 shown in FIG. In FIG. 3, an example of an operation when 4-bit data is transferred from an external large-capacity memory (SDRAM) 4 and 4-bit data is transferred from the orthogonal transformation circuit 40 to the memory cell mat 30 in the main arithmetic circuit 20 is an example. As shown.

  In the SDRAM 4, 4-bit data A (bits a0 to a3) to I (bits i3 to i0) are stored. Each bit of 4-bit data DTE (data I: bits i3-i0) is transferred in parallel from the SDRAM 4 via the internal system bus (7). The data DTE from the SDRAM 4 is entry unit data stored in the same entry ERY of the memory cell mat 30. In the orthogonal transform circuit 40, each bit of the transferred 4-bit data is stored aligned in the Y direction. In the memory of the orthogonal transformation circuit 40, transfer data from the SDRAM 4 is sequentially stored in the X direction. In FIG. 3, 4-bit data E (bits e3-e0), F (bits f3-f0), G (bits g3-g0), and H (bits h3-h0) are stored in the memory of the orthogonal transformation circuit 40. The stored state is shown as an example.

  When data is transferred from the orthogonal transform circuit 40 to the memory cell mat 30, the bits aligned in the X direction are read in parallel in the internal memory, and the selected bit position is sequentially updated along the Y direction to execute the data transfer. Is done. Therefore, data DTA composed of bits e 1, f 1, g 1 and h 1 is transferred and stored in parallel in 4 entries of memory cell mat 30. This address unit data DTA is data stored when one address is designated in the memory cell mat 30, and the entry position information (bit line address) and write bit position information (word line address) of the memory cell mat 30 are stored. Stored at the indicated position. By sequentially repeating this operation and executing all the transfer data, a plurality of data bits are written in parallel to a plurality of entries (for example, in units of four entries) in memory cell mat 30, and in the addressed entry (ERY) Each stores data DTE in units of entry, for example, data A (bits a0 to a3).

  When data is transferred from the memory cell mat 30 to the outside via the internal system bus (7), data flows in the opposite direction. That is, the address unit data DTA is sequentially stored in the memory in the orthogonal transform circuit 40 along the Y direction. Next, entry unit data DTE aligned in the X direction is read from the memory of the orthogonal transform circuit 40 and transferred via the system bus I / F (24). Here, the entry-unit data DTE is data stored in one entry. That is, when data is transferred from the memory cell mat 30 to the SDRAM 4 via the system bus, only the data flow shown in FIG. 3 is reversed, and a similar conversion operation is executed in the orthogonal transform circuit 40. The

  As described above, basically, data is transferred between the SDRAM 4 and the orthogonal transformation circuit 40 in bit parallel and word serial, and between the orthogonal transformation circuit 40 and the memory cell mat 30 is bit serial and word parallel. Data is transferred to

  Data transferred by the SDRAM 4 is not limited to 4 bits. Depending on the application, it is required to transfer data of various bit widths such as 8-bit data, 16-bit data, 32-bit data, and 64-bit data. Even when processing data of such multiple types of bit widths, it is required to transfer data without reducing the data transfer efficiency, and it is possible to suppress an increase in the size of the orthogonal transform circuit. Required. As will be described in detail below, the present invention provides an orthogonal transform circuit that satisfies such requirements.

  FIG. 4 schematically shows a configuration of orthogonal transform circuit 40 according to the first embodiment of the present invention. In FIG. 4, the orthogonal transformation circuit 40 includes four 2-port orthogonal transformation memories TM0 to TM3. In these 2-port orthogonal transformation memories TM0 to TM3, the first and second ports each have a configuration of 32 bits × 32 words. The first ports of the two-port orthogonal transformation memories TM0 to TM3 are commonly coupled to a 32-bit data bus (first data bus) 50, and the second ports of these two-port orthogonal transformation memories TM0 to TM3 are Are commonly coupled to a 64-bit data bus (second data bus) 55.

  The orthogonal transform circuit 40 further transfers a 64-bit width data between the 32-bit data bus 50 and the system bus I / F 24 and controls the transfer, and a 64-bit data bus. 55 includes a main arithmetic circuit side control unit 65 for transferring data between the main arithmetic circuit I / F 66 and controlling the data transfer. Main operation circuit I / F 66 is coupled to main operation circuit 20 via a 64-bit internal memory data bus.

  The main arithmetic circuit side control unit 65 includes a 64-bit buffer 68 for adjusting the arrangement of data bits during data transfer. The 64-bit buffer 68 only needs to be able to store and transfer 64-bit data, and may be composed of a 64-bit register or a 64-bit memory. In order to transfer data bidirectionally with the main arithmetic circuit, the 64-bit buffer 68 only needs to be able to transfer data bidirectionally.

  4 shows a configuration in which an orthogonal transformation circuit 40 is provided in each basic operation block FBi (i = 1 to h), similarly to the configuration shown in FIG. When the orthogonal transform circuit 40 is provided in common to the basic operation blocks FB1 to FBh, a basic operation block I / F is provided instead of the main operation circuit I / F.

  64-bit data is transferred between the system bus control unit 60 and the system bus I / F 24. The system bus side control unit 60 converts the 64-bit width data into 32-bit width data and transfers the data to the internal data bus 50. Also, the 32-bit width data from the internal data bus 50 is converted to 64-bit width data. Data is converted and transferred to the system bus I / F 24.

  64-bit width data is transferred between the main arithmetic circuit side controller 65 and the main arithmetic circuit I / F 66. In FIG. 4, the main arithmetic circuit I / F 66 is shown to transfer data to and from the main arithmetic circuit via a 64-bit internal memory data bus. However, this internal memory data bus need not be 64 bits wide. In this case, the main arithmetic circuit I / F 66 adjusts the bus width by the bus width conversion function.

  As an example, four-port 2-port orthogonal transformation memories TM0 to TM3 are divided into two groups, and data access is executed in units of 32 bits. The system bus side control unit 60 executes conversion of the 64-bit / 32-bit data array and address generation. Regardless of the bit width of the data transferred via the system bus, in this orthogonal transformation circuit 40, the bus connection of the 2-port orthogonal transformation memories TM0 to TM3 is switched, and the entire data bus width can be increased without changing the bus configuration. Data access can be executed using the entire memory area. In the following description, a case where the minimum bit width of external data (data transferred by the SDRAM) is 8 bits and the maximum bit width is 64 bits will be described.

  FIG. 5 schematically shows a structure of 2-port orthogonal transformation memories TM0 to TM3 shown in FIG. Since these two-port orthogonal transformation memories TM0 to TM3 have the same configuration, FIG. 5 shows the two-port orthogonal transformation memories TM as representatives of these two-port orthogonal transformation memories TM0 to TM3.

  In FIG. 5, the 2-port orthogonal transformation memory TM includes a memory cell array 70 in which memory cells MC are arranged in a matrix. In memory cell array 70, word lines AWL and bit line pairs EBLP are arranged corresponding to memory cells MC aligned in the X direction, and word lines EWL and bit line pairs ABLP are arranged corresponding to memory cells aligned in the Y direction. Arranged. A memory cell storing address unit data DTA of the memory cell mat in the main arithmetic circuit is connected to the word line AWL, and data DTE of the entry unit of the memory cell mat of the main arithmetic circuit is stored in the word line EWL. A memory cell is connected. When word line EWL is selected, data stored in the memory cell corresponding to bit line pair EBLP is read. Similarly, when word line AWL is selected, the data stored in the memory cell corresponding to bit line pair ABLP is read.

  The 2-port orthogonal transformation memory TM further includes a system bus side write / read circuit 72, a system bus side cell selection circuit 74, a main arithmetic circuit side write / read circuit 76, and a main arithmetic circuit side cell selection circuit 78. including. The system bus side write / read circuit 72 sequentially accesses in the X direction and executes data access to the memory cells aligned in the Y direction. The system bus side cell selection circuit 74 selects a memory cell from the memory cell array 70 in accordance with a selection signal SSEL, a data input / output instruction signal SDIOE, and an address signal SADD given from the system bus side control unit (60).

  For system bus side write / read circuit 72, read enable signal SRE for activating data reading from system bus side control unit (60), write enable signal SWE for activating data writing, and bit write mask control A signal SDM is provided. With the bit write mask control signal SDM, the system bus side write / read circuit 72 masks data access in units of 16 bits.

  The main arithmetic circuit side write / read circuit 76 performs parallel processing on the memory cells aligned in the X direction of the memory cell array 70 in accordance with the read enable signal MRE and the write enable signal MWE supplied from the main arithmetic circuit side control unit (65). And access. Main operation circuit side cell selection circuit 78 selects a memory cell of memory cell array 70 in accordance with selection signal MSEL, data input / output control signal MDIO, address signal MADD and data mask signal MDM supplied from main operation circuit side control unit (65). To do. Data mask signal MDM masks data writing / reading, for example, in units of 16 bits, similarly to bit write mask control signal SDM.

  The system bus side control unit 60 generates an address signal and each control signal in accordance with the address signal and control signal transferred from the system side, and the main arithmetic circuit side control unit 65 transfers from the controller in the main arithmetic circuit. The address signal and each control signal are generated according to the instruction, the address signal, and the control signal. The generation manner of these address signals and control signals will be described later in detail.

  System side cell selection circuit 74, system bus side write / read circuit 72, word line EWL and bit line pair EBLP constitute a first port, and main operation circuit side cell selection circuit 78, main operation circuit side write / read Read circuit 76, word line AWL and bit line pair ABLP constitute a second port.

  In this 2-port orthogonal transformation memory TM, the system bus side write / read circuit 72 transfers the data DTE in entry units aligned in the Y direction as data HDQ, and the main arithmetic circuit side write / read circuit 76 As data VDQ, data in units of addresses DTA aligned in the X direction is transferred. The configuration of this orthogonal transform circuit is substantially the same as that of the 2-port SRAM.

  FIG. 6 is a diagram showing an example of the configuration of the memory cell MC shown in FIG. 6, memory cell MC includes cross-coupled P-channel MOS transistors (insulated gate field effect transistors) PQ1 and PQ2, and cross-coupled N-channel MOS transistors NQ1 and NQ2. MOS transistors PQ1 and PQ2 pull up and hold the high-side node of storage nodes SN1 and SN2 to the power supply voltage level. MOS transistors NQ1 and NQ2 drive and hold the low-side nodes of storage nodes SN1 and SN2 to the ground voltage level. These MOS transistors PQ1 and PQ2, NQ1 and NQ2 constitute an inverter latch. Therefore, storage nodes SN1 and SN2 hold complementary data.

  Memory cell MC further configures N channel MOS transistors NQB1 and NQB2 constituting a data access port (first port) in entry units and a port (second port) for accessing data in address units. N channel MOS transistors NQA1 and NQA2 are included. MOS transistors NQA1 and NQA2 selectively electrically couple storage nodes SN1 and SN2 to bit lines ABL and / ABL, respectively, according to the signal potential on word line AWL. MOS transistors NQB1 and NQB2 selectively electrically couple storage nodes SN1 and SN2 to bit lines EBL and / EBL, respectively, according to the signal potential on word line EWL. Bit lines ABL and / ABL constitute a bit line pair ABLP, and bit lines EBL and / EBL constitute a bit line pair EBLP.

  As shown in FIG. 6, memory cell MC is a two-port memory cell that can access storage nodes SN and / SN from different ports, and bit line pairs ABLP and EBLP are orthogonal to each other. Therefore, the data array stored in the memory cells aligned in the word line EWL direction and the data array stored in the memory cells aligned in the word line AWL direction are in an orthogonal transformation relationship.

  FIG. 7 schematically shows an address arrangement at the time of data transfer between 2-port orthogonal transformation memories TM0 to TM3 shown in FIG. 4 and the system bus. In FIG. 7, the 2-port orthogonal transformation memories TM0 to TM3 are assigned addresses 0 to 31 along the X direction.

  Along the Y direction, the memory block is divided into four memory blocks BKa-BKd in units of 8 bits. A mask signal for masking writing is applied to two memory blocks, that is, 16-bit data. That is, mask instructions DMi0 and DMi1 are given in the 2-port orthogonal transformation memory TMi (i = 0-3). When mask instruction DMi0 is in a valid state and indicates a write mask, data writing to corresponding blocks BKa and BKb is stopped. When mask instruction DMi1 is valid, data writing to memory block blocks BKc and BKd is stopped.

  When both mask instruction signals DMi0 and DMi1 are set to the valid state, data writing to the corresponding 2-port orthogonal transformation memory TMi is stopped. In this case, however, the write enable to the corresponding orthogonal transformation memory is rather performed. Signal WE is set to an inactive state. These mask signals DMij (i = 0-3, j = 0, 1) are generated according to the bit write control signal SDM at the time of writing data to the orthogonal transformation memory.

  The system bus side controller 60 individually generates control signals for these 2-port orthogonal transformation memories TM0 to TM3.

  The configuration for masking data writing / reading is such that a configuration for setting the data write circuit (driver with write) or the read circuit (preamplifier) to the disabled state or the output high impedance state is used. Well-known mask circuits can be used.

  FIG. 8 is a diagram schematically showing a data transfer sequence at the time of data transfer from the SDRAM 4 to the orthogonal transform circuit 40. Now, consider the case where 8-bit data is stored in the SDRAM 4 and the data is transferred in units of 8 data via the 64-bit internal system bus 7. In this case, data is stored in the two-port orthogonal transformation memories TM0 to TM3 in FIG. Each of the two-port orthogonal transformation memories TM0 to TM3 has a configuration of 32 words × 32 bits, and can write / read data having a 32-bit width. The internal data bus 50 is a 32-bit data bus. The system bus side control unit 60 performs data bus width conversion.

  When data is written to the orthogonal transformation memories TM0 to TM3, 16-bit data is written in parallel to the two-port orthogonal transformation memories TM0 and TM1, and then to the two-port orthogonal transformation memories TM2 and TM3. Bit data is written. Therefore, 32-bit data is alternately written into orthogonal transformation memories TM0 and TM1 and orthogonal transformation memories TM2 and TM3. In each of the orthogonal transformation memories TM0 to TM3, data is written into the first 16-bit data area over all addresses (0-31), and then data is written into the latter 16-bit data area over all addresses. Is done.

  A write control signal and an address signal are commonly applied to the 2-port orthogonal transformation memories TM0 to TM3. Selection of the orthogonal memories TM0 to TM3 is performed by a write enable signal WE (SWE). In the selected orthogonal transformation memory, the selection / non-selection of the memory block is set by the above-described mask instruction signal DM (bit write control signal SDM), and writing of 16-bit data to each of the orthogonal transformation memories TM0 to TM3. Is executed.

  In these 2-port orthogonal transformation memories TM0 to TM3, 64-bit data transferred from the SDRAM 4 at a time is distributed and stored in the same bit position of the same address.

  FIG. 9 is a timing chart showing a write sequence of 8-bit data to the 2-port orthogonal transformation memory shown in FIG. The data write sequence for the 2-port orthogonal transform memories TM0 to TM3 shown in FIG. 8 will be described below with reference to FIG.

  The SDRAM 4 transfers 64-bit data via the internal system bus 7 in synchronization with the system clock signal SCLK. In the orthogonal transform circuit, data is written according to the transfer clock signal TCLK.

  Data transferred from the SDRAM 4 via the system bus 7 at a time includes eight 8-bit data. At the first data transfer, data 0-7 is transferred and address 0 is designated. At this time, in the orthogonal transform circuit, the 2-port orthogonal transform memories TM0 and TM1 are enabled by the write enable signal, data 0 and 1 are stored in the orthogonal transform memory TM0, and data 2 and 3 are stored in the orthogonal transform memory TM1. Is done. At this time, the orthogonal transformation memories TM2 and TM3 are disabled according to the write enable signal WE (WE2, WE3), and data writing is prohibited.

  Next, in the next cycle of the transfer clock signal TCLK in the orthogonal transform circuit, the orthogonal transform memories TM0 and TM1 are disabled, and the orthogonal transform memories TM2 and TM3 are enabled. At this time, the address is 0. Therefore, data 4 and 5 and data 6 and 7 are stored at the position of address 0 of orthogonal transformation memories TM2 and TM3, respectively.

  Next, in the next cycle, data 8-15 is transferred from SDRAM 4 via system bus 7 in synchronization with system clock signal SCLK. The address at this time is 1. Also in this case, as in the previous cycle, the orthogonal transform memories TM0 and TM1 are enabled in accordance with the write enable signal in synchronization with the transfer clock signal TCLK, the data 8 and 9 are stored in the orthogonal transform memory TM0, and the data 10 and 11 are stored. Is stored in the orthogonal transformation memory TM1. At this time, the orthogonal transformation memories TM2 and TM3 are in a disabled state according to the respective write enable signals.

  Next, when the transfer clock signal TCLK rises, the orthogonal transformation memories TM0 and TM1 are disabled and set in a write-inhibited state. On the other hand, writing is permitted to orthogonal transformation memories TM2 and TM3, data 12 and 13 are stored in orthogonal transformation memory TM2, and data 14 and 15 are stored in address 1 of orthogonal transformation memory TM3.

  When the next cycle starts, address 2 is given together with the next eight data in accordance with system clock signal SCLK. According to transfer clock signal TCLK, data 16 and 17 are stored in orthogonal transform memory TM0, and data 18 and 19 are stored in orthogonal transform memory TM1. Next, according to the rise of the next transfer clock signal TCLK, the orthogonal transformation memories TM0 and TM1 are set to the write-inhibited state, while the orthogonal transformation memories TM2 and TM3 are set to the write-permitted state. Data 20, 21 and data 22 and 23 are stored at the addresses of the orthogonal transformation memories TM2 and TM3, respectively.

  In the timing chart shown in FIG. 9, 64-bit data is transferred via the system bus 7, and the bit width of the data is changed by the system bus side control unit 60 and transferred via the system bus 7. Data is alternately written in accordance with the transfer clock signal TCLK at a period twice as long as the transfer cycle.

  Temporarily, the SDRAM 4 has a × 8 configuration, and a bus width conversion circuit is provided in the SDRAM 4, and 8-bit data transferred in the burst mode is converted into 64-bit data and transferred via the internal system bus 7. The data transfer cycle has a cycle length four times that of the SDRAM 4 8-bit data read cycle. Therefore, in this case, data is only transferred once in 8 cycles of the operation cycle of SDRAM 4 (cycle defined by the system clock signal SCLK), and the data transfer cycle in the orthogonal transform circuit has a sufficient margin. The data can be transferred to the orthogonal transformation memory in a half cycle.

  When the SDRAM 4 is configured to input / output 64-bit data at the time of data transfer, the transfer clock signal TCLK in the orthogonal transform circuit 40 is a system clock signal (a clock signal that defines the transfer cycle of the SDRAM 4). ) It has a cycle that is 1/2 of SCLK. In this case, the SDRAM 4 transfers data in a single data rate mode (SDR mode). The orthogonal transform memories TM0 to TM3 are composed of SRAM, and are higher-speed memories than the SDRAM 4. Therefore, data can be sufficiently written at twice the speed of SDRAM data transfer, and the difference in transfer clock cycle between system bus 7 and internal data bus 50 can be sufficiently absorbed. .

  When the SDRAM 4 operates in a double data rate mode (DDR mode) in which data is transferred in synchronization with the rise and fall of the system clock signal SCLK, the orthogonal transformation circuits TM0 to TM3 are connected to the orthogonal transformation memories TM0 to TM3. Similarly, data writing is executed in synchronization with the transfer clock signal TCLK in the double data rate mode.

  In FIG. 9, data is transferred in the single data rate mode in synchronization with the rise of system clock signal SCLK. However, data may be transferred via the system bus in synchronization with the fall of the system clock signal SCLK.

  FIG. 10 shows a write sequence of 8-bit data to 2-port orthogonal transformation memories TM0 to TM3. FIG. 10 shows the storage position of data 0-255 transferred from the first cycle to the 32nd cycle via the system bus.

  In FIG. 10, in the 2-port orthogonal transformation memories TM0 to TM3, transfer data is stored at addresses 0 to 31 in the areas of the memory blocks BKa and BKb. Write masking is applied to memory blocks BKc and BKd. In this case, data writing may be performed on memory blocks BKc and BKd. Since the data written in the memory blocks BKc and BKd is rewritten by the data transferred from the next 33rd cycle to the 64th cycle, there is no problem (in this case, for the memory blocks BKa and BKb, Mask is applied).

  FIG. 11 is a diagram showing a storage position of data transferred to the orthogonal transformation memories TM0 to TM3 through the system bus from the 33rd cycle to the 64th cycle. As shown in FIG. 11, in the 2-port orthogonal transformation memories TM0 to TM3, data are sequentially stored in the memory blocks BKc and BKd from addresses 0 to 31. In this case, each of the 2-port orthogonal transformation memories TM0 to TM3 is enabled to be written according to the write enable signal SWE (WE0 to WE3), so that writing to the memory blocks BKa and BKb is performed according to the data mask signal DM (SDM). Is prohibited. As a result, the data transferred from the first cycle to the 32nd cycle is securely held.

  Accordingly, 64-bit data of 64 system addresses transferred from the SDRAM 4 over 64 cycles are distributed and stored in the orthogonal transformation memories TM0 to TM3 of 31 addresses in the orthogonal transformation circuit, and equivalently, the orthogonal transformation memory TM0- As a whole, TM3 is accessed as a 64-bit memory having a 64-bit width from the system side.

  FIG. 12 is a timing chart showing a data writing sequence to orthogonal transformation memories TM0 to TM3 at the time of 16-bit data transfer. As shown in FIG. 12, in the 16-bit mode in which 16-bit data is transferred, four 16-bit data are stored at a time via the 64-bit internal system bus. In the first transfer cycle of the transfer clock signal TCLK, data 0 and 1 are stored in the orthogonal transform memory TM0, and data 2 and 3 are stored in the orthogonal transform memory TM1 in the next transfer cycle. In this system cycle, the orthogonal transformation memories TM2 and TM3 are in a disabled state.

  In the next system cycle, data 4-7 is transferred along with address 1. In this cycle, the orthogonal transformation memories TM0 and TM1 are disabled, and data 4, 5 and 6, 7 are stored for address 1 of the orthogonal transformation memories TM2 and TM3, respectively.

  Data 8-11 at address 2 transferred in the next system cycle is written into the address 2 position of orthogonal transform memories TM0 and TM1. In this cycle, the orthogonal transformation memories TM2 and TM3 are in a disabled state.

  That is, when the transfer data is 16-bit data, the set of orthogonal transform memories TM0 and TM1 and the set of orthogonal transform memories TM2 and TM3 are alternately enabled for each system cycle to write data.

  Since the data storage state in the 16-bit mode is obtained by regarding the area shown by hatching in FIG. 11 as a 32-bit area, that figure is omitted.

  In the 16-bit mode, by alternately accessing the orthogonal transform memories TM0 and TM1 and the orthogonal transform memories TM2 and TM3, for example, even when 12-bit data excluding parity is transferred, the data is aligned and 12 for each address. Bit data can be stored.

  FIG. 13 schematically shows an arrangement of data stored in orthogonal transform memories TM0 to TM3 when transferring 32-bit data. In FIG. 13, when storing 32-bit data, data 0-63 are alternately stored in the 2-port orthogonal transformation memories TM0 and TM1. In this case, the two-port orthogonal transformation memories TM2 and TM3 are maintained in the write prohibited state (the write enable signal is inactive). Data 64-127 are alternately stored in the 2-port orthogonal transformation memories TM2 and TM3.

  FIG. 14 is a timing chart showing a writing sequence to the orthogonal transformation memories TM0 to TM3 when transferring 32-bit data. In FIG. 14, 32-bit data 0 and 1 are transferred together with address 0 from the system side. The orthogonal transform memories TM0 and TM1 are sequentially enabled in synchronization with the transfer clock signal TCLK, and these data 0 and 1 are stored at address 0 of the orthogonal transform memories TM0 and TM1. At this time, the orthogonal transformation memories TM2 and TM3 are in a disabled state.

  In the next system cycle, 32-bit data 2 and 3 are transferred together with address 1. The orthogonal transformation memories TM0 and TM1 are sequentially enabled according to the transfer clock signal TCLK, and data 2 and 3 are stored in the respective addresses 1. Also in this system cycle, the orthogonal transformation memories TM2 and TM3 are in a disabled state. Thereafter, this operation is repeated 32 cycles, and when the address transferred from the system is 31, data 62 and 63 are stored in the address 31 of the orthogonal transformation memories TM0 and TM1.

  In the next cycle, when the address transferred from the system side becomes 32, the orthogonal transformation memories TM0 and TM1 are maintained in a disabled state in the subsequent 32 cycles, and the address 0 is transmitted to the orthogonal transformation memories TM2 and TM3. The transfer data 64-127 are sequentially stored at positions 31 to 31.

  When storing 64-bit data, data is stored by expanding 32-bit data in 32-bit mode for transferring 32-bit data to 64-bit data. The internal data bus is 32 bits wide, and the write sequence of 32-bit data and 64-bit data is the same. The high-order 32-bit data of 64-bit data is stored in the orthogonal transformation memories TM0 and TM2, and the low-order 32-bit data of 64-bit data is stored in the orthogonal transformation memories TM1 and TM3. In the 64-bit mode in which 64-bit data is transferred, 64-bit data at 64 addresses is sequentially stored in the orthogonal transformation memories TM0, TM1, TM2, and TM3.

  FIG. 15 is a diagram schematically showing a configuration of a main part of system bus side control unit 60 included in orthogonal transform circuit 40 shown in FIG. In FIG. 15, the system bus side control unit 60 includes a data register 100 that stores 64-bit data from the system bus I / F 24, an address register 102 that stores a 6-bit address from the system bus I / F 24, and a system bus. And a bit width setting register 104 for storing information indicating the bit width of the transfer data. An internal transfer path is set according to the bit width information.

  The data register 100 includes registers REG0 to REG3 each having a bit width of 16 bits. Data from the most significant bit MSB to the least significant bit LSB is stored from the register REG0 toward the register REG3. The address register 102 stores a 6-bit address A5-A0 in which the most significant bit MSB is the address bit A5 and the least significant bit LSB is the bit A0. With this 6-bit system address, 64 addresses are designated.

  Selectors SL0-SL3 are provided corresponding to registers REG0-REG3, respectively. Selectors SL0 and SL1 are formed of, for example, tristate buffers, and couple registers REG0 and REG1 to 16-bit data buses 50U and 50L, respectively, when switching signal MX0 is activated. Here, the 16-bit data buses 50U and 50L are an upper data bus and a lower data bus of the internal data bus 50, respectively. Selectors SL2 and SL3 couple registers REG2 and REG3 to 16-bit data buses 50U and 50L, respectively, when switching signal MX1 is activated.

  By switching the conduction / non-conduction state of these selectors SL0-SL3 by switching signals MX0 and MX1, 64-bit data can be transmitted to data bus 50 by 32-bit data.

  The system bus side controller 60 further includes selectors SSL0 to SS1L3 for setting data transfer paths corresponding to the 2-port orthogonal transformation memories TM0 to TM3. Selector SSL0 couples one of 16-bit data buses 50U and 50L to lower 16-bit port L of corresponding orthogonal transformation memory TM0 according to the bit width information from bit width setting register 104. The upper 16-bit port U of the orthogonal transformation memory TM0 is coupled to the 16-bit data bus 50U.

  The selector SSL1 couples one of the 16-bit data buses 50U and 50L to the upper 16-bit port U of the corresponding 2-port orthogonal transformation memory TM1 according to the bit width information from the bit width setting register 104. The lower 16-bit port L of the orthogonal transformation memory TM1 is coupled to the 16-bit data bus 50L.

  Selector SSL2 selects one of 16-bit data buses 50U and 50L according to the bit width information, and couples it to lower 16-bit port L of 2-port orthogonal transformation memory TM2. The upper 16-bit port U of the orthogonal transformation memory TM2 is coupled to the 16-bit data bus 50U. The selector SSL3 couples one of the 16-bit data buses 50U and 50L to the upper 16-bit port U of the 2-port orthogonal transformation memory TM3 according to the bit width information. The lower 16-bit port L of the orthogonal transformation memory TM3 is coupled to the 16-bit data bus 50L.

  By switching the data bus connection in units of 16 bits using these selectors SSL0 to SSL3, the transfer data is stored sequentially in the same address of these orthogonal transformation memories TM0 to TM3 accurately according to the bit width of the transfer data. can do.

  A selector SL4 is provided for the address register 102 to specify an address corresponding to the bit width of the transfer data. The selector SL4 selects one of the upper 5-bit address A5-A1 and the lower 5-bit address A4-A0 according to the bit width information from the bit width setting register 104, and generates the internal address AD [4: 0].

  FIG. 16 is a diagram illustrating a bus connection mode in the 8-bit mode and the 16-bit mode of the selectors SSL0 to SSL3 of the system bus side control unit 60 illustrated in FIG. In the 8-bit mode and the 16-bit mode, that is, when the bit width of the transfer data is 8 bits and 16 bits, the selectors SSL0 and SSL2 respectively select the 16-bit data bus 50U and the corresponding orthogonal transformation memory Coupling to the lower 16-bit port L of TM0 and TM2. On the other hand, selectors SSL1 and SSL3 couple 16-bit data bus 50L to upper 16-bit port U of corresponding orthogonal transformation memories TM1 and TM3 in the 8-bit mode and 16-bit mode.

  Therefore, the upper 16-bit bus 50U data is stored in the orthogonal transformation memories TM0 and TM2, and the lower 16-bit bus data is stored in the orthogonal transformation memories TM1 and TM3.

  The selector SL4 selects the lower 5-bit address A4-A0 of the 6-bit address transferred from the system side as the internal address AD [4: 0] in the 8-bit mode. Accordingly, in the 8-bit mode, the internal address AD [4: 0] is updated from 0 to 31 similarly to the address from the system side, and when the system address is 32 to 63, the addresses 0 to 31 are designated again. As a result, as shown in FIGS. 9 to 11, in the orthogonal transformation memories TM0 to TM3, after data is stored in the first half of each address, the data can be stored in the second half of each address.

  In the 16-bit mode, the upper 5-bit address A5-A1 of the 6-bit address transferred from the system side is selected. Therefore, the value of the internal address AD [4: 0] is updated by 1 every two system cycles. Thereby, in the 16-bit mode, 16-bit data can be stored in the orthogonal transformation memories TM0 to TM3 in the sequence shown in FIG.

  FIG. 17 is a diagram showing a bus connection mode in the 32-bit mode and 64-bit mode of selectors SSL0 to SSL3 shown in FIG. In the 32-bit mode and the 64-bit mode, the bit width of the transfer data is 32 bits and 64 bits, respectively. In these modes, selectors SSL0 and SSL2 couple 16-bit data bus 50L to lower 16-bit port L of corresponding orthogonal transformation memories TM0 and TM2. Selectors SSL1 and SSL3 couple 16-bit data bus 50U to upper 16-bit ports U of corresponding orthogonal transformation memories TM1 and TM3, respectively. Accordingly, the 32-bit data of the 32-bit data bus 50 is transferred to each of the orthogonal transformation memories TM0 to TM3.

  At this time, the selector SL4 selects the lower 5-bit address A4-A0 among the address bits A5-A0 stored in the address register 102. In these 32-bit mode and 64-bit mode, 32-bit data is sequentially stored in the orthogonal transformation memories TM0 and TM1, and after the address areas of these orthogonal transformation memories TM0 and TM1 are all designated and stored, Next, data access is performed on the orthogonal transformation memories TM2 and T3. Thereby, the data access sequence in the 32-bit mode or 64-bit mode shown in FIGS. 13 and 14 can be realized.

  FIG. 18 is a diagram illustrating an example of a configuration of a portion that generates switching signals MX0 and MX1 for switching registers in the system bus side control unit 60. In FIG. In FIG. 18, the switching signal generator includes an inverter 112 that receives system clock signal SCLK, an AND gate 114 that receives a write command WEN indicating a write instruction from the system side and system clock signal SCLK, and an output of inverter 112. An AND gate 116 receiving the signal and write instruction WEN is included. The control unit 60 is also provided with a frequency dividing circuit 110 that divides the system clock signal SCLK to generate the transfer clock signal TCLK. The AND circuit 114 outputs a switching signal MX0, and the AND gate 116 outputs a switching signal MX1.

  FIG. 19 is a timing chart showing the operation of the switching signal generator shown in FIG. The operation of the switching signal generator shown in FIG. 18 will be described below with reference to FIG.

  The frequency dividing circuit 110 divides the system clock signal SCLK and generates a transfer clock signal TCLK having a cycle that is ½ times the system clock SCLK. When write instruction WEN from the system side is asserted to instruct data writing, AND gates 114 and 116 are enabled. Switching signal MX0 changes in synchronization with system clock signal SCLK, and switching signal MX1 changes in synchronization with the inverted signal of system clock signal SCLK. Therefore, upper 32-bit data UD (32) of 64-bit data D (64) is transmitted on data bus 50 while switching signal MX0 is at the H level, and data is transmitted while switching signal MX1 is at the H level. The low-order 32-bit data LD (32) of the 64-bit data D (64) is transmitted to the bus 50. By using switching signals MX0 and MX1, selectors SL0-SL3 shown in FIG. 15 are selectively turned on, and 64-bit data is transferred on data bus 50 in units of 32 bits within one cycle of system clock signal SCLK. Can be communicated to.

  FIG. 20 is a diagram schematically showing a configuration of a portion for generating a write control signal in system bus side control unit 60. In FIG. 20, system bus side control unit 60 includes selection circuits 120-123 provided corresponding to 2-port orthogonal transformation memories TM0-TM3, respectively. These selection circuits 120-123 are commonly provided with a write instruction WEN from the system side and bit width information from the bit width setting register 104 in common. When write instruction WEN is asserted, these selection circuits 120-123 perform a selection operation according to the bit width information from bit width setting register 104. Bit width information may be set in the bit width setting register 104 in accordance with control information from the system side, or the bit width information may be set by the controller 22 shown in FIG.

  Each of these selection circuits 120-123 includes an 8-bit mode control terminal, a 16-bit mode control terminal, and a 32 / 64-bit mode control terminal and a reset terminal R for setting a reset state. The 32 / 64-bit mode control terminal is a terminal for receiving a write control signal in the 32-bit mode and the 64-bit mode. According to the signals applied to these terminals, the activation sequence of the orthogonal transformation memories TM0 to TM3 can be set according to the bit width of the data at the time of data transfer, and data can be written accurately according to the bit width. it can.

  The selection circuit 120 receives the complementary switching control signal / MX0 at the 8-bit mode control terminal and the output signal of the OR gate G0 receiving the least significant address bit A0 and the switching control signal / MX0 at the 16-bit mode control terminal. receive. Select circuit 120 further receives at its 32 / 64-bit mode control terminal an output signal of OR gate G1 receiving complementary switching control signal / MX0 and most significant address bit A5. The reset terminal R receives a “1” signal indicating a disabled state. From this selection circuit 120, a write enable signal / WE0 for the orthogonal transformation memory TM0 is given.

  Note that the symbol “/” added in front of each signal indicates a negative logic signal that is activated when it is “0”. The write enable signal / WENi (i = 0-3) corresponds to the write enable signal SWE shown in FIG. 5, but the symbol “/ WENi” is used here in order to clarify the logic of the signal.

  The selection circuit 121 receives the complementary switching control signal / MX0 at the 8-bit mode control terminal and the output signal of the OR gate G2 receiving the least significant address bit A0 and the complementary switching control signal / MX1 at the 16-bit mode control terminal. Receive. The selection circuit 121 further receives the output signal of the OR gate G3 receiving the complementary switching control signal / MX1 and the complementary most significant address bit / A5 at the 32 / 64-bit mode control terminal, and receives “1” at the reset terminal R. ”Is received.

  Selection circuit 122 receives complementary switching control signal / MX1 at the 8-bit mode input terminal and OR gate G4 receiving complementary least significant address bit / A0 and complementary switching control signal / MX0 at the 16-bit mode control terminal. The output signal is received. The selection circuit 122 further receives an output signal of the OR gate G5 receiving the complementary switching control signal / MX0 and the complementary most significant address bit / A5 at the 32 / 64-bit mode control terminal. 1 "signal is received. A write enable signal / WE2 is applied from the selection circuit 122 to the orthogonal transformation memory TM2.

  Select circuit 123 receives complementary switching control signal / MX1 at the 8-bit mode control terminal, and OR gate G6 receiving complementary least significant address bit / A0 and complementary switching control signal / MX1 at the 16-bit mode control terminal. The output signal is received. The selection circuit 123 further receives the output signal of the OR gate G7 receiving the complementary switching control signal / MX1 and the complementary most significant address bit / A5 at the 32 / 64-bit mode control terminal, and “1” at the reset terminal. Receive the signal. From this selection circuit 123, a write enable signal / WE3 for the orthogonal transformation memory TM3 is generated.

  Further, system bus side control unit 60 sets "0" as a set of address bits A5 and / A5 according to bit width information from inverters IV1 and IV2 for inverting address bits A0 and A5, respectively, and bit width setting register 104. And a mask selection circuit 130 that selects one of the set of “0” and generates data mask signals DM0 and DM1. The mask selection circuit 130 selects one of the address bits A5 and “0” to generate the data mask signal DM0 for the upper 16-bit data, and one of the complementary most significant address bits / A5 and “0”. And a switching circuit MUX1 for generating a data mask signal DM1 for lower 16-bit data.

  These data mask signals DM0 and DM1 are commonly applied to the orthogonal transformation memories TM0 to TM3. Select circuit 130 generates data mask signals DM0 and DM1 in accordance with address bits A5 and / A5 when the 8-bit mode is specified, and selects “0” in the 16-bit mode and the 32 / 64-bit mode to select data Mask signals DM0 and DM1 are generated.

  FIG. 21 to FIG. 23 are timing charts showing the data write control operation of the system bus side controller 60 shown in FIG. Hereinafter, the operation of the system bus side controller 60 shown in FIG. 20 will be described with reference to FIGS.

  First, the operation in the 8-bit mode will be described with reference to FIG. In this case, selection circuits 120 and 121 select complementary switching control signal / MX0 as write enable signals / WE0 and / WE1. Selection circuits 122 and 123 select complementary switching control signal / MX1 as write enable signals / WE2 and / WE3.

  Therefore, when a data write instruction is first given and write instruction WEN is asserted, switching control signals MX0 and MX1 change in complementary phases in synchronization with system clock signal SCLK in that cycle. In cycles 0 to 31, the most significant address bit A5 is “0”. The lowest address bit A0 alternately changes to “0” and “1” for each cycle of the system clock signal SCLK. Write enable signals / WE0 and / WE1 are activated to L level ("0") when switching signal MX0 is at H level, and writing to corresponding orthogonal transformation memories TM0 and TM1 is permitted. Write enable signals Write enable signals / WE2 and / WE3 are activated and L level ("0") when switching signal MX1 is at H level, and writing to corresponding orthogonal transformation memories TM2 and TM3 is permitted. .

  Data mask signals DM0 and DM1 are generated by select circuit 130 according to most significant address bit A5 and complementary most significant address bit / A5, respectively, in the 8-bit mode. Therefore, during cycles 0 to 31, the data mask signal DM0 is at the L level (“0”), and the data mask signal DM1 is at the L level (“1”). That is, during cycle 0 to cycle 31 of system clock signal SCLK, the set of orthogonal transform memories TM0 and TM1 and the set of orthogonal transform memories TM2 and TM3 are alternately activated in the same cycle, and data is stored in the upper 16-bit area. Is written. Writing is masked in the lower 16-bit area.

  When the cycle 32 is reached, the most significant address bit A5 becomes “1” (H level), and accordingly, the data mask signal DM0 becomes H level and the data mask signal DM1 becomes L level. Data mask signals DM0 and DM1 mask writing when they are at the H level. Therefore, from cycle 32, data is written into the lower 16-bit area of orthogonal transform memory TM0-TM3, and no data is written into the upper 16-bit area.

  From cycle 32 to subsequent cycle 63, as in cycle 0 to cycle 31, the set of orthogonal transform memories TM0 and TM1 and the set of orthogonal transform memories TM2 and TM3 are alternately activated in each cycle of system clock SCLK. .

  As described above, in the 8-bit mode, data can be written into the orthogonal transform memories TM0 to TM3 by 16 bits every cycle of the system clock SCLK.

  FIG. 22 is a timing chart showing the operation in the 16-bit mode of the system side control unit 60 shown in FIG. In the 16-bit mode, selection circuit 120 generates write enable signal / WE0 according to the logical sum signal of least significant address bit A0 from OR gate G0 and complementary switching control signal / MX0, and selection circuit 121 Write enable signal / WE1 is generated in accordance with the logical sum signal of lower address bit A0 and complementary switching control signal / MX1. Select circuit 122 generates write enable signal / WE2 in accordance with the logical sum signal of complementary least significant address bit / A0 and complementary switching control signal / MX0, and selector circuit 123 complements complementary least significant address bit / A0. The write enable signal / WE3 is generated according to the logical sum of the switching control signal / MX1.

  Therefore, when write instruction WEN is asserted and data writing is started, in cycle 0, write enable signals / WE0 and / WE1 are activated according to switching control signals MX0 and MX1, respectively. At this time, write enable signals / WE2 and / WE3 are at the H level (“1”) in the inactive state. In cycle 1, the least significant address bit A0 becomes “1”, and the write enable signals / WE0 and / WE1 are maintained at “1”. In cycle 1, write enable signals / WE2 and / WE3 are activated according to switching control signals MX0 and MX1, respectively. Thereafter, at even addresses (even-numbered system cycles), write enable signals / WE0 and / WE1 are sequentially activated according to switching control signals MX0 and MX1, and at odd addresses (odd-numbered system cycles), write enable is performed. Signals / WE2 and / WE3 are sequentially activated in accordance with switching control signals MX0 and MX1, respectively.

  Data mask signals DM0 and DM1 are fixed to “0” in the 16-bit mode. Therefore, 32-bit data is written to each of orthogonal transform memories TM0 to TM3. For the set of orthogonal transform memories TM0 and TM1 and the set of orthogonal transform memories TM2 and TM3, 64-bit data is alternately written every clock cycle of the system clock signal CLK.

  FIG. 23 is a timing chart showing the operation of the system bus side control unit 60 shown in FIG. 20 in the 32 / 64-bit mode. In the 32 / 64-bit mode, the data bit width is 32 bits or 64 bits. In this 32 / 64-bit mode, selection circuit 120 generates write enable signal / SE0 in accordance with the logical sum of most significant address bit A5 and complementary switching control signal / MX0, and selection circuit 121 has most significant address bit A5. The write enable signal / WE1 is generated according to the logical sum of the complementary control signal / MX1. Select circuit 122 generates write enable signal / WE2 in accordance with the logical sum of complementary most significant address bit / A5 and complementary switching control signal / MX0, and select circuit 123 selects complementary most significant address bit / A5 and complementary A write enable signal / WE3 is generated in accordance with the logical sum of the switching control signal / MX1. Therefore, during cycles 0 to 31, the most significant address bit A5 is “0”, the write enable signals / WE2 and / WE3 are maintained at “1”, and data writing to the orthogonal transformation memories TM2 and TM3 is not performed. It is forbidden. On the other hand, write enable signals / WE0 and / WE1 are activated in each clock cycle in accordance with switching control signals MX0 and MX1, and 32-bit data is alternately written into orthogonal transformation memories TM0 and TM1. .

  On the other hand, in cycle 32, the most significant address bit A5 becomes “1”, and the write enable signals / WE0 and / WE1 are maintained at “1”. On the other hand, write enable signals / WE2 and / WE3 are sequentially activated according to switching control signals MX0 and MX1. Therefore, in the 32 / 64-bit mode, data is written to the orthogonal transformation memories TM0 and TM1, and after 32 pieces of data (32-address data) are stored in the orthogonal transformation memories TM0 and TM1, The subsequent 32 address data is written into the orthogonal transformation memories TM2 and TM3.

  As described above, the orthogonal transformation memories TM0 to TM3 operate as a memory of 64 words × 64 bits as a whole, and data with a data bit width of 8, 16, 32, and 64 bits is externally applied. It is possible to write 64-bit data at 64 addresses without considering the internal configuration and internal address.

  As shown in parentheses in FIG. 20, when reading data from the orthogonal transformation memories TM0 to TM3, a read instruction (REN) is given instead of the write instruction WEN. In this case, Instead of the write enable signals / WE0− / WE3, read enable signals (/ RE0− / RE3) are generated. In this case, as will be described below, selection circuits 120-123 can be commonly used for data writing and reading.

  FIG. 24 is a diagram showing an example of the configuration of a portion that performs writing / reading in the system bus side control unit 60. FIG. 24 representatively shows a configuration of selection circuit 120 provided for orthogonal transformation memory TM0. In FIG. 24, a selection signal SEL requesting data transfer and bit width information are given to the selection circuit 120. This selection signal SEL is a signal that requests data writing or data reading, and corresponds to the selection signal SSEL from the system side shown in FIG.

  OR gates G8 and G9 are provided at the output of the selection circuit 120. The OR gate G8 receives the complementary write instruction / WEN which is an inverted signal of the write instruction WEN and the output signal of the selection circuit 120, and generates a write enable signal / WE0. OR gate G9 receives complementary read instruction / REN which is an inverted signal of read instruction REN and the output signal of selection circuit 120, and generates read enable signal / RE0. Write instruction WEN and read instruction REN are at the H level (“1”) when asserted, while write enable signal / WE0 and read enable signal / RE0 are at the L level (“0”) when activated. is there.

  When writing is performed, write enable signal / WE0 is activated when complementary write instruction / WEN is at L level and the output signal of selection circuit 120 is at L level. At this time, read instruction WEN is negated and at L level, and read enable signal / RE0 is maintained at H level. On the other hand, when data is read, read instruction REN is asserted to become H level, while write instruction WEN is in the negated L level. Therefore, when the output signal of selection circuit 120 becomes L level, read enable signal / RE0 becomes L level and is activated to read data. Data mask signals DM0 and DM1 can be used in common during writing and reading.

  By using the configuration shown in FIG. 24, data writing and data reading can be executed in the same control mode by using a common control circuit configuration only by reversing the data flow.

  FIG. 25 schematically shows a configuration of main arithmetic circuit side control unit 65 for transferring data between 2-port orthogonal transform memories TM0 to TM3 and the memory cell mat of the main arithmetic circuit. In FIG. 25, a 64-bit data bus 55 for performing data transfer between the orthogonal transform circuit and the main arithmetic circuit has 16-bit data buses 150a to 150d. The main arithmetic circuit side control unit 65 is provided with bus selectors 140a-140c and 142a-142c for switching the bus connection paths according to the bit width information M8 / 16, corresponding to the 2-port orthogonal transformation memories TM0-TM3. Selector 140a couples lower 16-bit port L of 2-port orthogonal transformation memory TM0 to one of 16-bit data buses 150a and 150b. The 16-bit port U of the orthogonal transformation memory TM0 is coupled to the 16-bit data bus 150a. These 16-bit data buses 150a and 150b form an upper 32-bit data bus of the 64-bit data bus.

  Bus selector 140b couples upper 16-bit port U of orthogonal transformation memory TM2 to one of 16-bit data buses 150c and 150b. The bus selector 142c connects the lower 16-bit port L of the orthogonal transformation memory TM2 to any of the 16-bit data buses 150c, 150b, and 150d.

  The bus selector 142a couples the upper 16-bit port U of the orthogonal transformation memory TM1 to any of the 16-bit data buses 150b, 150c and 150a. The bus selector 142b couples the lower 16-bit port L of the orthogonal transformation memory TM1 to any of the 16-bit data buses 150a, 150d, and 150b.

  Bus selector 140c couples upper 16-bit port U of orthogonal transformation memory TM3 to one of 16-bit data buses 150d and 150c. The lower 16-bit port L of the orthogonal transformation memory TM3 is coupled to the 16-bit data bus 150d.

  The connection path of these bus selectors 140a-140c and 142-142c is set according to the bit width information BWS. Bit width information BWS designates any of 8-bit mode, 16-bit mode, 32-bit mode, and 64-bit mode.

  FIG. 26 is a diagram schematically showing a configuration of a portion that performs data transfer control of the main arithmetic circuit side control unit 65. In FIG. 26, the main operation side control unit 65 includes a status register 162 for storing status information indicating a transfer state, a transfer address generation circuit 164 for generating an address MADD for the orthogonal transformation memories TM0 to TM3, and these orthogonal transformation memories. And a transfer control circuit 166 for controlling access of TM0 to TM3.

  Transfer address generation circuit 164 includes a transfer address counter, and generates transfer address MADD in a sequence set according to the bit width information stored in bit width setting register 160 when read instruction MREN is asserted. The transfer address MADD from the transfer address generation circuit 164 is updated according to the status update of the status register 162. Read instruction MREN is given from the main arithmetic circuit.

  When the read instruction MREN is asserted, the transfer control circuit 166, according to the transfer address MADD generated by the transfer address generation circuit 164 and the bit width setting information from the bit width setting register 160, transfers the transfer enable signal MRE0- to the orthogonal transformation memories TM0 to TM3. MRE3 and 16-bit unit transfer mask signals MDM0 and MDM1 are selectively generated.

  The main arithmetic circuit side control unit 65 further counts the data transfer clock signal MTCLK to generate an address for data transfer with the memory cell mat, and update data for the 64-bit buffer 68. And a transfer data selection circuit 172 for generating 64-bit transfer data for the main arithmetic circuit according to the data from the 64-bit buffer 68 and the data from the data bus 55.

  The buffer update circuit 170 selectively executes (alternately executes) the update of all the bits and 32 bits of the 64-bit buffer 68 according to the count value WCNT [0] of the mat transfer address counter 168. The transfer data selection circuit 172 follows the count value WCNT [0] from the mat transfer address counter 168 and sets the 32-bit data of the 64 data bus 55 and the 32-bit data from the 64-bit buffer memory 68, and the 64-bit buffer memory 68. Is selected to generate transfer data for the main arithmetic circuit.

  FIG. 27 is a diagram showing an example of the configuration of transfer address generation circuit 164 shown in FIG. In FIG. 27, the transfer address generation circuit 164 includes a 6-bit transfer counter RCNT that counts the number of data transfer cycles, an inverter IV3 that inverts the count bit RCNT [2] of the transfer counter RCNT, and the least significant bit of the transfer counter RCNT. An inverter IV4 that inverts RCNT [0], and an address selection circuit 180 that generates a transfer address MADD by selecting a combination of count bits according to each data bit width according to the bit width setting information BWS from the bit width setting register 160 Including. By rearranging the count bits by the address selection circuit 180, an address corresponding to the data bit width can be generated accurately.

The address selection circuit 180 receives the count bit RCNT [! Of the transfer counter RCNT at the 8-bit mode input terminal. 2 ,! 0; 5: 3]. The symbol “!” Means an inverted value of the count bit. In the 8-bit mode, the inverted value of the count bit RCNT [2] of the transfer counter, the inverted value of RCNT [0], and RCNT [5: 3] are sequentially provided. Arranged to generate a forwarding address. In 8-bit mode, the transfer address changes as follows for each transfer cycle:
24, 16, 24, 16, 8, 0, 8, 0, 25, 17, 25, 17,.

  That is, in the 8-bit mode, data 0-512 are sequentially read from the least significant bit of 8-bit data in the orthogonal transformation memory to transfer the data.

The address selection circuit 180 receives the count value RCNT [!] Of the transfer counter RCNT at the 16-bit mode input terminal. 0; 5: 2]. This count value RCNT [! 0; 5: 2] indicates an inverted value of the count value RCNT [0] and a 5-bit count value in which RCNT [5: 2] are sequentially arranged, and the transfer address changes as follows for each transfer cycle. :
16, 0, 16, 0, 17, 1, 17, 1,.

  That is, in the 16-bit mode, data 0-256 is sequentially transferred from the least significant bit of 16-bit data.

Address selection circuit 180 further receives 5-bit count value RCNT [4: 0] of transfer counter RCNT at a 32 / 64-bit input terminal indicating 32-bit and 64-bit modes. In this case, the address RCNT [4: 0] changes as follows for each transfer cycle:
0, 1, 2, ... 31, 0, 1, 2, ... 31.

  Therefore, in the 32-bit mode and the 64-bit mode, the first half data and the second half data of data 0-63 are transferred from the least significant bit in a set of two orthogonal transformation memories.

  FIG. 28 schematically shows an example of the configuration of transfer control circuit 166 shown in FIG. In FIG. 28, the transfer control circuit 166 includes an inverter IV5 that receives the most significant count bit RCNT [5] of the transfer counter RCNT, a read activation circuit 182a-182d provided for each of the orthogonal transformation memories TM0 to TM3, A transfer mask generation circuit 184 provided in common to conversion memories TM0 to TM3 is included.

  These read activation circuits 182a-182d and transfer mask generation circuit 184 correspond to the bit corresponding to bit width setting information BWS when data transfer instruction MREN is asserted from orthogonal transformation memories TM0-TM3 to the memory cell mat of the main arithmetic circuit. A read enable signal for activating the read operation is selected by selecting a signal applied to the mode input. As a result, the orthogonal transform memories TM0 to TM3 can be activated in a sequence according to the data bit width, and data transfer can be activated.

  Read activation circuit 182a receives a "0" signal at the 8 / 16-bit mode input terminal, receives the most significant count bit RCNT [5] of transfer counter RCNT at the 32-bit mode input terminal, and receives a 64-bit mode input. The terminal receives the inverted count bit / RCNT [5] from the inverter IV5 and generates a negative logic read enable signal / MRE0 for the orthogonal transformation memory TM0.

  Read activation circuit 182b receives a signal of "0" at the 8 / 16-bit mode input terminal, receives count value RCNT [5] at the 32-bit mode input terminal and the 64-bit input terminal, and outputs to orthogonal transform memory TM1. A negative logic read enable signal / MRE1 is generated.

  Read activation circuit 182c receives a "0" signal at the 8 / 16-bit mode input terminal, receives the inverted count bit / RCNT [5] from inverter IV5 at the 32-bit mode input terminal, and receives the 64-bit mode input. The terminal receives the count value RCNT [5] and generates a read enable signal / MRE2 for the orthogonal transformation memory TM2.

  Read activation circuit 182d receives a "0" signal at the 8 / 16-bit mode input terminal, receives the inverted count bit / RCNT [5] at the 32-bit mode input terminal, and count bit RCNT at the 64-bit mode input terminal. In response to [5], the read enable signal / MRE3 for the orthogonal transform memory TM3 is generated.

  Transfer mask generation circuit 184 receives count values RCNT [1] and / RCNT [1] at the 8 / 16-bit mode input terminal, receives a signal of “0” at the 32 / 64-bit mode input terminal, and receives the upper bit A transfer mask signal MDM0 and a lower bit mask control signal HDM1 are generated. In the 8 / 16-bit mode, these transfer mask signals MDM0 and MDM1 are generated according to the count bits RCNT [1] and / RCNT [1], respectively, and in the 32-bit and 64-bit modes, the transfer mask signals MDM0 and MDM1 Is set to “0”, the read mask of the orthogonal transformation memories TM0 to TM3 is maintained in an inactive state, and the mask operation is stopped.

  FIG. 29 schematically shows an example of the configuration of buffer update circuit 170 and transfer data selection circuit 172 shown in FIG. In FIG. 29, the 64-bit buffer 68 includes an upper 32-bit area 68U for storing upper 32 bits and a lower 32-bit area 68L for storing lower 32 bits.

  The buffer update circuit 170 receives the bus value according to the count value WCNT [0] from the mat transfer address counter 168 and the 32 / 64-bit width instruction signal BWS32 / 64 indicating the 32-bit and 64-bit data widths from the bit width setting register 160. A bus switching circuit 190 for switching the connection is included. The bus switching circuit 190 passes 64-bit data from the 64-bit bus 55 regardless of the value of the count value WCNT [0] when the 32 / 64-bit width instruction signal BWS32 / 64 is activated. On the other hand, bus switching circuit 190 operates in accordance with count value WCNT [0] from mat transfer address counter 168 when 32/64 bit width instruction signal BWS32 / 64 is inactive, that is, in the 8-bit mode and 16-bit mode. One of the set of 32-bit data from the 64-bit data on the bit data bus 55 and the 32-bit sub data bus 150SL and the lower 32-bit area 68L of the buffer 68 is selected and transmitted to the 64-bit buffer 68.

  The sub data bus 150SL is composed of lower 8-bit buses of the 16-bit data buses 150a to 150d constituting the 64-bit data bus 55. When the count value WCNT [0] is “1”, the bus switching circuit 190 sets the 32 bits from the lower 32-bit area 68L to the upper side, and sets the 32 bits from the 32-bit data bus 150SL to the lower 32-bit area 68L. To the 64-bit buffer 68. Thereby, updating and rearranging of data in the buffer 68 are executed.

  The transfer data selection circuit 172 receives the 64-bit data from the buffer 68 according to the count value WCNT [0] from the transfer address counter 168 and the 64-bit width instruction signal BWS64, and the 32-bit and 64-bit buffers 68 on the sub data bus 150SU. It includes a bus switching circuit 192 that selects one of the sets of 32-bit data from the upper 32-bit area 68U and transmits it to the main arithmetic circuit I / F. The sub data bus 150SU is composed of a data bus of upper 8 bits of each of the 16-bit data buses 150a to 150d.

  When the count value WCNT [0] is “1”, the bus switching circuit 192 selects 32-bit data from the upper 32-bit area 68U of the buffer 68 and data on the 32-bit sub data bus 150SU. In the bus switching circuit 192, the bus position may be switched by wiring so that the data from the upper 32-bit area 68L and the data from the sub-data bus 150SU are continuously arranged in numerical order, and the data bus The data may be transferred without changing the arrangement. In the memory cell mat in the main arithmetic circuit, arithmetic processing is executed for each entry. Therefore, if a set of data to be calculated is arranged in each entry, there is no particular problem.

  When 32-bit and 64-bit width instruction signal BWS32 / 64 is in the active state and the bit width of the transfer data is 32 bits or 64 bits, bus switching circuit 192 selects 64-bit data from 64-bit buffer 68. Then, the data is transferred to the main arithmetic circuit I / F.

  Note that data is transferred bidirectionally between the orthogonal transform circuit and the main arithmetic circuit. Therefore, the bus switching circuits 190 and 192 are constituted by bidirectional data transfer circuits such as CMOS transmission gates, and the 64-bit buffer is constituted by bidirectional registers. The data transfer direction of the bidirectional register is set according to the data transfer direction between the orthogonal transformation circuit and the main arithmetic circuit. Next, the operation in each transfer mode will be described.

A: 8-bit mode FIG. 30 is a diagram showing a connection path of bus selectors 140a to 140c and 142a and 142b in the 8-bit mode in which the transfer data is 8 bits wide. These bus selectors 140a-140c and 142a-142c have their connection paths set in accordance with 8 / 16-bit width instruction signal BWS8 / 16. The bit width instruction signal BWS8 / 16 is included in the bit width information provided from the bit width setting register 160 shown in FIG.

  The bus selector 140a couples the lower 16-bit port L of the orthogonal transformation memory TM0 to the 16-bit data bus 150a. Similarly, the upper 16-bit port U of the orthogonal transformation memory TM0 is coupled to the 16-bit data bus 150a. Bus selectors 140b and 1420c couple upper 16-bit port U and lower 16-bit port L of orthogonal transformation memory TM2 to 16-bit data bus 150c, respectively. Bus selectors 142a and 142b couple both upper 16-bit port U and lower 16-bit port L of orthogonal transform memory TM1 to 16-bit data bus 150b. The bus selector 140c couples the upper 16-bit port U of the orthogonal transformation memory TM3 to the 16-bit data bus 150d. The lower 16-bit port L of the orthogonal transformation memory TM3 is always coupled to the 16-bit data bus 150d. By the connection of the bus selector, transfer data is arranged on the 16-bit data buses 150a to 150d according to the transfer order.

  In this 8-bit mode, read activation circuits 182a-182d shown in FIG. 28 set read enable signals / MRE0- / MRE3 to the active state at all times when read instruction MREN is asserted. Therefore, data is read commonly to the orthogonal transformation memories TM0 to TM3. However, since data transfer mask signals MDM0 and MDM1 mask data transfer in units of 16 bits by transfer mask generation circuit 184, data reading is masked in units of 16 bits in orthogonal transform memories TM0 to TM3.

  FIG. 31 is a diagram schematically showing an arrangement of data stored in the orthogonal transformation memories TM0 to TM3 in the 8-bit mode. As shown in FIG. 31, in the 8-bit mode, 8-bit data 8k and 8k + 1 are stored in the orthogonal transformation memory TM0, and 8-bit data 8k + 2 and 8k + 3 are stored in the orthogonal transformation memory TM1. 8-bit data 8k + 4 and 8k + 5 are stored in the orthogonal transformation memory TM2, and 8-bit data 8k + 6 and 8k + 7 are stored in the orthogonal transformation memory TM3. Here, k is 0 to 63.

  Through the connection path of bus selectors 140a-140c and 142a-142c shown in FIG. 30, the orthogonal transformation memory TM0 transfers 16-bit data to and from the 16-bit bus 150a, and the orthogonal transformation memory TM1 is connected to the 16-bit bus 150b. 16-bit data is transferred between them, the orthogonal transformation memory TM2 transfers 16-bit data to and from the 16-bit bus 150c, and the orthogonal transformation memory TM3 transfers 16-bit data to and from the 16-bit bus 150d. To do. Therefore, in order to transfer 16-bit data in each orthogonal transform memory TM0 to TM3, data transfer mask signals MDM0 and MDM1 are commonly applied to orthogonal transform memories TM0 to TM3, and data access is controlled in units of 16 bits. Is done.

  FIG. 32 is a diagram showing transition of the data transfer status in the 8-bit mode. Status IDLE is in a standby state, and stops data access until a transfer instruction (read instruction MREN) is given. Status ST0 reads data from orthogonal transformation memories TM0 to TM3 when a data transfer instruction is given. In this case, the data read from the orthogonal transformation memories TM0 to TM3 is stored in the 64-bit buffer 68.

  Status ST1 reads data from orthogonal transformation memories TM0 to TM3 and the 64-bit buffer and transfers data to the main arithmetic circuit block. In this status ST1, half of the data read from the orthogonal transformation memory is stored in the 64-bit buffer 68, and the read data from the remaining half of the orthogonal transformation memory and the data stored in the 64-bit buffer 68 are applied to the main arithmetic circuit. It is done. At the time of transition from status ST0 to status ST1, the count value of the transfer counter RCNT is incremented by one. As described above, in the 8-bit mode, the count value RCNT [! 2 ,! 0; 5: 3] is used as the address. Accordingly, in the first cycle, the address 24 is designated in the orthogonal transformation memories TM0 to TM3.

  The status ST2 is data reading from the 64-bit buffer memory to the main arithmetic circuit block. In the status ST2, 64-bit data stored in the 64-bit buffer memory is transferred to the main arithmetic circuit. This completes the transfer of the data of one 64 pieces of data to the 1-bit main arithmetic circuit. This operation is repeated for each bit of data. The count value WCNT [0] of the mat transfer address counter 168 (see FIG. 26) is updated between the status ST1 and the status ST2.

  FIG. 33 is a diagram schematically showing the flow of data of status ST0. In this status ST0, the transfer of the upper 16 bits or lower 16 bits of the orthogonal transformation memories TM0 to TM3 is masked according to the data transfer mask signals MDM0 and MDM1. FIG. 33 shows an example in which the data transfer mask signal MDM0 is “0” and the data transfer mask signal MDM1 is “1”, and the masking state is set.

  In this case, in the orthogonal transformation memories TM0 to TM3, the upper 16-bit data of the memory block BKa is read to the 16-bit data buses 150a to 150d, respectively. The data read to these data buses 150a to 150d is stored in the 64-bit buffer 68 by the bus switching circuit 190 shown in FIG. 29 because the count value WCNT [0] of the mat transfer address counter is “0”. . At this time, the data stored in the 64-bit buffer 68 is selected by the bus switching circuit 192 in the status ST2 and transferred to the main arithmetic circuit.

  Therefore, in the status ST0, the data read from the orthogonal transformation memories TM0 to TM3 is not transferred to the main arithmetic circuit block, but is stored in the 64-bit buffer, and the read data from the direct conversion memory itself is the main arithmetic circuit. Is not forwarded to.

  FIG. 34 is a diagram schematically showing the flow of data in status ST1. In the status ST1, at the time of transition from the status ST0, the count value of the transfer address counter RCNT is updated by 1. In 8-bit mode, the count value RCNT [! 2 ,! 0; 5: 3] is used as an address, and when address 24 is specified in status ST0, address 16 is specified in status ST1. In this case, the memory block BKb is addressed in each of the orthogonal transform memories TM0 to TM3, and data reading is executed in each orthogonal transform memory. Also in this case, the count bit RCNT [1] is “0”, the transfer mask signals MDM0 and MDM1 are “0” and “1”, respectively, and the upper 16-bit area of the orthogonal transformation memories TM0 to TM3 That is, reading of data in the area of addresses 0 to 15 in the X direction is executed.

  The count value WCNT [0] of the transfer address counter 168 (see FIG. 26) is updated to “1”. Therefore, in this case, the bus switching circuit 190 shown in FIG. 26 selects the lower 8-bit data of each of the data buses 150 a to 150 d and the data stored in the lower area of the buffer 68 and stores them in the buffer 68. . Therefore, the 32-bit data written in the previous cycle is stored in the upper 16-bit area in the buffer 68, and the data in the area of addresses 8 to 15 in the X direction of the orthogonal transformation memories TM0 to TM3 is stored in the lower half of the buffer 68. Stored in a 32-bit area.

  In parallel with the data storage in the buffer 68, the upper 32-bit data of the buffer 68 and the data on the data bus 150UL, that is, the upper 8-bit data of the data buses 150a to 150d, that is, the orthogonal transformation memories TM0 to TM3 The upper 8-bit data of addresses 0 to 7 in the X direction is transferred to the main arithmetic circuit.

  The status ST2 is a state in which 64-bit data from the buffer 68 is transferred to the main arithmetic circuit, and the orthogonal transformation memory then returns to the status IDLE.

  In the next status ST0, the count bit RCNT [1] of the transfer address counter RCNT becomes “1”, and as shown in FIG. 35, the transfer mask instruction signals MDM0 and MHDM1 become “1” and “0”, respectively. . In this case, the area of addresses 0 to 15 in the X direction of the orthogonal transformation memories TM0 to TM3 is masked for access, and data in the areas of addresses 16 to 31 is transferred. In the transfer operation, the same operations as those shown in FIGS. 33 and 34 are repeated.

  Therefore, the data stored in the orthogonal transformation memories TM0 to TM3 are alternately read from the least significant bit of the even data and the odd data, and all the least significant bits of the data 0 to the data 511 are transferred, and then the data from the data 0 to the data again. The next upper bit [1] of 511 is transferred.

  FIG. 36 is a diagram showing the flow of data to the interface (I / F) bus connected to the orthogonal transform memory of data, the 64-bit buffer, and the main arithmetic circuit interface (I / F) in the 8-bit mode.

  In FIG. 36, the count value WCNT [0] of the mat transfer address counter repeats “0” and “1” for each data transfer cycle. The mat address MADD changes in the sequence of 24, 16, 24, 16, 25, 17,. In the 8-bit mode, as shown in FIG. 36, according to the count value of the transfer cycle, that is, the value of the count bit RCNT [1] of the transfer address counter, the transfer mask instruction signals MDM0 and MDM1 are “ Repeat “0” and “1”.

  First, in cycle 1, the least significant bits D0 [0] to D126 [0] of the even data D0 to D126 are read from the orthogonal transformation memories TM0 to TM3 according to the address 24. This cycle 1 is the status ST0, and all the data read from the orthogonal transformation memories TM0 to TM3 are stored in the 64-bit buffer 68.

  In cycle 2, the count value WCNT [0] becomes “1” and the address MDD becomes 16. In the orthogonal transformation memories TM0 to TM3, the least significant bits D1 [0] to D127 [0] of the odd data D1 to D127 are read from the address 16. For the buffer 68, the least significant bit data D0 [0] -D62 [0] of even data is replaced by the least significant bits D65 [0] -D127 [0] of odd data of 32 bits. At this time, the data bits D0 [0] -D62 [0] have already been read from the 64-bit buffer, and the least significant bit bits D0 [0]-of the even data from the 64-bit buffer 68 are read to the interface bus. D62 [0] and the least significant bits D1 [0] -D63 [0] of the odd data read from the orthogonal transformation memories TM0 to TM3 are output by the bus switching circuit 192. This transfer cycle 1 is status ST1.

  In cycle 3, the count value WCNT [0] becomes “0” again and the address MADD becomes 24. In this case, data transfer mask signals MDM0 and MDM1 are set to “1” and “0”, respectively, in accordance with transfer address count bit RCNT [1]. Therefore, the least significant bits D128 [0] -D256 [0] of the even data in the lower 16-bit area are read from the orthogonal transformation memories TM0 to TM3 and stored in the 64-bit buffer 68. At this time, the even data bits D64 [0] -D126 [0] and the odd data bits D65 [0] -D127 [0] stored in the 64-bit buffer 68 are selected on the interface bus by the bus switching circuit. Transferred. This transfer cycle 3 is status ST2.

  Thereafter, this operation is repeatedly executed. That is, for writing to the 64-bit buffer, the entire buffer is updated and half of the buffer is updated repeatedly, while for reading from the 64-bit buffer, the entire 64-bit buffer is read and the 64-bit buffer is read. Reading of half of the 32 bits of data to be updated and 32 bits of data read from the orthogonal transformation memories TM0 to TM3 are repeatedly executed.

  In cycle 64, the most significant bits D385 [7] -D511 [7] of the odd-numbered data at address 7 of the orthogonal transformation memories TM0 to TM3 are read. In this cycle 64, the status ST1 is reached, the half of the 64-bit buffer 68 is updated, and the most significant bits D449 [7] -D511 [7 of the odd-numbered data D449-D511 at the address 7 are updated to the 64-bit buffer. ] Is stored. In the buffer 68, the most significant bits D448 [7] -D510 [7] of even data are re-stored as non-updated data.

  In parallel with the storage of data in the 64-bit buffer, the most significant bits D384 [7] -D446 [7] of the even-numbered data D384-D446 and the data bits D385 [7] -D447 to be updated in the 64-bit buffer. [7] is read on the interface bus.

  In cycle 65, all the data are read by reading the most significant bits D448 [7] -D510 [7] of the even data stored in the 64-bit buffer and the most significant bits D449 [7] -D511 [7] of the odd data. Transfer is complete.

  Therefore, since pre-reading is performed with respect to the buffer 68, although one cycle of latency occurs, 512 8-bit data read by updating 64 addresses can be transferred in 65 cycles.

B: 16-bit mode In the 16-bit mode, the bit width of data stored in the orthogonal transformation memories TM0 to TM3 is only different from that in the 8-bit mode. Therefore, the bus connection is the same as in the 8-bit mode, and read enable signals / MRE0- / MRE3 and transfer mask signals MDM0 and MDM1 are generated in the same manner as in the 8-bit mode. The read transfer address MADD is simply the count value RCNT [! 0; 5: 2], the read address is generated only in the sequence of 16, 0, 16, 0, 17, 1,..., And the data transfer mode of the memory cell is an 8-bit mode. Is the same. Also in this 16-bit mode, all 256 pieces of 16-bit data can be transferred in 65 cycles.

C: 32-bit Mode FIG. 37 is a diagram schematically showing the connection between the orthogonal transformation memories TM0 to TM3 and the 64-bit data bus 55 in the 32-bit mode. In FIG. 37, the bus selector 140a couples the lower 16-bit port L of the orthogonal transformation memory TM0 to the 16-bit data bus 150b in accordance with the 32-bit width designation signal BWS3. Bus selectors 140b and 142c couple upper 16-bit port U and lower 16-bit port L of orthogonal transformation memory TM2 to 16-bit data buses 150a and 150b, respectively.

  Bus selectors 142a and 142b couple upper 16-bit port U and lower 16-bit port L of orthogonal transformation memory TM1 to 16-bit data buses 150c and 150d, respectively, according to 32-bit width designation signal BWS32. The selector 140c couples the upper 16-bit port U of the orthogonal transformation memory TM3 to the 16-bit data bus 150c according to the 32-bit width designation signal BWS32.

  The upper 16-bit port U of the orthogonal transformation memory TM0 is coupled to the 16-bit data bus 150a, and the lower 16-bit port L of the orthogonal transformation memory TM3 is coupled to the 16-bit data bus 150d.

  As shown in FIG. 29, in the 32-bit mode, the bus switching circuit 190 in the buffer update circuit 170 transfers the data from the 64-bit data bus 55 to the 64-bit buffer 68, and the bus switching in the transfer data selection circuit 172. The circuit 192 also transfers 64-bit data from the 64-bit buffer 68 to the main arithmetic circuit interface (I / F). Therefore, the 64-bit data transmitted on the data bus 55 is temporarily stored in the buffer 68 and then transferred to the main arithmetic circuit I / F.

  FIG. 38 schematically shows an access sequence in the 32-bit mode. The read enable signals / MRE0 and / MRE1 are generated according to the most significant bit RCNT [5] of the transfer address counter RCNT, and the read enable signals / MRE2 and / MRE3 are generated according to the inverted value of the count value RCNT [5]. (See FIG. 28). The read address MADD is generated according to the lower count bits RCNT [4: 0] (see FIG. 27). Transfer mask signals MDM0 and MDM1 are both set to “0” in an inactive state in the 32-bit mode.

  Therefore, in the first 32 cycles, orthogonal transformation memories TM0 and TM1 are activated, respectively, and while read address MADD indicates addresses 0 to 31, these orthogonal transformation memories TM0 and TM1 and data buses 150a-150d Data transfer between the two. Through the buffer 68, 64-bit data of 32 consecutive addresses is sequentially transferred to the main arithmetic circuit interface (I / F) with a delay of 1 cycle from the data reading.

  During this time, the orthogonal transformation memories TM2 and TM3 are inactive and have no effect on the data transfer operation.

  FIG. 39 is a diagram schematically showing a data flow when reading the latter half of data in the 32-bit mode. When the transfer of the first half continuous data D0 to D63 is completed in the first 32 cycles, the most significant count bit RCNT [5] of the transfer address counter RCNT becomes “1”. Therefore, from the next cycle, the read enable signals / MRE0 and / NRE1 for the orthogonal transformation memories TM0 and TM1 are both “1”, and access to the orthogonal transformation memories TM0 and TM1 is stopped. On the other hand, the read enable signals / MRE2 and / MRE3 for the orthogonal transformation memories TM2 and TM3 are both "0", and access to these orthogonal transformation memories TM2 and TM3 is permitted.

  In this case, addresses 0 to 31 are sequentially designated according to the count value RCNT [4: 0] of the transfer address counter RCNT, and the second half of the continuous data D64 to D127 is transmitted in a bit serial manner on the data buses 150a to 150d. Transferred.

  In this 32-bit mode, status control similar to that in the 8-bit mode is executed. Since the bus switching in the bus switching circuits 190 and 192 is fixedly set and half of the buffer is not updated and the buffer is fully updated, the status ST1 seems to be omitted, but the transfer address counter and mat The update operation of the transfer address counter is the same as that in the 8-bit mode, and 32-bit data can be transferred reliably by updating the address by the same transfer control as in the 8-bit mode.

D: 64-bit mode FIG. 40 schematically shows a connection mode of bus selectors 140a-140c and 142a-142c in the 64-bit mode. In the 64-bit mode, orthogonal transform memories aligned in the X direction in the figure are enabled in parallel. Therefore, the bus selector 140a couples the lower 16-bit port L of the orthogonal transformation memory TM0 to the 16-bit data bus 150b. Bus selectors 140b and 142c couple upper 16-bit port U and lower 16-bit port L of orthogonal transform memory TM2 to 16-bit data buses 150c and 150d, respectively. Bus selectors 142a and 142b couple upper 16-bit port U and lower 16-bit port L of orthogonal transform memory TM1 to 16-bit data buses 150a and 150b, respectively. The bus selector 142c couples the upper 16-bit port U of the orthogonal transformation memory TM3 to the 16-bit data bus 150c.

  Connection paths of these bus selectors 140a-140c and 142a-142c are set according to a 64-bit width instruction signal BWS64. In the 64-bit mode, as shown in FIG. 28, read enable signals / MRE0 and / MRE2 are generated according to the inverted value of count value RCNT [5] of transfer address counter RCNT, and read enable signals / MRE1 and / MRE3 are The transfer address counter RCNT is generated according to the count value RCNT [5]. Accordingly, data is read from the orthogonal transformation memories TM1 and TM3 in the first 32 cycles, and data is read from the orthogonal transformation memories TM0 and TM2 in the latter 32 cycles.

  FIG. 41 schematically shows an access mode in the first cycle 0 to cycle 31 in the 64-bit mode. Read enable signals / MRE0 and / MRE3 for orthogonal transformation memories TM1 and TM3 are active during these cycles 0-31 as described above. Therefore, in cycles 0 to 31, memory cells are sequentially selected from addresses 0 to 31 in the orthogonal transformation memories TM1 and TM3, and 64 continuous data D0 to D63 are respectively bit-serialized on the data buses 150a to 150d. Transferred in a manner.

  When the transfer of the lower 31 bits of the 64-bit data of the orthogonal transformation memories TM1 and TM3 is completed, the most significant bit RCNT [5] of the transfer address counter RCNT becomes “1”. In this case, as shown in FIG. 42, the read enable signals / MRE1 and / MRE3 for the orthogonal transformation memories TM1 and TM3 are set to “1”, and the orthogonal transformation memories TM1 and TM3 are set to a disabled state. On the other hand, the read enable signals / MRE0 and / MRE2 for the orthogonal transformation memories TM0 and TM2 become “0”, and data access to the orthogonal transformation memories TM0 to TM2 is executed. According to the remaining count value RCNT [4: 0], the upper 32 bits of the 64-bit data at addresses 0 to 31 are transferred to the data buses 150a to 150d in a bit serial manner.

  In the 64-bit mode, bus switching circuits 190 and 192 are fixed so that the connection path transfers 64-bit data to and from the 64-bit buffer according to bit width designation signal BWS 32/64. Therefore, the 64-bit data read from the set of the orthogonal transformation memories TM1 and TM3 and the 64-bit data read from the orthogonal transformation memories TM0 and TM2 are temporarily transferred from the data bus 55 to the 64-bit buffer 68, as in the 32-bit mode. After being stored, it is transferred to the main arithmetic circuit I / F. Therefore, even in this 64-bit mode, 64-bit data at 64 addresses can be transferred in 65 cycles.

  In this case, unlike the previous 8-bit mode, 16-bit mode, and 32-bit mode, 64-word data is sequentially arranged in the order of the data numbers on the data bus 55, and is not separated into even-numbered data and odd-numbered data groups. . However, as will be described, no particular problem occurs even if the data arrangement is different in the 64-bit mode from that in the other modes.

  That is, as shown in FIG. 43, in the memory cell mat in the main arithmetic circuit, arithmetic processing is executed in an entry parallel and bit serial manner. For memory cell mat 30, 64-bit data is sequentially transferred and stored in a bit serial manner from main operation circuit block I / F via internal data bus 200. Data to be calculated is stored in the entries ERY0 to ERY (M-1), and calculation processing is executed in a bit-serial manner with the corresponding calculation units (ALU) 31 respectively. Therefore, in the entries ERY0, ERY1,... ERY (M-2) and ERY (M-1), a set of operation data, for example, a data set (Da, Db), (Dc, Dd) in the case of binary operation, .., (De, Df), and (Dg, Dh) can be stored, respectively, the arithmetic processing can be executed in an entry parallel and bit serial manner. In memory cell mat 30, it is not particularly required to sequentially arrange data in the order of data numbers in accordance with entries ERY0 to ERY (M-1).

  When data is transferred from the memory cell mat 30 to the orthogonal transformation circuit, the data is transferred in the same data arrangement order as that transferred from the orthogonal transformation circuit 40 to the memory cell mat 30. Thereafter, orthogonal transformation is performed in accordance with the orthogonal transformation memories TM0 to TM3 in the orthogonal transformation circuit, and transferred to the internal system bus.

  Data transfer from the memory cell mat 30, that is, from the main arithmetic circuit 20 to the orthogonal transformation memories TM0 to TM3 of the orthogonal transformation circuit, is merely the reverse of the data transfer direction shown in FIGS. That is, in accordance with a transfer instruction from the controller (22) included in the main arithmetic circuit, the write enable signal (/ MWE0− / MWE3) is activated in the same sequence as the data read in place of the read enable signal. Data writing may be performed in these orthogonal transformation memories TM0 to TM3 instead of data reading.

  The data storage and reading to the buffer 68 and the connection mode of the bus switching circuits 170 and 172 and the bus selectors 140a to 140c and 142a to 142c at the time of data transfer from the memory cell mat to the orthogonal transformation circuit in the main arithmetic circuit are orthogonal. This is the same as when data is transferred from the conversion circuit to the main arithmetic circuit. Therefore, in the configuration shown in FIG. 26, write instruction MWEN is applied to transfer address generation circuit 160 and transfer control circuit 166 in place of read instruction MREN of the memory controller of the main arithmetic circuit, and the status register is initialized. It only has to be done.

  Further, at the time of data transfer between the orthogonal transform circuit and the main arithmetic circuit, in the above description, even data is accessed first, and then odd data is accessed. However, this order may be reversed. It suffices that even-numbered data sets and odd-numbered data sets are accessed alternately in a continuous data group.

  Even in the 64-bit mode, the status information stored in the status register is the same as the status information shown in FIG. 32. The same control is performed, the bus connection path is switched, and the range of generated addresses is changed. (The count-up operation of the transfer address counter RCNT is the same).

  In the above description, the minimum data bit width is assumed to be 8 bits. When the minimum data bit width is 4 bits, the configuration is as follows. At the time of transfer to and from the system bus, the orthogonal transform memories TM0 to TM3 are each divided into memories of 32 addresses and 16 bits. Data is transferred to / from each divided memory in units of 8 bits. The mode of data transfer between the four divided memories is the same as that of 8-bit data transfer between the two orthogonal transformation memories. When transferring data to and from the main arithmetic circuit, the same bus connection as in the 8-bit mode is performed, and data transfer is performed by alternately switching even addresses and odd addresses in units of 8 bits to all the divided memories. The access mode to the 64-bit buffer is the same as in the 8-bit mode. Even in this case, each divided memory has two sets of even data and odd data, and the address area is divided into four, so that data can be transferred to the divided memory in a total of 64 cycles. That is, a configuration in which an 8-bit mask is used instead of a 16-bit mask may be used.

  Therefore, the bit width of the transferred data is not limited to a set of 8, 16, 32, and 62 bits. Data is transferred between the system bus and the orthogonal transformation circuit using a data bus having a bit width that is ½ of the system bus bit width, and data having the same bit width as that of the system bus is transferred to the main arithmetic circuit. What is necessary is just to be able to transfer using a bus | bath.

  When the configuration of the orthogonal transform circuit according to the present invention is generalized, the configuration can be expressed as follows.

[conditions]
Minimum bit width of system transfer data: M,
System data bus bit width: K,
Bit width of the data bus (50) on the system side in the orthogonal transformation circuit: L,
Bit width of main operation side data bus (55) in orthogonal transformation circuit: K,
Bit width of main arithmetic circuit side buffer memory: K.

[Orthogonal transformation memory configuration]
Number N = L · M / K,
System bus side address: L,
Main arithmetic circuit side address: MN.

[Main arithmetic circuit side access sequence]
Transfer data bit width: J,
Number of orthogonal transform memories activated in one transfer cycle:
INT {(L / J)}, function INT {} indicates the nearest integer not less than (L / J);
Number of orthogonal transform memories activated in one system cycle:
MIN {(L / J), (K / L)} and function MIN {} indicate the smaller of (L / J) and (K / L).

Access bit width to the orthogonal transformation memory: MIN (2 · J, MN).
[Main arithmetic circuit side]
Number of orthogonal transform memories activated in one transfer cycle:
MIN {(J / L), (K / L)},
Access width to orthogonal transformation memory:
MIN {2 · J, MN},
(I) When the memory access width is 2 · J:
Transfer half-update and full update to K-bit buffer repeatedly,
(Ii) When the memory access width is MN:
All transfer cycles, transfer through K-bit buffer.

  As described above, according to the present invention, the bus connection is switched, the address is set according to the data bit width, the data is transferred between the orthogonal transformation memory and the system bus, and the orthogonal transformation circuit and the main bus are transferred. Data is transferred between the arithmetic circuits through a buffer. Therefore, data of multiple types of bit widths can be transferred using all bit widths of the data bus using the entire memory area of the orthogonal transformation memory in the orthogonal transformation circuit without changing the bus width. Can transfer data efficiently.

  In addition, this orthogonal transform circuit performs orthogonal transform of the data array between the system side in the parallel arithmetic processing unit and the memory cell mat in the main arithmetic circuit. However, the orthogonal transform operation is generally required in matrix calculation processing. Therefore, by providing the orthogonal transformation circuit according to the present invention in a system that executes such matrix calculation processing, it is possible to efficiently transfer data and execute matrix calculation processing of a plurality of types of bit width data. it can.

  By applying the orthogonal transform circuit according to the present invention to a parallel arithmetic processing device in which an arithmetic unit is provided for each entry of the arithmetic memory cell mat, data transfer can be efficiently performed and processing performance is further improved. can do.

  Further, by applying the orthogonal transform circuit according to the present invention to a circuit portion that performs matrix transposition for a circuit device that performs matrix multiplication, data is transferred at high speed, and transpose matrix for data of various bit widths. Can be generated to perform matrix multiplication.

  Further, the present invention is not limited to such matrix multiplication, and by applying the orthogonal transformation circuit according to the present invention to a circuit portion that requires matrix transposition operation, efficient orthogonal transformation can be performed, and vector multiplication Processing such as processing can be efficiently performed on data of various data bit widths.

1 is a diagram schematically showing an overall configuration of a signal processing system to which an orthogonal transform circuit according to the present invention is applied. It is a figure which shows roughly the flow of the data at the time of arithmetic operation in the main arithmetic circuit shown in FIG. It is a figure which shows roughly the data flow at the time of the data transfer between the system side and the memory cell mat in a main arithmetic circuit. It is a figure which shows roughly the whole structure of the orthogonal transformation circuit according to Embodiment 1 of this invention. FIG. 5 is a diagram schematically showing a configuration of a 2-port orthogonal transformation memory shown in FIG. 4. FIG. 6 is a diagram illustrating an example of a configuration of a memory cell of the orthogonal transform memory illustrated in FIG. 5. FIG. 5 is a diagram schematically showing a bit configuration of the 2-port orthogonal transform memory shown in FIG. 4. It is a figure which shows roughly the data arrangement at the time of the data transfer between the systems of the orthogonal transformation circuit according to Embodiment 1 of this invention. FIG. 9 is a timing chart showing a data transfer operation of the orthogonal transform memory shown in FIG. 8. FIG. 9 is a diagram schematically showing an arrangement of stored data at the time of data transfer in the first half of the orthogonal transform memory shown in FIG. 8. FIG. 9 is a diagram schematically showing an arrangement of data in the latter half cycle of the orthogonal transformation memory shown in FIG. 8. FIG. 10 is a timing diagram illustrating a data transfer operation during 16-bit data transfer. It is a figure which shows roughly the storage arrangement | positioning of 32-bit data in an orthogonal transformation memory. FIG. 14 is a timing diagram illustrating a transfer operation of the 32-bit data illustrated in FIG. 13. It is a figure which shows schematically the structure of the system bus side control part shown in FIG. FIG. 16 is a diagram schematically showing an example of a bus connection path and an address generation sequence when 8-bit data and 16-bit data are transferred by the system bus side control unit shown in FIG. 15. FIG. 16 is a diagram schematically showing an example of a bus connection path and an address generation sequence when transferring 32-bit data and 64-bit data of the bus-side control unit shown in FIG. 15. FIG. 16 is a diagram illustrating an example of a configuration of a part that generates a transfer clock signal and a switching control signal illustrated in FIG. 15. FIG. 19 is a timing diagram illustrating an operation of the signal generation unit illustrated in FIG. 18. FIG. 5 is a diagram schematically showing a configuration of an orthogonal transformation memory control unit of the system bus side control unit shown in FIG. 4. FIG. 21 is a timing chart showing an operation at the time of 8-bit data transfer of the control unit shown in FIG. 20. FIG. 21 is a timing diagram illustrating an operation of the control unit illustrated in FIG. 20 during 16-bit data transfer. FIG. 21 is a timing chart showing an operation at the time of 32-bit and 64-bit data transfer of the control unit shown in FIG. 20. It is a figure which shows schematically the structure of the principal part of the example of a change of the system bus side control part shown in FIG. FIG. 5 is a diagram schematically illustrating an example of a configuration of a bus connection unit of a main arithmetic circuit side control unit illustrated in FIG. 4. FIG. 5 is a diagram schematically illustrating an example of a configuration of a data transfer control unit of the main arithmetic circuit side control unit illustrated in FIG. 4. FIG. 27 is a diagram showing an example of a configuration of a transfer address generation circuit shown in FIG. 26. FIG. 27 is a diagram illustrating an example of a configuration of a transfer control circuit illustrated in FIG. 26. FIG. 27 is a diagram more specifically showing the configuration of a buffer update circuit and a transfer data selection circuit shown in FIG. 26. FIG. 26 is a diagram schematically showing a connection path during 8-bit data transfer of the bus selector shown in FIG. 25. FIG. 31 is a diagram schematically showing a data array in an orthogonal transformation memory at the time of 8-bit data transfer in the connection shown in FIG. 30. It is a figure which shows roughly the status transition at the time of 8-bit data transfer. FIG. 33 schematically shows a data transfer mode in status ST0 shown in FIG. 32. FIG. 33 schematically shows a data transfer path in status ST1 shown in FIG. 32. It is a figure which shows roughly the transfer aspect of the latter half data at the time of 8-bit data transfer. It is a figure which shows roughly the flow of the data at the time of 8-bit data transfer. It is a figure which shows roughly the connection path | route of the bus selector in the main arithmetic circuit side control part at the time of 32-bit data transfer. FIG. 38 schematically shows a data transfer sequence in the 32-bit mode transfer arrangement shown in FIG. 37. It is a figure which shows roughly the transfer sequence of the latter half data at the time of 32-bit data transfer in the connection arrangement | positioning shown in FIG. It is a figure which shows roughly the connection path | route at the time of 64-bit data transfer of the bus selector of the main arithmetic circuit block side control part. FIG. 41 is a diagram schematically showing a data transfer sequence in the first half cycle of a data transfer sequence in the connection arrangement shown in FIG. 40. FIG. 41 is a diagram schematically showing a transfer path of latter half data in the connection arrangement shown in FIG. 40. It is a figure which shows roughly the data transfer sequence to the memory cell mat in a main arithmetic circuit, and an arithmetic sequence.

Explanation of symbols

  1 signal processing system, 2 system LSI, 20 main arithmetic circuit, 24 system bus I / F, 30 memory cell mat, 31 arithmetic unit (ALU), 40 orthogonal transform circuit, 7 internal system bus, FB1-FBh basic arithmetic block, TM0-TM3 2-port orthogonal transformation memory, 50, 55 internal data bus, 60 system bus side control unit, 65 main arithmetic circuit side control unit, 68 64-bit buffer, 70 memory cell array, 72 system bus side write / read circuit, 74 System bus side cell selection circuit, 76 Main arithmetic circuit side write / read circuit, 78 Main arithmetic circuit side cell selection circuit, MC memory cell, 100 64-bit register, SL0-SL3, SSL0-SSL3 selector, 104 bit width setting Register, 102 address register, 120-123 Read / write control signal generation circuit, 130 write mask instruction signal generation circuit, 140a-140c, 142a-142c bus selector, 160-bit width setting register, 162 status register, 164 transfer address generation circuit, 166 transfer control circuit, 168 mat Transfer address counter, 170 Buffer update circuit, 172 Transfer data selection circuit, RCLT Transfer address counter, 180 address generation circuit, 182a-182d Read activation circuit, 184 Transfer mask generation circuit, 190, 192 Bus switching circuit

Claims (10)

A plurality of orthogonal transformation memories each having a first port and a second port, and an array of data transferred via the first and second ports being orthogonal to each other; and A first port coupled in common to the first port and having a bit width equal to a data bit width that can be input / output via the first port of each of the orthogonal transformation memories and smaller than a bit width of an external data bus; Data bus,
A second data bus coupled in common to the second ports of the plurality of orthogonal transformation memories and having a bit width larger than the bit width of the data that can be input / output via the second ports of the orthogonal transformation memories; ,
At the time of data transfer via the first data bus, addresses and transfer control signals for the plurality of orthogonal transform memories are individually generated in accordance with the bit width information having the bit width of the transfer data. A system-side control circuit for setting a connection path between the first port of the orthogonal transformation memory and the first data bus, and the second data bus during data transfer via the second data bus Including a buffer for selectively storing and transferring the above data, and setting a bus connection path for the plurality of orthogonal transformation memories according to the bit width information at the time of data transfer via the second data bus In addition, an address and a transfer control signal are generated individually for each of the orthogonal transformation memories, and further, data is written to and read from the buffer. An orthogonal transform circuit comprising a main arithmetic circuit side control circuit that selectively outputs data and generates final transfer data from data from the second port and data from the buffer. The system side control circuit is:
2. The orthogonal transform circuit according to claim 1, further comprising means for generating a mask signal for masking data transfer in units of a predetermined number of bits for each of the plurality of orthogonal transform memories.   The system-side control circuit is configured such that the upper bit and the lower bit of the first port of each of the orthogonal transformation memories are set to the upper and lower bits of the first data bus according to the bit width setting information. The bus selector for setting a connection path between the first port and the first data bus for each of the plurality of orthogonal transformation memories so as to be coupled to a common lower bit data bus. Orthogonal transformation circuit.   The system-side control circuit includes an address selection circuit that generates an address signal for each of the orthogonal transformation memories by selecting one of an upper bit and a lower bit of an external address according to the data bit width information. Item 4. An orthogonal transform circuit according to item 1.   The system-side control circuit includes a selection circuit that individually activates the plurality of orthogonal transformation memories according to the data bit width information, and the selection circuit is configured to parallel the plurality of orthogonal transformation memories according to the data bit width information. The orthogonal transform circuit according to claim 1, wherein the number of activated memories and an activation sequence are set. The main arithmetic circuit side control circuit is:
A multi-bit transfer address counter that counts the number of transfer cycles;
The orthogonal transformation circuit according to claim 1, further comprising an address selection circuit that rearranges count bits of the transfer address counter according to the bit width information to generate addresses for the plurality of orthogonal transformation memories. The main arithmetic circuit side control circuit is:
2. The orthogonal transform circuit according to claim 1, further comprising a circuit that selectively masks access to the upper data bit region and the lower data bit region of the plurality of orthogonal transform memories according to the bit width information. The main arithmetic circuit side control circuit is:
A transfer control circuit for generating an activation signal for activating access to the second port of the plurality of orthogonal transform memories in accordance with the bit width information and the data transfer cycle number information; The orthogonal transform circuit according to claim 1. The second port of the orthogonal transform memory finally transfers data to and from the interface;
The main arithmetic control circuit is
A mat transfer counter for counting the number of data transfer cycles via the second data bus;
A buffer update circuit for setting a data transfer path between the second data bus and the buffer according to the count value of the mat transfer counter and the bit width information;
2. The orthogonal transform according to claim 1, further comprising: a transfer data selection circuit that sets a connection path between the second data bus and the buffer and the interface according to the count value of the mat transfer counter and the bit width information. circuit. The buffer update circuit performs transfer between all the data bits of the second data bus and the buffer and the second data bus every transfer cycle when the bit width information specifies the first bit width. The data transfer path to repeat the transfer of half of the data bits and half of the data bits of the buffer to the buffer,
When the bit width information indicates the first bit width, the transfer data selection circuit transfers the remaining half of the data bits of the second data bus and the remaining half of the buffer, and The orthogonal transform circuit according to claim 9, wherein the connection path is set so as to repeat transfer of all bits.

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