CN103943138A - Per unit multi-bit storage device - Google Patents
Per unit multi-bit storage device Download PDFInfo
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- CN103943138A CN103943138A CN201410156241.5A CN201410156241A CN103943138A CN 103943138 A CN103943138 A CN 103943138A CN 201410156241 A CN201410156241 A CN 201410156241A CN 103943138 A CN103943138 A CN 103943138A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1673—Reading or sensing circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1675—Writing or programming circuits or methods
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Abstract
The invention provides a per unit multi-bit storage device which comprises a storage cell array, a row address decoding module, a column address decoding module, a reading/writing control module, a plurality of first word lines and a plurality of first bit lines. According to the storage device disclosed by the invention, a semi-floating gate transistor with an embedded tunneling field-effect tube serves as a storage unit for data storage; on one hand, writing operation at relatively high speed can be realized through a band-to-band tunneling property of a tunneling diode, and on the other hand, threshold voltage of the transistor is controlled in a segmented manner, thus realizing per unit multi-bit storage.
Description
Technical field
The present invention relates to field of semiconductor devices, particularly relate to the many bit memory in every unit.
Background technology
The data that random access memory (SRAM and DRAM) is stored after power-off can be lost thereupon, and its " 0 " and " 1 " two data bit of can only encoding, cannot realize the storage of the many bits in every unit, people design and develop except nonvolatile memory subsequently, for example flash memory, can either in power-off, store data, can realize again many bits of encoded, and integrated level be high.
The storage unit of flash memory can comprise on the floating grid, substrate of electricity isolation respectively in source electrode and the drain region of the first and second sides of floating grid and be configured to control the control grid of this floating grid.Typically, the threshold voltage of the storage unit of flash memory depends on the quantity of electric charge being stored in this floating grid.The variable quantity of the cell current of the storage unit of the flash memory causing because of threshold voltage difference by sensing can detect the data of storing in storage unit.
When writing to the storage unit of flash memory and/or when obliterated data, typically using the high voltage with respect to power source voltage Vcc.Write and/or erase operation in, can or extract out from this floating grid this floating grid of charge injection around the insulation course of floating grid by tunnelling.
Typically, the grid of the storage unit of flash memory is electrically connected to word line, and drain electrode is electrically connected to bit line.This word line is electrically connected to line decoder and this bit line is electrically connected to read/write circuit.Can configuration line code translator to select in multi-word-line and can apply word line voltage to selecteed word line.Word line voltage is to be applied to word line to write, read for carrying out and/or the voltage of erase operation.Configuration read/write circuit makes it select in multiple bit lines and can apply bit-line voltage to selecteed bit line.Bit-line voltage is to be applied to bit line to write, read for carrying out and/or the voltage of erase operation.In addition, this read/write circuit is electrically connected to selecteed word line and selecteed bit line equally, can be by the data of selecteed bit line output storage unit.
But, flash memory data write with erase process in all to adopt high voltage (5V～15V), and erase operation speed is slower.
Summary of the invention
The shortcoming of prior art in view of the above, the object of the present invention is to provide the many bit memory in every unit, for solving many bit memory of prior art write operation speed slowly and write operation and the higher problem of erase operation required voltage.
For achieving the above object and other relevant objects, the invention provides the many bit memory in every unit, the many bit memory in described every unit comprise: memory cell array, row address decoding module, column address decoding module, read-write control module, many first word lines and many first bit lines, wherein
Described memory cell array comprises multiple storage unit subarrays, the control grid of the storage unit of each subarray is coupled to same the first word line, the drain electrode of each storage unit of each subarray and the drain coupled of storage unit that is positioned at same row with it are to same the first bit line, drain electrode and drain coupled to the same that is positioned at the storage unit of same row with it connecting line that drains, described storage unit is except controlling grid, source electrode, drain electrode, also comprise half floating boom, and the doping type of described half floating boom and source electrode, drain electrode are contrary; Described half floating boom contacts and forms an embedded type diode with drain doping region; Described control grid extends to drain doping region top and covers its surface, described half floating boom, drain doping region and the control grid that extends to drain doping region top form an embedded tunneling field-effect transistor, described storage unit produces multiple predetermined current value under multistage predetermined voltage effect, and described multiple predetermined current value is for characterizing the multiple store status of described storage unit;
Described row address decoding module is coupled to described many first word lines, selects signal, and select signal to choose a first word line according to described row for generation of row;
Described column address decoding module is coupled to described read-write control module, for generation of column selection signal, and be sent to read-write control module make it choose first bit line according to described column selection signal;
Described read-write control module is coupled to the drain electrode connecting line of described many first bit lines and described storage unit, be used for receiving described column selection signal and read write command signal, and read and data writing according to storage unit described in described column selection signal and read write command signal controlling.
Preferably, described row address decoding module comprises the first word line decoding unit and the second word line decoding unit, wherein:
Described the second word line decoding element coupling, to described the first word line decoding unit, for generation of the second word-line signal and chip selection signal, and inputs to described the first word line decoding unit;
Described the first word line decoding unit is the control grid to described storage unit by the first word line coupling, for described the second word-line signal and chip selection signal are decoded as to the capable signal that selects, and select signal to choose a first word line according to described row, and receive read write command signal, and the first word line of choosing described in read-write level being applied to according to described read write command signal.
Preferably, described the first word line decoding unit further comprises and gate logic unit, for described the second word-line signal and chip selection signal are carried out to AND operation.
Preferably, described and gate logic unit are multistage and gate logic unit, and wherein, AND operation is carried out in upper level and the output of gate logic unit and the input of the chip selection signal of appropriate level by next stage and gate logic unit.
Preferably, described the first word line decoding unit comprises:
Multiple resistive elements, described multiple resistive elements are connected serially to chip power supply power supply, for generation of a point voltage level;
Data selector, is coupled to described multiple resistive element and many first word lines, for exporting respectively the first corresponding word line to by carrying out the required level of described read write command signal and the required level of the described read write command signal of non-execution.
Preferably, described data selector comprises: one-level data selector and multiple secondary data selector switch, wherein,
Described one-level data selector is coupled to described multiple secondary data selector switch, for exporting described multiple secondary data selector switch to by carrying out required level and the required level of the described read write command signal of non-execution of described read write command signal;
Described multiple secondary data selector switch correspondence is coupled to described many first word lines and described the second word line decoding unit, be used for receiving described row and select signal, and select signal to choose and a first word line of its coupling according to described row, and export described the first word line to by carrying out required level and the required level of the described read write command signal of non-execution of described read write command signal.
Preferably, described data selector also comprises read write command signaling switch, is coupled to described multiple resistive element and one-level data selector, for according to described read write command signal conduction or shutoff.
Preferably, described read-write control module comprises; Data reading port, data are write inbound port, analog to digital converter, digital to analog converter and internal data selector switch, wherein,
Described data reading port is for exporting the data of reading from described storage unit;
Described data are write inbound port for receiving external data;
Described analog to digital converter is for being converted to digital signal by the data of the current forms of reading from described cell source;
Described internal data selector switch is in the time of reading out data, only read the data of Destination Storage Unit, and be stored in described internal data selector switch by sharing with Destination Storage Unit the data that other storage unit of same the first word line read, and in the time of write operation, external data is write to Destination Storage Unit, and will re-write each storage unit in the data of described internal data selector switch with other cell stores of shared same the first word line of Destination Storage Unit;
Described digital to analog converter is converted to voltage signal for the digital signal that will export from described internal data selector switch, and exports the drain electrode of described storage unit to.
Preferably, described internal data selector switch further comprises the first data selector, the second data selector, the 3rd data selector and the 4th data selector, described the first data selector, the second data selector, the 3rd data selector and the 4th data selector comprise three input ports and an output port separately, wherein:
The first input end mouth of described the first data selector is coupled to described analog to digital converter and data reading port, and the second input port is coupled to data and writes inbound port, and the 3rd input port connects column selection signal, and output port is coupled to described digital to analog converter;
The first input end mouth of described the second data selector connects idle voltage signal, and the second input port connects erasing voltage signal, and the 3rd input port connects column selection signal, and output port is coupled to the second input port of described the 3rd data selector;
The first input end mouth of described the 3rd data selector is coupled to described digital to analog converter, the second input port is coupled to the output port of described the second data selector, the 3rd input port connects erasing instruction signal, and output port is coupled to the second input port of described the 4th data selector;
The first input end mouth of described the 4th data selector connects idle voltage signal, and described the second input port is coupled to the output port of described the 3rd data selector, and the 3rd input port connects write command signal, and output port is coupled to the drain electrode of described storage unit.
Preferably, the output of described analog to digital converter is also connected to data reading port by switching transistor, and the grid of described switching transistor is connected to column selection signal.
Preferably, also comprise refresh module, described refresh module is coupled to described row address decoding module, column address decoding module and read-write control module, for periodically producing refresh signal, and according to this signal from described storage unit sense data, and sense data is re-write to described storage unit.
Preferably, described refresh module further comprises counting unit, and described counting unit is for described refresh signal is counted, and output is for the row address of refresh operation.
As mentioned above, many bit memory of the present invention, have following beneficial effect:
First, the present invention has adopted the half floating boom transistor with embedded tunneling field-effect pipe to carry out data storage as storage unit, utilize the bandtoband characteristic of tunnel-through diode can realize the write operation of fast speed on the one hand, by the segmentation control to transistor threshold voltage, realize the storage of the many bits in every unit on the other hand.
Secondly, traditional floating boom transistor needs to apply high level in write operation and erase operation process, as 5V～15V, and the present invention only need apply lower level (3V～3V) and can realize in storage unit the storage of multi-bit data, greatly reduces the power consumption of memory storage.
Again, the present invention has adopted multi-stage data selector switch to combine to carry out decoding in the first word line decoding unit, thereby can choose accurately and efficiently a line storage unit, and by voltage required the first word line of selected line storage unit and not the required voltage of the first word line of selected line storage unit shunt to corresponding storage unit.
In addition, read-write control module of the present invention is by four data selectors, the synergy of digital to analog converter and analog to digital converter, in the time of reading out data, only read the data of Destination Storage Unit, and convert digital signal by sharing with Destination Storage Unit the current signal that other storage unit of same the first word line read to by analog to digital converter, and be stored in internal data selector switch, in the time of write operation, external data is write to Destination Storage Unit, and the data of described storage are re-write to corresponding stored unit, thereby realize exactly the read-write operation to object element.
Finally, the present invention has adopted refresh module in the many bit memory in every unit, with the data in dynamic refresh storage unit, eliminate the electric leakage defect of novel storage unit of the present invention, thereby in matching process, can realize more exactly coupling, improve efficiency and the accuracy of Data Matching.
Brief description of the drawings
Fig. 1 is shown as the schematic diagram of the many bit memory in every unit of the present invention.
Fig. 2 is shown as the schematic diagram of memory cell array of the present invention.
Fig. 3 is shown as the schematic diagram of storage unit of the present invention.
Fig. 4 is shown as the schematic diagram of the gate capacitance of storage unit of the present invention.
Fig. 5 is shown as the schematic diagram of the first word line decoding unit of the present invention.
Fig. 6 is shown as the connection diagram of read-write control module of the present invention and memory cell array.
Fig. 7 is shown as the schematic diagram of read-write control module of the present invention.
Fig. 8 is shown as the time sequential routine schematic diagram of Destination Storage Unit in memory cell array of the present invention.
Element numbers explanation
1 controls grid
2 half floating booms
3 source doping region
4 substrates
5 drain doping region
6 tunneling field-effect transistors
7 diffusion regions
8 diodes
9 heavily doped regions
101 memory cell arrays
102 row address decoding modules
103 column address decoding modules
104 read-write control modules
105 first word line decoding unit
106 second word line decoding unit
107 with gate logic unit
108 refresh module
301,302,303 transmission lines
LWL the first word line
GWL the second word line
BL the first bit line
The DL connecting line that drains
D drain electrode
S source electrode
The capable signal that selects of Row_Signal
Block chip selection signal
Command_read reads command signal
Command_write write command signal
Command_erase erasing instruction signal
Data_read reading out data
Data_write data writing
Column column selection signal
V
d_idleidle voltage signal
M Destination Storage Unit
X1 one-level data selector
X2 secondary data selector switch
MUX1 the first data selector
MUX2 the second data selector
MUX3 the 3rd data selector
MUX4 the 4th data selector
ADC analog to digital converter
DAC digital to analog converter
T1 switching transistor
T2 erasing instruction signal and read command signal switching transistor
T3 write operation command signal switching transistor
T4 switching transistor
T5 switching transistor
Embodiment
Below, by specific instantiation explanation embodiments of the present invention, those skilled in the art can understand other advantages of the present invention and effect easily by the disclosed content of this instructions.The present invention can also be implemented or be applied by other different embodiment, and the every details in this instructions also can be based on different viewpoints and application, carries out various modifications or change not deviating under spirit of the present invention.
Be understandable that, in the time that an element is called as " connecing " or " being coupled to " another element, it can be directly connect or be coupled to another element, can be also to have marginal element.And in the time that an element is called as " directly connecting " or " coupling directly to " another element, there is not marginal element.
Unless otherwise defined, all terms used herein (comprising technical term and scientific terminology) have the general same implication of understanding of those skilled in the art.
Refer to the schematic diagram of the many bit memory in Fig. 1 every unit of the present invention.
It should be noted that, the diagram providing in the present embodiment only illustrates basic conception of the present invention in a schematic way, satisfy and only show with assembly relevant in the present invention in graphic but not component count, shape and size drafting while implementing according to reality, when its actual enforcement, kenel, quantity and the ratio of each assembly can be a kind of random change, and its assembly layout kenel also may be more complicated.
The many bit memory in described every unit comprise: memory cell array 101, row address decoding module 102, column address decoding module 103, read-write control module 104, many first word line LWL and many first bit line BL, wherein,
Described memory cell array 101 comprises multiple storage unit subarrays, the control grid of the storage unit of each subarray is coupled to same the first word line LWL, the drain electrode of each storage unit of each subarray and the drain coupled of storage unit that is positioned at same row with it are to same the first bit line BL, drain electrode and the drain coupled of storage unit that is positioned at same row with it are to same drain electrode connecting line DL, described storage unit is except controlling grid 1, source doping region 3, outside drain doping region 5, also comprise half floating boom 2, and the doping type of described half floating boom 2 and source doping region 3, drain doping region 5 is contrary, described half floating boom 2 contacts and forms an embedded type diode with drain doping region 5, described control grid 1 extends to drain doping region 5 tops and covers its surface, described half floating boom 2, drain doping region 5 and the control grid 1 that extends to drain doping region 5 tops form an embedded tunneling field-effect transistor, described storage unit produces multiple predetermined current value under multistage predetermined voltage effect, described multiple predetermined current value is for characterizing the multiple store status of described storage unit, preferably, the scope of described predetermined voltage is-3V～3V.
Described row address decoding module 102 is coupled to described many first word line LWL, selects signal Row_Signal, and select signal Row_Signal to choose a first word line LWL according to described row for generation of row;
Described column address decoding module 103 is coupled to described read-write control module 104, for generation of column selection signal Column, and be sent to read-write control module make it choose a first bit line BL according to described column selection signal Column;
Described read-write control module 104 is coupled to the drain electrode connecting line DL of described many first bit line BL and described storage unit, be used for receiving described column selection signal Column and read write command signal, and read and data writing according to storage unit described in described column selection signal Column and read write command signal controlling.
Preferably, described row address decoding module 102 comprises the first word line decoding unit 105 and the second word line decoding unit 106, wherein:
Described the second word line decoding unit 106 is coupled to described the first word line decoding unit 105, for generation of the second word-line signal and chip selection signal Block, and inputs to described the first word line decoding unit 105;
Described the first word line decoding unit 105 is coupled to the control grid of described storage unit by the first word line LWL, for described the second word-line signal and chip selection signal Block are decoded as to the capable signal Row_Signal that selects, and select signal Row_Signal to choose a first word line LWL according to described row, and receive read write command signal, and the first word line LWL choosing described in read-write level being applied to according to described read write command signal.
It should be noted that, after the electric charge injecting in half floating boom due to the tunneling field-effect pipe of storage unit of the present invention, have leaky, therefore, in the many bit memory in every unit, also increase by a refresh module 108, as shown in Figure 1, described refresh module 108 is coupled to described row address decoding module 102, column address decoding module 103 and read-write control module 104, for periodically producing refresh signal, and according to this signal from described storage unit sense data, and sense data is re-write to described storage unit.
The groundwork mode of described refresh module 108 is periodically to produce a row by described row address decoding module 102 and column address decoding module 103 to select signal Row_Signal and column selection signal Column, successively data array is scanned, first word line LWL of every gating, all storage unit that this first word line LWL connected once refresh.Concrete refresh operation is that an internal data is read and write operation, first by data reading to reading and writing control module 104, then these data are re-write.
Preferably, described refresh module 108 further comprises counting unit, and described counting unit is for described refresh signal is counted, and output is for the row address of refresh operation.System generates row according to this row address and selects signal Row_Signal and column selection signal Column, and selected storage unit is carried out to refresh operation.
Fig. 2 shows the schematic diagram of memory cell array of the present invention.
It should be noted that, described storage unit subarray 101 can be matrix form, can be also single file storage unit or single storage unit, and preferably, described storage unit subarray 101 is single file storage unit.All storage unit of every a line are shared same the second word line GWL, are connected to read-write control module 104 with the source electrode of all storage unit of the same row of a line by the first bit line BL, and drain electrode is also connected to read-write control module 104 by drain electrode connecting line DL.In subarray, the control grid of all storage unit of every a line links together, and is connected with the first corresponding word line LWL.Described the second Zi XianGWLWei Overall word line, the first word line LWL is local word line, the second word line GWL signal is entering the chip selection signal Block that needs associating subarray before concrete certain subarray, and after row address decoding module 102 carries out decoding, produces row and select signal Row_Signal.
Fig. 3 shows the schematic diagram of storage unit of the present invention.
It should be noted that, the present invention utilizes the half floating boom transistor that embeds tunnel-through diode as storage unit, to realize highdensity storage.As shown in Figure 3, half floating boom 2 parts are positioned at raceway groove top and isolate with substrate 4, part contacts with drain doping region 5, and the region contacting with drain doping region 5 at half floating boom 2 forms a more shallow p type diffusion region 7, this p type diffusion region is positioned at the region that drain doping region 5 is surperficial near substrate 4 and contact with half floating boom 2, and half floating boom 2 of this P type doping and p type diffusion region 7 form a PN junction diode 8 with the doped region, building 5 of N-type doping.In addition, control the sidewall that grid 1 covers half floating boom 2 surfaces by gate oxide and is positioned at drain doping region 2 one sides, part extends to drain doping region 5 tops and covers its surface, and the N-type heavily doped region 9 that half floating boom 2/P type diffusion region 7 of this part and the doping of P type and drain doping region 5 are drawn drain electrode forms an embedded tunneling field-effect transistor 6.It should be noted that, between part half floating boom 2 and substrate 4, control between grid 1 and half floating boom 2 and substrate 4 and be all arranged at intervals with gate oxide or other similar insulation systems, the conventional techniques that this is well known to those skilled in the art, therefore not to repeat here.
Fig. 4 is gate capacitance distribution schematic diagram in storage unit of the present invention.
As shown in Figure 4, storage unit of the present invention can be regarded as and in the gate capacitance medium of normal transistor, inserted an electrode (i.e. half floating boom 2), so just original gate capacitance has been divided into two capacitor C
1and C
2series connection.Can change the threshold voltage of storage unit by iunjected charge on half floating boom 2, the electric conductivity of regulation and control raceway groove.The principle of its regulation and control threshold voltage can be understood as: storage unit has initial threshold voltage V
th, in the time that storage unit is started working, the electric charge injecting on half floating boom 2 can be by the gate capacitance C between half floating boom 2 and transistor channel
2induce channel charge in transistor channel one side, the positive charge on half floating boom 2 is more, and the negative charge of responding in raceway groove is also more, and the electric conductivity of N-type raceway groove is stronger.This effect equivalence is to controlling grid 1, compared with before half floating boom 2 chargings, control the channel charge that grid 1 need add less gate voltage and just can induce in raceway groove equivalent, reach identical conductive effect, the threshold voltage of storage unit has just reduced so in form.
Storage unit of the present invention utilizes stored charge amount in half floating boom to represent to store data.Taking N-type transistor as example, writing of data is by control grid is placed in to low-voltage, and drain electrode is placed in high voltage, makes embedded tunnel-through diode generation band-to-band-tunneling, and positive charge flows to half floating boom from drain region.Wiping of data is by control grid is placed in to high voltage, and drain electrode is placed in low-voltage, makes tunnel-through diode positively biased, and the positive charge in half floating boom flows back to drain region.Reading of data is by being placed in suitable voltage by controlling grid and draining, make the i.e. positively biased not of tunnel-through diode, tunneling effect does not occur yet, thereby keep the positive charge in half floating boom constant, read transistorized source-drain current, judge according to the size of electric current the data that this transistor deposits in.The working method of P transistor npn npn is similar with it, and it is different that difference is that it controls the voltage that grid, drain electrode apply with source electrode, is not repeated at this.
In the time that control grid 1, drain electrode and the source voltage of storage unit are fixed, the size of source-drain current is subject to the impact of storage unit threshold voltage, and threshold voltage is relevant with the quantity of the positive charge injecting in floating boom, so by controlling control grid 1 and the drain voltage in data writing process, can control the positive charge quantity injecting in half floating boom 2, thereby the size of controlling source-drain current, realizes the storage of the many bits of per unit.For example, drain-source current is divided into fourth gear: 00 grade, 01 grade, 10 grades and 11 grades, and define 00 grade, inject positive charge A0; 01 grade, inject positive charge A1; 10 grades, inject positive charge A2 shelves; 11 grades, inject positive charge A3, thereby each storage unit can be stored 4 Bit datas, if drain-source current is divided into more grades, each storage unit can be stored the data of more bits, will not enumerate at this.Those skilled in the art can, according to the structure of the many bit memory in every unit of the present invention, adopt more high-precision digital to analog converter and analog to digital converter, and the control of associated level can realize.
It should be noted that, the storage unit that adopted is in embodiments of the present invention N-type transistor, and this storage unit can be stored 2 Bit datas.
Fig. 5 is shown as the schematic diagram of the first word line decoding unit 105 of the present invention.
As shown in Figure 5, described the first word line decoding unit 105 further comprises and gate logic unit 107, for described the second word-line signal and chip selection signal Block are carried out to AND operation.When the second word line decoding unit 106 produces after the second word-line signal and chip selection signal Block, the second word-line signal and chip selection signal Block carry out AND operation by described with gate logic unit 107, and obtain going selecting signal Row_Signal by transmission line 301, input to described the first word line decoding unit 105.
Preferably, described and gate logic unit 107 be multistage and gate logic unit, and wherein, AND operation is carried out in upper level and the output of gate logic unit and the input of the chip selection signal of appropriate level by next stage and gate logic unit.The first order and gate logic unit carry out AND operation by the second word-line signal and first order chip selection signal and obtain the first row and select after signal, selecting signal and second level chip selection signal to carry out AND operation the first row by the second level and gate logic unit again obtains the second row and selects signal, obtain successively the capable signal that selects of afterbody according to this logic.From with the structure of gate logic unit 107, the first order and gate logic unit are and door, should comprise two input ends with door, first input end is the second word line, the second input end is first order chip selection signal line, output terminal is as the first input end of the second level and gate logic unit, and the second input end of the second level and gate logic unit is second level chip selection signal line, is connected to successively afterbody and gate logic unit.
Preferably, described the first word line decoding unit 105 comprises:
Multiple resistive elements, described multiple resistive elements are connected serially to chip power supply power supply, for generation of a point voltage level;
Data selector, is coupled to described multiple resistive element and many first word line LWL, for exporting respectively the first corresponding word line LWL to by carrying out the required level of described read write command signal and the required level of the described read write command signal of non-execution.
Preferably, described data selector comprises: one-level data selector X1 and multiple secondary data selector switch X2, wherein,
Described one-level data selector X1 is coupled to described multiple secondary data selector switch X2, for exporting described multiple secondary data selector switch X2 to by carrying out required level and the required level of the described read write command signal of non-execution of described read write command signal;
Described multiple secondary data selector switch X2 correspondence is coupled to described many first word line LWL and described the second word line decoding unit 106, be used for receiving described row and select signal Row_Signal, and select signal Row_Signal to choose and a first word line LWL of its coupling according to described row, and export described the first word line LWL to by carrying out required level and the required level of the described read write command signal of non-execution of described read write command signal.
Preferably, described data selector also comprises read write command signaling switch, is coupled to described multiple resistive element and one-level data selector, for according to described read write command signal conduction or shutoff.
It should be noted that, in described the first word line decoding unit 105, produce different point voltage levels by the electric resistance array of connecting based on total voltage, then provide selection signal by address signal and read write command signal for inner each data selector, thereby produce the voltage of the needed control grid of every line storage unit in each subarray.In embodiments of the present invention, adopt 4 resistive elements to connect for dividing potential drop, described one-level data selector X1 and secondary data selector switch X2 are MUX selector switch, one-level data selector X1 comprises three input ports and the output port arranged from top to bottom, three input ports connecting resistance element respectively, thereby three corresponding passages of input port can obtain different dividing potential drops, write command signal (comprising write operation command signal and erase operation command signal) switch is set respectively on the connecting path of first input end mouth " 01 " and the 3rd input port " 10 " and resistive element and reads command signal switch.In this embodiment, the voltage that is applied to the first word line LWL during due to read operation and erase operation is identical, therefore erasing instruction signal and read command signal be set to share same switching transistor T2, write operation command signal is set to separately to switching transistor T3.Described switching transistor T2 and T3 can be union switch transistor, and this union switch is two transistorized associations, have two grids, a source electrode and a drain electrode, thus can input more quickly and accurately read write command signal.
The second input port " 00 " of described one-level data selector X1 is connected to the first input end mouth " 0 " of secondary data selector switch X2 simultaneously by connecting line 302, the output port of one-level data selector X1 is connected to the second input port " 1 " of secondary data selector switch X2 by connecting line 303, the 3rd input port of secondary data selector switch X2 connects the second word line decoding unit 106, the row that the second word line decoding unit 106 is exported selects signal Row_Signal by the 3rd input port input secondary data selector switch X2, this row selects signal Row_Signal to carry out AND operation generation by the second word-line signal and chip selection signal Block, the output port of secondary data selector switch X2 meets the first word line LWL.
When the first word line decoding unit 105 produces after the second word-line signal and chip selection signal Block, the second word-line signal and chip selection signal Block carry out AND operation generation row and select signal Row_Signal, and one-level data selector X1 receives after row selects signal Row_Signal and chooses connected the first word line LWL.Secondary data selector switch X2 is according to reading command signal, erasing instruction signal or reading command signal, select corresponding component voltage, this component voltage is inputted the first selected word line LWL by one-level data selector X1, and is applied on the control grid of the storage unit that this first word line LWL connects.Described secondary data selector switch X2 has multiple, the output port of each secondary data selector switch X2 connects a first word line LWL, for unchecked the first word line LWL, one-level data selector X1 inputs the corresponding secondary data selector switch of unchecked the first word line LWL X2 by the second input port " 00 " by the required voltage of control grid of not choosing storage unit and is sent to corresponding unchecked the first word line LWL, and is applied on the control grid 1 of the storage unit that corresponding the first word line LWL connects.
It should be noted that, the setting of one-level data selector X1, secondary data selector switch X2, read write command signaling switch T2 and T3 is only for illustrating the present invention herein, but not for limiting the scope of the invention, those skilled in the art can adopt other that form is set as required.
Fig. 6 is shown as the connection diagram of read-write control module 104 of the present invention and memory cell array 101.
As shown in Figure 6, one array storage unit shares a read-write control module 104, read-write control module 104 receives column selection signal Column and read write command signal (comprises and reads command signal and write command signal, wherein, write command signal comprises write operation command signal and erase operation command signal) control, all read-write control modules 104 have data reading port Data_out and data to write two ports of inbound port Data_in, and are all connected with data bus.Data reading port Data_out and data are write inbound port Data_in and are respectively equipped with switching transistor T4 and T5, control data reading and write read-write control module 104 by reading command signal Command_read and write command signal Command_write.Write operation command signal Command_write and erase operation command signal Command_erase directly input read-write control module 104 by two paths or a path.
It should be noted that, multiple row storage unit can be shared same read-write control module 104.In the time that multiple row storage unit is shared same read-write control module 104, by reading and writing of switching transistor control data being set on the corresponding drain electrode connecting line of every array storage unit and the first bit line BL respectively.When to a certain the corresponding storage unit sense data of the first word line LWL, switching transistor conducting on the source electrode connecting line of each row of the corresponding storage unit of this first word line LWL, by sense data input read-write control module 104, when data writing according to the switching transistor that writes voltage turn-on respective column.
Fig. 7 is shown as the schematic diagram of read-write control module 104 of the present invention.
Described read-write control module 104 comprises; Data reading port Data_out, data are write inbound port Data_in, analog to digital converter ADC, digital to analog converter DAC and internal data selector switch, wherein,
Described data reading port Data_out is for exporting the data of reading from described storage unit;
Described data are write inbound port Data_in for receiving external data;
Described analog to digital converter ADC is for being converted to digital signal by the data of the current forms of reading from the source S of described storage unit, described digital signal inputs to the first input end mouth " 0 " of the first data selector, and be coupled to data-out port Data_out by switching transistor, the grid of described switching transistor is controlled by column selection signal Column;
Described internal data selector switch is in the time of reading out data, only read the data of Destination Storage Unit M, and be stored in described internal data selector switch by sharing with Destination Storage Unit M the data that other storage unit of same the first word line read, and in the time of write operation, external data is write to Destination Storage Unit M, and will re-write each storage unit in the data of described internal data selector switch with other cell stores of shared same the first word line of Destination Storage Unit.
Described digital to analog converter DAC is converted to voltage signal for the digital signal that will export from described internal data selector switch, and exports the drain D of described storage unit to.
Preferably, described internal data selector switch further comprises the first data selector MUX1, the second data selector MUX2, the 3rd data selector MUX3 and the 4th data selector MUX4, described the first data selector MUX1, the second data selector MUX2, the 3rd data selector MUX3 and the 4th data selector MUX4 comprise three input ports and an output port separately, wherein:
The first input end mouth " 0 " of described the first data selector MUX1 is coupled to the output terminal of described analog to digital converter ADC, the second input port is coupled to data and writes inbound port Data_in, and the 3rd input port meets column selection signal Column, and output port is coupled to described digital to analog converter DAC; The first input end mouth " 0 " of described the first data selector MUX1 is provided with switching transistor T1, and the control grid of described switching transistor T1 is coupled to the 3rd input port of described the first data selector MUX1.
The first input end mouth " 0 " of described the second data selector MUX2 meets idle voltage signal V
d_idle, the second input port " 1 " meets erasing voltage signal Vd_erase, and the 3rd input port is coupled to the 3rd input port of described the first data selector MUX1, and output port connects the second input port of the 3rd data selector MUX3;
The first input end mouth " 0 " of described the 3rd data selector MUX3 is coupled to the output terminal of described digital to analog converter DAC, the second input port " 1 " is coupled to the output port of described the second data selector MUX2, the 3rd input port meets erasing instruction signal Command_erase, and output port connects the second input port " 1 " of the 4th data selector MUX4;
The first input end mouth " 0 " of described the 4th data selector MUX4 meets idle voltage signal V
d_idle, described the second input port " 1 " is coupled to the output port of described the 3rd data selector MUX3, and the 3rd input port meets write command signal Command_write, and output port is coupled to the drain D of described storage unit.
It should be noted that, described the first data selector, the second data selector, the 3rd data selector and the 4th data selector are MUX selector switch, its the 3rd input port is used for receiving column selection signal Column, wherein, first input end mouth " 0 " is provided with switching transistor T1, and the grid of switching transistor T1 connects the 3rd input port.In the time of reading out data, Destination Storage Unit M and the data of other storage unit that share same the first word line LWL with the Destination Storage Unit M source S input read-write control module 104 by each storage unit, by analog to digital converter ADC, the data of current forms are converted to digital signal, now, Destination Storage Unit M is chosen by column selection signal Column, switching transistor T1 conducting, the data (drain-source current) of Destination Storage Unit M read out to external circuit, and be stored in the first data selector MUX1 with the data that other storage unit of shared same the first word line LWL of Destination Storage Unit M are read.
In the time of data writing, need to carry out two operations: erase operation and write operation.For Destination Storage Unit M, the concrete methods of realizing of erase operation is: write command signal Command_write inputs the 4th data selector MUX4, the 4th data selector MUX4 selects first input end mouth " 1 " as data transmission port, the 3rd data selector MUX3 selects the second input port " 1 " according to erasing instruction signal Commond_erase, the second data selector MUX2 receives after column selection signal Column, selective erasing voltage signal Vd_erase is by the second input port " 1 " input the 3rd data selector MUX3 of the 3rd data selector MUX3, export again the drain D of Destination Storage Unit M to through the output port of the 4th data selector MUX4.In the time of erase operation, Destination Storage Unit M is chosen by column selection signal Column, carry out erase operation, in reading state, its data of reading are temporary in the first data selector MUX1 with other storage unit of shared same the first word line LWL of Destination Storage Unit.
For Destination Storage Unit M, the concrete methods of realizing of write operation is: write command signal Command_write inputs the 4th data selector MUX4, the 4th data selector MUX4 selects first input end mouth " 1 " as data transmission port, owing to there is no the input of erasing instruction signal, the 3rd data selector MUX3 selects first input end mouth " 0 ", the second data selector MUX2 and the 3rd data selector MUX3 do not have signal transmission, external data is by the second input port " 1 " input the first data selector MUX1 of the first data selector MUX1, be that the data of digital signal form are changed into voltage signal by DAC by digital to analog converter again, export the drain D of Destination Storage Unit M to by the 3rd data selector MUX3 and the 4th data selector MUX4.Other storage unit that share same the first word line LWL with Destination Storage Unit M are also the drain D that DAC, the 3rd data selector MUX3 and the 4th data selector MUX4 export respective memory unit to by digital to analog converter by the data that are temporary in the first data selector MUX1.
Fig. 8 shows the time sequential routine schematic diagram of Destination Storage Unit M in memory cell array of the present invention.
It should be noted that, Destination Storage Unit M of the present invention refers to selected for carrying out the storage unit of data read-write operation, does not comprise other storage unit that share same the first word line LWL with this Destination Storage Unit M.
Before Destination Storage Unit M is selected, (suppose that other storage unit are not selected yet), the control gate pole tension of all storage unit is placed in intermediate level Vg_idle, and the drain voltage of all storage unit is placed in intermediate level Vd_idle.Now all storage unit are in blocking state, and on half floating boom, amount of charge remains unchanged.
When need to read in Destination Storage Unit M data time, the second word-line signal and chip selection signal Block joint decoding produce row and select signal Row_Signal, and transfer to Destination Storage Unit M and share the control grid of other storage unit of same the first word line with Destination Storage Unit M by the first word line, control gate pole tension is placed in higher level Vg_read, drain voltage remains on medium voltage Vd_idle, the all storage unit that are now connected with this first word line are all in reading state, but according to column selection signal Column, the data that only Destination Storage Unit M stores are read out, the sense data that shares other storage unit of same the first word line with Destination Storage Unit M is stored in read-write control module 104.
Destination Storage Unit M is write fashionable when needs, need to pass through erase operation and two steps of write operation.
While carrying out erase operation, the first word line decoding unit 105 selects signal Row_Signal to the second word-line signal and chip selection signal Block joint decoding generation row, and choose the first word line LWL being connected with Destination Storage Unit M, and apply a higher level Vg_erase by this first word line LWL to Destination Storage Unit M with the control grid of other storage unit that Destination Storage Unit M shares same the first word line LWL, drain electrode applies low voltage Vd_erase, now, Destination Storage Unit M is in erase status, electric charge in its half floating boom is cleared, and share other storage unit of same the first word line LWL still in reading state with Destination Storage Unit M, its sense data is temporary in the first data selector MUX1 in corresponding read-write control module 104.
Then carry out write operation, the control grid that Destination Storage Unit and M and Destination Storage Unit M share other storage unit of same the first word line LWL is applied in one compared with low level Vg_write, drain voltage is applied in a high voltage Vd_write, now Destination Storage Unit M and share other storage unit of same the first word line LWL all in data writing state with Destination Storage Unit M, different is, and Destination Storage Unit M writes is external data, with Destination Storage Unit M share that other storage unit of same the first word line LWL write be before be stored in the data in the first data selector MUX1, other storage unit that share same the first word line LWL with Destination Storage Unit M have been similar to refresh operation one time.
It should be noted that, what in the present invention, storage unit adopted is N-type transistor, if adopt P transistor npn npn, changes the voltage level of its three end, does not affect its technique effect.
In sum, the many bit memory in every unit of the present invention have the following advantages:
First, the present invention has adopted the half floating boom transistor with embedded tunneling field-effect pipe to carry out data storage as storage unit, utilize the bandtoband characteristic of tunnel-through diode can realize the write operation of fast speed on the one hand, by the segmentation control to transistor threshold voltage, realize the storage of the many bits in every unit on the other hand.
Secondly, traditional floating boom transistor needs to apply high level in write operation and erase operation process, as 5V～15V, and the present invention only need apply lower level (3V～3V) and can realize in storage unit the storage of multi-bit data, greatly reduces the power consumption of memory storage.
Again, the present invention has adopted multi-stage data selector switch to combine to carry out decoding in the first word line decoding unit, thereby can choose accurately and efficiently a line storage unit, and by voltage required the first word line of selected line storage unit and not the required voltage of the first word line of selected line storage unit shunt to corresponding storage unit.
In addition, read-write control module of the present invention is by four data selectors, the synergy of digital to analog converter and analog to digital converter, in the time of reading out data, only read the data of Destination Storage Unit, and convert digital signal by sharing with Destination Storage Unit the current signal that other storage unit of same the first word line read to by analog to digital converter, and be stored in internal data selector switch, in the time of write operation, external data is write to Destination Storage Unit, and the data of described storage are re-write to corresponding stored unit, thereby realize exactly the read-write operation to object element.
Finally, the present invention has adopted refresh module in the many bit memory in every unit, with the data in dynamic refresh storage unit, eliminate the electric leakage defect of novel storage unit of the present invention, thereby in matching process, can realize more exactly coupling, improve efficiency and the accuracy of Data Matching.
So the present invention has effectively overcome various shortcoming of the prior art and tool high industrial utilization.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any person skilled in the art scholar all can, under spirit of the present invention and category, modify or change above-described embodiment.Therefore, such as in affiliated technical field, have and conventionally know that the knowledgeable, not departing from all equivalence modifications that complete under disclosed spirit and technological thought or changing, must be contained by claim of the present invention.
Claims (12)
1. the many bit memory in every unit, it is characterized in that, the many bit memory in described every unit comprise: memory cell array, row address decoding module, column address decoding module, read-write control module, many first word lines and many first bit lines, wherein
Described memory cell array comprises multiple storage unit subarrays, the control grid of the storage unit of each subarray is coupled to same the first word line, the source electrode of each storage unit of each subarray and the source-coupled of storage unit that is positioned at same row with it are to same the first bit line, drain electrode and drain coupled to the same that is positioned at the storage unit of same row with it connecting line that drains, described storage unit is except controlling grid, source electrode, drain electrode, also comprise half floating boom, and the doping type of described half floating boom and source electrode, drain electrode are contrary; Described half floating boom contacts and forms an embedded type diode with drain doping region; Described control grid extends to drain doping region top and covers its surface, described half floating boom, drain doping region and the control grid that extends to drain doping region top form an embedded tunneling field-effect transistor, described storage unit produces multiple predetermined current value under multistage predetermined voltage effect, and described multiple predetermined current value is for characterizing the multiple store status of described storage unit;
Described row address decoding module is coupled to described many first word lines, selects signal, and select signal to choose a first word line according to described row for generation of row;
Described column address decoding module is coupled to described read-write control module, for generation of column selection signal, and be sent to read-write control module make it choose first bit line according to described column selection signal;
Described read-write control module is coupled to the drain electrode connecting line of described many first bit lines and described storage unit, be used for receiving described column selection signal and read write command signal, and read and data writing according to storage unit described in described column selection signal and read write command signal controlling.
2. the many bit memory in every unit according to claim 1, is characterized in that, described row address decoding module comprises the first word line decoding unit and the second word line decoding unit, wherein:
Described the second word line decoding element coupling, to described the first word line decoding unit, for generation of the second word-line signal and chip selection signal, and inputs to described the first word line decoding unit;
Described the first word line decoding unit is the control grid to described storage unit by the first word line coupling, for described the second word-line signal and chip selection signal are decoded as to the capable signal that selects, and select signal to choose a first word line according to described row, and receive read write command signal, and the first word line of choosing described in read-write level being applied to according to described read write command signal.
3. the many bit memory in every unit according to claim 2, is characterized in that: described the first word line decoding unit further comprises and gate logic unit, for described the second word-line signal and chip selection signal are carried out to AND operation.
4. the many bit memory in every unit according to claim 3, it is characterized in that: described and gate logic unit is multistage and gate logic unit, wherein, AND operation is carried out in upper level and the output of gate logic unit and the input of the chip selection signal of appropriate level by next stage and gate logic unit.
5. the many bit memory in every unit according to claim 2, is characterized in that, described the first word line decoding unit comprises:
Multiple resistive elements, described multiple resistive elements are connected serially to chip power supply power supply, for generation of a point voltage level;
Data selector, is coupled to described multiple resistive element and many first word lines, for exporting respectively the first corresponding word line to by carrying out the required level of described read write command signal and the required level of the described read write command signal of non-execution.
6. the many bit memory in every unit according to claim 5, is characterized in that, described data selector comprises: one-level data selector and multiple secondary data selector switch, wherein,
Described one-level data selector is coupled to described multiple secondary data selector switch, for exporting described multiple secondary data selector switch to by carrying out required level and the required level of the described read write command signal of non-execution of described read write command signal;
Described multiple secondary data selector switch correspondence is coupled to described many first word lines and described the second word line decoding unit, be used for receiving described row and select signal, and select signal to choose and a first word line of its coupling according to described row, and export described the first word line to by carrying out required level and the required level of the described read write command signal of non-execution of described read write command signal.
7. the many bit memory in every unit according to claim 6, it is characterized in that, described data selector also comprises read write command signaling switch, is coupled to described multiple resistive element and one-level data selector, for according to described read write command signal conduction or shutoff.
8. the many bit memory in every unit according to claim 1, is characterized in that, described read-write control module comprises; Data reading port, data are write inbound port, analog to digital converter, digital to analog converter and internal data selector switch, wherein,
Described data reading port is for exporting the data of reading from described storage unit;
Described data are write inbound port for receiving external data;
Described analog to digital converter is for being converted to digital signal by the data of the current forms of reading from described cell source;
Described internal data selector switch is in the time of reading out data, only read the data of Destination Storage Unit, and be stored in described internal data selector switch by sharing with Destination Storage Unit the data that other storage unit of same the first word line read, and in the time of write operation, external data is write to Destination Storage Unit, and will re-write each storage unit in the data of described internal data selector switch with other cell stores of shared same the first word line of Destination Storage Unit;
Described digital to analog converter is converted to voltage signal for the digital signal that will export from described internal data selector switch, and exports the drain electrode of described storage unit to.
9. the many bit memory in every unit according to claim 8, it is characterized in that, described internal data selector switch further comprises the first data selector, the second data selector, the 3rd data selector and the 4th data selector, described the first data selector, the second data selector, the 3rd data selector and the 4th data selector comprise three input ports and an output port separately, wherein:
The first input end mouth of described the first data selector is coupled to described analog to digital converter and data reading port, and the second input port is coupled to data and writes inbound port, and the 3rd input port connects column selection signal, and output port is coupled to described digital to analog converter;
The first input end mouth of described the second data selector connects idle voltage signal, and the second input port connects erasing voltage signal, and the 3rd input port connects column selection signal, and output port is coupled to the second input port of described the 3rd data selector;
The first input end mouth of described the 3rd data selector is coupled to described digital to analog converter, the second input port is coupled to the output port of described the second data selector, the 3rd input port connects erasing instruction signal, and output port is coupled to the second input port of described the 4th data selector;
The first input end mouth of described the 4th data selector connects idle voltage signal, and described the second input port is coupled to the output port of described the 3rd data selector, and the 3rd input port connects write command signal, and output port is coupled to the drain electrode of described storage unit.
10. the many bit memory in every unit according to claim 8, is characterized in that: the output of described analog to digital converter is also connected to data reading port by switching transistor, and the grid of described switching transistor is connected to column selection signal.
The 11. many bit memory in every unit according to claim 1, it is characterized in that: also comprise refresh module, described refresh module is coupled to described row address decoding module, column address decoding module and read-write control module, for periodically producing refresh signal, and according to this signal from described storage unit sense data, and sense data is re-write to described storage unit.
The 12. many bit memory in every unit according to claim 11, is characterized in that, described refresh module further comprises counting unit, and described counting unit is for described refresh signal is counted, and output is for the row address of refresh operation.
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