CN103714853B - NAND content addressable memory - Google Patents
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- CN103714853B CN103714853B CN201310724562.6A CN201310724562A CN103714853B CN 103714853 B CN103714853 B CN 103714853B CN 201310724562 A CN201310724562 A CN 201310724562A CN 103714853 B CN103714853 B CN 103714853B
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Abstract
The present invention provides a NAND content addressable memory, including some kernel unit, described kernel unit includes again comparing unit, read-write cell and data storage cell, wherein, data storage cell includes two and half floating transistor, and this half floating transistor is stored in data bit by changing self threshold voltage. The structure that the present invention not only simplifies the content addressable memory (CAM) cell in prior art based on SRAM is complicated, and achieves the flexible switching between binary form Content Addressable Memory and ternary form Content Addressable Memory.
Description
Technical field
The present invention relates to memory technology, particularly relate to NAND content addressable memory.
Background technology
The pith of the buffer memory in Content Addressable Memory (ContentAddressableMemory, CAM) processor, is also for judging the pith of packet sending direction in router. In common memorizer such as random access storage device (RandomAccessMemory, RAM) is applied, user provides a storage address, and memorizer returns the data being stored in this address according to this address. And in the application of Content Addressable Memory, user provides data, Content Addressable Memory can travel through whole memory space, search for whether these data are present in memorizer, if it is, namely hit, Content Addressable Memory returns to the address of one or more hiting datas.
Content Addressable Memory, as a kind of special memory, can search for whole memorizer in word computing, so in search application, Content Addressable Memory than normal memory fast a lot. The fast search characteristic of Content Addressable Memory makes Content Addressable Memory be particularly well-suited to such as the network equipment, CPU(CenterProcessingUnit, CPU) and DSP(DigitalSignalProcessor, digital signal processor) Cache(buffer storage), the application such as hard encoding and decoding of video.
NAND content addressable memory is a kind of common Content Addressable Memory framework, for binary form Content Addressable Memory (namely the storage data of Content Addressable Memory are for " 0 " or " 1 "), as shown in Figure 1, completed the storage of data by the SRAM including two cross-linked phase inverters in the elementary cell of Content Addressable Memory, M1 is switching tube, it is series on matched line, M2 and M3 and M1 connects, for being mated with storage inside data by external search signal, M4 and M5 is used as the gate tube that SRAM is written and read. Owing to the grid of M2 and M3 is controlled respectively by two complementary signals, so both always have and only one of which is in the conduction state. SL_a and SL_b is the search signal of a pair complementation, and M4 and M5 all connects wordline and bit line, for controlling the conducting of M4 and M5 and the reading of data.
As in figure 2 it is shown, multiple content addressable memory (CAM) cells composition multiple line content addressable memory block, last content addressable memory (CAM) cell of each Content Addressable Memory block is connected with lower trombone slide T1 again.Under original state, each matched line is charged to a certain level (being charged to supply voltage Vdd generally in advance) by preliminary filling pipe T2 in advance, and preliminary filling pipe T2 disconnects afterwards, and lower trombone slide T1 turns on. Search signal is input to each Content Addressable Memory block parallel and is compared, if the content addressable memory (CAM) cell stored data of certain a line is mated completely with search signal, then the switching tube corresponding to each content addressable memory (CAM) cell of this row all turns on, and namely combines lower trombone slide T1 and matched line is pulled down to low level. If certain unit stored data is not mated with search signal in the Content Addressable Memory of certain a line, then the switching tube that this content addressable memory (CAM) cell is corresponding disconnects, so that the matched line of this row is unsettled, keeps high level. By whether stored data in comparison all the elements addressable memory row mates with the search signal of input, from multiple Content Addressable Memory blocks, finally produce a matched signal, thus completing content-based addressing operation.
If using A dotted state as the SRAM data stored, SL_a is the value of search signal, it is assumed that search signal SL_a is " 1 ", then its complementary signal SL_b is " 0 ", now the conducting of M2 pipe, and M3 pipe blocks. If it is " 1 " that SRAM stores data, namely match with search signal, then the conducting of M1 pipe; If it is " 0 " that SRAM stores data, namely do not mate with search signal, then M1 pipe blocks. If in like manner search signal SL_a is " 0 ", then its complementary signal SL_b is " 1 ", and now M2 pipe blocks, and M3 pipe turns on. If it is " 0 " that SRAM stores data, namely match with search signal, then the conducting of M1 pipe; If it is " 1 " that SRAM stores data, namely do not mate with search signal, then M1 pipe blocks.
Thus, if the storage data of certain row all the elements addressable memory (CAM) cell are all mated with search signal, then the matched line of this row can be connected to ground by the lower trombone slide T1 of the gate tube in each content addressable memory (CAM) cell and, thus being pulled low; If the storage data having one or more content addressable memory (CAM) cell in certain row are not mated with search signal, then the switching tube of corresponding contents addressable memory (CAM) cell disconnects, the matched line of this row is in vacant state, thus keeping its original state, i.e. and high level.
For ternary form Content Addressable Memory, (namely no matter search signal is " 0 " or " 1 " then to need storage " X ", can both the match is successful), correspondingly, need to adopt two independent sram cells to make A in Content Addressable Memory, B 2 is " 1 " simultaneously, as shown in Figure 3, thus ensureing that the grid of M1 is whether by M2 or M3, high level can be pulled to, thus ensureing the normally open of M1, also need to configure corresponding coupling pipe and switching tube simultaneously, a content addressable memory (CAM) cell is made to need at least 15 transistors of employing, cause content addressable memory (CAM) cell structure complicated, the problem that area occupied is bigger. additionally, itself circuit structure of ternary form Content Addressable Memory and binary form Content Addressable Memory is different, needing the occasion realizing ternary form Content Addressable Memory and binary form Content Addressable Memory function at the same time, both can not switch flexibly.
Summary of the invention
The shortcoming of prior art in view of the above, it is an object of the invention to provide a NAND content addressable memory, complicated based on the content addressable memory (CAM) cell structure of SRAM for solving in prior art, and the problem that ternary form Content Addressable Memory and binary form Content Addressable Memory can not switch flexibly.
For achieving the above object and other relevant purposes, the present invention provides a NAND content addressable memory, described Content Addressable Memory includes some kernel unit, described kernel unit includes comparing unit, read-write cell and data storage cell, wherein: described comparing unit includes the first transistor, transistor seconds and third transistor, described the first transistor is connected on a match line, the grid of described transistor seconds and third transistor connects the search signal of a pair complementation respectively, and the first electrode couples with the grid of described the first transistor; Described read-write cell includes the 4th transistor and the 5th transistor, and the grid of described 4th transistor and the 5th transistor connects wordline, and the first electrode connects the first bit line and the second bit line respectively; Described data storage cell includes the 6th transistor and the 7th transistor, the control gate of described 6th transistor and the 7th transistor connects the first wiring, drain electrode connects the second wiring and the 3rd wiring respectively, the source electrode of the 6th transistor connects transistor seconds and the second electrode of the 4th transistor, the source electrode of the 7th transistor connects third transistor and the second electrode of the 5th transistor, described 6th transistor and the 7th transistor and is stored in data bit by changing self threshold voltage.
Preferably, also include: precharge unit, be coupled to described matched line, in order to described matched line is precharged to predetermined voltage.
Preferably, also including: the first wiring and the second wiring, described first wiring connects the grid of the 6th transistor and the 7th transistor, and the second wiring connects the drain electrode of the 6th transistor and the 7th transistor.
Preferably, described 6th transistor and the 7th transistor store two kinds of data bit, and the one of which in described 6th transistor and the 7th transistor has more less threshold voltage than another one.
Preferably, described 6th transistor and the 7th transistor storage three kinds of data bit, the one of which in described 6th transistor and the 7th transistor have than the less threshold voltage of another one or both there is identical lower threshold voltage.
Preferably, described data bit is " 0 ", " 1 " and " X ", and when data bit is " 0 " or " 1 ", the one of which in described 6th transistor and the 7th transistor has more less threshold voltage than another one; When data bit is " X ", described 6th transistor and the 7th transistor have identical lower threshold voltage.
Preferably, described identical lower threshold voltage is described 6th transistor and the 7th transistor is stored in the threshold voltage after data " 1 ".
Preferably, described 6th transistor and the 7th transistor, except control gate, source doping region, drain doping region, also include half floating boom, and the doping type of described half floating boom and source doping region, drain doping region are contrary; Described half floating boom contacts with drain doping region and forms an embedded type diode; Described control gate extends to above drain doping region and covers its surface, described half floating boom, drain doping region and extend to the control gate above drain doping region and form an embedded tunneling field-effect transistor.
Preferably, described some kernel unit constitute a matrix, the corresponding matched line of every a line kernel unit in described matrix, every a line kernel unit is connected on a match line by the first transistor, the end of described matched line connects trombone slide, described lower trombone slide connects common ground end, and transistor seconds and the grid of third transistor in every string kernel unit are shared with a pair complementary search signal.
Preferably, also including refresh unit, described refresh unit coupled to described read-write cell and memory element, and reads data by controlling described read-write cell, by controlling described memory element erasing data and re-writing data.
Preferably, described refresh unit includes:
Memory element, for storing the data read from described memory element;
Write operation element, for re-writing described memory element by the data of described reading.
As it has been described above, the NAND content addressable memory of the present invention, have the advantages that
First, the present invention have employed the transistor with data storage function in NAND content addressable memory, compared with storing data with traditional SRAM adopting paired phase inverter, not only reduce the area of Content Addressable Memory, when needs realize ternary form Content Addressable Memory, save substantial amounts of area especially.
Secondly, the NAND content addressable memory of the present invention can when not changing circuit structure, realize the flexible conversion between binary form and ternary form Content Addressable Memory, with traditional based on compared with the NAND content addressable memory of SRAM, substantially increasing the service efficiency of chip area.
Again, the present invention have employed refresh unit in NAND content addressable memory, with the data in dynamic refresh memory element, eliminate the electric leakage defect of novel memory element of the present invention, thus coupling can be realized in the matching process more exactly, improve efficiency and the accuracy of Data Matching.
Accompanying drawing explanation
The cellular construction schematic diagram that Fig. 1 is shown as in prior art based on the NAND binary content addressable memory of SRAM.
The structural representation that Fig. 2 is shown as in prior art NAND content addressable memory array.
The cellular construction schematic diagram that Fig. 3 is shown as in prior art based on the NAND ternary content addressable memorizer of SRAM.
The cellular construction schematic diagram of the NAND content addressable memory embodiment that Fig. 4 is shown as in the present invention.
The structural representation of the memory element that Fig. 5 is shown as in the NAND content addressable memory embodiment in the present invention.
The capacitance profile schematic diagram of the memory element that Fig. 6 is shown as in the NAND content addressable memory embodiment in the present invention.
The structural representation of the NAND content addressable memory array that Fig. 7 is shown as in the present invention.
The read-write operation time diagram of the NAND content addressable memory that Fig. 8 is shown as in the present invention.
Element numbers explanation
M1 the first transistor
M2 transistor seconds
M3 third transistor
M4 the 4th transistor
M5 the 5th transistor
M6 the 6th transistor
M7 the 7th transistor
1 control gate
2 half floating booms
3 source doping region
4 substrates
5 drain doping region
6 tunneling field-effect transistors
7 diffusion regions
8 diodes
9 heavily doped regions
SL_a search signal
The complementary search signal of SL_bSL_a
Line_n matched line
Row_select wordline
G_n first connects up
Datain_a second connects up
Datain_b the 3rd connects up
Dataout_a the first bit line
Dataout_b the second bit line
CAM content addressable storage unit
Trombone slide under T1
T2 preliminary filling pipe
Adress address
Data data
The Read data read-out stage
The Erase data erasing stage
Write data write phase
Detailed description of the invention
Below by way of specific instantiation, embodiments of the present invention being described, those skilled in the art the content disclosed by this specification can understand other advantages and effect of the present invention easily. The present invention can also be carried out by additionally different detailed description of the invention or apply, and the every details in this specification based on different viewpoints and application, can also carry out various modification or change under the spirit without departing from the present invention.
It is understood that when an element is referred to as " connecing " or " coupleding to " another element, it can be directly connected to or be coupled to another element, it is also possible to is there is marginal element. And when an element is referred to as " being directly connected to " or " coupling directly to " another element, then it is absent from marginal element.
Existing NAND binary content addressable memory and NAND ternary content addressable memory cell need mostly adopt the SRAM of the paired cross-linked phase inverter storage completing data, add multiple supporting transistor, make content addressable memory (CAM) cell structure complexity, area occupied bigger, additionally, itself circuit structure of NAND ternary content addressable memorizer and NAND binary content addressable memory is different, it is impossible to switch over flexibly. The present invention is based on above-mentioned consideration, design a kind of novel Content Addressable Memory, not only simplify the structure of memory cell, and when not changing memory unit, binary content addressable memory can be realized, ternary form Content Addressable Memory can be realized again, substantially increase the utilization rate of Content Addressable Memory.
Present disclosure addressable memory includes some kernel unit, described kernel unit includes data storage cell, comparing unit and read-write cell, described data storage cell, comparing unit and read-write cell intercouple, and it being respectively provided with the transistor of a pair positional symmetry, all of transistor is combined and is together constituted symmetrical structure. Transistor in described data storage cell, comparing unit and read-write cell can be nmos pass transistor or PMOS transistor, and the annexation of each transistor source and drain electrode can do proper transformation. The pair of transistor of described data storage cell can be stored in " 0 " and " 1 " of complementation by changing self threshold voltage, " 1 " can also be stored in simultaneously, both can serve as binary content addressable memory, it is also possible to as ternary form Content Addressable Memory.
Structure and the embodiment of present invention addressable memory is illustrated below with reference to accompanying drawing.
Refer to the cellular construction schematic diagram of Content Addressable Memory embodiment in Fig. 4 present invention.
It should be noted that, the diagram provided in the present embodiment only illustrates the basic conception of the present invention in a schematic way, then assembly that in graphic, only display is relevant with the present invention but not component count when implementing according to reality, shape and size drafting, during its actual enforcement, the kenel of each assembly, quantity and ratio can be a kind of random change, and its assembly layout kenel is likely to increasingly complex.
Also, it should be noted in the present embodiment, the transistor in described data storage cell, comparing unit and read-write cell is nmos pass transistor.
Content Addressable Memory includes some kernel unit, and described kernel unit includes comparing unit, read-write cell and data storage cell, wherein,
Described comparing unit includes the first transistor M1, transistor seconds M2 and third transistor M3, described the first transistor M1 is connected on matched line Line_n, the grid of described transistor seconds M2 and third transistor M3 meets search signal SL_a and the SL_b of a pair complementation respectively, and the first electrode couples with the grid of described the first transistor M1;
Described read-write cell includes the 4th transistor M4 and the five transistor M5, and the grid of described 4th transistor M4 and the five transistor M5 meets wordline row_select, and the first electrode meets the first bit line dataout_a and the second bit line dataout_b respectively;
Described data storage cell includes the 6th transistor M6 and the seven transistor M7, the control gate of described 6th transistor M6 and the seven transistor M7 meets the first wiring G_n, drain electrode connects the second wiring datain_a and the three respectively and connects up datain_b, the source electrode of the 6th transistor M6 connects second electrode of transistor seconds M2 and the four transistor M4, the source electrode of the 7th transistor M7 connects second electrode of third transistor M3 and the five transistor M5, and described 6th transistor M6 and the seven transistor M7 is stored in data bit by changing self threshold voltage.
It should be noted that the first transistor M1, transistor seconds M2, third transistor M3, the source electrode of the 4th transistor M4 and the five transistor M5 and the annexation of drain electrode can do proper transformation, for instance described first electrode is drain electrode, and the second electrode is source electrode; Or the first electrode is source electrode, the second electrode is drain electrode. In embodiments of the present invention, described first electrode is drain electrode, and the second electrode is source electrode.
Described first wiring G_n is for providing grid voltage to the control gate of described 6th transistor M6 and the seven transistor M7, and the second wiring datain_a and the three connects up datain_b for being stored in data bit to described 6th transistor M6 and the seven transistor M7 respectively.
Fig. 5 is the structural representation of memory element the 6th transistor M6 and the seven transistor M7 of the present invention.
It should be noted that described 6th transistor M6 and the seven transistor M7 includes outside control gate 1, source doping region 3, drain doping region 5, also include half floating boom 2, and the doping type of described half floating boom 2 and source doping region 3, drain doping region 5 are contrary; Described half floating boom 2 contacts and is formed an embedded type diode with drain doping region 5; Described control gate 1 extends to above drain doping region 5 and covers its surface, described half floating boom 2, drain doping region 5 and extend to the control gate 1 above drain doping region 5 and form an embedded tunneling field-effect transistor. For comparison other, described 6th transistor M6 and the seven transistor M7 principle of adjustment and control to transistor threshold voltage is described with common MOS transistor below:
The electric conductivity of common MOS transistor raceway groove by gate voltage regulate and control, when grid voltage exceedes threshold voltage, the semiconductor surface under grid will transoid (n-type semiconductor becomes p-type semiconductor or contrary), generate conducting charge. Gate voltage is more big, and the conducting charge quantity of the accumulation in raceway groove is more many.
As it is shown in figure 5, described 6th transistor M6 and the seven transistor M7 includes control gate 1, half floating boom 2, source doping region 3, substrate 4, drain doping region 5. As better embodiment, the 6th transistor M6 and the seven transistor M7 structure is placed in P type substrate 4 or P type trap zone, and its source doping region 3, drain doping region 5 are n-type doping, the polysilicon structure that its half floating boom 2 adulterates for P type. It is to be noted, half floating boom 2 part is positioned at above raceway groove and isolates with substrate 4, part contacts with drain doping region 5, and a shallower p type diffusion region 7 is formed with drain doping region 5 in the region that half floating boom 2 contacts, this p type diffusion region is positioned at close substrate 4 surface, drain doping region 5 and namely the region contacted with half floating boom 2, half floating boom 2 of this P type doping and the building doped region 5 of p type diffusion region 7 and n-type doping form a PN junction diode 8. In addition, control gate 1 covers half floating boom 2 surface by gate oxide and is positioned at the sidewall of side, drain doping region 2, extending partially into above drain doping region 5 and cover its surface, half floating boom 2/P type diffusion region 7 of this part and the doping of P type and drain doping region 5 are drawn the N-type heavily doped region 9 of drain electrode and are formed an embedded tunneling field-effect transistor 6.It should be noted that between part half floating boom 2 and substrate 4, control gate 1 be all arranged at intervals with gate oxide or other similar insulation systems, this conventional techniques being well known to those skilled in the art between half floating boom 2 and substrate 4, therefore not to repeat here.
Fig. 6 is gate capacitance distribution schematic diagram in memory element the 6th transistor M6 and the seven transistor M7 in the present invention.
As shown in Figure 6, the 6th transistor M6 and the seven transistor M7 is considered as inserting an electrode (i.e. half floating boom 2) in the gate capacitance medium of normal transistor, thus original gate capacitance has been divided into two electric capacity Cg1And Cg2Series connection. The threshold voltage of the 6th transistor M6 and the seven transistor M7, the electric conductivity of regulation and control raceway groove can be changed by injecting electric charge on half floating boom 2. The principle of its regulation and control threshold voltage is it is to be understood that the 6th transistor M6 and the seven transistor M7 has initial threshold voltage Vth, when the 6th transistor M6 and the seven transistor M7 starts working, the electric charge injected on half floating boom 2 can pass through the gate capacitance C between half floating boom 2 and transistor channelg2Inducing channel charge in transistor channel side, the positive charge on half floating boom 2 is more many, and in raceway groove, the negative charge of sensing is also more many, and the electric conductivity of N-type channel is more strong. This equivalent is to control gate 1, compared with before half floating boom 2 charging, 1 need of control gate add less gate voltage just can induce the channel charge of equivalent in channels, reaching identical conductive effect, the threshold voltage of the 6th transistor M6 and the seven transistor M7 just reduces so in form. When the 6th transistor M6 and the seven transistor M7 is N-type transistor, the write of data " 1 " is by control gate 1 is placed in low-voltage, drain electrode is placed in high voltage, makes embedded tunneling field-effect transistor 6 that band-to-band-tunneling to occur, and electric charge flows to half floating boom 2 from drain region. The erasing of data is then by control gate 1 is placed in high voltage, and drain electrode is placed in low-voltage, makes tunneling field-effect transistor 6 positively biased, and the positive charge in half floating boom 2 flows back to drain region. Owing to the positive charge in half floating boom 2 can reduce the threshold voltage of N pipe so that N pipe is easier to conducting. So can set that a grid voltage, if being not injected into abundant positive charge in half floating boom 2, then N pipe is not turned on, if half floating boom 2 injects abundant positive charge, then N pipe conducting, thus realizing the storage of data. If write data " 0 ", then drain electrode datain_a and datain_b is set to low level, so that half floating boom 2 keeps the original state without positive charge.
It should be noted that, described the first transistor M1 is switching tube, grid connects the drain electrode of transistor seconds M2 and third transistor M3, source electrode and drain electrode matching connection line Line_n, the grid of transistor seconds M2 and third transistor M3 meets search signal SL_a and the SL_b of a pair complementation respectively, the source electrode of transistor seconds M2 connects the source electrode of the 4th transistor M4 and the source electrode of the 6th transistor M6, and the source electrode of third transistor M3 connects the source electrode of the 5th transistor M5 and the source electrode of the 7th transistor M7. The drain electrode of the 4th transistor M4 and the five transistor M5 meets the first bit line dataout_a and the second bit line dataout_b respectively.
It should be noted that, described some kernel unit constitute a matrix, the corresponding matched line of every a line kernel unit in described matrix, every a line kernel unit is connected on matched line Line_n by the first transistor M1, the end of described matched line Line_n connects trombone slide T1, described lower trombone slide T1 connects common ground end, and transistor seconds M2 and the grid of third transistor M3 in every string kernel unit are shared with a pair complementary search signal SL_a and SL_b.
Preferably, described Content Addressable Memory also includes refresh unit, and described refresh unit coupled to described read-write cell and memory element, and reads data by controlling described read-write cell, by controlling described memory element erasing data and re-writing data.
Specifically, described refresh unit includes: memory element, for storing the data read from described memory element; Write operation element, for re-writing described memory element by the data of described reading.
Due to after the electric charge that the tunneling field-effect pipe 6 of the 6th transistor M6 and the seven transistor M7 injects in half floating boom 2, have leaky, therefore, the present invention also add a refresh unit in Content Addressable Memory, refreshes the data of storage in described content addressable memory (CAM) cell CAM for dynamic. Its refresh operation is with behavior unit, by the 4th transistor M4 and the five transistor M5 conducting of the content addressable memory (CAM) cell CAM of each row, its storage inside data can be read, then the data of this reading are re-write the 6th transistor M6 and the seven transistor M7.
Fig. 7 is the structural representation of the Content Addressable Memory array in the present invention.
Some kernel unit of described Content Addressable Memory constitute a matrix, the first transistor M1 of the kernel unit of every a line is commonly connected on same matched line Line_n, the output matching line of last kernel unit of each row kernel unit group connects the lower trombone slide T1 of a ground connection, the grid of all lower trombone slide T1 receives same control signal wire, all lower trombone slide T1 are placed in unified level and lower trombone slide T1 are turned on by described control signal wire, when certain row all the elements stored data of addressable memory (CAM) cell CAM all matches with corresponding search signal, then the matched line of this row can be connected to ground by the first transistor M1 in each content addressable memory (CAM) cell CAM and lower trombone slide T1, thus level is pulled low. and when certain row there being one or more stored data of content addressable memory (CAM) cell CAM do not mate with corresponding search signal, then this row matched line can because these not matching unit the first transistor M1 disconnect and be in vacant state, thus keeping its original state, i.e. high level.
Two complementary search signals are connect respectively with the grid of the transistor seconds M2 and third transistor M3 that belong to comparing unit in some kernel unit of string, such as, when the transistor seconds M2 search signal connect is for " 1 ", the search signal that third transistor M3 connects is then for " 0 ". Preferably, Content Addressable Memory also includes precharge unit, is connected to described matched line, in order to described matched line is precharged to predetermined voltage. Described precharge unit includes a preliminary filling pipe T2, each row content addressable memory (CAM) cell CAM meets a preliminary filling pipe T2, one end matching connection line of all preliminary filling pipe T2, grid is received on same preliminary filling holding wire, the conducting of preliminary filling pipe T2 is controlled by controlling preliminary filling signal, in order to charge to matched line, the original state of matched line is made to be in high level.
Embodiment 1
In this embodiment, described Content Addressable Memory is used as NAND binary content addressable memory, the 6th transistor M6 and the seven transistor M7 in described memory element stores two kinds of data bit " 0 " and " 1 ", one of which in described 6th transistor M6 and the seven transistor M7 has more less threshold voltage than another one, and namely the threshold voltage of the transistor of write data " 1 " is lower than the threshold voltage of the transistor of write data " 0 ".
As shown in Figure 7, SL_a and SL_b is the search signal of a pair complementation, Line_n is matched line, row_select is wordline, G_n is the first wiring, control gate for the 6th transistor M6 and the seven transistor M7 provides control signal, datain_a is the second wiring, datain_b is the 3rd wiring, the drain electrode that datain_a and datain_b is the 6th transistor M6 and the seven transistor M7 provides data write signal, dataout_a is the first bit line, dataout_b is the second bit line, dataout_a and dataout_b connects the drain electrode of the 4th transistor M4 and the five transistor M5 respectively.
It should be noted that, as shown in Figure 8, in described content addressable memory (CAM) cell CAM, stored data write in the following manner: first wipe former data, the control gate G_n of the 6th transistor M6 and the seven transistor M7 is set to high level, its drain electrode datain_a and datain_b is set to low level, tunneling field-effect pipe positively biased in 6th transistor M6 and the seven transistor M7, the electric charge in half floating boom 2 all flows to drain region. Then new data is write, the control gate G_n of the 6th transistor M6 and the seven transistor M7 is set to low level, according to the data to write, drain electrode datain_a and datain_b is set to corresponding level, specifically, if write data " 1 ", then drain electrode datain_a and datain_b is set to high level, so that positive charge is injected in half floating boom 2 by drain region, if write data " 0 ", then drain electrode datain_a and datain_b is set to low level, so that half floating boom 2 keeps the original state without positive charge.
Before mating, conducting preliminary filling pipe T2, and every matched line is charged to all in advance a certain level (being charged to supply voltage Vdd generally in advance), it is then turned off preliminary filling pipe T2, all of search signal SL_a and SL_b is set to high level, all of wordline row_select is set to high level, dataout_a and dataout_b is set to low level, the control gate G_n of the 6th transistor M6 and the seven transistor M7 is set to relatively low level, now, 4th transistor M4 and the five transistor M5 conducting, half floating boom 2 of the 6th transistor M6 and the seven transistor M7 is in poised state but is not turned on, A point and B point are moved to low level in advance respectively through the 4th transistor M4 and the five transistor M5, C point is by transistor seconds M2 and the four transistor M4, or moved to low level in advance by third transistor M3 and the seven transistor M7, then turns on pull-down pipe T1, complete the work before coupling.
Starting afterwards normally to mate work, the 4th transistor M4 and the five transistor M5 blocks, and datain_a and datain_b connects uniform level, and G_n also connects uniform level. In the present embodiment, 6th transistor M6 and the seven transistor M7 stores two kinds of data bit " 0 " and " 1 ", if unification is injected abundant positive charge in half floating boom 2 of the 6th transistor M6 and the seven transistor M7 and is represented that this transistor stored data is for " 1 ", if not being stored in abundant positive charge to represent that this transistor stored data is 0.
Search signal SL_a and SL_b is compared by the content addressable memory (CAM) cell group being input to each row parallel, and the number of the content addressable memory (CAM) cell CAM that each content addressable memory (CAM) cell group comprises depends on the bit wide of data. If search signal SL_a is " 1 ", then its complementary signal SL_b is " 0 ", transistor seconds M2 turns on, third transistor M3 pipe blocks, now, if the 6th transistor M6 stored data is " 1 ", then the 7th transistor M7 stored data is " 0 ", 6th transistor M6 conducting, 7th transistor M7 blocks, now search signal SL_a and SL_b and the six transistor M6 and the seven transistor M7 stored data matches, and the grid voltage of the first transistor M1 is drawn high to datain_a by the 6th transistor M6 and transistor seconds M2, thus in the conduction state.If all of content addressable memory (CAM) cell CAM stored data of this row is all mated with search signal, then all of the first transistor M1 that changes one's profession is both turned on, and matched line is pulled down to low level by lower trombone slide T1.
If it is " 0 " that the 6th transistor M6 stores data, then the 7th transistor M7 stored data is " 1 ", 6th transistor M6 blocks, 7th transistor M7 conducting, now search signal SL_a and the six transistor M6 stored data is not mated, and search signal SL_b and the seven transistor M7 does not also mate, the grid voltage of the first transistor M1 is unsettled, the first transistor M1 blocks, so that the matched line of this row is unsettled, keeps high level.
In like manner, if search signal SL_a is " 0 ", then its complementary signal SL_b is " 1 ", transistor seconds M2 blocks, third transistor M3 pipe turns on, now, if the 6th transistor M6 stored data is " 0 ", then the 7th transistor M7 stored data is " 1 ", 6th transistor M6 blocks, the 7th transistor M7 conducting, and now search signal SL_a and SL_b and the six transistor M6 and the seven transistor M7 stored data matches, the grid voltage of the first transistor M1 is drawn high to datain_b by third transistor M3 and the seven transistor M7, thus in the conduction state. If all of content addressable memory (CAM) cell CAM stored data of this row is all mated with search signal, then all of the first transistor M1 of this row is both turned on, and matched line is pulled down to low level by lower trombone slide T1.
If the 6th transistor M6 pipe storage data are " 1 ", then the 7th transistor M7 stored data is " 0 ", 6th transistor M6 conducting, 7th transistor M7 blocks, and now search signal SL_a and the six transistor M6 stored data is not mated, and search signal SL_b and the seven transistor M does not also mate, the grid voltage of the first transistor M1 is unsettled, the first transistor M1 blocks, so that the matched line of this row is unsettled, keeps high level.
By whether content addressable memory (CAM) cell CAM stored data in all row of comparison mates with the search signal of input, from multiple row, finally produce a matched signal, thus completing content-based addressing operation.
The above analysis, it is similar to the NAND content addressable memory based on above-mentioned SRAM, when certain row all the elements stored data of addressable memory (CAM) cell CAM all matches with corresponding search signal, then the matched line of this row can be connected to ground by the lower trombone slide T1 of the switching tube in each content addressable memory (CAM) cell CAM and, thus being pulled low. And when certain row all the elements addressable memory (CAM) cell CAM has one or more storage data not mate with corresponding search signal, then this row matched line can because these not matching unit switching tube disconnect and be in vacant state, thus keeping its original state, i.e. high level. In the matching process, due to half floating boom 2 of the 6th transistor M6 and the seven transistor M7 always has one and only have one be written into data " 1 ", the threshold voltage of the one of write data is lower than the threshold voltage of the one of write data " 0 ".
Embodiment 2
In this embodiment, described Content Addressable Memory is used as NAND ternary content addressable memorizer, in described memory element the 6th transistor M6 and the seven transistor M7 store three kinds of data bit " 0 ", " 1 " and " X ", the one of which in described 6th transistor M6 and the seven transistor M7 have than the less threshold voltage of another one or both there is identical threshold voltage.
It should be noted that X is commonly referred to " mask bit ", or being called " ignoring " state, namely no matter search signal is " 0 " or " 1 ", can both the match is successful.When the data bit of storage is " 0 " or " 1 ", the one of which in described 6th transistor M6 and the seven transistor M7 has more less threshold voltage than another one; When the data bit of storage is " X ", described 6th transistor M6 and the seven transistor M7 has identical threshold voltage. Described identical threshold voltage is the threshold voltage after described 6th transistor M6 and the seven transistor M7 is stored in data bit " 1 ".
When the data bit of storage is " 0 " or " 1 ", the matching process of described Content Addressable Memory is identical with embodiment 1, now, owing to having one need to be written into data in half floating boom 2 of the 6th transistor M6 and the seven transistor M7, the threshold voltage of the one of write data is lower than the threshold voltage of the one of write data " 0 ". When the data bit of storage is " X ", 6th transistor M6 and the seven transistor M7 all writes " 1 ", then the 6th transistor M6 and the seven transistor M7 is in the conduction state all the time, described 6th transistor M6 and the seven transistor M7 has an identical threshold voltage, and threshold voltage when being below write data " 0 ".
If search signal SL_a is " 1 ", then its complementary signal SL_b is " 0 ", transistor seconds M2 turns on, third transistor M3 pipe blocks, now, search signal SL_a and the six transistor M6 matches, and the grid voltage of the first transistor M1 is drawn high to datain_a by transistor seconds M2 and the six transistor M6, thus in the conduction state.
If search signal SL_a is 0, then its complementary signal SL_b is " 1 ", transistor seconds M2 blocks, third transistor M3 pipe turns on, now, search signal SL_b and the seven transistor M7 stored data matches, and the grid voltage of the first transistor M1 is drawn high to datain_b by third transistor M3 and the seven transistor M7, thus in the conduction state.
So no matter search signal SL_a is " 0 " or " 1 ", this content addressable memory (CAM) cell CAM can the match is successful, the switching tube the first transistor M1 of its correspondence can turn on, thus realizing the storage of similar X value, described Content Addressable Memory is converted to the ternary form of the present embodiment by the binary form of embodiment 1.
It should be noted that, due to after the electric charge that the tunneling field-effect pipe of the 6th transistor M6 and the seven transistor M7 injects in half floating boom 2, have leaky, therefore, the present invention also add a refresh unit in Content Addressable Memory, for reading the data of storage in described content addressable memory (CAM) cell CAM dynamically, then the data read are write in content addressable memory (CAM) cell CAM. Described refresh unit coupled to grid and the drain electrode of the 4th transistor M4 and the five transistor M5, and the control gate of the 6th transistor M6 and the seven transistor M7 and drain electrode. Preferably, described refresh unit includes: memory element, for storing the data read from described memory element; Write operation element, for re-writing described memory element by the data of described reading.
In sum, the NAND content addressable memory of the present invention, have the advantages that
First, the present invention have employed the transistor with data storage function in NAND content addressable memory, compared with storing data with traditional SRAM adopting paired phase inverter, not only reduce the area of Content Addressable Memory, when needs realize ternary form Content Addressable Memory, save substantial amounts of area especially.
Secondly, the NAND content addressable memory of the present invention can when not changing circuit structure, realize the flexible conversion between binary form and ternary form Content Addressable Memory, with traditional based on compared with the NAND content addressable memory of SRAM, substantially increasing the service efficiency of chip area.
Again, the present invention have employed refresh unit in NAND content addressable memory, with the data in dynamic refresh memory element, eliminate the electric leakage defect of novel memory element of the present invention, thus coupling can be realized in the matching process more exactly, improve efficiency and the accuracy of Data Matching.
So, the present invention effectively overcomes various shortcoming of the prior art and has high industrial utilization.
Above-described embodiment is illustrative principles of the invention and effect thereof only, not for the restriction present invention. Above-described embodiment all under the spirit and category of the present invention, can be modified or change by any those skilled in the art. Therefore, art has usually intellectual such as modifying without departing from all equivalences completed under disclosed spirit and technological thought or change, must be contained by the claim of the present invention.
Claims (9)
1. a NAND content addressable memory, it is characterised in that described Content Addressable Memory includes some kernel unit, and described kernel unit includes comparing unit, read-write cell and data storage cell, wherein,
Described comparing unit includes the first transistor, transistor seconds and third transistor, described the first transistor is connected on a match line, the grid of described transistor seconds and third transistor connects the search signal of a pair complementation respectively, and the first electrode couples with the grid of described the first transistor;
Described read-write cell includes the 4th transistor and the 5th transistor, and the grid of described 4th transistor and the 5th transistor connects wordline, and the first electrode connects the first bit line and the second bit line respectively;
Described data storage cell includes the 6th transistor and the 7th transistor, the control gate of described 6th transistor and the 7th transistor connects the first wiring, drain electrode connects the second wiring and the 3rd wiring respectively, the source electrode of the 6th transistor connects transistor seconds and the second electrode of the 4th transistor, the source electrode of the 7th transistor connects third transistor and the second electrode of the 5th transistor, described 6th transistor and the 7th transistor and is stored in data bit by changing self threshold voltage.
2. NAND content addressable memory according to claim 1, it is characterised in that also include: precharge unit, is coupled to described matched line, in order to described matched line is precharged to predetermined voltage.
3. NAND content addressable memory according to claim 1, it is characterized in that: described 6th transistor and the 7th transistor two kinds of data bit of storage, the one of which in described 6th transistor and the 7th transistor has more less threshold voltage than another one.
4. NAND content addressable memory according to claim 1, it is characterized in that: described 6th transistor and the 7th transistor three kinds of data bit of storage, described data bit is " 0 ", " 1 " and " X ", when data bit is " 0 " or " 1 ", the one of which in described 6th transistor and the 7th transistor has more less threshold voltage than another one; When data bit is " X ", described 6th transistor and the 7th transistor have identical threshold voltage.
5. NAND content addressable memory according to claim 4, it is characterised in that: described identical threshold voltage is the threshold voltage behind described 6th transistor and the 7th transistor write data position " 1 ".
6. NAND content addressable memory according to claim 1, it is characterized in that: described 6th transistor and the 7th transistor are except control gate, source doping region, drain doping region, also include half floating boom, and the doping type of described half floating boom and source doping region, drain doping region are contrary;Described half floating boom contacts with drain doping region and forms an embedded type diode; Described control gate extends to above drain doping region and covers its surface, described half floating boom, drain doping region and extend to the control gate above drain doping region and form an embedded tunneling field-effect transistor.
7. NAND content addressable memory according to claim 1, it is characterized in that: described some kernel unit constitute a matrix, the corresponding matched line of every a line kernel unit in described matrix, every a line kernel unit is connected on a match line by the first transistor, the end of described matched line connects trombone slide, described lower trombone slide connects common ground end, and transistor seconds and the grid of third transistor in every string kernel unit share the search signal with a pair complementation.
8. NAND content addressable memory according to claim 1, it is characterized in that: also include refresh unit, described refresh unit coupled to described read-write cell and data storage cell, and read data by controlling described read-write cell, by controlling described data storage cell erasing data and re-writing data.
9. NAND content addressable memory according to claim 8, it is characterised in that described refresh unit includes: memory element, for storing the data read from described data storage cell;
Write operation element, for re-writing described data storage cell by the data of described reading.
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| US9916896B1 (en) * | 2016-11-01 | 2018-03-13 | Globalfoundries Inc. | Ternary content addressable memory (TCAM) for multi bit miss detect circuit |
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