CN103714853A - NAND content addressable memory - Google Patents
NAND content addressable memory Download PDFInfo
- Publication number
- CN103714853A CN103714853A CN201310724562.6A CN201310724562A CN103714853A CN 103714853 A CN103714853 A CN 103714853A CN 201310724562 A CN201310724562 A CN 201310724562A CN 103714853 A CN103714853 A CN 103714853A
- Authority
- CN
- China
- Prior art keywords
- transistor
- addressable memory
- content addressable
- data
- unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The invention provides an NAND content addressable memory. The NAND content addressable memory comprises a plurality of kernel units, wherein each kernel unit comprises a comparison unit, a reading-writing unit and a data storage unit; each data storage unit comprises two semi-floating-gate transistors, and the semi-floating-gate transistor is used for storing data bits by changing the self threshold value. By adopting the NAND content addressable memory, not only can the structural complexity of the content addressable memory unit based on SRAM in the prior art be simplified, but also the flexibility for switching the binary content addressable memory and a ternary content addressable memory can be realized.
Description
Technical field
The present invention relates to memory technology, particularly relate to NAND type Content Addressable Memory.
Background technology
The pith of the buffer memory in Content Addressable Memory (Content Addressable Memory, CAM) processor is also in router, to be used for judging the pith of Packet Generation direction.In common storer is applied as random access storage device (Random Access Memory, RAM), user provides a storage address, and storer returns to data that are stored in this address according to this address.And in the application of Content Addressable Memory, user provides data, Content Addressable Memory can travel through whole storage space, whether search for these data is present in storer, if so, hit, Content Addressable Memory returns to the address of one or more hiting datas.
Content Addressable Memory, as a kind of special memory, can be searched for whole storer in word computing, so in search application, Content Addressable Memory is fast more a lot of than normal memory.The fast search characteristic of Content Addressable Memory is specially adapted to as the network equipment, CPU(Center Processing Unit Content Addressable Memory, CPU (central processing unit)) and DSP(Digital Signal Processor, Cache(memory buffer digital signal processor)), the application such as hard encoding and decoding of video.
NAND type Content Addressable Memory is a kind of common Content Addressable Memory framework, the binary form Content Addressable Memory (the storage data that are Content Addressable Memory are " 0 " or " 1 ") of take is example, as shown in Figure 1, in the elementary cell of Content Addressable Memory, by the SRAM that comprises two cross-linked phase inverters, completed the storage of data, M1 is switching tube, be series on matched line, M2 is connected with M1 with M3, for external search signal is mated with storage inside data, the gate tube of doing SRAM to read and write for M4 and M5.Because the grid of M2 and M3 is controlled respectively by two complementary signals, so both always have and only have one in conducting state.SL_a and SL_b are the search signals of a pair of complementation, and M4 and M5 all connect word line and bit line, for controlling the conducting of M4 and M5 and reading of data.
As shown in Figure 2, a plurality of content addressable memory (CAM) cells form multiple line content addressable memory piece, and last content addressable memory (CAM) cell of each Content Addressable Memory piece is connected with lower trombone slide T1 again.Under original state, preliminary filling pipe T2 is charged to a certain level (being conventionally charged in advance supply voltage Vdd) in advance by each matched line, and preliminary filling pipe T2 disconnects afterwards, lower trombone slide T1 conducting.Search signal is input to each Content Addressable Memory piece and compares by parallel, if the content addressable memory (CAM) cell stored data of certain a line is mated completely with search signal, all conductings of the corresponding switching tube of each content addressable memory (CAM) cell of this row, combine lower trombone slide T1 matched line are pulled down to low level.If certain unit stored data is not mated with search signal in the Content Addressable Memory of certain a line, the switching tube that this content addressable memory (CAM) cell is corresponding disconnects, thereby makes the matched line of this row unsettled, keeps high level.In capable by comparison all the elements addressable memory, whether stored data mates with the search signal of input, finally from a plurality of Content Addressable Memory pieces, produces a matched signal, thereby completes content-based addressing operation.
If the data that the A dotted state of usining is stored as SRAM, the value that SL_a is search signal, supposes that search signal SL_a is for " 1 ", and its complementary signal SL_b is " 0 ", now M2 pipe conducting, and M3 pipe blocks.If SRAM storage data are " 1 ", match with search signal, the conducting of M1 pipe; If SRAM storage data are " 0 ", do not mate with search signal, M1 pipe blocks.If in like manner search signal SL_a is " 0 ", its complementary signal SL_b is " 1 ", and now M2 pipe blocks, and M3 manages conducting.If SRAM storage data are " 0 ", match with search signal, the conducting of M1 pipe; If SRAM storage data are " 1 ", do not mate with search signal, M1 pipe blocks.
Thus, if the storage data of certain row all the elements addressable memory (CAM) cell are all mated with search signal, the matched line of this row can be connected to ground by the gate tube in each content addressable memory (CAM) cell and a lower trombone slide T1, thereby is dragged down; If having the storage data of one or more content addressable memory (CAM) cells in certain row does not mate with search signal, the switching tube of corresponding contents addressable memory (CAM) cell disconnects, the matched line of this row is in vacant state, thereby keeps its original state, i.e. high level.
For ternary form Content Addressable Memory, need storage " X " (no matter search signal is " 0 " or " 1 ", can both the match is successful), correspondingly, need in Content Addressable Memory, adopt two independently sram cell make A, 2 of B are " 1 " simultaneously, as shown in Figure 3, thereby guarantee that no matter the grid of M1 is by M2 or M3, can be pulled to high level, thereby guarantee the normally open of M1, also need to configure corresponding coupling pipe and switching tube simultaneously, make a content addressable memory (CAM) cell need at least adopt 15 transistors, cause content addressable memory (CAM) cell complex structure, the problem that area occupied is larger.In addition, itself circuit structure of ternary form Content Addressable Memory and binary form Content Addressable Memory is different, the occasion that needs at the same time to realize ternary form Content Addressable Memory and binary form Content Addressable Memory function, both can not switch flexibly.
Summary of the invention
The shortcoming of prior art in view of the above, the object of the present invention is to provide a NAND type Content Addressable Memory, for solving the content addressable memory (CAM) cell complex structure of prior art based on SRAM, and the problem that can not switch flexibly of ternary form Content Addressable Memory and binary form Content Addressable Memory.
For achieving the above object and other relevant objects, the invention provides a NAND type Content Addressable Memory, described Content Addressable Memory comprises some kernel unit, described kernel unit comprises comparing unit, read-write cell and data storage cell, wherein: described comparing unit comprises the first transistor, transistor seconds and the 3rd transistor, described the first transistor is connected on matched line, described transistor seconds and the 3rd transistorized grid connect respectively the search signal of a pair of complementation, the grid coupling of the first electrode and described the first transistor; Described read-write cell comprises the 4th transistor and the 5th transistor, and described the 4th transistor and the 5th transistorized grid connect word line, and the first electrode connects respectively the first bit line and the second bit line; Described data storage cell comprises the 6th transistor and the 7th transistor, described the 6th transistor and the 7th transistorized control grid connect the first wiring, drain electrode connects respectively the second wiring and the 3rd wiring, the 6th transistorized source electrode connects transistor seconds and the 4th transistorized the second electrode, the 7th transistorized source electrode connects the 3rd transistor and the 5th transistorized the second electrode, and described the 6th transistor and the 7th transistor deposit data bit in by changing self threshold voltage.
Preferably, also comprise: precharge unit, is coupled to described matched line, in order to described matched line is precharged to predetermined voltage.
Preferably, also comprise: the first wiring and the second wiring, described the first wiring connects the 6th transistor and the 7th transistorized grid, and the second wiring connects the 6th transistor and the 7th transistorized drain electrode.
Preferably, described the 6th transistor and two kinds of data bit of the 7th transistor storage, the wherein one in described the 6th transistor and the 7th transistor has the threshold voltage lower than another one.
Preferably, three kinds of data bit of described the 6th transistor and the 7th transistor storage, the wherein one in described the 6th transistor and the 7th transistor have than the lower threshold voltage of another one or both, have identical compared with low threshold voltage.
Preferably, described data bit is " 0 ", " 1 " and " X ", and when data bit is " 0 " or " 1 ", the wherein one in described the 6th transistor and the 7th transistor has the threshold voltage lower than another one; When data bit is " X ", described the 6th transistor and the 7th transistor have identical compared with low threshold voltage.
Preferably, described identical compared with low threshold voltage, be that described the 6th transistor and the 7th transistor deposit the threshold voltage after data " 1 " in.
Preferably, described the 6th transistor and the 7th transistor, except controlling grid, source doping region, drain doping region, also comprise half floating boom, and the doping type of described half floating boom and source doping region, drain doping region are contrary; Described half floating boom contacts and forms an embedded type diode with drain doping region; Described control grid extends to drain doping region top and covers its surface, and described half floating boom, drain doping region and the control grid that extends to drain doping region top form an embedded tunneling field-effect transistor.
Preferably, described some kernel unit form a matrix, the corresponding matched line of every a line kernel unit in described matrix, every a line kernel unit is connected on matched line by the first transistor, the end of described matched line connects trombone slide, described lower trombone slide connects common ground end, and the transistor seconds in each row kernel unit and the 3rd transistorized grid are shared with a pair of complementary search signal.
Preferably, also comprise refresh unit, described refresh unit is coupled to described read-write cell and storage unit, and by controlling described read-write cell sense data, by controlling described cell erase data and data writing again.
Preferably, described refresh unit comprises:
Memory element, for storing the data of reading from described storage unit;
Write operation element, for again writing described storage unit by described data of reading.
As mentioned above, NAND type Content Addressable Memory of the present invention, has following beneficial effect:
First, the present invention has adopted the transistor with data storage function in NAND type Content Addressable Memory, the SRAM storage data of the phase inverter paired with traditional employing are compared, not only reduced the area of Content Addressable Memory, when needs are realized ternary form Content Addressable Memory, saved especially a large amount of areas.
Secondly, NAND type Content Addressable Memory of the present invention can be in the situation that not changing circuit structure, realize the flexible conversion between binary form and ternary form Content Addressable Memory, compare with traditional NAND type Content Addressable Memory based on SRAM, greatly improved the service efficiency of chip area.
Again, the present invention has adopted refresh unit in NAND type Content Addressable Memory, with the data in dynamic refresh storage unit, eliminated the electric leakage defect of novel storage unit of the present invention, thereby in matching process, can realize more exactly coupling, improve efficiency and the accuracy of Data Matching.
Accompanying drawing explanation
Fig. 1 is shown as the cellular construction schematic diagram of the NAND type binary content addressable memory based on SRAM in prior art.
Fig. 2 is shown as the structural representation of NAND type Content Addressable Memory array in prior art.
Fig. 3 is shown as the cellular construction schematic diagram of the NAND type ternary content addressable storer based on SRAM in prior art.
Fig. 4 is shown as the cellular construction schematic diagram of the NAND type Content Addressable Memory embodiment in the present invention.
Fig. 5 is shown as the structural representation of the storage unit in the NAND type Content Addressable Memory embodiment in the present invention.
Fig. 6 is shown as the capacitance profile schematic diagram of the storage unit in the NAND type Content Addressable Memory embodiment in the present invention.
Fig. 7 is shown as the structural representation of the NAND type Content Addressable Memory array in the present invention.
Fig. 8 is shown as the read-write operation sequential schematic diagram of the NAND type Content Addressable Memory in the present invention.
Element numbers explanation
M1 the first transistor
M2 transistor seconds
M3 the 3rd transistor
M4 the 4th transistor
M5 the 5th transistor
M6 the 6th transistor
M7 the 7th transistor
1 controls grid
2 half floating booms
3 source doping region
4 substrates
5 drain doping region
6 tunneling field-effect transistors
7 diffusion regions
8 diodes
9 heavily doped regions
SL_a search signal
The complementary search signal of SL_b SL_a
Line_n matched line
Row_select word line
G_n the first wiring
Datain_a the second wiring
Datain_b the 3rd wiring
Dataout_a the first bit line
Dataout_b the second bit line
CAM content addressable storage unit
Trombone slide under T1
T2 preliminary filling pipe
Adress address
Data data
The Read data reading stage
The Erase data erase stage
Write data write phase
Embodiment
Below, by specific instantiation explanation embodiments of the present invention, those skilled in the art can understand other advantages of the present invention and effect easily by the disclosed content of this instructions.The present invention can also be implemented or be applied by other different embodiment, and the every details in this instructions also can be based on different viewpoints and application, carries out various modifications or change not deviating under spirit of the present invention.
Be understandable that, when an element is called as " connecing " or " being coupled to " another element, it can be directly connect or be coupled to another element, can be also to have marginal element.And when an element is called as " directly connecting " or " coupling directly to " another element, there is not marginal element.
In existing NAND type binary content addressable memory and NAND type ternary content addressable memory cell, mostly need to adopt the SRAM of paired cross-linked phase inverter to complete the storage of data, add a plurality of supporting transistors, make content addressable memory (CAM) cell complex structure, area occupied larger, in addition, itself circuit structure of NAND type ternary content addressable storer and NAND type binary content addressable memory is different, can not switch flexibly.The present invention is based on above-mentioned consideration, design a kind of novel Content Addressable Memory, not only simplified the structure of memory cell, and in the situation that not changing memory unit, can realize binary content addressable memory, can realize ternary form Content Addressable Memory again, greatly improve the utilization factor of Content Addressable Memory.
Content Addressable Memory of the present invention comprises some kernel unit, described kernel unit comprises data storage cell, comparing unit and read-write cell, described data storage cell, comparing unit and read-write cell intercouple, and the transistor respectively with a pair of position symmetry, all transistor associatings have formed symmetrical structure jointly.Transistor in described data storage cell, comparing unit and read-write cell can be nmos pass transistor or PMOS transistor, and the annexation of each transistor source and drain electrode can be done proper transformation.The pair of transistor of described data storage cell can deposit complementary " 0 " and " 1 " in by changing self threshold voltage, also can deposit " 1 " in simultaneously, both binary content addressable memory can be used as, also ternary form Content Addressable Memory can be used as.
Below with reference to accompanying drawing, illustrate structure and the embodiment of Content Addressable Memory of the present invention.
Refer to the cellular construction schematic diagram of the Content Addressable Memory embodiment in Fig. 4 the present invention.
It should be noted that, the diagram providing in the present embodiment only illustrates basic conception of the present invention in a schematic way, satisfy and only show with assembly relevant in the present invention in graphic but not component count, shape and size drafting while implementing according to reality, during its actual enforcement, kenel, quantity and the ratio of each assembly can be a kind of random change, and its assembly layout kenel also may be more complicated.
Also it should be noted that, in the present embodiment, the transistor in described data storage cell, comparing unit and read-write cell is nmos pass transistor.
Content Addressable Memory comprises some kernel unit, and described kernel unit comprises comparing unit, read-write cell and data storage cell, wherein,
Described comparing unit comprises the first transistor M1, transistor seconds M2 and the 3rd transistor M3, described the first transistor M1 is connected on matched line Line_n, the grid of described transistor seconds M2 and the 3rd transistor M3 meets respectively search signal SL_a and the SL_b of a pair of complementation, the grid coupling of the first electrode and described the first transistor M1;
Described read-write cell comprises the 4th transistor M4 and the 5th transistor M5, and the grid of described the 4th transistor M4 and the 5th transistor M5 meets word line row_select, and the first electrode meets respectively the first bit line dataout_a and the second bit line dataout_b;
Described data storage cell comprises the 6th transistor M6 and the 7th transistor M7, the control grid of described the 6th transistor M6 and the 7th transistor M7 meets the first wiring G_n, drain electrode meets respectively the second wiring datain_a and the 3rd wiring datain_b, the source electrode of the 6th transistor M6 connects the second electrode of transistor seconds M2 and the 4th transistor M4, the source electrode of the 7th transistor M7 connects the second electrode of the 3rd transistor M3 and the 5th transistor M5, and described the 6th transistor M6 and the 7th transistor M7 deposit data bit in by changing self threshold voltage.
It should be noted that, the first transistor M1, transistor seconds M2, the 3rd transistor M3, the 4th transistor M4 and the 5th source electrode of transistor M5 and the annexation of drain electrode can be done proper transformation, and for example described the first electrode is drain electrode, and the second electrode is source electrode; Or the first electrode is source electrode, the second electrode is drain electrode.In embodiments of the present invention, described the first electrode is drain electrode, and the second electrode is source electrode.
Described the first wiring G_n provides grid voltage for the control grid to described the 6th transistor M6 and the 7th transistor M7, and the second wiring datain_a and the 3rd wiring datain_b are for depositing data bit in to described the 6th transistor M6 and the 7th transistor M7 respectively.
Fig. 5 is the structural representation of storage unit of the present invention the 6th transistor M6 and the 7th transistor M7.
It should be noted that, described the 6th transistor M6 and the 7th transistor M7 comprise and controlling outside grid 1, source doping region 3, drain doping region 5, also comprise half floating boom 2, and the doping type of described half floating boom 2 and source doping region 3, drain doping region 5 are contrary; Described half floating boom 2 contacts and forms an embedded type diode with drain doping region 5; Described control grid 1 extends to drain doping region 5 tops and covers its surface, and described half floating boom 2, drain doping region 5 and the control grid 1 that extends to drain doping region 5 tops form an embedded tunneling field-effect transistor.Take below common MOS transistor as comparison other illustrates described the 6th transistor M6 and the principle of adjustment and control of the 7th transistor M7 to transistor threshold voltage:
The electric conductivity of common MOS transistor raceway groove is subject to gate voltage regulation and control, and when grid voltage surpasses threshold voltage, the semiconductor surface under grid will transoid (N-shaped semiconductor variable is p-type semiconductor or contrary), generates conduction electric charge.Gate voltage is larger, and the conduction amount of charge of the accumulation in raceway groove is just more.
As shown in Figure 5, described the 6th transistor M6 and the 7th transistor M7 comprise control grid 1, half floating boom 2, source doping region 3, substrate 4, drain doping region 5.As better embodiment, the 6th transistor M6 and the 7th transistor M7 structure are placed in P type substrate 4 or P type well region, and its source doping region 3, drain doping region 5 are N-type doping, and its half floating boom 2 is the polysilicon structure of P type doping.It is to be noted, half floating boom 2 parts are positioned at raceway groove top and isolate with substrate 4, part contacts with drain doping region 5, and the region contacting with drain doping region 5 at half floating boom 2 forms a more shallow p type diffusion region 7, this p type diffusion region is positioned at the region that drain doping region 5 is surperficial near substrate 4 and contact with half floating boom 2, and half floating boom 2 of this P type doping and p type diffusion region 7 form a PN junction diode 8 with the doped region, building 5 of N-type doping.In addition, control the sidewall that grid 1 covers half floating boom 2 surfaces by gate oxide and is positioned at drain doping region 2 one sides, part extends to drain doping region 5 tops and covers its surface, and half floating boom 2/P type diffusion region 7 of this part and the doping of P type and the N-type heavily doped region 9 that drain doping region 5 is drawn drain electrode form an embedded tunneling field-effect transistor 6.It should be noted that, between part half floating boom 2 and substrate 4, control between grid 1 and half floating boom 2 and substrate 4 and be all arranged at intervals with gate oxide or other similar insulation systems, the conventional techniques that this is well known to those skilled in the art, therefore not to repeat here.
Fig. 6 is gate capacitance distribution schematic diagram in storage unit the 6th transistor M6 and the 7th transistor M7 in the present invention.
As shown in Figure 6, the 6th transistor M6 and the 7th transistor M7 can regard as and in the gate capacitance medium of normal transistor, inserted an electrode (i.e. half floating boom 2), so just original gate capacitance have been divided into two capacitor C
g1and C
g2series connection.By iunjected charge on half floating boom 2, can change the threshold voltage of the 6th transistor M6 and the 7th transistor M7, the electric conductivity of regulation and control raceway groove.The principle of its regulation and control threshold voltage can be understood as: the 6th transistor M6 and the 7th transistor M7 have initial threshold voltage V
th, when the 6th transistor M6 and the 7th transistor M7 start working, the electric charge injecting on half floating boom 2 can be by the gate capacitance C between half floating boom 2 and transistor channel
g2in transistor channel one side, induce channel charge, the positive charge on half floating boom 2 is more, and the negative charge of responding in raceway groove is also more, and the electric conductivity of N-type raceway groove is stronger.This effect equivalence is to controlling grid 1, compare before with half floating boom 2 chargings, 1 need of control grid add less gate voltage and just can in raceway groove, induce the channel charge of equivalent, reach identical conductive effect, the threshold voltage of the 6th transistor M6 and the 7th transistor M7 has just reduced so in form.When the 6th transistor M6 and the 7th transistor M7 are N-type transistor, writing of data " 1 " is by control grid 1 is placed in to low-voltage, drain electrode is placed in high voltage, makes embedded tunneling field-effect transistor 6 that band-to-band-tunneling occur, and electric charge flows to half floating boom 2 from drain region.Wiping of data is by control grid 1 is placed in to high voltage, and drain electrode is placed in low-voltage, makes tunneling field-effect transistor 6 positively biaseds, and the positive charge in half floating boom 2 flows back to drain region.Because the positive charge in half floating boom 2 can reduce the threshold voltage of N pipe, make the easier conducting of N pipe.So can set a grid voltage, if do not inject abundant positive charge in half floating boom 2, N manages not conducting, if half floating boom 2 injects abundant positive charge, N manages conducting, thereby realizes the storage of data.If data writing " 0 ", is set to low level by drain electrode datain_a and datain_b, thus the original state that half floating boom 2 is kept without positive charge.
It should be noted that, described the first transistor M1 is switching tube, grid connects the drain electrode of transistor seconds M2 and the 3rd transistor M3, source electrode and drain electrode matching connection line Line_n, the grid of transistor seconds M2 and the 3rd transistor M3 meets respectively search signal SL_a and the SL_b of a pair of complementation, the source electrode of transistor seconds M2 connects the source electrode of the 4th transistor M4 and the source electrode of the 6th transistor M6, and the source electrode of the 3rd transistor M3 connects the source electrode of the 5th transistor M5 and the source electrode of the 7th transistor M7.The drain electrode of the 4th transistor M4 and the 5th transistor M5 meets respectively the first bit line dataout_a and the second bit line dataout_b.
It should be noted that, described some kernel unit form a matrix, the corresponding matched line of every a line kernel unit in described matrix, every a line kernel unit is connected on matched line Line_n by the first transistor M1, the end of described matched line Line_n connects trombone slide T1, described lower trombone slide T1 connects common ground end, and the transistor seconds M2 in each row kernel unit and the grid of the 3rd transistor M3 are shared with a pair of complementary search signal SL_a and SL_b.
Preferably, described Content Addressable Memory also comprises refresh unit, and described refresh unit is coupled to described read-write cell and storage unit, and by controlling described read-write cell sense data, by controlling described cell erase data and data writing again.
Particularly, described refresh unit comprises: memory element, for storing the data of reading from described storage unit; Write operation element, for again writing described storage unit by described data of reading.
After the electric charge injecting in half floating boom 2 due to the tunneling field-effect pipe 6 of the 6th transistor M6 and the 7th transistor M7, have leaky, therefore, the present invention has also increased by a refresh unit in Content Addressable Memory, the data of storing for refreshing dynamically described content addressable memory (CAM) cell CAM.Its refresh operation is with behavior unit, by the 4th transistor M4 of the content addressable memory (CAM) cell CAM of every row and the 5th transistor M5 conducting, can read its storage inside data, the data of then this being read write the 6th transistor M6 and the 7th transistor M7 again.
Fig. 7 is the structural representation of the Content Addressable Memory array in the present invention.
Some kernel unit of described Content Addressable Memory form a matrix, the first transistor M1 of the kernel unit of every a line is connected on same matched line Line_n jointly, the output matching line of last kernel unit of every row kernel unit group connects the lower trombone slide T1 of a ground connection, the grid of all lower trombone slide T1 is received same control signal wire, described control signal wire is placed in unified level by all lower trombone slide T1 and makes lower trombone slide T1 conducting, the data of storing as certain row all the elements addressable memory (CAM) cell CAM are all when corresponding search signal matches, the matched line of this row can be connected to ground by the first transistor M1 in each content addressable memory (CAM) cell CAM and lower trombone slide T1, thereby level is dragged down.And when having data that one or more content addressable memory (CAM) cell CAM store and corresponding search signal not mating in certain row, the matched line of this row can because these not the first transistor M1 of matching unit disconnect and in vacant state, thereby keep its original state, i.e. high level.
In some kernel unit of same row, belong to the transistor seconds M2 of comparing unit and the grid of the 3rd transistor M3 connects respectively two complementary search signals, for example, the search signal connecing as transistor seconds M2 is during for " 1 ", and the search signal that the 3rd transistor M3 connects is " 0 ".Preferably, Content Addressable Memory also comprises precharge unit, is connected to described matched line, in order to described matched line is precharged to predetermined voltage.Described precharge unit comprises a preliminary filling pipe T2, every row content addressable memory (CAM) cell CAM meets a preliminary filling pipe T2, one end matching connection line of all preliminary filling pipe T2, grid is received on same preliminary filling signal wire, by controlling the conducting of preliminary filling signal controlling preliminary filling pipe T2, in order to matched line charging, make the original state of matched line in high level.
Embodiment 1
In this embodiment, described Content Addressable Memory is as NAND type binary content addressable memory, the 6th transistor M6 in described storage unit and the 7th transistor M7 storage two kinds of data bit " 0 " and " 1 ", wherein one in described the 6th transistor M6 and the 7th transistor M7 has the threshold voltage lower than another one, and the transistorized threshold voltage of data writing " 1 " is lower than the transistorized threshold voltage of data writing " 0 ".
As shown in Figure 7, SL_a and SL_b are the search signal of a pair of complementation, Line_n is matched line, row_select is word line, G_n is the first wiring, for the control grid of the 6th transistor M6 and the 7th transistor M7 provides control signal, datain_a is the second wiring, datain_b is the 3rd wiring, datain_a and datain_b provide data write signal for the drain electrode of the 6th transistor M6 and the 7th transistor M7, dataout_a is the first bit line, dataout_b is the second bit line, dataout_a and dataout_b connect respectively the drain electrode of the 4th transistor M4 and the 5th transistor M5.
It should be noted that, as shown in Figure 8, the data of storing in described content addressable memory (CAM) cell CAM write in the following manner: first wipe former data, the control grid G_n of the 6th transistor M6 and the 7th transistor M7 is set to high level, its drain electrode datain_a and datain_b are set to low level, tunneling field-effect pipe positively biased in the 6th transistor M6 and the 7th transistor M7, the electric charge in half floating boom 2 all flows to drain region.Then write new data, the control grid G_n of the 6th transistor M6 and the 7th transistor M7 is set to low level, according to the data that will write, drain electrode datain_a and datain_b are set to corresponding level, particularly, if data writing " 1 ", drain electrode datain_a and datain_b are set to high level, thereby make positive charge inject half floating boom 2 by drain region, if data writing " 0 ", drain electrode datain_a and datain_b are set to low level, thus the original state that half floating boom 2 is kept without positive charge.
Before mating, conducting preliminary filling pipe T2, and every matched line is all charged to a certain level (being conventionally charged in advance supply voltage Vdd) in advance, then disconnect preliminary filling pipe T2, all search signal SL_a and SL_b are set to high level, all word line row_select are set to high level, dataout_a and dataout_b are set to low level, the control grid G_n of the 6th transistor M6 and the 7th transistor M7 is set to compared with low level, now, the 4th transistor M4 and the 5th transistor M5 conducting, half floating boom 2 of the 6th transistor M6 and the 7th transistor M7 is in equilibrium state but not conducting, A point and B point are moved to low level in advance by the 4th transistor M4 and the 5th transistor M5 respectively, C point is by transistor seconds M2 and the 4th transistor M4, or moved in advance to low level by the 3rd transistor M3 and the 7th transistor M7, then trombone slide T1 under conducting, complete the work before coupling.
Start afterwards normally to mate work, the 4th transistor M4 and the 5th transistor M5 block, and datain_a and datain_b connect unified level, and G_n also connects unified level.In the present embodiment, the 6th transistor M6 and the 7th transistor M7 storage two kinds of data bit " 0 " and " 1 ", if unified, take and inject abundant positive charge in half floating boom 2 of the 6th transistor M6 and the 7th transistor M7 and represent that this transistor stored data is as " 1 ", if deposit abundant positive charge in, do not represent that this transistor stored data is 0.
Search signal SL_a and SL_b are compared by the parallel content addressable memory (CAM) cell group that is input to every row, and the number of the content addressable memory (CAM) cell CAM that each content addressable memory (CAM) cell group comprises depends on the bit wide of data.If search signal SL_a is " 1 ", its complementary signal SL_b is " 0 ", transistor seconds M2 conducting, the 3rd transistor M3 pipe blocks, now, if the 6th transistor M6 stored data is " 1 ", the 7th transistor M7 stored data is " 0 ", the 6th transistor M6 conducting, the 7th transistor M7 blocks, now search signal SL_a and SL_b and the 6th transistor M6 and the 7th transistor M7 stored data match, and the grid voltage of the first transistor M1 is drawn high to datain_a by the 6th transistor M6 and transistor seconds M2, thereby in conducting state.If all content addressable memory (CAM) cell CAM stored data of this row are all mated with search signal, the equal conducting of the first transistor M1 of changing one's profession all, lower trombone slide T1 is pulled down to low level by matched line.
If the 6th transistor M6 storage data are " 0 ", the 7th transistor M7 stored data is " 1 ", the 6th transistor M6 blocks, the 7th transistor M7 conducting, now search signal SL_a does not mate with the 6th transistor M6 stored data, and search signal SL_b does not mate with the 7th transistor M7 yet, the grid voltage of the first transistor M1 is unsettled, the first transistor M1 blocks, thereby makes the matched line of this row unsettled, keeps high level.
In like manner, if search signal SL_a is " 0 ", its complementary signal SL_b is " 1 ", transistor seconds M2 blocks, the 3rd transistor M3 pipe conducting, now, if the 6th transistor M6 stored data is " 0 ", the 7th transistor M7 stored data is " 1 ", the 6th transistor M6 blocks, the 7th transistor M7 conducting, and now search signal SL_a and SL_b and the 6th transistor M6 and the 7th transistor M7 stored data match, the grid voltage of the first transistor M1 is drawn high to datain_b by the 3rd transistor M3 and the 7th transistor M7, thereby in conducting state.If all content addressable memory (CAM) cell CAM stored data of this row are all mated with search signal, all equal conductings of the first transistor M1 of this row, lower trombone slide T1 is pulled down to low level by matched line.
If the 6th transistor M6 pipe storage data are " 1 ", the 7th transistor M7 stored data is " 0 ", the 6th transistor M6 conducting, the 7th transistor M7 blocks, and now search signal SL_a does not mate with the 6th transistor M6 stored data, and search signal SL_b does not mate with the 7th transistor M yet, the grid voltage of the first transistor M1 is unsettled, the first transistor M1 blocks, thereby makes the matched line of this row unsettled, keeps high level.
By comparing content addressable memory (CAM) cell CAM stored data in all row, whether mate with the search signal of input, finally from a plurality of row, produce a matched signal, thereby complete content-based addressing operation.
The above analysis, be similar to the NAND type Content Addressable Memory based on above-mentioned SRAM, the data of storing as certain row all the elements addressable memory (CAM) cell CAM are all when corresponding search signal matches, the matched line of this row can be connected to ground by the switching tube in each content addressable memory (CAM) cell CAM and a lower trombone slide T1, thereby is dragged down.And when having one or more storage data and corresponding search signal not mating in certain row all the elements addressable memory (CAM) cell CAM, the matched line of this row can because these not the switching tube of matching unit disconnect and in vacant state, thereby keep its original state, i.e. high level.In matching process, in half floating boom 2 due to the 6th transistor M6 and the 7th transistor M7, always there is one and only have one to be written into data " 1 ", the threshold voltage of the one of data writing is lower than the threshold voltage of the one of data writing " 0 ".
Embodiment 2
In this embodiment, described Content Addressable Memory is as NAND type ternary content addressable storer, the 6th transistor M6 in described storage unit and the 7th transistor M7 storage three kinds of data bit " 0 ", " 1 " and " X ", the wherein one in described the 6th transistor M6 and the 7th transistor M7 has than the lower threshold voltage of another one or both and has identical threshold voltage.
It should be noted that, X is commonly referred to " mask bit ", or is called " ignoring " state, no matter search signal is " 0 " or " 1 ", and can both the match is successful.When the data bit of storage is " 0 " or " 1 ", the wherein one in described the 6th transistor M6 and the 7th transistor M7 has the threshold voltage lower than another one; When the data bit of storage is " X ", described the 6th transistor M6 and the 7th transistor M7 have identical threshold voltage.Described identical threshold voltage is that described the 6th transistor M6 and the 7th transistor M7 deposit the threshold voltage after data bit " 1 " in.
When the data bit of storage is " 0 " or " 1 ", the matching process of described Content Addressable Memory is identical with embodiment 1, now, in half floating boom 2 due to the 6th transistor M6 and the 7th transistor M7, have one need be written into data, the threshold voltage of the one of data writing is lower than the threshold voltage of the one of data writing " 0 ".When the data bit of storage is " X ", the 6th transistor M6 and the 7th transistor M7 all write " 1 ", the 6th transistor M6 and the 7th transistor M7 are all the time in conducting state, described the 6th transistor M6 and the 7th transistor M7 have identical threshold voltage, and the threshold voltage during all lower than data writing " 0 ".
If search signal SL_a is " 1 ", its complementary signal SL_b is " 0 ", transistor seconds M2 conducting, the 3rd transistor M3 pipe blocks, now, search signal SL_a and the 6th transistor M6 match, and the grid voltage of the first transistor M1 is drawn high to datain_a by transistor seconds M2 and the 6th transistor M6, thereby in conducting state.
If search signal SL_a is 0, its complementary signal SL_b is " 1 ", transistor seconds M2 blocks, the 3rd transistor M3 pipe conducting, now, search signal SL_b and the 7th transistor M7 stored data match, and the grid voltage of the first transistor M1 is drawn high to datain_b by the 3rd transistor M3 and the 7th transistor M7, thereby in conducting state.
So no matter search signal SL_a is " 0 " still " 1 ", this content addressable memory (CAM) cell CAM can the match is successful, its corresponding switching tube the first transistor M1 can conducting, thereby realize the storage of similar X value, described Content Addressable Memory is converted to the ternary form of the present embodiment by the binary form of embodiment 1.
It should be noted that, after the electric charge injecting in half floating boom 2 due to the tunneling field-effect pipe of the 6th transistor M6 and the 7th transistor M7, have leaky, therefore, the present invention has also increased by a refresh unit in Content Addressable Memory, for reading dynamically the data that described content addressable memory (CAM) cell CAM stores, then the data of reading are write in content addressable memory (CAM) cell CAM.Described refresh unit is coupled to grid and the drain electrode of the 4th transistor M4 and the 5th transistor M5, and control grid and the drain electrode of the 6th transistor M6 and the 7th transistor M7.Preferably, described refresh unit comprises: memory element, for storing the data of reading from described storage unit; Write operation element, for again writing described storage unit by described data of reading.
In sum, NAND type Content Addressable Memory of the present invention, has following beneficial effect:
First, the present invention has adopted the transistor with data storage function in NAND type Content Addressable Memory, the SRAM storage data of the phase inverter paired with traditional employing are compared, not only reduced the area of Content Addressable Memory, when needs are realized ternary form Content Addressable Memory, saved especially a large amount of areas.
Secondly, NAND type Content Addressable Memory of the present invention can be in the situation that not changing circuit structure, realize the flexible conversion between binary form and ternary form Content Addressable Memory, compare with traditional NAND type Content Addressable Memory based on SRAM, greatly improved the service efficiency of chip area.
Again, the present invention has adopted refresh unit in NAND type Content Addressable Memory, with the data in dynamic refresh storage unit, eliminated the electric leakage defect of novel storage unit of the present invention, thereby in matching process, can realize more exactly coupling, improve efficiency and the accuracy of Data Matching.
So the present invention has effectively overcome various shortcoming of the prior art and tool high industrial utilization.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any person skilled in the art scholar all can, under spirit of the present invention and category, modify or change above-described embodiment.Therefore, such as in affiliated technical field, have and conventionally know that the knowledgeable, not departing from all equivalence modifications that complete under disclosed spirit and technological thought or changing, must be contained by claim of the present invention.
Claims (10)
1. a NAND type Content Addressable Memory, is characterized in that, described Content Addressable Memory comprises some kernel unit, and described kernel unit comprises comparing unit, read-write cell and data storage cell, wherein,
Described comparing unit comprises the first transistor, transistor seconds and the 3rd transistor, described the first transistor is connected on matched line, described transistor seconds and the 3rd transistorized grid connect respectively the search signal of a pair of complementation, the grid coupling of the first electrode and described the first transistor;
Described read-write cell comprises the 4th transistor and the 5th transistor, and described the 4th transistor and the 5th transistorized grid connect word line, and the first electrode connects respectively the first bit line and the second bit line;
Described data storage cell comprises the 6th transistor and the 7th transistor, described the 6th transistor and the 7th transistorized control grid connect the first wiring, drain electrode connects respectively the second wiring and the 3rd wiring, the 6th transistorized source electrode connects transistor seconds and the 4th transistorized the second electrode, the 7th transistorized source electrode connects the 3rd transistor and the 5th transistorized the second electrode, and described the 6th transistor and the 7th transistor deposit data bit in by changing self threshold voltage.
2. NAND type Content Addressable Memory according to claim 1, is characterized in that, also comprises: precharge unit, is coupled to described matched line, in order to described matched line is precharged to predetermined voltage.
3. NAND type Content Addressable Memory according to claim 1, it is characterized in that: described the 6th transistor and two kinds of data bit of the 7th transistor storage, the wherein one in described the 6th transistor and the 7th transistor has the threshold voltage lower than another one.
4. NAND type Content Addressable Memory according to claim 1, it is characterized in that: described the 6th transistor and three kinds of data bit of the 7th transistor storage, the wherein one in described the 6th transistor and the 7th transistor has than the lower threshold voltage of another one or both and has identical threshold voltage.
5. NAND type Content Addressable Memory according to claim 4, it is characterized in that: described data bit is " 0 ", " 1 " and " X ", when data bit is " 0 " or " 1 ", the wherein one in described the 6th transistor and the 7th transistor has the threshold voltage lower than another one; When data bit is " X ", described the 6th transistor and the 7th transistor have identical threshold voltage.
6. according to the NAND type Content Addressable Memory described in claim 4 or 5, it is characterized in that: described identical threshold voltage is the threshold voltage behind described the 6th transistor and the 7th transistor data writing position " 1 ".
7. NAND type Content Addressable Memory according to claim 1, it is characterized in that: described the 6th transistor and the 7th transistor are except controlling grid, source doping region, drain doping region, also comprise half floating boom, and the doping type of described half floating boom and source doping region, drain doping region are contrary; Described half floating boom contacts and forms an embedded type diode with drain doping region; Described control grid extends to drain doping region top and covers its surface, and described half floating boom, drain doping region and the control grid that extends to drain doping region top form an embedded tunneling field-effect transistor.
8. NAND type Content Addressable Memory according to claim 1, it is characterized in that: described some kernel unit form a matrix, the corresponding matched line of every a line kernel unit in described matrix, every a line kernel unit is connected on matched line by the first transistor, the end of described matched line connects trombone slide, described lower trombone slide connects common ground end, and the transistor seconds in each row kernel unit and the 3rd transistorized grid are shared with a pair of complementary search signal.
9. NAND type Content Addressable Memory according to claim 1, it is characterized in that: also comprise refresh unit, described refresh unit is coupled to described read-write cell and storage unit, and by controlling described read-write cell sense data, by controlling described cell erase data and data writing again.
10. NAND type Content Addressable Memory according to claim 9, is characterized in that, described refresh unit comprises:
Memory element, for storing the data of reading from described storage unit;
Write operation element, for again writing described storage unit by described data of reading.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310724562.6A CN103714853B (en) | 2013-12-24 | 2013-12-24 | NAND content addressable memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310724562.6A CN103714853B (en) | 2013-12-24 | 2013-12-24 | NAND content addressable memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103714853A true CN103714853A (en) | 2014-04-09 |
| CN103714853B CN103714853B (en) | 2016-06-15 |
Family
ID=50407746
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310724562.6A Active CN103714853B (en) | 2013-12-24 | 2013-12-24 | NAND content addressable memory |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103714853B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103943138A (en) * | 2014-04-18 | 2014-07-23 | 中国科学院上海高等研究院 | Per unit multi-bit storage device |
| CN108022622A (en) * | 2016-11-01 | 2018-05-11 | 格芯公司 | Ternary content addressable memories for more bit error detection circuits |
| CN111341365A (en) * | 2020-03-05 | 2020-06-26 | 北京大学 | Ternary content addressable memory and method of operating the same |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1014382A1 (en) * | 1998-12-22 | 2000-06-28 | STMicroelectronics, Inc. | Floating gate content addressable memory |
| US6195278B1 (en) * | 1999-12-30 | 2001-02-27 | Nortel Networks Limited | Content addressable memory cells and words |
| CN1357892A (en) * | 2000-12-06 | 2002-07-10 | 国际商业机器公司 | Memory unit containing implicit updated DRAM and with addressable contents |
| US6529395B1 (en) * | 2001-11-15 | 2003-03-04 | Broadcom Corporation | Content addressable memory cell techniques |
| CN1469392A (en) * | 2002-06-28 | 2004-01-21 | ���ǵ�����ʽ���� | Ternary content addressable memory |
| CN1643617A (en) * | 2002-03-18 | 2005-07-20 | 因芬尼昂技术股份公司 | Content addressable memory cell |
| CN101859596A (en) * | 2010-06-02 | 2010-10-13 | 中国科学院声学研究所 | Content addressable memory |
-
2013
- 2013-12-24 CN CN201310724562.6A patent/CN103714853B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1014382A1 (en) * | 1998-12-22 | 2000-06-28 | STMicroelectronics, Inc. | Floating gate content addressable memory |
| US6195278B1 (en) * | 1999-12-30 | 2001-02-27 | Nortel Networks Limited | Content addressable memory cells and words |
| CN1357892A (en) * | 2000-12-06 | 2002-07-10 | 国际商业机器公司 | Memory unit containing implicit updated DRAM and with addressable contents |
| US6529395B1 (en) * | 2001-11-15 | 2003-03-04 | Broadcom Corporation | Content addressable memory cell techniques |
| CN1643617A (en) * | 2002-03-18 | 2005-07-20 | 因芬尼昂技术股份公司 | Content addressable memory cell |
| CN1469392A (en) * | 2002-06-28 | 2004-01-21 | ���ǵ�����ʽ���� | Ternary content addressable memory |
| CN101859596A (en) * | 2010-06-02 | 2010-10-13 | 中国科学院声学研究所 | Content addressable memory |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103943138A (en) * | 2014-04-18 | 2014-07-23 | 中国科学院上海高等研究院 | Per unit multi-bit storage device |
| CN103943138B (en) * | 2014-04-18 | 2017-01-11 | 中国科学院上海高等研究院 | Per unit multi-bit storage device |
| CN108022622A (en) * | 2016-11-01 | 2018-05-11 | 格芯公司 | Ternary content addressable memories for more bit error detection circuits |
| CN108022622B (en) * | 2016-11-01 | 2021-07-27 | 马维尔亚洲私人有限公司 | Ternary content addressable memory for multi-bit error detection circuit |
| CN111341365A (en) * | 2020-03-05 | 2020-06-26 | 北京大学 | Ternary content addressable memory and method of operating the same |
| CN111341365B (en) * | 2020-03-05 | 2022-02-15 | 北京大学 | Ternary content addressable memory and method of operating the same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103714853B (en) | 2016-06-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101174455B (en) | Sram device with a low operation voltage | |
| KR101054322B1 (en) | Semiconductor memory circuit device, read control method | |
| US9082486B2 (en) | Row decoding circuit and memory | |
| CN101572122B (en) | Novel sram cell array structure | |
| CN103928050B (en) | Storage unit and storage equipment with storage unit | |
| CN204966056U (en) | Nonvolatile memory and integrated circuit on semiconductor chip | |
| TW200537488A (en) | 3 TID memory cells using gated diodes and methods of use thereof | |
| US10347340B2 (en) | Memory array and method for reading, programming and erasing the same | |
| CN105070315B (en) | SRAM memory cell, SRAM circuit and its reading/writing method | |
| CN101685667A (en) | Sram cell | |
| CN106448725A (en) | Read/write splitting memory cell based on FinFET (fin field-effect transistor) devices | |
| WO2013105460A1 (en) | Semiconductor memory circuit and device | |
| CN103456359A (en) | Improved differential framework Nor flash storage unit based on serially-connected transistor type | |
| CN101986389B (en) | Flash memory unit, flash memory device and programming method thereof | |
| CN103943138A (en) | Per unit multi-bit storage device | |
| CN103714853A (en) | NAND content addressable memory | |
| CN102544022A (en) | Hybrid non-volatile flash memory and memory system thereof | |
| CN107369466B (en) | A kind of three wordline storage units based on FinFET | |
| CN103646666A (en) | Not or (NOR)-type content addressable memory | |
| CN103094282B (en) | P type disposal programmable device structure | |
| CN104347110A (en) | Semiconductor storage device | |
| US9064555B2 (en) | Secondary bit line equalizer | |
| CN107393581A (en) | A kind of asymmetric memory cell of unit line based on FinFET | |
| CN104217753A (en) | Sram unit | |
| CN117337621A (en) | Memory and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |