WO2022233158A1

WO2022233158A1 - Memory cell, memory array, logic calculation memory and logic calculation method

Info

Publication number: WO2022233158A1
Application number: PCT/CN2022/072690
Authority: WO
Inventors: 崔小乐; 魏枫
Original assignee: 北京大学深圳研究生院
Priority date: 2022-01-19
Filing date: 2022-01-19
Publication date: 2022-11-10

Abstract

Disclosed in the present application are a memory cell, a memory array, a logic calculation memory and a logic calculation method. The memory cell comprises a memory circuit, a first write control circuit, a second write control circuit, a first read control circuit and a second read control circuit, wherein the first write control circuit and the second write control circuit are used for writing a first write data signal or a second write data signal into the memory circuit, the memory circuit is used for taking the first write data signal or the second write data signal as a memory data signal, and the first read control circuit and the second read control circuit are used for reading the memory data signal from the memory circuit. Since two groups of respectively independent read and write control circuits are comprised, a memory array can read or write data in rows, and can also read or write data in columns, and the transposition of stored data can be easily obtained when data, which is stored in rows or columns, is read in columns or rows.

Description

Memory unit, memory array, logic computing memory, and logic computing method

technical field

The present invention relates to the technical field of storage devices, in particular to a storage unit, a memory array, a logical computing memory and a logical computing method.

Background technique

The existing static random access memory (Static Random Access Memory, SRAM) is mainly based on a 6-tube structure or an 8-tube structure. Please refer to Figure 1, which is a schematic diagram of the memory cell circuit structure of the 6T SRAM. The 8T SRAM is composed of six transistors. Storage unit, each bit in the SRAM is stored in two cross-coupled inverters composed of four field effect transistors (M1, M2, M3 and M4). The other two field effect transistors (M5 and M6) are the control switches of the bit line (Bit Line) used by the memory cell for reading and writing. The basic storage unit of an SRAM has two stable states of 0 and 1. It is composed of two CMOS inverters. The input and output of these two inverters are cross-connected, that is, the output of the first inverter is connected. The input of the second inverter, the output of the second inverter is connected to the input of the first inverter. This realizes the locking and saving of the output states of the two inverters, that is, the state of one bit is stored. When accessing the SRAM, the word line (Word Line) is increased to a high level, so that the transistors M5 and M6 used for the two control switches of each basic unit are turned on, and the basic unit is connected to the bit line (Bit Line). The bit lines are used to read or write the saved state of the base cell. Although it is not necessary to have two inverted bit lines, such inverted bit lines help to improve noise margin. In addition to the six-tube SRAM, other SRAMs have 8-tube, 10-tube and even more transistor implementations per bit.

Please refer to Figure 2, Figure 3 and Figure 4, wherein Figure 2 is an 8T Schematic diagram of the memory cell circuit structure of SRAM, Figure 3 is based on 8T Schematic diagram of column-oriented logic operation of SRAM. Figure 4 shows the relationship between RBL discharge and operation results. When memory calculation is implemented based on SRAM, the two operands A and B involved in logic operation are stored in two SRAM cells Cell1 and Cell2 respectively. When the logic operation is to be performed, the read word line RWL corresponding to the SRAM cell that stores the operand is activated at the same time. According to the stored value, the read bit line RBL precharged to a high level will maintain the original high level ( When A=B=0) or discharged to a low level (when at least one of A and B is 1), the result of the last operation is read out by the sense amplifier SA at the end of the RBL. What they implement are logical operations or CAM search operations based on the column direction, and the operation operands or search data must be stored in the same column.

Therefore, in traditional SRAM, data is generally read/written/stored in the row direction, and the logical operation in the column direction can realize the bitwise operation of data in different rows, however, the CAM in the column direction requires data to be written in the column direction. input/storage, so existing based on 6T The logic operation function implemented in the memory computing circuit of SRAM and 8T SRAM is not compatible with the CAM search function, and the circuit flexibility is poor.

technical problem

The present application mainly provides a storage unit, which is used to solve the technical problem of how to realize the poor flexibility of logic calculation of memory data based on SRAM.

technical solutions

According to a first aspect, an embodiment provides a memory cell including a memory circuit, a first write control circuit, a second write control circuit, a first read control circuit, a second read control circuit, and a node Q and node QB;

The first write control circuit includes a VBL connection end, a VBLB connection end, a HWWL connection end, a first storage connection end and a second storage connection end; the HWWL connection end is used to input a write control signal HWWL, the VBL The connection terminal and the VBLB connection terminal are used for inputting the first write data signal, the first storage connection terminal is connected to the node Q, and the second storage connection terminal is connected to the node QB; the first storage connection terminal is connected to the node QB; The write control circuit is configured to output the electrical signals input to the VBL connection end and the VBLB connection end to the node Q and the node QB respectively when the write control signal HWWL is input to the HWWL connection end;

The second write control circuit includes an HBL connection end, an HBLB connection end, a VWWL connection end, a third storage connection end and a fourth storage connection end; the VWWL connection end is used for inputting the write control signal VWWL, the HBL connection end The connection terminal and the HBLB connection terminal are used for inputting a second write data signal, the third storage connection terminal is connected to the node Q, and the fourth storage connection terminal is connected to the node QB; the second storage connection terminal is connected to the node QB. The write control circuit is configured to output the electrical signal input to the HBL connection end and the HBLB connection end to the node Q and the node QB respectively when the write control signal VWWL is input to the VWWL connection end;

The storage circuit is connected to the node Q and the node QB; the storage circuit is used to hold the first write data signal or the second write data signal input from the node Q or the node QB, and to The first write data signal or the second write data signal is used as the storage data signal of the storage unit;

The first read control circuit is connected to the node Q for reading the memory cell; the first read control circuit includes a VRWL connection end and an HRBL connection end; the VRWL connection end is used for read control The input of the signal VRWL, when the VRWL connection terminal inputs the read control signal VRWL, the HRBL connection terminal is used to output the stored data signal;

The second read control circuit is connected to the node Q for reading the memory cell; the first read control circuit includes a HRWL connection end and a VRBL connection end; the HRWL connection end is used for read control The input of the signal HRWL, when the HRWL connection end inputs the read control signal HRWL, the VRBL connection end is used for outputting the stored data signal.

According to a second aspect, an embodiment provides a memory array including N rows and M columns of the memory cells described in the first aspect; wherein N and M are both natural numbers.

According to a third aspect, an embodiment provides a logical computing memory, comprising the memory array of the second aspect;

The logical calculation memory further includes a horizontal read word line, a vertical read word line, a horizontal read bit line, a vertical read bit line, a first write control line and a second write control line;

The horizontal read word line is connected to the HRWL connection end of each of the memory cells of the memory array, and the vertical read bit line is connected to the VRBL connection end of each of the memory cells of the memory array, using reading the stored data signal through the second read control circuit;

The vertical read word line is connected to the VRWL connection end of each of the memory cells of the memory array, and the horizontal read bit line is connected to the HRBL connection end of each of the memory cells of the memory array, using reading the stored data signal through the first read control circuit;

The first write control line is connected to the HWWL connection terminal of the first write control circuit of each of the memory cells of the memory array, and is used for connecting the first write control circuit in the row direction of the memory array. writing data signals into the storage unit;

The second write control line is connected to the VWWL connection terminal of the second write control circuit of each of the memory cells of the memory array, and is used for connecting the second write control circuit in the column direction of the memory array. Write data signals are input to the memory cells.

According to a third aspect, an embodiment provides a logical computing method based on the logical computing memory described in the third aspect, the logical computing method comprising:

the horizontal read bit line reads the stored data signal through the first read control circuit;

the vertical read bit line reads the stored data signal through the second read control circuit;

Logic calculation is performed on the stored data signal output by the horizontal read bit line or the vertical read bit line to obtain and output a result of the logic calculation.

beneficial effect

The memory cell according to the above embodiment includes a memory circuit, a first write control circuit, a second write control circuit, a first read control circuit and a second read control circuit; the first write control circuit and the second write control circuit The input control circuit is used to write the first write data signal or the second write data signal into the storage circuit, the storage circuit is used to use the first write data signal or the second write data signal as the stored data signal, the first read The fetch control circuit and the second read control circuit are used for reading the stored data signal from the storage circuit. Since it includes two sets of independent read and write control circuits, the memory array can read or write data in rows or columns, and when the data stored in rows or columns , the transposition of the stored data can be easily obtained when the column-direction or column-row readout is performed.

Description of drawings

Figure 1 is 6T Schematic diagram of the memory cell circuit structure of SRAM;

Figure 2 is 8T Schematic diagram of the memory cell circuit structure of SRAM;

Figure 3 is based on the 8T Schematic diagram of column-oriented logic operation of SRAM;

Fig. 4 is the relation table of RBL discharge condition and operation result;

5 is a schematic circuit diagram of a memory cell in an embodiment;

FIG. 6 is a schematic diagram of column-direction logic computation implemented by a logic computation memory in an embodiment;

7 is a schematic diagram of a logic calculation memory implementing row-direction logic calculation in an embodiment;

Fig. 8 is a row or column logical operation result relation table in an embodiment;

9 is a schematic diagram of a column-wise CAM search operation in an embodiment;

FIG. 10 is a correspondence table of matching results between column-direction storage data and search data in an embodiment;

11 is a schematic diagram of a row-wise CAM search operation in an embodiment;

FIG. 12 is a correspondence table of matching results between row-direction stored data and search data in an embodiment.

Embodiments of the present invention

The present invention will be further described in detail below through specific embodiments in conjunction with the accompanying drawings. Wherein similar elements in different embodiments have used associated similar element numbers. In the following embodiments, many details are described so that the present application can be better understood. However, those skilled in the art will readily recognize that some of the features may be omitted under different circumstances, or may be replaced by other elements, materials, and methods. In some cases, some operations related to the present application are not shown or described in the specification, in order to avoid the core part of the present application from being overwhelmed by excessive description, and for those skilled in the art, these are described in detail. The relevant operations are not necessary, and they can fully understand the relevant operations according to the descriptions in the specification and general technical knowledge in the field.

Additionally, the features, acts, or characteristics described in the specification may be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can also be exchanged or adjusted in order in a manner obvious to those skilled in the art. Therefore, the various sequences in the specification and drawings are only for the purpose of clearly describing a certain embodiment and are not meant to be a necessary order unless otherwise stated, a certain order must be followed.

The serial numbers themselves, such as "first", "second", etc., for the components herein are only used to distinguish the described objects, and do not have any order or technical meaning. The "connection" and "connection" mentioned in this application, unless otherwise specified, include both direct and indirect connections (connections).

Existing SRAM structure (6T SRAM and 8T SRAM, etc.) can only store and read/write data in the row direction, and the memory computing circuit designed by it can realize the logical operation or CAM search operation based on the column direction. The data read/written is not compatible with the column-direction based CAM search operation it implements. The 12T SRAM circuit structure proposed by the present invention can not only store and read/write data in the row direction, but also store and read/write data in the column direction. At the same time, the designed memory computing circuit can realize Bidirectional logical operation or CAM search operation based on column direction/row direction, data stored/read/written based on row direction matches with CAM search operation based on row direction, data stored/read/written based on column direction Matches column-direction based CAM search operations. In addition, the data stored in the row direction is read out in the column direction, and the transposition readout of the stored data can be easily performed.

Some terms involved in this application are first described below.

The transistors in this application may be transistors of any structure, such as bipolar transistors (BJTs) or field effect transistors (FETs). When the transistor is a bipolar transistor, its control electrode refers to the gate of the bipolar transistor, the first electrode can be the collector or emitter of the bipolar transistor, and the corresponding second electrode can be the bipolar transistor. Emitter or collector, in the actual application process, "emitter" and "collector" can be interchanged according to the signal flow; when the transistor is a field effect transistor, its control electrode refers to the gate of the field effect transistor, the first One electrode can be the drain or source of the field effect transistor, and the corresponding second electrode can be the source or drain of the field effect transistor. In practical application, the "source" and "drain" can be based on the signal flow direction And exchange. It should be noted that, for the convenience of description and for those skilled in the art to understand the technical solutions of the present application more clearly, node Q and node QB are introduced into this application document to identify the relevant parts of the circuit structure, which cannot be regarded as extra in the circuit. incoming terminals. For the convenience of description, the potential is represented by V _DD , the ground terminal of the unit is GND, and the actual ground terminal is represented by GND.

In the embodiment of the present application, the memory unit includes two independent sets of read and write control circuits, so that the memory array can read or write data in rows, or read or write data in columns, and when When reading data stored in rows or columns column-wise or column-row-wise, it is easy to get the transpose of the stored data

Example 1:

Please refer to FIG. 5 , which is a schematic circuit diagram of a storage unit in an embodiment. The storage unit includes a storage circuit 1 , a first writing control circuit 2 , a second writing control circuit 3 , a first reading control circuit 4 , and a second writing control circuit 4 . Read control circuit 5, node Q and node QB. The first write control circuit 2 includes a VBL connection terminal, a VBLB connection terminal, a HWWL connection terminal, a first storage connection terminal and a second storage connection terminal. The HWWL connection terminal is used to input the write control signal HWWL, the VBL connection terminal and the VBLB connection terminal are used to input the first write data signal, the first storage connection terminal is connected to the node Q, and the second storage connection terminal is connected to the node QB. The first write control circuit 2 is configured to output the electrical signals input to the VBL connection end and the VBLB connection end to the node Q and the node QB respectively when the write control signal HWWL is input to the HWWL connection end. The second write control circuit 3 includes an HBL connection terminal, an HBLB connection terminal, a VWWL connection terminal, a third storage connection terminal and a fourth storage connection terminal. The VWWL connection terminal is used to input the write control signal VWWL, the HBL connection terminal and the HBLB connection terminal are used to input the second write data signal, the third storage connection terminal is connected to the node Q, and the fourth storage connection terminal is connected to the node QB. The second write control circuit 3 is configured to output the electrical signals input to the HBL connection end and the HBLB connection end to the node Q and the node QB respectively when the write control signal VWWL is input to the VWWL connection end. The storage circuit 1 is connected to the node Q and the node QB. The memory circuit 1 is used to hold the first write data signal or the second write data signal input from the node Q or the node QB, and use the first write data signal or the second write data signal as the storage data signal of the memory unit. The first read control circuit 4 is connected to the node Q for reading the memory cells. The first read control circuit 4 includes a VRWL connection end and an HRBL connection end. The VRWL connection end is used to read the input of the control signal VRWL. When the VRWL connection end inputs the read control signal VRWL, the HRBL connection end is used to output the stored data signal. . The second read control circuit 5 is connected to the node Q for reading the memory cells. The first read control circuit 5 includes a HRWL connection end and a VRBL connection end. The HRWL connection end is used for the input of the read control signal HRWL. When the HRWL connection end inputs the read control signal HRWL, the VRBL connection end is used to output the stored data signal. .

In one embodiment, the storage circuit 1 includes a latch, and the latch includes a transistor P10 , a transistor P11 , a transistor N10 and a transistor N11 , wherein each transistor includes a first electrode, a second stage and a control electrode. The control electrode of the transistor P10 is connected to the node QB, the first electrode of the transistor P10 is used for inputting the working voltage signal V _DD , and the second electrode of the transistor P10 is connected to the node Q. The control electrode of the transistor P11 is connected to the node Q, the first electrode of the transistor P11 is used for inputting the working voltage signal V _DD , and the second electrode of the transistor P11 is connected to the node QB. The control electrode of the transistor N10 is connected to the node QB, the first electrode of the transistor N10 is connected to the node Q, and the second electrode of the transistor N10 is grounded. The control electrode of the transistor N11 is connected to the node Q, the first electrode of the transistor N11 is connected to the node QB, and the second electrode of the transistor N11 is grounded.

In one embodiment, the first write control circuit 2 includes a transistor N12 and a transistor N13, wherein each transistor includes a first electrode, a second stage and a control electrode. The control electrode of the transistor N12 is connected to the HWWL connection end, the first electrode of the transistor N12 is connected to the VBLB connection end, and the second electrode of the transistor N12 is connected to the second storage connection end. The control electrode of the transistor N13 is connected to the HWWL connection end, the first electrode of the transistor N13 is connected to the VBL connection end, and the second electrode of the transistor N13 is connected to the first storage connection end.

In one embodiment, the second writing control circuit includes a transistor N14 and a transistor N15, wherein each transistor includes a first electrode, a second stage and a control electrode. The control pole of the transistor N14 is connected to the VWWL connection terminal, the first pole of the transistor N14 is connected to the HBLB connection terminal, and the second pole of the transistor N14 is connected to the fourth storage connection terminal. The control electrode of the transistor N15 is connected to the VWWL connection end, the first electrode of the transistor N15 is connected to the HBL connection end, and the second electrode of the transistor N15 is connected to the third storage connection end.

In one embodiment, the first read control circuit includes a transistor N16 and a transistor N17, wherein each transistor includes a first electrode, a second stage and a control electrode. The control terminal of the transistor N17 is connected to the VRWL connection terminal, the first terminal of the transistor N17 is connected to the HRBL connection terminal, and the second terminal of the transistor N17 is connected to the first terminal of the transistor N16. The control electrode of the transistor N16 is connected to the node Q, and the second electrode of the transistor N16 is grounded.

In one embodiment, the second read control circuit includes a transistor N18 and a transistor N19, wherein each transistor includes a first electrode, a second stage and a control electrode. The control terminal of the transistor N19 is connected to the HRWL connection terminal, the first terminal of the transistor N19 is connected to the VRBL connection terminal, and the second terminal of the transistor N19 is connected to the first terminal of the transistor N18. The control electrode of the transistor N18 is connected to the node QB, and the second electrode of the transistor N18 is grounded.

In an embodiment of the present application, a memory array is also disclosed, including N rows and M columns of the above-mentioned memory cells. Among them, N and M are both natural numbers.

In an embodiment of the present application, a logic computing memory is also disclosed, including the memory array as described above. The logic computation memory further includes a horizontal read word line, a vertical read word line, a horizontal read bit line, a vertical read bit line, a first write control line and a second write control line. The horizontal read word line is connected to the HRWL connection end of each memory cell of the memory array, and the horizontal read bit line is connected to the VRBL connection end of each memory cell of the memory array, for reading the memory through the second read control circuit data signal. The vertical read word line is connected to the VRWL connection end of each memory cell of the memory array, and the vertical read bit line is connected to the HRBL connection end of each memory cell of the memory array for reading through the first read control circuit Take the stored data signal. The first write control line is connected to the HWWL connection terminal of the first write control circuit of each memory cell of the memory array, and is used for inputting the first write data signal into the memory cell in the row direction of the memory array. The second write control line is connected to the VWWL connection terminal of the second write control circuit of each memory cell of the memory array, and is used for inputting the second write data signal into the memory cells in the column direction of the memory array.

In one embodiment, the logic calculation memory further includes a logic operation circuit, the logic operation circuit is connected to the horizontal read bit line and the vertical read bit line, and is used for performing the operation on the stored data signal output by the horizontal read bit line or the vertical read bit line. Logical calculation, and output the logical calculation result obtained by the logical calculation.

In an embodiment of the present application, a logical calculation method is also disclosed. Based on the above-mentioned logical calculation memory, the logical calculation method includes:

First, the horizontal read bit line reads the stored data signal through the first read control circuit, or the vertical read bit line reads the stored data signal through the second read control circuit; then the horizontal read bit line or the vertical read bit line is read. The output stored data signal is used for logic calculation to obtain and output the result of the logic calculation.

Please refer to FIG. 6 , which is a schematic diagram of column-direction logic computation implemented by a logic computation memory in an embodiment. The logic computation circuit SA reads the VRBL connection terminals of two memory cells connected by a vertical read bit line, and reads the memory of the two memory cells. data signal, and perform logical operations on the two stored data signals.

Please refer to FIG. 7 , which is a schematic diagram of a logic calculation memory implementing row-direction logic calculation in an embodiment. The logic calculation circuit SA reads the stored data of the two memory cells through the HRBL connection terminals of the two memory cells connected by the horizontal read bit line. signal, and perform logical operations on the two stored data signals.

Please refer to FIG. 8 , which is a logical operation result relation table by row or column in an embodiment. The logical operation result relation table is used to represent two stored data signals (Q1 is the first bit line) obtained by the horizontal read bit line or the vertical read bit line. The storage data signal stored in one storage unit and the storage data signal stored in the second storage unit of Q2) perform logical calculation (OR and/or NOR) to obtain a corresponding table of results.

The SRAM structure proposed in the embodiments of the present application can implement reading/writing of data in a row direction or a column direction.

1. The read operation includes:

1. When the data is to be read in the row direction, activate the horizontal read word line HRWL of the row to be read, and the data will be read from the SA at the end of the vertical read bit line VRBL precharged to a high level.

2. When data is to be read in the column direction, the vertical read word line VRWL of the column to be read is activated, and the data will be read from the SA at the end of the horizontal read bit line HRBL precharged to a high level.

2. The write operation includes:

1. When the data is to be written into the storage array by row, the data to be written is preloaded on the vertical bit lines VBLs and VBLBs, the horizontal write word line HWWL corresponding to the row to be written is activated, and the data will be written to the row by row. SRAM.

2. When data is to be written into the storage array in columns, the data to be written is preloaded on the horizontal bit lines HBLs and HBLBs, the vertical write word line VWWL corresponding to the row to be written is activated, and the data will be written in columns to SRAM.

3. Carry out logical operations (OR/NOR) including:

1. When the row-direction logic operation is to be performed, activate the vertical read word line VRWLs corresponding to the SRAM cell that stores the operand, and the OR/NOR logic operation result will be read from the SA at the end of the pre-charged high-level horizontal read bit line HRBL. read out.

2. When the column-oriented logic operation is to be performed, activate the horizontal read word line HRWLs corresponding to the SRAM cell that stores the operand, and the OR/NOR logic operation result will be pre-charged to a high level from the SA at the end of the vertical read bit line VRBL. read out.

An embodiment of the present application also discloses a CAM search operation method, based on the above-mentioned memory array, please refer to FIG. 9 and FIG. 10 , FIG. 9 is a schematic diagram of a column-wise CAM search operation in an embodiment, and FIG. 10 A corresponding table of matching results between the stored data and the search data in the column direction, wherein the memory array is taken as an example of memory cells with 3 rows and 3 columns. When the memory array is configured for row-to-CAM search operation, the vertical write word lines and vertical read word lines VWWL/VRWL are configured as search lines SL/SLB (that is, when the data to be searched is 1, a high level is loaded on VWWL/VRWL/ Low level (1/0)), the horizontal bit line and the horizontal read bit line HBL/HRBL are configured as matching lines ML/ML′, when the data stored in a row matches the searched data direction, the result 1 is output, otherwise it is output Result 0.

Please refer to FIGS. 11 and 12. FIG. 11 is a schematic diagram of a row-wise CAM search operation in an embodiment. Take the storage unit as an example. When the memory array is configured in the column-oriented CAM search mode, the horizontal write word lines and horizontal read word lines HWWL/HRWL are configured as search lines SL/SLB (that is, when the data to be searched is 1, the HWWL/HRWL is loaded with high level/low power Flat (1/0)), the vertical bit line and the vertical read bit line VBL/VRBL are configured as matching lines ML/ML′, when the data stored in a certain column matches the searched data direction, the output result is 1, otherwise it is output Result 0.

In the memory array disclosed in the embodiments of the present application, when the data stored in rows is read out in the column direction, the transposition of the stored data can be easily obtained. Similarly, the row-wise readout of the data stored in columns can also obtain the transposition of the stored data.

The memory cells disclosed in the embodiments of the present application are 12T SRAM cells, and the composed memory array can read/write/store data in the row/column direction (traditional SRAM memory arrays can only read/write/store data in the row direction). write/store data), and the present invention also proposes a method for using the 12T SRAM circuit structure to implement bidirectional logic operations in row/column directions and CAM search operations (traditional SRAM-based memory computing circuits can only implement logic in column directions) operations and CAM search operations, and their stored data based on the row direction is not compatible with the CAM search operation based on the column direction). The 12T SRAM cell structure has row access ports (horizontal write word line HWWL, vertical bit line VBL/VBLB, transistors N12 and N13 for writing, horizontal read word line HRWL, vertical read bit line VRBL, transistors N18 and N19 for read/compute) and column access ports (vertical write word line VWWL, horizontal bit line HBL/HBLB, transistors N14 and N15 for writing, vertical read word line VRWL, horizontal read bit line HRBL, transistor N16 and N17 is used for reading/computing), the 12T SRAM can be read/written/stored in row direction/column direction, and a method of using this circuit structure to realize bidirectional logic operation in row/column direction and CAM search operation is proposed .

The present application discloses a storage unit, comprising a storage circuit, a first write control circuit, a second write control circuit, a first read control circuit and a second read control circuit; the first write control circuit and the second write control circuit The write control circuit is used to write the first write data signal or the second write data signal into the storage circuit, and the storage circuit is used to use the first write data signal or the second write data signal as the stored data signal, the first The read control circuit and the second read control circuit are used for reading the stored data signal from the storage circuit. Since it includes two sets of independent read and write control circuits, the memory array can read or write data in rows or columns, and when the data stored in rows or columns When performing column-wise or column-row-wise readout, the transpose of the stored data can be easily obtained.

Descriptions are made herein with reference to various exemplary embodiments. However, those skilled in the art will recognize that changes and modifications may be made to the exemplary embodiments without departing from the scope of this document. For example, the various operational steps, and the components used to perform the operational steps, may be implemented in different ways depending on the particular application or considering any number of cost functions associated with the operation of the system (eg one or more steps may be deleted, modified or incorporated into other steps).

Although the principles herein have been shown in various embodiments, many modifications may be made in structure, arrangement, proportions, elements, materials and components as are particularly suited to particular environmental and operating requirements without departing from the principles and scope of the present disclosure use. The above modifications and other changes or corrections are intended to be included within the scope of this document.

The foregoing Detailed Description has been described with reference to various embodiments. However, those skilled in the art will recognize that various modifications and changes can be made without departing from the scope of the present disclosure. Accordingly, this disclosure is to be considered in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within its scope. Likewise, the advantages, other advantages, and solutions to problems of the various embodiments have been described above. However, the benefits, advantages, solutions to the problems, and any elements that give rise to them, or make them more explicit, should not be construed as critical, necessary, or essential. As used herein, the term "comprising" and any other variations thereof are non-exclusive inclusion, such that a process, method, article or device including a list of elements includes not only those elements, but also not expressly listed or included in the process , method, system, article or other elements of a device. Furthermore, as used herein, the term "coupled" and any other variations thereof refer to physical connections, electrical connections, magnetic connections, optical connections, communication connections, functional connections, and/or any other connection.

Those skilled in the art will recognize that many changes may be made to the details of the above-described embodiments without departing from the underlying principles of the invention. Accordingly, the scope of the invention should be determined in accordance with the following claims.

Claims

A storage unit, characterized in that it comprises a storage circuit, a first write control circuit, a second write control circuit, a first read control circuit, a second read control circuit, a node Q and a node QB;

The first write control circuit includes a VBL connection end, a VBLB connection end, a HWWL connection end, a first storage connection end and a second storage connection end; the HWWL connection end is used to input a write control signal HWWL, the VBL The connection terminal and the VBLB connection terminal are used for inputting the first write data signal, the first storage connection terminal is connected to the node Q, and the second storage connection terminal is connected to the node QB; the first storage connection terminal is connected to the node QB; The write control circuit is configured to output the electrical signals input to the VBL connection end and the VBLB connection end to the node Q and the node QB respectively when the write control signal HWWL is input to the HWWL connection end;

The second write control circuit includes an HBL connection end, an HBLB connection end, a VWWL connection end, a third storage connection end and a fourth storage connection end; the VWWL connection end is used for inputting the write control signal VWWL, the HBL connection end The connection terminal and the HBLB connection terminal are used for inputting a second write data signal, the third storage connection terminal is connected to the node Q, and the fourth storage connection terminal is connected to the node QB; the second storage connection terminal is connected to the node QB. The write control circuit is configured to output the electrical signal input to the HBL connection end and the HBLB connection end to the node Q and the node QB respectively when the write control signal VWWL is input to the VWWL connection end;

The storage circuit is connected to the node Q and the node QB; the storage circuit is used to hold the first write data signal or the second write data signal input from the node Q or the node QB, and to The first write data signal or the second write data signal is used as the storage data signal of the storage unit;

The first read control circuit is connected to the node Q for reading the memory cell; the first read control circuit includes a VRWL connection end and an HRBL connection end; the VRWL connection end is used for read control The input of the signal VRWL, when the VRWL connection terminal inputs the read control signal VRWL, the HRBL connection terminal is used to output the stored data signal;

The second read control circuit is connected to the node Q for reading the memory cell; the first read control circuit includes a HRWL connection end and a VRBL connection end; the HRWL connection end is used for read control The input of the signal HRWL, when the HRWL connection end inputs the read control signal HRWL, the VRBL connection end is used for outputting the stored data signal.
The storage unit according to claim 1, wherein the storage circuit comprises a latch, and the latch comprises a transistor P10, a transistor P11, a transistor N10 and a transistor N11; wherein each transistor comprises a first pole , the second stage and the control pole;

The control pole of the transistor P10 is connected to the node QB, the first pole of the transistor P10 is used for the input of the working voltage signal V DD , and the second pole of the transistor P10 is connected to the node Q;

The control pole of the transistor P11 is connected to the node Q, the first pole of the transistor P11 is used for the input of the working voltage signal V DD , and the second pole of the transistor P11 is connected to the node QB;

The control pole of the transistor N10 is connected to the node QB, the first pole of the transistor N10 is connected to the node Q, and the second pole of the transistor N10 is grounded;

The control electrode of the transistor N11 is connected to the node Q, the first electrode of the transistor N11 is connected to the node QB, and the second electrode of the transistor N11 is grounded.
The memory cell according to claim 2, wherein the first write control circuit comprises a transistor N12 and a transistor N13; wherein each transistor comprises a first pole, a second level and a control pole;

The control pole of the transistor N12 is connected to the HWWL connection terminal, the first pole of the transistor N12 is connected to the VBLB connection terminal, and the second pole of the transistor N12 is connected to the second storage connection terminal;

The control electrode of the transistor N13 is connected to the HWWL connection end, the first electrode of the transistor N13 is connected to the VBL connection end, and the second electrode of the transistor N13 is connected to the first storage connection end.
The memory cell according to claim 2, wherein the second write control circuit comprises a transistor N14 and a transistor N15; wherein each transistor comprises a first pole, a second level and a control pole;

The control pole of the transistor N14 is connected to the VWWL connection terminal, the first pole of the transistor N14 is connected to the HBLB connection terminal, and the second pole of the transistor N14 is connected to the fourth storage connection terminal;

The control electrode of the transistor N15 is connected to the VWWL connection end, the first electrode of the transistor N15 is connected to the HBL connection end, and the second electrode of the transistor N15 is connected to the third storage connection end.
The memory cell according to claim 2, wherein the first read control circuit includes a transistor N16 and a transistor N17; wherein each transistor includes a first electrode, a second stage and a control electrode;

The control pole of the transistor N17 is connected to the VRWL connection terminal, the first pole of the transistor N17 is connected to the HRBL connection terminal, and the second pole of the transistor N17 is connected to the first pole of the transistor N16;

The control electrode of the transistor N16 is connected to the node Q, and the second electrode of the transistor N16 is grounded.
The memory cell of claim 2, wherein the second read control circuit comprises a transistor N18 and a transistor N19; wherein each transistor comprises a first pole, a second level and a control pole;

The control pole of the transistor N19 is connected to the HRWL connection terminal, the first pole of the transistor N19 is connected to the VRBL connection terminal, and the second pole of the transistor N19 is connected to the first pole of the transistor N18;

The control electrode of the transistor N18 is connected to the node QB, and the second electrode of the transistor N18 is grounded.
A memory array, characterized in that it includes N rows and M columns of the memory cells according to any one of claims 1 to 6; wherein, N and M are both natural numbers.
A logic computing memory, characterized in that, comprising the memory array as claimed in claim 7;

The logical calculation memory further includes a horizontal read word line, a vertical read word line, a horizontal read bit line, a vertical read bit line, a first write control line and a second write control line;

The horizontal read word line is connected to the HRWL connection end of each of the memory cells of the memory array, and the vertical read bit line is connected to the VRBL connection end of each of the memory cells of the memory array, using reading the stored data signal through the second read control circuit;

The vertical read word line is connected to the VRWL connection end of each of the memory cells of the memory array, and the horizontal read bit line is connected to the HRBL connection end of each of the memory cells of the memory array, using reading the stored data signal through the first read control circuit;

The first write control line is connected to the HWWL connection terminal of the first write control circuit of each of the memory cells of the memory array, and is used for connecting the first write control circuit in the row direction of the memory array. Write data signals are input to the memory cells.
The logic calculation memory according to claim 8, further comprising a logic operation circuit;

The logic operation circuit is connected to the horizontal read bit line and the vertical read bit line, and is used for performing logical calculation on the stored data signal output by the horizontal read bit line or the vertical read bit line, And output the logical calculation result obtained by the logical calculation.
A logical calculation method, characterized in that, based on the logical calculation memory according to any one of claims 8 and 9, the logical calculation method comprises:

the horizontal read bit line reads the stored data signal through the first read control circuit;

the vertical read bit line reads the stored data signal through the second read control circuit;

Logic calculation is performed on the stored data signal output by the horizontal read bit line or the vertical read bit line to obtain and output a result of the logic calculation.