CN111883191B

CN111883191B - 10T SRAM cell, and memory logic operation and BCAM circuit based on 10T SRAM cell

Info

Publication number: CN111883191B
Application number: CN202010677211.4A
Authority: CN
Inventors: 蔺智挺; 朱知勇; 吴秀龙; 彭春雨; 卢文娟; 黎轩; 陈军宁
Original assignee: Anhui University
Current assignee: Anhui University
Priority date: 2020-07-14
Filing date: 2020-07-14
Publication date: 2023-02-03
Anticipated expiration: 2040-07-14
Also published as: CN111883191A

Abstract

The invention discloses an in-memory logic operation and BCAM circuit based on a 10T SRAM unit, wherein the 10T SRAM unit is provided with two decoupling read ports and a transverse and longitudinal bidirectional word line, and the provided 10T SRAM decoupling independent port is used for in-memory calculation and data reading, so that the independence of stored data is ensured, and the anti-interference capability of the unit is improved. And the structure shows the characteristic of good symmetry, so that the memory logic operation and BCAM search can realize the advantages of horizontal and vertical bidirectional operation.

Description

10T SRAM cell, and memory logic operation and BCAM circuit based on 10T SRAM cell

Technical Field

The invention relates to the field of integrated circuit design, in particular to a 10T SRAM unit circuit and a memory logic operation and BCAM circuit based on the 10T SRAM unit.

Background

To date, most computing platforms are built based on a von neumann architecture, which is a form in which a memory module is separated from a computing module, frequent exchange of data between the memory module and the computing module requires a large amount of energy consumption, and a limited bandwidth between a memory and a processor greatly limits the computing efficiency. With the rapid development of application fields such as artificial intelligence, machine learning and edge computing, undoubtedly, huge challenges are brought to the von neumann architecture, massive data needs to be processed in data-intensive applications of the type, and the requirement on computing energy consumption efficiency is high, so that the von neumann bottleneck appears. In order to find a way to deal with the bottleneck of von neumann, memory Computing (CIM) is attracting attention as a very potential computing model. The memory calculation avoids large-scale data transfer between the memory and the calculation module, the data does not need to be read and is directly processed in the memory, and meanwhile, the memory calculation has the characteristic of multi-row parallel reading and can simultaneously access a plurality of addresses, so that the high energy consumption caused by the data transfer is reduced, and the data calculation efficiency is improved. Thus, memory computing can effectively address the problems with von neumann architectures.

Logic operations are the basis of operations, and in-memory logic operations are also important components of in-memory computations. Agrawal et al propose an X-SRAM circuit architecture modified with 8T SRAM cells that can implement existing nebull operations (including NAND, NOR, etc.); zhang et al also propose an IoT SRAM cell structure, which can implement internal logic operations AND, OR, XOR, etc. in cooperation with certain peripheral circuits; the two structures reprocess the discharge condition of the related bit line by adding an extra circuit, so that the operation efficiency is low, the structure is complex and the accuracy of the operation result is limited. The content addressable memory (abbreviated as BCAM) is used as a special application of memory calculation, and by comparing data input with stored data bit by bit, comparison operation is completed in the memory, so that the search efficiency is improved, and the power consumption is reduced. The existing BCAM research is mainly limited by unidirectional data search, some data are input longitudinally, compared with array storage words line by line, the structure is complex and solidified, the reusability of a module is poor, and the function is single; some data are transversely input, are compared with array storage words column by column, are contradictory to SRAM data in a row writing mode, and are not easy to write data to be compared.

Disclosure of Invention

The invention aims to provide a memory logic operation and BCAM circuit based on a 10T SRAM unit, wherein the 10T SRAM unit is provided with two decoupling read ports and a transverse and longitudinal bidirectional word line, so that memory logic operation and BCAM data search in different directions can be realized, and the stability and the operation efficiency of the unit are improved.

The purpose of the invention is realized by the following technical scheme:

a memory logic operation and BCAM circuit based on a 10T SRAM unit comprises: an array structure composed of a plurality of 10T SRAM units; the 10T SRAM cell includes: the device comprises a storage module, a left write path and a right write path which are connected with the storage module, and a left decoupled read path and a right decoupled read path which are connected with the storage module;

the left-side decoupling read accesses of the 10T SRAM units in the same row are all accessed to the same bit line RL, the right-side decoupling read accesses are all accessed to the same bit line RR and the same word line RWR, and the left-side write accesses and the right-side write accesses are all accessed to the same word line WL; the left-side decoupling read paths of the 10T SRAM units in the same column are all connected to the same bit line BL and the same word line RWL, the right-side decoupling read paths are all connected to the same bit line BLB, the left-side write paths are all connected to the same bit line BL, and the right-side write paths are all connected to the same bit line BLB;

the same column realizes the bitwise logical AND operation through the read path decoupled at the right side, and the same row realizes the bitwise logical OR operation through the read path decoupled at the left side; the left and right decoupled read paths form a comparison module, and the logic operation result is read out at a single end through a transverse and longitudinal double-bit line structure and then synthesized to obtain a matching result.

A 10T SRAM-based cell as a basic cell in the aforementioned in-memory logic operation and BCAM circuit, comprising: eight NMOS transistors and two PMOS transistors; the eight NMOS transistors are respectively marked as N0-N7, and the two PMOS transistors are respectively marked as P0-P1;

the PMOS transistor P0 and the NMOS transistor N0 form an inverter, the PMOS transistor P1 and the NMOS transistor N1 form another inverter, and the two inverters form a cross-coupling structure to serve as a storage module;

the NMOS transistor N2 and the NMOS transistor N3 are used as transmission tubes and are respectively positioned at the left side and the right side of the storage module to be used as a left writing channel and a right writing channel;

NMOS transistor N4 and NMOS transistor N6 form the left path, and NMOS transistor N5 and NMOS transistor N7 form the right path.

According to the technical scheme provided by the invention, the memory calculation and data reading are carried out by utilizing the decoupling independent port of the 10T SRAM, so that the independence of stored data is ensured, and the anti-interference capability of the unit is improved. And the structure shows the characteristic of good symmetry, so that the advantages of horizontal and vertical bidirectional operation can be realized by in-memory logic operation and BCAM search.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.

FIG. 1 is a schematic structural diagram of a 10T SRAM cell according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a row-wise and column-wise OR logic operation structure for 1-bit data according to an embodiment of the present invention;

fig. 3 is a schematic diagram of a structure of a simplified memory array (2 × 4) according to an embodiment of the present invention for implementing a row-by-row BCAM data search operation;

fig. 4 is a schematic structural diagram of a simplified memory array (4 × 2) according to an embodiment of the present invention, illustrating a structure of implementing a column-by-column search operation of BCAM data;

fig. 5 is a timing diagram illustrating the operation of the BCAM search according to the embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention are clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.

The embodiment of the invention provides a 10T SRAM unit, and a memory logic operation and BCAM circuit based on the 10T SRAM unit. The memory logic operation and BCAM circuit based on 10T SRAM unit is an array structure formed by 10T SRAM unit circuit as basic unit.

The 10T SRAM cell mainly comprises: the memory comprises a memory module, a left write path and a right write path which are connected with the memory module, and a left read path and a right read path which are decoupled and connected with the memory module. As shown in fig. 1, the 10T SRAM cell mainly includes: eight NMOS transistors and two PMOS transistors; the eight NMOS transistors are respectively marked as N0-N7, and the two PMOS transistors are respectively marked as P0-P1; the PMOS transistor P0 and the NMOS transistor N0 form an inverter, the PMOS transistor P1 and the NMOS transistor N1 form another inverter, and the two inverters form a cross-coupling structure to serve as a storage module; the NMOS transistor N2 and the NMOS transistor N3 are used as transmission tubes and are respectively positioned at the left side and the right side of the storage module to be used as a left writing channel and a right writing channel; NMOS transistor N4 and NMOS transistor N6 form a left path (noted as PORT _ L), and NMOS transistor N5 and NMOS transistor N7 form a right path (noted as PORT _ R).

The complete structure is described below:

the source electrode of the PMOS transistor P0 is connected with the source electrode of the PMOS transistor P1 and is connected with VDD;

the drain electrode of the PMOS transistor P0 is connected with the drain electrode of the NMOS transistor N0, the drain electrode of the NMOS transistor N2, the grid electrode of the NMOS transistor N1, the grid electrode of the NMOS transistor N4 and the grid electrode of the PMOS transistor P1, and the connected node is marked as Q;

the drain electrode of the PMOS transistor P1 is connected with the drain electrode of the NMOS transistor N1, the drain electrode of the NMOS transistor N3, the grid electrode of the NMOS transistor N0, the grid electrode of the NMOS transistor N7 and the grid electrode of the PMOS transistor P0, and the connected node is marked as QB;

the grid electrode of the NMOS transistor N2 and the grid electrode of the NMOS transistor N3 are both connected with a word line WL;

the source electrode of the NMOS transistor N2 and the source electrode of the NMOS transistor N6 are connected with a bit line BL;

the source of the NMOS transistor N3 and the source of the NMOS transistor N7 are connected with a bit line BLB;

the source electrode of the NMOS transistor N4 is connected with the drain electrode of the NMOS transistor N6, and the source electrode of the NMOS transistor N5 is connected with the drain electrode of the NMOS transistor N7;

the drain of NMOS transistor N5 is connected to bit line RR, the drain of NMOS transistor N4 is connected to bit line RL, the gate of NMOS transistor N5 is connected to word line RWR, and the gate of NMOS transistor N6 is connected to word line RWL.

In the embodiment of the invention, the word line WL is only used for data writing of the 10T SRAM, and is set to be at a high level when data is written, and is at a low level under other conditions.

On the basis of the 10T SRAM unit, an array structure is built to realize internal logic operation and a BCAM circuit, the internal logic operation and BCAM circuit provided by the invention is symmetrical in structure, bidirectional search operation is realized under the condition of not increasing the number of transistors, the writing mode of the SRAM can be well adapted, the reusability of the structure is increased, the data anti-interference capability is greatly improved, and various complex application scenes can be adapted. FIG. 2 illustrates the structure of 10T SRAM cells in the same row and the same column in various exemplary circuits.

As shown in part (a) of fig. 2, left-side decoupled read vias of the same column of 10T SRAM cells all access the same bit line BL and the same word line RWL (i.e., RWL1 in the figure, where "1" is the serial number of the word line RWL), right-side decoupled read vias all access the same bit line BLB, left-side write vias all access the same bit line BL (not shown in fig. 2), and right-side write vias all access the same bit line BLB (not shown in fig. 2).

As shown in part (b) of fig. 2, left-side decoupled read vias of the same row of 10T SRAM cells all access the same bit line RL, right-side decoupled read vias all access the same bit line RR and the same word line RWR (i.e., RWR1 in the figure, where "1" is the serial number of the word line RWR), and left-side write vias and right-side write vias all access the same word line WL.

In the embodiment of the invention, in the memory logic operation and BCAM circuit based on the 10T SRAM unit, the bitwise logic AND operation is realized between the same columns through the read access decoupled on the right side, and the bitwise logic OR operation is realized between the same rows through the read access decoupled on the left side; the left and right decoupled read paths form a comparison module, and the logic operation result is read out at a single end through a transverse and longitudinal double-bit line structure and then synthesized to obtain a matching result.

As shown in part (a) of fig. 2, a 1-bit logical and operation is used as an example to describe that the read path coupled through the right side decoupling between the same columns realizes a bitwise logical and operation. In part (a) of fig. 2, CELL1 to CELL2 indicate write paths and memory blocks of two 10T SRAM CELLs in the same column, and NMOS transistors corresponding to the right path PORT _ R are denoted as M1 and M2, and M3 and M4, respectively.

The left-side decoupled read path PORT _ L of two 10T SRAM cells in the same column is in an empty state, which is not illustrated. The read paths decoupled on the right side are respectively connected to different bit lines RR and different word lines RWR, two bit lines RR are grounded, and two word lines RWR are denoted as RWR1 and RWR2; the read paths decoupled on the right side are all connected into the same bit line BLB, and the bit line BLB is provided with a single-ended Sense Amplifier (SA); the connection nodes of the memory modules in the two 10T SRAM units, the right write path and the right decoupling read path are respectively marked as QB1 and QB2, and four combinations exist between QB1 and QB 2: 00. 01, 10, 11; bit line BLB is precharged to high level, word lines RWR1 and RWR2 are set to high level, data 1 exists in any node of QB1 and QB2, and bit line BLB is discharged; only if the nodes QB1 and QB2 are simultaneously 0, the bit line BLB maintains a high level, and the logical or operation of the nodes QB1 and QB2 can be realized, the node QB1 is inverted to obtain Q1, and the node QB2 is inverted to obtain Q2, which is equivalent to realizing the logical and operation of the nodes Q1 and Q2.

As shown in part (b) of fig. 2, the read path with left-side decoupling between the same rows is described by taking 1-bit logical or operation as an example to implement bitwise logical or operation. CELL1 to CELL2 in the portion (b) of fig. 2 indicate the write path and the memory block of two 10T SRAM CELLs in the same row, and the NMOS transistors corresponding to the left path PORT _ L are denoted as T1 and T2, and T3 and T4, respectively.

The read path PORT _ R decoupled from the right side of the two 10T SRAM cells in the same row is in an empty state, which is not illustrated. The left-side decoupled read paths of two 10T SRAM cells in the same row are respectively connected to different bit lines BL and different word lines RWL, the two bit lines BL are grounded, and the two word lines RWL are marked as RWL1 and RWL2; the left-side decoupling read paths are connected to the same bit line RL, and the bit line RL is provided with a single-ended sense amplifier; the connection nodes of the memory modules in the two 10T SRAM units, the left write path and the left decoupling read path are respectively marked as Q1 and Q2, and four combinations of Q1 and Q2 exist: 00. 01, 10, 11; bit line RL is precharged to a high level, word lines RWL1 and RWL2 are set to a high level, data 1 exists at any node of Q1 and Q2, bit line RL discharges, only nodes Q1 and Q2 are simultaneously 0, and bit line RL keeps the high level, so that logical OR operation of nodes Q1 and Q2 can be realized.

The circuit provided by the embodiment of the invention fully utilizes the 10T SRAM unit, and the comparison module is formed by the left and right decoupling read paths in the 10T SRAM unit, and the logic operation result is read by the single-ended sense amplifier through the transverse and longitudinal double-bit line structure and then is synthesized to obtain the matching result. The in-memory logic operation is directly read out through the sensitive amplifier, the speed is high, the calculation efficiency is high, and the result is accurate and reliable. The array formed by the 10T SRAM unit is of a symmetrical structure, and horizontal and vertical bidirectional BCAM data searching is realized through horizontal and vertical double bit lines: 1) When data is searched ROW by ROW according to the array, the bit line BL and the bit line BLB are respectively used as data input lines (SL and SLB), the bit line RL and the bit line RR are used as matched lines (ML and ML'), and matching results are read out through sense amplifiers at the ends of the bit line RL and the bit line RR and are marked as ROW SEARCH; 2) When data is searched COLUMN by COLUMN in the array, bit lines RL and RR are used as data input lines (SL and SLB), bit lines BL and BLB are used as match lines (ML and ML'), and the matching result is sensed by sense amplifiers at the ends of bit lines BL and BLB, and is denoted as COLUMN SEARCH.

In the embodiment of the invention, bit lines BL and BLB, bit lines RL and RR are provided with a pre-charging circuit and a dual-ground tube, and if the bit lines are required to be in a high level, the dual-ground tube is turned off to perform pre-charging; if the bit line needs to be grounded, the opposite ground tube is opened; the sense amplifiers are not always enabled, but are enabled according to a specific operation, so bit lines BL and BLB, bit lines RL and RR may be set high, grounded, and connected to the sense amplifiers.

The following describes the two data searching methods.

1、ROW SEARCH。

The simplified array 2 by 4 is taken as an example for description, as shown in fig. 3 and 5.

The first row of 10T SRAM CELLs are marked as CELL 00-CELL 03, the storage nodes are marked as Q1-Q4 and QB 1-QB 4 respectively, the second row of 10T SRAM CELLs are marked as CELL 10-CELL 13, and the storage nodes are marked as Q1 '-Q4' and QB1 '-QB 4' respectively. Before data searching, CELL 00-CELL 03 and CELL 10-CELL 13 store binary data to be searched, the matchlines ML (RL) and ML' (RR) are precharged to high level, the data input lines SL (BL) and SLB (BLB) are set to high level or grounded according to the searched data, if the data is 1, SL is set to high level, SLB is grounded; if the data is 0, SL ground, SLB goes high.

In order to more clearly show the technical solutions and the technical effects provided by the present invention, taking 4-bit binary data 1010 as an example, SL1 is set to high level, SLB1 is grounded, SL2 is grounded, SLB2 is set to high level, SL3 is set to high level, SLB3 is grounded, SL4 is grounded, SLB4 is set to high level, nodes Q1 to Q4 are stored in 1010, QB1 to QB4 are 0101 respectively, nodes Q1 'to Q4' are stored in 1100, and QB1 'to QB4' are 0011 respectively. Word lines RWR1 and RWR2 are set to high level, if the search bit is 1, word line RWL is turned off, if the search bit is 0, word line RWL is turned on, as illustrated by CELL00, the search bit is 1, bit line SL1 is set to high level, bit line ML1 is precharged to high level before, no matter whether word line RWL1 is turned on or not, bit line ML1 will be kept to high level, directly turning off word line RWL can reduce power consumption and interference, and improve result accuracy.

Analyzing the data bit comparison process, taking CELL10 as an example, describing the situation of searching bit 1 and matching, the searching bit is 1, the bit line SL1 is set to high level, the bit line SLB1 is grounded, the word line RWL is turned off, the match line ML2 does not discharge through the left path PORT _ L of CELL10, and keeps high level, looking again at ML2', since QB1' is 0 and the right path PORT _ R of celll 10 is turned off, the match line ML2' also keeps high level, the searching bit is 1, the node Q1' is 1, the match lines ML2 and ML2' keep high level, and data is matched; taking CELL13 as an example, the condition that the search bit is 0 and matched is introduced, the search bit is 0, the bit line SL4 is grounded, the bit line SLB4 is set to high level, the word line RWL4 and the word line RWR2 are turned on, the data are compared, Q4' stores 0, QB4' stores 1, the left channel PORT _ L of the CELL CELL13 is turned off, ML2 can not discharge to SL4 through PORT _ L, the high level is kept, the right channel PORT _ R is turned on, and the data are matched because SLB4 is high level and ML2' also keeps high level; taking CELL11 as an example, introducing the mismatch condition that the search bit is 0 and the storage bit is 1, grounding SL2, high level SLB2, starting line RWL2 and word line RWR2, comparing data, 1 storing Q2', 0 storing QB2', on-state of the left path PORT _ L of the CELL CELL12, discharging ML2 to SL2 through PORT _ L, off-state of the right path PORT _ R, and keeping high level of ML2', as long as the matched line ML2 or ML2' has power failure, the result is mismatched; taking CELL13 as an example, introducing the mismatch condition that the search bit is 1 and the storage bit is 0, SL3 is high level, SLB3 is grounded, line RWL3 is turned off, word line RWR2 is turned on, data starts to be compared, Q3 'stores 0, QB3' stores 1, the left path PORT _ L of CELL12 is turned off, ML2 keeps high level, the right path PORT _ R is turned on, ML2 'discharges to bit line SLB3 through PORT _ R, the match lines ML2 and ML2' have power failure, and the result is mismatched. Since the match lines ML and ML 'are shared by rows, all bits of the memory words of 1 row are matched, the final result is matched, 1-bit mismatch exists, and the result is mismatch, so that the first row CELLs CELL 00-CELL 03 are matched bit by bit, the match lines ML1 and ML1' keep high level, and the result match is read to be 1 by a sensitive amplifier group; the second row of CELLs CELL10 to CELL13 have mismatch bits, and as a result, the mismatch bits are read to 0 by a Sense Amplifier Set (SAs).

2、COLUMN SEARCH

A simplified array of 4 x 2 is used as an example, as shown in fig. 4 and 5.

The first row of 10T SRAM CELLs is marked as CELL 00-CELL 03, the storage nodes are marked as Q1-Q4 and QB 1-QB 4 respectively, the second row of 10T SRAM CELLs is marked as CELL 10-CELL 13, and the storage nodes are marked as Q1 '-Q4' and QB1 '-QB 4' respectively. Before data searching, CELL 00-CELL 03 and CELL 10-CELL 13 store binary data to be searched, the matchlines ML (BL) and ML' (BLB) are precharged to high level, the data input lines SL (RL) and SLB (RR) are set to high level or grounded according to the searched data, if the data is 1, SL is set to high level, SLB is grounded; if the data is 0, SL ground, SLB is high.

In order to more clearly show the technical solutions and the technical effects thereof provided by the present invention, taking the 4-bit binary data 1001 lookup as an example, the nodes Q1 to Q4 are stored in 1001, respectively 0110 for QB1 to QB4, respectively 0101 for QB1 'to QB4', respectively 1010 for QB1 'to QB4'. Word lines RWL1 and RWL2 are set at high level, by judging the search bit, if the word line RWR is turned off, if the word line RWR is 0, the word line RWL is turned on, taking CELL01 as an example, the search bit is 0, bit line SLB2 is set at high level, bit line ML1 'is precharged to high level before, no matter whether word line RWR2 is turned on or not, bit line ML1' is kept at high level, and directly turning off word line RWR can reduce power consumption and interference and improve result accuracy. The specific comparison process is the same as the ROW SEARCH comparison process, and is not described herein again.

The 10T SRAM unit provided by the invention adopts special port arrangement and cross layout of word lines and bit lines, so that a storage array constructed by the 10T SRAM unit has good symmetry, can perform horizontal and vertical bidirectional memory logic operation and BCAM data search operation, ensures data independence during operation, improves the stability and the calculation efficiency of the unit, and reduces the calculation energy consumption.

The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A memory logic operation and BCAM circuit based on a 10T SRAM unit is characterized by comprising: an array structure composed of a plurality of 10T SRAM cells; the 10T SRAM cell includes: the device comprises a storage module, a left write path and a right write path which are connected with the storage module, and a left decoupled read path and a right decoupled read path which are connected with the storage module;

the left-side decoupled read paths of the 10T SRAM units in the same row are all connected into the same bit line RL, the right-side decoupled read paths are all connected into the same bit line RR and the same word line RWR, and the left-side write paths and the right-side write paths are all connected into the same word line WL; the left-side decoupling read paths of the 10T SRAM units in the same column are all connected to the same bit line BL and the same word line RWL, the right-side decoupling read paths are all connected to the same bit line BLB, the left-side write paths are all connected to the same bit line BL, and the right-side write paths are all connected to the same bit line BLB;

the same column realizes bitwise logical AND operation through the read path decoupled on the right side, and the same row realizes bitwise logical OR operation through the read path decoupled on the left side; the left and right decoupled read paths form a comparison module, and the logic operation result is read at a single end through a transverse and longitudinal double-bit line structure, and then the matching result is obtained through synthesis.

2. The memory logic operation and BCAM circuit based on 10T SRAM cell of claim 1, wherein said 10T SRAM cell comprises: eight NMOS transistors and two PMOS transistors; the eight NMOS transistors are respectively marked as N0-N7, and the two PMOS transistors are respectively marked as P0-P1;

3. The memory logic operation and BCAM circuit of claim 2,

the source of the NMOS transistor N3 and the source of the NMOS transistor N7 are connected to the bit line BLB;

4. The in-memory logic operation and BCAM circuit based on 10T SRAM cell as claimed in claim 1, 2 or 3, wherein the implementing of bitwise logic AND operation between the same columns through the right-side decoupled read path comprises:

the right side decoupled read paths of two 10T SRAM cells in the same column are respectively connected to different bit lines RR and different word lines RWR, the two bit lines RR are grounded, and the two word lines RWR are denoted as RWR1 and RWR2; the read paths decoupled on the right side are all connected into the same bit line BLB, and the bit line BLB is provided with a single-ended sensitive amplifier; the connection nodes of the memory modules in the two 10T SRAM units, the right write path and the right decoupling read path are respectively marked as QB1 and QB2, and four combinations exist between QB1 and QB 2: 00. 01, 10, 11;

bit line BLB is precharged to high level, word lines RWR1 and RWR2 are set to high level, data 1 exists in any node of QB1 and QB2, and bit line BLB is discharged; only if the nodes QB1 and QB2 are simultaneously 0, the bit line BLB maintains a high level, that is, the logical or operation of the nodes QB1 and QB2 is realized, the node QB1 gets inverted Q1, and the node QB2 gets inverted Q2, that is, the logical and operation of the nodes Q1 and Q2 is equivalently realized.

5. The in-memory logic operation and BCAM circuit based on 10T SRAM cell as claimed in claim 1, 2 or 3, wherein the implementation of bitwise logic OR operation between the same rows through the left-side decoupled read path comprises:

the left-side decoupled read paths of two 10T SRAM units in the same row are respectively connected to different bit lines BL and different word lines RWL, the two bit lines BL are grounded, and the two word lines RWL are marked as RWL1 and RWL2; the left-side decoupling read paths are connected to the same bit line RL, and the bit line RL is provided with a single-ended sense amplifier;

the connection nodes of the memory modules in the two 10T SRAM units, the left write path and the left decoupling read path are respectively marked as Q1 and Q2, and four combinations of Q1 and Q2 exist: 00. 01, 10, 11;

bit line RL is precharged to a high level, word lines RWL1 and RWL2 are set to a high level, data 1 exists in any node of Q1 and Q2, bit line RL discharges, only nodes Q1 and Q2 are simultaneously 0, bit line RL keeps a high level, and therefore logical OR operation of nodes Q1 and Q2 can be achieved.

6. The in-memory logic operation and BCAM circuit based on 10T SRAM cell as claimed in claim 1, 2 or 3, wherein the array is a symmetric structure, and the horizontal and vertical bidirectional BCAM data lookup is realized by horizontal and vertical double bit lines:

when data are searched line by line according to the array, the bit line BL and the bit line BLB are respectively used as data input lines, the bit line RL and the bit line RR are used as matched lines, and the matching result is read out through a sense amplifier at the tail ends of the bit line RL and the bit line RR;

when data is searched column by column according to the array, a bit line RL and a bit line RR are used as data input lines, a bit line BL and a bit line BLB are used as matched lines, and a matching result is read through end sensitive amplifiers of the bit line BL and the bit line BLB.

7. A 10T-based SRAM cell, as a basic cell in the in-memory logic operation and BCAM circuit of any one of claims 1-6, comprising: eight NMOS transistors and two PMOS transistors; the eight NMOS transistors are respectively marked as N0-N7, and the two PMOS transistors are respectively marked as P0-P1;

8. The 10T-based SRAM cell of claim 7,