CN110364203A - A kind of interior storage system and calculation method calculated of support storage - Google Patents
A kind of interior storage system and calculation method calculated of support storage Download PDFInfo
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- CN110364203A CN110364203A CN201910536811.6A CN201910536811A CN110364203A CN 110364203 A CN110364203 A CN 110364203A CN 201910536811 A CN201910536811 A CN 201910536811A CN 110364203 A CN110364203 A CN 110364203A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4094—Bit-line management or control circuits
Abstract
The invention discloses the storage systems and calculation method that calculate in a kind of support storage, wherein system includes SRAM array and m computing module, the SRAM array includes the SRAM memory cell of row address decoding module and n row m column, the row address decoding module includes two groups of decoders, each computing module includes Boolean logic computing unit interconnected and adds computing unit entirely, each column SRAM memory cell is connect by two sense bit lines with Boolean logic computing unit, the Boolean logic computing unit is connected with complete plus computing unit, each complete plus computing unit is sequentially connected.After the present invention can read the data on two readout word lines simultaneously, carry out Boolean calculation and complete plus calculating, realize the function of calculating in storage, reduce the data transmission between CPU and memory, reduce the time overhead of memory access, to greatly improve arithmetic speed, storage wall and power consumption wall effect are cut down, can be widely applied to technical field of integrated circuits.
Description
Technical field
The present invention relates to the storage systems and calculating that calculate in technical field of integrated circuits more particularly to a kind of support storage
Method.
Background technique
In traditional von neumann machine architecture, computer will spatially calculate and storage separation, the two
Data communication is carried out by data/address bus.Processor is different with memory chip development trend: processor pursues high-frequency high-speed fortune
It calculates；Memory pursues intensive, low cost, thus speed is slower.Therefore, processor and memory performance gap are expanding year by year
Greatly, wall and the aggravation of power consumption wall effect are stored.Big data is using in the ascendant in recent years, it is desirable that computer can to mass data into
Row high-speed computation processing, calculation type memory become research hot topic again.The fundamental design idea of calculation type memory be
Computing function is integrated in memory, reduces the physical distance of arithmetic element and storage unit as far as possible, or even it is one that the two, which is melted,
Body.In this way, the big calculating of data volume can carry out reducing data access generation without sending to processor in memory
Time overhead, greatly improve the performance of computer.However, there are no similar calculation type memories currently on the market.
Summary of the invention
In order to solve the above-mentioned technical problem, the storage system calculated in storage can be supported the object of the present invention is to provide one kind
System and calculation method.
First technical solution of the present invention is:
A kind of interior storage system calculated of support storage, including SRAM array and m computing module, the SRAM array packet
The SRAM memory cell of row address decoding module and n row m column is included, the row address decoding module includes two groups of decoders, each institute
It states computing module to include Boolean logic computing unit interconnected and add computing unit entirely, each column SRAM memory cell passes through two
Sense bit line is connect with Boolean logic computing unit, the Boolean logic computing unit with entirely plus computing unit connect, it is each described in
Entirely plus computing unit is sequentially connected；
The SRAM array reads the storage number of the sram cell storage on two readout word lines when carrying out read operation
According to the Boolean logic computing unit carries out Boolean calculation to storing data, described to add computing unit to carry out storing data entirely
Step-by-step adds calculating entirely.
Further, the Boolean calculation includes and operation, NAND operation or operation, or non-operation and XOR operation.
Further, the SRAM memory cell be 9T structure SRAM memory cell, the 9T structure SRAM memory cell by
One group of cross coupling inverter and five NMOS tube compositions.
Further, the cross coupling inverter includes the first PMOS tube, the second PMOS tube, the first NMOS tube and second
NMOS tube, five NMOS tubes are respectively third NMOS tube, the 4th NMOS tube, the 5th NMOS tube, the 6th NMOS tube and the 7th
NMOS tube；
The source electrode of first PMOS tube and the source electrode of the second PMOS tube connect supply voltage, the source electrode of the first NMOS tube and
The source electrode of second NMOS tube is grounded, and the grid of the first PMOS tube connects the grid of the first NMOS tube, and the drain electrode of the first PMOS tube connects
The drain electrode for connecing the first NMOS tube constitutes first inverter structure；The grid of second PMOS tube connects the grid of the second NMOS tube,
The drain electrode of drain electrode the second NMOS tube of connection of second PMOS tube, constitutes second inverter structure；Second PMOS tube and second
The grid of NMOS tube is connected with the drain electrode of the first PMOS tube and the first NMOS tube, which is labeled as Q, the first PMOS tube
It is connected with the grid of the first NMOS tube with the drain electrode of the second PMOS tube and the second NMOS tube, which is labeled as QB；
The source electrode connecting node Q of third NMOS tube, drain electrode the first write bit line of connection, grid connect write word line, the 4th NMOS
The source electrode connecting node QB of pipe, drain electrode the second write bit line of connection, grid connect write word line, it is logical to constitute writing for SRAM memory cell
Road；
The grid connecting node QB of 5th NMOS tube, drain electrode the first sense bit line of connection, the grid of the 6th NMOS tube connect section
Point Q, drain electrode the second sense bit line of connection, the source electrode of the 5th NMOS tube is connected with the source electrode of the 6th NMOS tube, and is connected to the 7th
The drain electrode of NMOS tube, the source electrode of the 7th NMOS tube are grounded GND, and grid connects readout word line, constitutes the read channel of SRAM memory cell.
Further, the Boolean logic computing unit includes nor gate, the first sense amplifier and the second sense amplifier,
The homophase input of first sense amplifier terminates the first sense bit line, the inverting input terminal of first sense amplifier and the
The non-inverting input terminal of two sense amplifiers is all connected with reference voltage, and the anti-phase input termination second of second sense amplifier is read
Bit line, the input terminal connection of the in-phase output end AND OR NOT gate of first sense amplifier, second sense amplifier
Reversed-phase output AND OR NOT gate another input terminal connection；
In-phase output end output and operation signal, the reverse phase of first sense amplifier of first sense amplifier
Output end exports NAND operation signal, and the in-phase output end of second sense amplifier exports or operation signal, and described second
The reversed-phase output of sense amplifier exports or non-operation signal, and the output end of the nor gate exports XOR operation signal.
Further, it is described entirely plus computing unit include one with door, one or and an XOR gate；
Complete plus computing unit the control logic is as follows:
Cn=Cn-1*XOR+AND
Wherein, the SnFor one's own department or unit and the CnFor one's own department or unit carry, the Cn-1For low order carry, the XOR patrols for boolean
The XOR operation signal of volume computing unit output, the AND be the output of Boolean logic computing unit with operation signal.
Further, first sense amplifier includes the 8th NMOS tube, the 9th NMOS tube, the tenth NMOS tube, third
PMOS tube, the 4th PMOS tube, the 5th PMOS tube, the 6th PMOS tube, the 7th PMOS tube, the first phase inverter and the second phase inverter；
Non-inverting input terminal of the grid of 8th NMOS tube as the first sense amplifier, the grid of the 9th NMOS tube
The source electrode of inverting input terminal of the pole as the first sense amplifier, the source electrode of the 8th NMOS tube and the 9th NMOS tube is with
The drain electrode of ten NMOS tubes connects, and the grid of the tenth NMOS tube connects enable signal, and the source electrode of the tenth NMOS tube is grounded,
8th NMOS tube drain electrode respectively with the drain electrode of third PMOS tube, the drain electrode of the grid, the 5th PMOS tube of the 4th PMOS tube
It is connected with the drain electrode of the 7th PMOS tube, and the drain electrode of the 8th NMOS tube exports the same of the first sense amplifier by the first phase inverter
Phase output signal, the 9th NMOS tube drain electrode respectively with the drain electrode of the 4th PMOS tube, the grid of third PMOS tube, the 6th
The drain electrode of PMOS tube is connected with the source electrode of the 7th PMOS tube, and the drain electrode of the 9th NMOS tube passes through the first spirit of the second phase inverter output
The reversed-phase output signal of quick amplifier, grid, the grid of the 6th PMOS tube and the grid of the 7th PMOS tube of the 5th PMOS tube
Pole is all connected with precharging signal, the source electrode of the third PMOS tube, the source electrode of the 4th PMOS tube, the source electrode of the 5th PMOS tube and
The source electrode of six PMOS tube is all connected with supply voltage.
Second technical solution of the present invention is:
A kind of interior calculation method calculated of support storage, including data step is written and reads data step, the reading
Data step specifically includes the following steps:
The address information for needing to read is obtained, and the sram cell on two readout word lines is read according to address information simultaneously and is deposited
The storing data of storage；
Boolean calculation is carried out to the storing data of reading, and obtains multiple operation results；
It carries out complete to storing data according to operation result plus calculates.
Further, the Boolean calculation includes and operation, NAND operation or operation, or non-operation and XOR operation.
Further, said write data step specifically:
The write-in information and address information for needing to store are obtained, information will be successively written as unit of word according to address information
It is stored.
The beneficial effects of the present invention are: the present invention can read two readings when reading data using two groups of decoders simultaneously
Data in wordline, and Boolean calculation is carried out to data by Boolean logic computing unit, and by computing unit to data
It carries out step-by-step and adds calculating entirely, realize the function of calculating in storage, reduce the data transmission between CPU and memory, reduce memory access
Time overhead cut down storage wall and power consumption wall effect to greatly improve arithmetic speed.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of the storage system calculated in a kind of support storage of the present invention；
Fig. 2 is the electronic circuitry of 9T structure SRAM memory cell in the present invention；
Fig. 3 is the electrical schematic diagram of computing module in the present invention；
Fig. 4 is the electronic circuitry of the first sense amplifier in Fig. 3；
Fig. 5 is the waveform diagram that storage system carries out the first situation of Boolean calculation；
Fig. 6 is the waveform diagram that storage system carries out Boolean calculation second situation；
Fig. 7 is the waveform diagram that storage system carries out the third situation of Boolean calculation；
Fig. 8 is a kind of step flow chart of interior calculation method calculated of support storage.
Specific embodiment
Embodiment one
As shown in Figure 1, the storage system calculated in a kind of support storage, including SRAM array and m computing module, it is described
SRAM array includes the SRAM memory cell of row address decoding module and n row m column, and the row address decoding module includes two groups and translates
Code device, each computing module include Boolean logic computing unit interconnected and add computing unit entirely, each column SRAM storage
Unit is connect by two sense bit lines with Boolean logic computing unit, and the Boolean logic computing unit and complete plus computing unit connect
It connects, each complete plus computing unit is sequentially connected；
The SRAM array reads the storage number of the sram cell storage on two readout word lines when carrying out read operation
According to the Boolean logic computing unit carries out Boolean calculation to storing data, described to add computing unit to carry out storing data entirely
Step-by-step adds calculating entirely.
Referring to Fig.1, the reading circuit in Fig. 1, that is, Boolean logic computing unit, 1 full adder in Fig. 1 are complete plus calculate
Unit.The SRAM array only provides the address of a wordline when data are written every time, i.e., the number of a word is only written every time
According to.And it provides the address Addr of two wordline when reading data every timeiAnd Addrj, needs are chosen by row address decoder
The sram cell of interior calculating is read and store, i.e., the data of two words are subjected to step-by-step reading every time and is calculated.It reads simultaneously
The data that sram cell stores in two wordline out carry out output result signal after logical operation, then carry out entirely plus calculate, such as
This, reduces storage wall and power consumption wall effect, and accelerate arithmetic speed.
Wherein, the corresponding Boolean logic computing unit of each column SRAM memory cell, the SRAM memory cell of each column pass through
Two sense bit lines (RBL and RBLB) connect with the Boolean logic computing unit.Boolean logic computing unit is by reading two readings
The voltage of bit line carries out boolean calculation, and carries out step-by-step according to boolean calculation result and add operation entirely, reduces memory access
Time overhead, while simplifying the gate circuit needed for calculating, to also reduce cost.
It is further used as preferred embodiment, the Boolean calculation includes and operation, NAND operation or operation or non-
Operation and XOR operation.
By the exportable a variety of Boolean calculations of Boolean logic computing unit as a result, greatly enhancing Boolean logic computing unit
Function, provide more resources for subsequent operation.
Referring to Fig. 2, it is further used as preferred embodiment, the SRAM memory cell is that 9T structure SRAM storage is single
Member, the 9T structure SRAM memory cell are made of one group of cross coupling inverter and five NMOS tubes.
It is further used as preferred embodiment, the cross coupling inverter includes the first PMOS tube PM1, the 2nd PMOS
Pipe PM2, the first NMOS tube NM1, the second NMOS tube NM2, other five transistors are third NMOS tube NM3, the 4th NMOS respectively
Pipe NM4, the 5th NMOS tube NM5, the 6th NMOS tube NM6 and the 7th NMOS tube NM7；
The source electrode of the first PMOS tube PM1 and the source electrode of the second PMOS tube PM2 connect supply voltage VDD, the first NMOS
The source electrode of the source electrode of pipe NM1 and the second NMOS tube NM2 are grounded GND, and the grid of the first PMOS tube PM1 connects the first NMOS tube NM1
Grid, the first PMOS tube PM1 drain electrode connection the first NMOS tube NM1 drain electrode, constitute first inverter structure；Second
The grid of PMOS tube PM2 connects the grid of the second NMOS tube NM2, the second NMOS tube NM2's of drain electrode connection of the second PMOS tube PM2
Drain electrode, constitutes second inverter structure；The grid and the first PMOS tube PM1 of second PMOS tube PM2 and the second NMOS tube NM2 and
The drain electrode of first NMOS tube NM1 is connected, which is labeled as Q, the grid of the first PMOS tube PM1 and the first NMOS tube NM1
Pole is connected with the drain electrode of the second PMOS tube PM2 and the second NMOS tube NM2, which is labeled as QB；
The source electrode connecting node Q of third NMOS tube NM3, drain electrode the first write bit line WBL of connection, grid connect write word line WWL,
The source electrode connecting node QB of 4th NMOS tube NM4, drain electrode the second write bit line WBLB of connection, grid connect write word line WWL, constitute
The write access of SRAM memory cell；
The grid connecting node QB of 5th NMOS tube NM5, drain electrode the first sense bit line RBL of connection, the grid of the 6th NMOS tube NM6
Pole connecting node Q, drain electrode the second sense bit line RBLB of connection, the source electrode phase of the source electrode and the 6th NMOS tube NM6 of the 5th NMOS tube NM5
Connection, and it is connected to the drain electrode of the 7th NMOS tube NM7, the source electrode of the 7th NMOS tube NM7 is grounded GND, and grid connects readout word line
RWL constitutes the read channel of SRAM memory cell.
As process constantly reduces, SRAM (deposit by Static Random-Access Memory, static random-access
Reservoir) the read-write noise margin of storage unit becomes smaller, and data stability will receive influence.The SRAM cell structure of mainstream is 6T
(six pipe units) structure, read-write operation are carried out using same access.The structure, which will cause in read operation, under small size occurs
The problem of data corruption, i.e. read noise tolerance become smaller, and memory node data are influenced vulnerable to outside noise and are flipped, and cause
Data stability is poor.Therefore, study the higher SRAM memory cell circuit structure of stability, and by calculation type storage and SRAM
It combines, has positive meaning for promoting calculating speed and data stability.
It is equal for the 9T structure SRAM memory cell that the present embodiment proposes, including 9 metal-oxide-semiconductors, wordline and bit line referring to Fig. 2
It is divided into two groups, i.e. readout word line RWL, write word line WWL, sense bit line RBL and RBLB, write bit line WBL and WBLB.9T structure SRAM is deposited
Storage unit uses the design of read/write channel separation, and the data isolation of read channel and write-in, the noise for improving storage unit holds
Limit, and the structural symmetry is stronger, process complexity is relatively low, can satisfy the design requirement of sram cell.
Referring to Fig. 3, it is further used as preferred embodiment, the Boolean logic computing unit includes nor gate, first
The homophase input of sense amplifier SA1 and the second sense amplifier SA2, the first sense amplifier SA1 terminate the first read bit
Line, the inverting input terminal of the first sense amplifier SA1 and the non-inverting input terminal of the second sense amplifier SA2 are all connected with reference
The anti-phase input of voltage, the second sense amplifier SA2 terminates the second sense bit line, and the first sense amplifier SA1's is same
One input terminal of phase output terminal AND OR NOT gate connects, the reversed-phase output AND OR NOT gate of the second sense amplifier SA2 it is another
The connection of one input terminal；
In-phase output end output and operation signal, the first sense amplifier SA1 of the first sense amplifier SA1
Reversed-phase output export NAND operation signal, the second sense amplifier SA2 in-phase output end output or operation signal,
The reversed-phase output of the second sense amplifier SA2 exports or non-operation signal, and the output end of the nor gate exports exclusive or
Operation signal.
The Boolean logic computing unit is made of sense amplifier and logic gates, and each of SRAM uses two
Read sense amplifier, the first sense bit line RBL voltage and reference voltage respectively as first reading sense amplifier SA1 just
Phase input signal and rp input signal, reference voltage read sensitive put respectively as second with the second sense bit line RBLB voltage
The positive phase input signal and rp input signal of big device SA2.
SRAM array provided in this embodiment allows to same when carrying out a read operation with sensitive amplifier structure
The a variety of logical operations of Shi Jinhang, and logic gates quantity used in operation can be reduced, it reduces SRAM calculation type and deposits
The complexity of reservoir.Wherein, the full add operation circuit in Fig. 3 is to add computing unit entirely.
Referring to Fig. 3, be further used as preferred embodiment, it is described entirely plus computing unit include one with door, one or
Door and an XOR gate；
Complete plus computing unit the control logic is as follows:
Cn=Cn-1*XOR+AND
Wherein, the SnFor one's own department or unit and the CnFor one's own department or unit carry, the Cn-1For low order carry, the XOR patrols for boolean
The XOR operation signal of volume computing unit output, the AND be the output of Boolean logic computing unit with operation signal.
The present embodiment carries out step-by-step using boolean calculation result and adds calculating entirely.In traditional full adder, each
Computation formula are as follows:
Cn=Cn-l·Pn+Gn
Wherein:Gn=Qi·Qj
The operation of Boolean logic has been carried out by previous step in this present embodiment, therefore the full add operation of step-by-step can adjust
Boolean calculation is used as a result, using XOR operation signal XOR as carry lookhead Pn, will be used as with operation signal AND and partly add
Position Qn.Then circuit is simplified as:Cn=Cn-1XOR+AND, it is only necessary to three logic gates can carry out by
The full add operation of position, reduces design area.
It is further used as preferred embodiment, first sense amplifier includes the 8th NMOS tube NM8, the 9th NMOS
Pipe NM9, the tenth NMOS tube NM10, third PMOS tube PM3, the 4th PMOS tube PM4, the 5th PMOS tube PM5, the 6th PMOS tube PM6,
7th PMOS tube PM7, the first phase inverter P1 and the second phase inverter P2；
Non-inverting input terminal of the grid of the 8th NMOS tube NM8 as the first sense amplifier, the 9th NMOS tube
Inverting input terminal of the grid of NM9 as the first sense amplifier, the source electrode and the 9th NMOS tube of the 8th NMOS tube NM8
The source electrode of NM9 is connect with the drain electrode of the tenth NMOS tube NM10, and the grid of the tenth NMOS tube NM10 connects enable signal
The source electrode of SAE, the tenth NMOS tube NM10 are grounded, and the drain electrode of the 8th NMOS tube NM8 is respectively with third PMOS tube PM3's
Drain electrode, the drain electrode of the grid of the 4th PMOS tube PM4, the 5th PMOS tube PM5 are connected with the drain electrode of the 7th PMOS tube PM7, and the 8th
The drain electrode of NMOS tube NM8 exports the In-phase output signal of the first sense amplifier, the 9th NMOS by the first phase inverter P1
Pipe NM9 drain electrode respectively with the drain electrode of the 4th PMOS tube PM4, the drain electrode of the grid, the 6th PMOS tube PM6 of third PMOS tube PM3
It is connected with the source electrode of the 7th PMOS tube PM7, and the drain electrode of the 9th NMOS tube NM9 is put by the way that the second phase inverter P2 output first is sensitive
The reversed-phase output signal of big device, the grid and the 7th PMOS tube PM7 of the grid of the 5th PMOS tube PM5, the 6th PMOS tube PM6
Grid be all connected with precharging signal SPCE, the source electrode of the third PMOS tube PM3, the source electrode of the 4th PMOS tube PM4, the 5th
The source electrode of the source electrode of PMOS tube PM5 and the 6th PMOS tube PM6 are all connected with supply voltage VDD.
Embodiment two
As shown in figure 8, the present embodiment provides it is a kind of support storage in calculate calculation method, including write-in data step and
Read data step, the reading data step specifically includes the following steps:
S1, the address information for needing to read is obtained, and the SRAM read on two readout word lines simultaneously according to address information is mono-
The storing data of member storage；
S2, Boolean calculation is carried out to the storing data of reading, and obtains multiple operation results；
S3, it carries out complete to storing data according to operation result plus calculates.
The present embodiment method provides the address Addr of two wordline when reading data every timeiAnd Addrj, pass through row address
Decoder chooses the sram cell that needs to read and store interior calculating, i.e., the data of two words is carried out step-by-step reading every time
And it calculates.The data that sram cell stores in two wordline are read simultaneously, carry out output result signal after logical operation, then carry out
Complete plus calculating, in this way, reducing storage wall and power consumption wall effect, and accelerates arithmetic speed.
It is further used as preferred embodiment, the Boolean calculation includes and operation, NAND operation or operation or non-
Operation and XOR operation.
It is further used as preferred embodiment, said write data step specifically:
The write-in information and address information for needing to store are obtained, information will be successively written as unit of word according to address information
It is stored.
Specific embodiment
Detailed explanation is carried out to the systems and methods below in conjunction with Fig. 1 to Fig. 7.
As shown in connection with fig. 1, the SRAM calculation type memory includes n row m column SRAM memory cell, and main frame uses allusion quotation
The SRAM array framework of type forms, and is characterized in that at row address decoder using two groups of decoders, so that SRAM array
Two wordline can be chosen simultaneously in read operation；For 9T structure SRAM memory cell shown in Fig. 2, wordline and bit line are divided equally
It is two groups, i.e. readout word line RWL, write word line WWL, sense bit line RBL and RBLB, write bit line WBL and WBLB；Increase in reading circuit
Logic circuit with realize store in computing function.
Storage unit Cell in Fig. 1 uses 9T structure SRAM memory cell shown in Fig. 2, specifically below with reference to Fig. 2
The working principle of bright 9T structure Storage Unit read-write operation:
1, " 0 " is write:
Assuming that the current potential of original state node Q and QB are " 1 " and " 0 ".Two bit lines of WBL, WBLB first distinguish preliminary filling and are
Low level " 0 ", high level " 1 ".Subsequent write word line WWL is opened, and readout word line RWL is remained turned-off, so that third NMOS tube NM3 and the
Four NMOS tube NM4 are opened, and the 7th NMOS tube NM7 is remained off, and node Q is discharged by third NMOS tube NM3, are finally drawn
As low as " 0 " current potential.The 4th NMOS tube NM4 to the second write bit line WBLB access formed draws high node QB current potential to " 1 " current potential.
Logical zero is written 9T sram cell and completes.
2, one writing:
Assuming that the current potential of original state node Q and QB are " 0 " and " 1 ".Two bit lines of WBL, WBLB first distinguish preliminary filling and are
High level " 1 ", low level " 0 ".Subsequent write word line WWL is opened, and readout word line RWL is remained turned-off, so that third NMOS tube NM3 and the
Four NMOS tube NM4 are opened, and the 7th NMOS tube NM7 is remained off, and node QB is discharged by the 4th NMOS tube NM4, finally quilt
It is pulled down to " 0 " current potential.The access of the write bit line WBL of third NMOS tube NM3 to first of formation draws high node Q current potential to " 1 " electricity
Position.Logic 1 is written 9T sram cell and completes.
3, read operation
The reading of single 9T SRAM memory cell is for reading " 1 ".Sense bit line RBL and RBLB first is charged to high electricity in advance
Position " 1 ", subsequent readout word line RWL are opened, and write word line WWL is remained turned-off, so that the 7th NMOS tube NM7 is opened, third NMOS tube NM3
It is remained off with the 4th NMOS tube NM4.Node Q is high potential " 1 ", so that the 6th NMOS tube NM6 pipe is opened, is read by second
Bit line RBLB is formed through the discharge path of the 6th NMOS tube NM6, the 7th NMOS tube NM7 to ground GND, the electricity of the second sense bit line RBLB
Position is pulled down.And node QB is low potential " 0 ", the 5th NMOS tube NM5 is held off, so the first sense bit line RBL current potential is constant.
There are voltage differences, the voltage difference can detect and amplify by sense amplifier by two sense bit line RBL and RBLB at this time, individually
The data of sram cell storage are expressed on bit line.
SRAM storage array shown in FIG. 1 only provides the address of a wordline when data are written every time, i.e., only writes every time
Enter the data of a word.And it provides the address Addr of two wordline when reading data every timeiAnd Addrj, translated by row address
Code device chooses the sram cell that read and carry out storing interior calculating, i.e., the data of two words is carried out step-by-step reading every time and counted
It calculates.
The specific method calculated in storage is illustrated below with reference to Fig. 1, Fig. 3, Fig. 4, Fig. 5, Fig. 6 and Fig. 7:
Step 1: reading the data of storage unit, and reflected read bitline voltage value.Preliminary filling sense bit line RBL first
With RBLB to current potential " 1 ".Address AddriAnd AddrjThe two row SRAM that will be calculated are chosen simultaneously by row address decoder
Unit opens two readout word line RWL simultaneouslyiAnd RWLj, two row SRAM memory cell data are read, read bitline voltage will at this time
It can be pulled down.Assuming that the value that two units on same bit line store is Qi=0, Qj=0, then the electric discharge that two units are formed is logical
Lu Junhui drags down the voltage of the first sense bit line RBL, and the second sense bit line RBLB voltage remains unchanged.Assuming that two on same bit line
The value of a unit storage is Qi=1, Qj=1, then the discharge path that two units are formed can drag down the electricity of the second sense bit line RBLB
Pressure, and the first sense bit line RBL voltage remains unchanged.Assuming that the data that two units on same bit line store are different, as Qi
=0, Qj=1 or Qi=1, Qj=0, then the discharge path that a unit is formed can drag down the voltage of the first sense bit line RBL, and another
The discharge path that one unit is formed can drag down the voltage of the second sense bit line RBLB.The discharge capability of two units is identical, therefore two
The voltage decreasing rate of sense bit line is identical.It is shown in Figure 5, within the same RWL opening time, storing data distinct cases
The voltage fall for that sense bit line being pulled down under the Amplitude Ratio storing data same case of lower read bitline voltage decline is wanted
It is small.
Step 2: the sense amplifier detection read bitline voltage in reading circuit is poor and amplifies rapidly, Boolean logic is carried out
It calculates.A reference voltage, the voltage value V of the reference voltage are introduced in the reading circuit structure of Fig. 3refBetween storing data
That sense bit line being pulled down under voltage value and storing data same case under distinct cases after sense bit line stable discharge discharges
Between voltage value after stabilization.The structure of sense amplifier SA is as shown in Figure 4.SPCE is the precharging signal of sense amplifier,
SAE is the enable signal of sense amplifier.The working principle of sense amplifier SA are as follows:
Precharging state lower node A and B is charged to current potential " 1 " in advance.Under working condition, precharging signal SPCE is opened, and is disconnected
Precharging circuit.Next SAE enable signal is opened, sense amplifier starts to detect normal phase input end VinpAnd inverting input terminal
VinnVoltage difference.For the actual conditions of the present embodiment circuit, two input signals can be such that NMOS tube opens, thus shape
At the current potential of discharge path pulling down node A and node B.But due to two input end signal VinpAnd VinnThere is voltage difference, because
This their NMOS tube velocity of discharge for being dominated is different, and node A and node B current potential decrease speed are different.Assuming that input signal is electric
Pressure value VinpGreater than Vinn, node A current potential decrease speed is greater than node B, so that node A tries to be the first, the controlled PMOS tube of unlatching, makes
It obtains node B voltage and is clamped at high level, and the voltage of node A then continues to drop to low level.The voltage of finish node A and B
Value obtains positive output signal Vout after passing through phase inverterp=1 and reversed-phase output signal Voutn=0.
The normal phase input end Vin of sense amplifier SA1 shown in Fig. 3pMeet the first sense bit line RBL, inverting input terminal VinnIt connects
Reference voltage, the normal phase input end Vin of sense amplifier SA2pMeet reference voltage, inverting input terminal VinnConnect the second sense bit line
RBLB.When the value of two units storage on same bit line is Qi=0, QjWhen=0, it is as shown in Figure 5 to read waveform.Sense bit line is put
After piezoelectric voltage is stablized, voltage swing relationship are as follows: VRBLB> Vref> VRBL, while sense amplifier SA1 and SA2 are opened, obtain spirit
Quick amplifier SA1 positive output signal AND=0, reversed-phase output signal NAND=1, sense amplifier SA2 positive output signal 0R
=0, reversed-phase output signal NOR=1.Two storage unit exclusive or boolean calculations are obtained through or non-operation by AND and NOR signal
As a result XOR=0, boolean calculation are completed.
When the value of two units storage on same bit line is Qi=0, Qj=1 or Qi=1, QjWhen=0, waveform is read such as
Shown in Fig. 6.After sense bit line discharge voltage is stablized, voltage swing relationship are as follows: VRBL=VRBLB> Vref, while opening sense amplifier
SA1 and SA2 obtains sense amplifier SA1 positive output signal AND=0, reversed-phase output signal NAND=1, sense amplifier
SA2 positive output signal 0R=1, reversed-phase output signal NOR=0.Two storage lists are obtained through or non-operation by AND and NOR signal
First exclusive or boolean calculation result XOR=1, boolean calculation are completed.
When the value of two units storage on same bit line is Qi=1, QjWhen=1, it is as shown in Figure 7 to read waveform.Sense bit line
After discharge voltage is stablized, voltage swing relationship are as follows: VRBL> Vref> VRBLB, while sense amplifier SA1 and SA2 are opened, it obtains
Sense amplifier SA1 positive output signal AND=1, reversed-phase output signal NAND=0, sense amplifier SA2 positive output signal
0R=1, reversed-phase output signal NOR=0.Two storage unit exclusive or Boolean logics fortune is obtained through or non-operation by AND and NOR signal
Result XOR=0 is calculated, boolean calculation is completed.
Step 3: carry out step-by-step using boolean calculation result adds calculating entirely.In traditional full adder, each
Computation formula are as follows:
Cn=Cn-1·Pn+Gn
Wherein:Gn=Qi·Qj
Since the operation of Boolean logic has been carried out in the second step of the present embodiment, the full add operation of step-by-step can be called
Boolean calculation is as a result, using XOR operation signal XOR as carry lookhead Pn, will be with operation signal AND as half add carry
Qn.Then circuit is simplified as:Cn=Cn-1XOR+AND, it is only necessary to three logic gates can carry out by
The full add operation of position, reduces design area.
SRAM circuit structure provided in this embodiment can be supported in storage and be calculated, and reduce the number between CPU and memory
According to transmission, the time overhead of memory access is reduced, to greatly improve arithmetic speed, cuts down storage wall and power consumption wall effect.Meanwhile this
The SRAM array of invention design allows to carry out a variety of patrol simultaneously when carrying out a read operation with sensitive amplifier structure
Operation is collected, and logic gates quantity used in operation can be reduced, reduces the complexity of SRAM calculation type memory.
Further it is proposed that 9T structure SRAM memory cell use read/write channel separation design, the number of read channel and write-in
According to isolation, the noise margin of storage unit is improved, and the structural symmetry is stronger, process complexity is relatively low, Neng Gouman
The design requirement of sufficient sram cell.
It is to be illustrated to preferable implementation of the invention, but the invention is not limited to the implementation above
Example, those skilled in the art can also make various equivalent variations on the premise of without prejudice to spirit of the invention or replace
It changes, these equivalent deformations or replacement are all included in the scope defined by the claims of the present application.
Claims (10)
1. the storage system calculated in a kind of support storage, which is characterized in that described including SRAM array and m computing module
SRAM array includes the SRAM memory cell of row address decoding module and n row m column, and the row address decoding module includes two groups and translates
Code device, each computing module include Boolean logic computing unit interconnected and add computing unit entirely, each column SRAM storage
Unit is connect by two sense bit lines with Boolean logic computing unit, and the Boolean logic computing unit and complete plus computing unit connect
It connects, each complete plus computing unit is sequentially connected；
The SRAM array reads the storing data of the sram cell storage on two readout word lines when carrying out read operation,
The Boolean logic computing unit carries out Boolean calculation to storing data, described to add computing unit to carry out step-by-step to storing data entirely
Complete plus calculating.
2. the storage system calculated in a kind of support storage according to claim 1, which is characterized in that the Boolean calculation
Including with operation, NAND operation or operation, or non-operation and XOR operation.
3. the storage system calculated in a kind of support storage according to claim 1, which is characterized in that the SRAM storage
Unit is 9T structure SRAM memory cell, and the 9T structure SRAM memory cell is by one group of cross coupling inverter and five NMOS
Pipe composition.
4. the storage system calculated in a kind of support storage according to claim 3, which is characterized in that the cross-coupling
Phase inverter includes the first PMOS tube, the second PMOS tube, the first NMOS tube and the second NMOS tube, and five NMOS tubes are respectively the
Three NMOS tubes, the 4th NMOS tube, the 5th NMOS tube, the 6th NMOS tube and the 7th NMOS tube；
The source electrode of first PMOS tube and the source electrode of the second PMOS tube connect supply voltage, the source electrode of the first NMOS tube and second
The source electrode of NMOS tube is grounded, and the grid of the first PMOS tube connects the grid of the first NMOS tube, the drain electrode connection of the first PMOS tube the
The drain electrode of one NMOS tube constitutes first inverter structure；The grid of grid the second NMOS tube of connection of second PMOS tube, second
The drain electrode of drain electrode the second NMOS tube of connection of PMOS tube, constitutes second inverter structure；Second PMOS tube and the second NMOS tube
Grid be connected with the drain electrode of the first PMOS tube and the first NMOS tube, the connecting node be labeled as Q, the first PMOS tube and first
The grid of NMOS tube is connected with the drain electrode of the second PMOS tube and the second NMOS tube, which is labeled as QB；
The source electrode connecting node Q of third NMOS tube, drain electrode the first write bit line of connection, grid connect write word line, the 4th NMOS tube
Source electrode connecting node QB, drain electrode the second write bit line of connection, grid connect write word line, constitute the write access of SRAM memory cell；
The grid connecting node QB of 5th NMOS tube, drain electrode the first sense bit line of connection, the grid connecting node Q of the 6th NMOS tube,
Drain electrode the second sense bit line of connection, the source electrode of the 5th NMOS tube is connected with the source electrode of the 6th NMOS tube, and is connected to the 7th NMOS
The drain electrode of pipe, the source electrode of the 7th NMOS tube are grounded GND, and grid connects readout word line, constitutes the read channel of SRAM memory cell.
5. the storage system calculated in a kind of support storage according to claim 1, which is characterized in that the Boolean logic
Computing unit includes nor gate, the first sense amplifier and the second sense amplifier, first sense amplifier it is same mutually defeated
Enter the first sense bit line of termination, the inverting input terminal of first sense amplifier and the non-inverting input terminal of the second sense amplifier are equal
Reference voltage is connected, the anti-phase input of second sense amplifier terminates the second sense bit line, first sense amplifier
One input terminal of in-phase output end AND OR NOT gate connects, the reversed-phase output AND OR NOT gate of second sense amplifier it is another
Input terminal connection；
In-phase output end output and operation signal, the anti-phase output of first sense amplifier of first sense amplifier
End output NAND operation signal, the in-phase output end output of second sense amplifier or operation signal, described second is sensitive
The reversed-phase output of amplifier exports or non-operation signal, and the output end of the nor gate exports XOR operation signal.
6. a kind of support according to claim 5 stores the interior storage system calculated, which is characterized in that described complete plus calculating
Unit include one with door, one or and an XOR gate；
Complete plus computing unit the control logic is as follows:
Sn=Cn-1⊕XOR
Cn=Cn-1*XOR+AND
Wherein, the SnFor one's own department or unit and the CnFor one's own department or unit carry, the Cn-1For low order carry, the XOR is Boolean logic meter
Calculate unit output XOR operation signal, the AND be Boolean logic computing unit output with operation signal.
7. the storage system calculated in a kind of support storage according to claim 5, which is characterized in that described first is sensitive
Amplifier include the 8th NMOS tube, the 9th NMOS tube, the tenth NMOS tube, third PMOS tube, the 4th PMOS tube, the 5th PMOS tube,
6th PMOS tube, the 7th PMOS tube, the first phase inverter and the second phase inverter；
The grid of non-inverting input terminal of the grid of 8th NMOS tube as the first sense amplifier, the 9th NMOS tube is made
For the inverting input terminal of the first sense amplifier, the source electrode of the source electrode of the 8th NMOS tube and the 9th NMOS tube is with the tenth
The drain electrode of NMOS tube connects, and the grid of the tenth NMOS tube connects enable signal, the source electrode ground connection of the tenth NMOS tube, institute
State the 8th NMOS tube drain electrode respectively with the drain electrode of third PMOS tube, the grid of the 4th PMOS tube, the 5th PMOS tube drain electrode and
The drain electrode of 7th PMOS tube connects, and the drain electrode of the 8th NMOS tube exports the same phase of the first sense amplifier by the first phase inverter
Output signal, the 9th NMOS tube drain electrode respectively with the drain electrode of the 4th PMOS tube, the grid of third PMOS tube, the 6th PMOS
The drain electrode of pipe is connected with the source electrode of the 7th PMOS tube, and the drain electrode of the 9th NMOS tube is put by the way that the second phase inverter output first is sensitive
The reversed-phase output signal of big device, the grid of the grid of the 5th PMOS tube, the grid of the 6th PMOS tube and the 7th PMOS tube are equal
Connect precharging signal, the source electrode of the third PMOS tube, the source electrode of the 4th PMOS tube, the 5th PMOS tube source electrode and the 6th
The source electrode of PMOS tube is all connected with supply voltage.
8. the calculation method calculated in a kind of support storage, which is characterized in that including write-in data step and data step is read,
The reading data step specifically includes the following steps:
The address information for needing to read is obtained, and according to the sram cell storage in address information simultaneously two readout word lines of reading
Storing data；
Boolean calculation is carried out to the storing data of reading, and obtains multiple operation results；
It carries out complete to storing data according to operation result plus calculates.
9. the calculation method calculated in a kind of support storage according to claim 8, which is characterized in that the Boolean calculation
Including with operation, NAND operation or operation, or non-operation and XOR operation.
10. the calculation method calculated in a kind of support storage according to claim 8, which is characterized in that said write number
According to step specifically:
The write-in information and address information for needing to store are obtained, is successively carried out write-in information as unit of word according to address information
Storage.
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