CN113140246A

CN113140246A - Pipeline SRAM and operation method thereof

Info

Publication number: CN113140246A
Application number: CN202110517429.8A
Authority: CN
Inventors: 王镇
Original assignee: Nanjing Bosin Electronic Technology Co ltd
Current assignee: Nanjing Bosin Electronic Technology Co ltd
Priority date: 2021-05-12
Filing date: 2021-05-12
Publication date: 2021-07-20

Abstract

A pipeline SRAM and an operation method thereof belong to the technical field of special integrated circuit design. The pipelined SRAM includes: the circuit comprises a double-word-line storage unit, a word-line control circuit, a clock circuit and a capacitor-shared copy bit-line circuit; by adopting the double word line memory unit, the timing sequence problem caused by word line overlapping during SRAM continuous read operation is solved, and the SRAM read-write operation delay is effectively reduced. Meanwhile, the delay variation of the enabling of the sensitive amplifier is reduced through the capacitor sharing type bit line copying circuit, the process deviation resistance of the circuit is improved, and therefore the performance and the energy efficiency of the SRAM are improved. The pipelined SRAM divides one SRAM operation into three steps, thus solving the problem of SRAM performance deterioration at low voltage.

Description

Pipeline SRAM and operation method thereof

Technical Field

The invention relates to the technical field of special integrated circuit design, in particular to a pipeline SRAM and an operation method thereof.

Background

With the rapid popularization of consumer electronics such as smart phones, the demand for high-performance low-power System on chip (SoC) is continuously rising, and in order to achieve two major design goals of high performance and low power consumption, the design of wide-voltage SRAM down to the near-threshold region is gradually becoming a research hotspot in the industry.

As an important component module of SoC, a wide voltage Static Random Access Memory (SRAM) is a research hotspot in the industry. The performance of the SRAM is seriously deteriorated at low voltage, and cannot meet the demand of the logic circuit. In the prior art, the difficulties of SRAM design at low voltage include: (1) SAE delay change is increased sharply caused by local process deviation, and the reading performance of the SRAM is deteriorated; (2) the bit line discharge speed is slow, and the read delay and the read power consumption of the SRAM are increased.

Disclosure of Invention

In order to solve the defects in the prior art, the invention aims to provide a pipeline SRAM and an operation method thereof, which are used for improving the performance of the SRAM under low voltage.

The invention adopts the following technical scheme:

a pipeline SRAM adopts a bilateral symmetry circuit structure and comprises two registers, two address decoders, two sense amplifiers, a plurality of data selectors, a plurality of selection switch circuits and a bit line pre-charging circuit; the SRAM takes an external clock signal, a read-write enable signal, a chip selection control signal, an address input signal, a data input signal and an interrupt signal as input signals, and finally outputs a data output signal; the register is used for registering an address input signal and an external clock signal.

The SRAM includes: the device comprises a double word line memory cell array module, a first word line control module, a second word line control module, a first time sequence control module, a second time sequence control module and a capacitor sharing type copying bit line module;

in the dual word line memory cell array module, each dual word line memory cell takes two separated word line signals as input, namely a first word line signal and a second word line signal; for two continuous reading operations, controlling a first bit line signal to discharge through a first word line signal during the first reading operation; during the second read operation, the second word line signal controls the second bit line signal to discharge; during writing operation, a first word line signal and a second word line signal are simultaneously started, and input data are written into the double-word-line memory unit through a first bit line signal and a second bit line signal;

the first word line control module takes a positive read-write signal and a first word line control signal as input and takes a first word line signal as output; the second word line control module takes a positive read-write signal and a second word line control signal as input and takes a second word line signal as output; wherein, the positive read-write signal is the signal processed by the read-write enable signal through the register; when the positive read-write signal is at a high level, the inside of the pipeline SRAM is in a write operation, and when the positive read-write signal is at a low level, the inside of the pipeline SRAM is in a read operation; for two continuous reading operations, during the first reading operation, the address decoding results output by the two address decoders are used as a first word line control signal, and during the second reading operation, the address decoding results output by the two address decoders are used as a second word line control signal;

the first timing control module takes a chip selection signal, an interrupt signal, a first writing tracking signal and a first reading tracking signal as input and takes a first copy word line signal, a first word line enabling signal and a first word line selection signal as output; the second time sequence control module takes a chip selection signal, an interrupt signal, a second writing tracking signal and a second reading tracking signal as input and takes a second copy word line signal, a second word line enabling signal and a second word line selection signal as output; the chip selection signal is a signal processed by the chip selection control signal through a register;

the capacitance sharing type copy bit line module takes a first copy word line signal, a second copy word line signal, a first word line selection signal, a second word line selection signal and a chip selection signal as input, and takes a first reading tracking signal, a second reading tracking signal, a first writing tracking signal and a second writing tracking signal as output; the capacitance sharing type copy bit line module comprises a write tracking circuit and a read tracking circuit, and the two circuit structures are completely the same and work independently; for two consecutive read operations, a first read tracking signal is output during the first read operation, and a second read tracking signal is output during the second read operation.

Preferably, the first and second electrodes are formed of a metal,

the dual word line memory cell includes: a first PMOS transistor P1, a second PMOS transistor P2, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3 and a fourth NMOS transistor N4;

the source electrode of the first PMOS pipe P1 is connected with a working voltage VDD, the grid electrode is connected with a negative electrode storage signal QB, and the drain electrode is connected with a positive electrode storage signal Q; the source electrode of the second PMOS pipe P2 is connected with the working voltage VDD, the grid electrode is connected with the positive storage signal Q, and the drain electrode is connected with the negative storage signal QB; the source electrode of the first NMOS tube N1 is grounded, the grid electrode is connected with the negative electrode storage signal QB, and the drain electrode is connected with the positive electrode storage signal Q; the source electrode of the second NMOS tube N2 is grounded, the grid electrode is connected with the positive storage signal Q, and the drain electrode is connected with the negative storage signal QB; the source of the third NMOS transistor N3 is connected to the positive storage signal Q, the gate is connected to the first word line signal WLL, and the drain is connected to the first bit line signal BLL; the source of the fourth NMOS transistor N4 is connected to the negative storage signal QB, the gate is connected to the second word line signal WLR, and the drain is connected to the second bit line signal BLR.

When the pipeline SRAM is in write operation, according to an address decoding result, a first word line signal and a second word line signal of the double-word-line storage unit of the selected row are simultaneously started, a first word line signal and a second word line signal of the double-word-line storage unit of the unselected row are closed, and data are written into the double-word-line storage unit through a first bit line signal and a second bit line signal, so that double-end write operation is realized;

when the pipeline SRAM is in read operation, according to the address decoding result, the first word line signal and the second word line signal of the double word line memory cell of the selected row are turned on in turn, and the first word line signal and the second word line signal of the double word line memory cell of the unselected row are turned off; if the data stored in the memory cell is '0', the first bit line signal is discharged; if the data stored in the memory cell is '1', the second bit line signal is discharged, and thus, the single-ended sensing operation is realized.

Preferably, the first and second electrodes are formed of a metal,

in the first word line control module and the second word line control module, when the positive read-write signal is at a high level, namely when the write operation is being performed in the pipeline SRAM, the first word line control signal or the second word line control signal is at a high level, the first word line signal and the second word line signal are simultaneously started;

in the first word line control module and the second word line control module, when the forward read-write signal is at a low level, that is, when the pipeline SRAM is in read operation, the first word line control signal or the second word line control signal is at a high level, and the first word line signal or the second word line signal is turned on.

The circuit structures of the first word line control module and the second word line control module are the same, and both comprise: a read-write driving circuit and a read driving circuit; wherein the content of the first and second substances,

when writing operation is carried out in the pipeline SRAM, a reading driving circuit in a first word line control module and a reading driving circuit in a second word line control module are both in a high-impedance state, a writing driving circuit in the first word line control module starts a first word line signal, and a writing driving circuit in the second word line control module starts a second word line signal;

when a read operation is performed in the pipeline SRAM, the write driving circuit in the first word line control module and the write driving circuit in the second word line control module are both in a high-impedance state, the read driving circuit in the first word line control module starts a first word line signal according to a decoding result, or the read driving circuit in the second word line control module starts a second word line signal according to the decoding result.

Preferably, the first and second electrodes are formed of a metal,

the first time sequence control module and the second time sequence control module determine the output of an address decoding result and control the early turn-off of a word line signal according to the chip selection state of the pipeline SRAM and whether the current operation is read-first and write-later operation; meanwhile, the method can also receive a reading tracking signal and a writing tracking signal and carry out self-timing of the reading and writing operation in the SRAM; wherein, the first interrupt signal and the second terminal signal are changed into high level every time when the reading-first and writing-later operation of the pipeline SRAM occurs.

Preferably, the first and second electrodes are formed of a metal,

the capacitance-sharing replica bit line module includes: a write tracking circuit and a read tracking circuit;

the write tracking circuit includes: the circuit comprises 2n copying units, m redundant units, a third PMOS (P-channel metal oxide semiconductor) tube, a fourth PMOS tube, a first phase inverter and a second phase inverter;

the source of a third PMOS tube P3 of the write tracking circuit is connected with the working voltage, the grid is connected with the first pre-charge signal pre1, and the drain is connected with the input end of a first inverter INV _ 1; the source of the fourth PMOS transistor P4 is connected to the working voltage, the gate is connected to the second pre-charge signal pre2, and the drain is connected to the input terminal of the second inverter INV _ 2; the first inverter INV _1 outputs a third copy word line signal for controlling the read tracking circuit; the second inverter INV _2 outputs a fourth copy word line signal for controlling the read tracking circuit; the control signal of each copy unit in the writing tracking circuit is a first copy word line signal and a second copy word line signal;

the read tracking circuit includes: the circuit comprises 2n copying units, m redundancy units, a fifth PMOS (P-channel metal oxide semiconductor) tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a first OR gate, a second OR gate, a third phase inverter and a fourth phase inverter;

the source of a fifth PMOS transistor P5 of the read tracking circuit is connected to the working voltage, the gate is connected to the first pre-charge signal pre1, and the drain is connected to the first input terminal of a first OR gate OR2_ 1; the source of the sixth PMOS transistor P6 is connected to the operating voltage, the gate is connected to the second pre-charge signal pre2, and the drain is connected to the first input terminal of the second OR gate OR2_ 2; the source electrode of the fifth NMOS tube N5 is grounded, the grid electrode is connected with the working voltage, and the drain electrode is connected with the source electrode of the seventh NMOS tube N7; the source electrode of the sixth NMOS tube N6 is grounded, the grid electrode is connected with the working voltage, and the drain electrode is connected with the source electrode of the eighth NMOS tube N8; the gate of the seventh NMOS transistor N7 is connected to the first word line enable signal, and the drain is connected to the first input terminal of the first OR gate OR2_ 1; the gate of the eighth NMOS transistor N8 is connected to the second word line enable signal, and the drain is connected to the first input terminal of the second OR gate OR2_ 2; the second input end of the first OR gate OR2_1 is connected with the positive read-write signal, and the output end is connected with the first read-tracking signal; the second input end of the second OR gate OR2_2 is connected with the positive read write signal, and the output end is connected with the second read tracking signal; the control signal of each copy unit in the read tracking circuit is a third copy word line signal and a fourth copy word line signal output by the write tracking circuit unit;

the source of the ninth NMOS transistor N9 is connected to the first input terminal of the first OR gate OR2_1, the drain is connected to the drain of the seventh PMOS transistor P7, and the gate is connected to the gate of the seventh PMOS transistor P7; the source electrode of the eleventh NMOS tube N11 is grounded, the drain electrode is connected with the input end of the third inverter INV _3, and the grid electrode is connected with the drain electrode of the ninth NMOS tube N9; the source electrode of the seventh PMOS tube P7 is connected with the working voltage, the drain electrode is connected with the drain electrode of the ninth NMOS tube N9, and the grid electrode is connected with the grid electrode of the ninth NMOS tube N9; the source electrode of the ninth PMOS tube P9 is connected with the working voltage, the drain electrode is connected with the drain electrode of the ninth NMOS tube N9, and the grid electrode is connected with the input end of the third inverter INV _ 3; the source electrode of the eleventh PMOS tube P11 is connected with the power voltage, the drain electrode is connected with the input end of the third inverter INV _3, and the grid electrode is connected with the drain electrode of the ninth NMOS tube N9; the output end of the third inverter INV _3 is connected with the first write tracking signal WSTCLK 1; the source of the tenth NMOS transistor N10 is connected to the first input terminal of the second OR gate OR2_2, the drain is connected to the drain of the eighth PMOS transistor P8, and the gate is connected to the gate of the eighth PMOS transistor P8; the source electrode of the twelfth NMOS tube N12 is grounded, the drain electrode is connected with the input end of the fourth inverter INV _4, and the grid electrode is connected with the drain electrode of the tenth NMOS tube N10; the source electrode of the eighth PMOS tube P8 is connected with the working voltage, the drain electrode is connected with the drain electrode of the tenth NMOS tube N10, and the grid electrode is connected with the grid electrode of the tenth NMOS tube N10; the source electrode of the tenth PMOS tube P10 is connected with the power voltage, the drain electrode is connected with the drain electrode of the tenth NMOS tube N10, and the grid electrode is connected with the input end of the fourth inverter INV _ 4; the source electrode of the twelfth PMOS tube P12 is connected with the working voltage, the drain electrode is connected with the input end of the fourth inverter INV _4, and the grid electrode is connected with the drain electrode of the tenth NMOS tube N10; the output end of the fourth inverter INV _4 is connected with the second write tracking signal WSTCLK 2; the first pre-charging signal is obtained by charging the first bit line by the bit line pre-charging circuit during the first read-write operation of the pipeline SRAM, and the second pre-charging signal is obtained by charging the second bit line by the bit line pre-charging circuit during the second read-write operation of the pipeline SRAM.

A pipelined SRAM operating method divides an external clock cycle signal into three internal clock cycles, thereby dividing one SRAM read-write operation into three stages, comprising:

in the first stage, when the high level of the first internal clock period, the address decoder performs address decoding operation according to the address input signal, and the results are respectively input to the first word line control module and the second word line control module;

in the second stage, when the low level of the first internal clock cycle and the second internal clock cycle are in the first internal clock cycle, the first word line control module drives the first word line, and the second word line control module drives the second word line, so that in the double-word-line memory cell array module, the first word line signal controls the first bit line signal to discharge, the second word line signal controls the second bit line signal to discharge, and the potential of the first bit line and the potential of the second bit line are respectively input to the first sense amplifier and the second sense amplifier;

and in the third stage, in the third internal clock period, the first sense amplifier and the second sense amplifier respectively detect the potential of the first bit line and the potential of the second bit line, and the detection result is used as output data.

Compared with the prior art, the pipeline SRAM provided by the invention has the following beneficial effects:

1. the one-time complete operation of the SRAM is divided into three steps, so that the read-write operation delay of the SRAM is effectively reduced; at 0.6V TT25 ℃, the maximum working frequency of the SRAM is 808MHZ, which is improved by 1.91 times compared with the traditional scheme;

2. by improving the copy bit line circuit, the delay variation of Sense Amplifier Enable (SAE) is effectively reduced, and the process deviation resistance of the circuit is improved; at 0.6V TT25 ℃, the time delay change sigma of SAE is reduced from 821.38ps of the traditional scheme to 518.37ps which is reduced by 37% when the K value is 32.

Drawings

FIG. 1 is a circuit diagram of a pipelined SRAM of the present invention;

the symbols in the drawings illustrate that:

a bitcell: a dual word line memory cell;

switch: a selection switch circuit; precharge: bit line precharge circuit

And SA: a sense amplifier;

a matching unit: redundant dual word line memory cells;

d [31:0 ]: a data input signal; q [31:0 ]: a data output signal;

ADDR [8:0 ]: an address input signal;

CLK 1: a first external clock signal; CLK 2: a second external clock signal;

WLL [511:0 ]: a first word line signal; WLR [511:0 ]: a second word line signal;

DWL 1: a first word line control signal; DWL 2: a second word line control signal;

BLL [511:0 ]: a first bit line signal; BLR [511:0 ]: a second bit line signal;

WL _ EN 1: a first word line enable signal; WL _ EN 2: a second word line enable signal;

LWE: a positive read write signal; LME: a chip select signal;

RWL 1: a first replica word line signal; RWL 2: a second replica word line signal;

RSTCK 1: a first read tracking signal; RSTCLK 2: a second read tracking signal;

WSTCLK 1: a first write tracking signal; WSTCLK 2: a second write tracking signal;

WCX 1: a first word line selection signal; WCX 2: a second word line selection signal;

SWITCH: an interrupt signal;

FIG. 2 is a circuit diagram of a dual word line memory cell of a pipelined SRAM in accordance with one embodiment of the present invention;

FIG. 3 is a circuit diagram of a capacitor-shared replica bit line module of a pipelined SRAM in accordance with one embodiment of the present invention;

FIG. 4 is a circuit diagram of a word line control module of a pipelined SRAM in accordance with one embodiment of the present invention;

FIG. 5 is a circuit diagram of a timing control module of a pipelined SRAM in accordance with an embodiment of the present invention;

FIG. 6 is a timing comparison diagram of a conventional SRAM and a pipelined SRAM in accordance with one embodiment of the present invention.

FIG. 7 is an internal timing diagram of a read operation of a pipelined SRAM in accordance with one embodiment of the present invention;

FIG. 8 is a timing diagram illustrating an internal write operation of a pipelined SRAM according to an embodiment of the present invention.

Detailed Description

The present application is further described below with reference to the accompanying drawings. The following examples are only for illustrating the technical solutions of the present invention more clearly, and the protection scope of the present application is not limited thereby.

Referring to fig. 1, a pipeline SRAM with a bilateral symmetric circuit structure includes a first register, a second register, a first address decoder, a second address decoder, a first sense amplifier, a second sense amplifier, a plurality of data selectors, a plurality of selection switch circuits, and a bit line precharge circuit.

The SRAM takes an external clock signal CLK, a read-write enable signal WE, a chip selection control signal WE, an address input signal, a data input signal and an interrupt signal SWITCH as input signals and finally outputs a data output signal; the register is used for registering an address input signal and an external clock signal.

In the present preferred embodiment, the external clock signal CLK is a clock signal that synchronizes the entire operation of the SRAM; the read-write enable signal WE is used for controlling read-write enable, represents read enable when WE is at low level, and represents write enable when WE is at high level; the chip selection control signal ME is used for controlling chip selection, and when the chip selection is in a high level, the SRAM chip works normally; the address input signals ADDR [8:0] have 9-bit addresses for decoding the SRAM with the capacity of 512_ 32; d [31:0] is a 32-bit data input signal and Q [31:0] is a 32-bit data output signal.

In the preferred embodiment, a clock modulation module is used to generate a clock with a duty ratio of 1: 3, a first external clock signal CLK1 and a second external clock signal CLK 2; the positive read-write signal LWE and the chip selection signal LME are signals processed by a read-write enable signal WE and a chip selection signal ME through an internal register respectively; the external address is clocked into the SRAM via two sets of registers controlled by a first external clock signal CLK1 and a second external clock signal CLK2, respectively.

The core part of the SRAM comprises: the memory comprises a double word line memory cell array module, a first word line control module, a second word line control module, a first time sequence control module, a second time sequence control module and a capacitor sharing type copying bit line module.

In particular, the amount of the solvent to be used,

in the dual word line memory cell array module, each dual word line memory cell takes two separated word line signals as input, namely a first word line signal WLL and a second word line signal WLR; for two consecutive read operations, in the first read operation, the first bit line signal BLL is controlled to discharge by the first word line signal WLL; during the second read operation, the second bit line signal BLR is controlled to discharge by the second word line signal WLR; in a write operation, the first word line signal WLL and the second word line signal WLR are simultaneously turned on, and input data is written into the dual word line memory cell by the first bit line signal BLL and the second bit line signal BLR.

Further, as shown in fig. 2, the dual word line memory cell includes: a first PMOS transistor P1, a second PMOS transistor P2, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3 and a fourth NMOS transistor N4.

According to the double word line storage unit structure designed by the invention, one word line in the traditional 6-tube storage unit is isolated into two independent word lines, so that the problem of time sequence conflict caused by word line overlapping during continuous read operation of the SRAM is solved.

When the pipeline SRAM is in a write operation, according to an address decoding result, a first word line signal and a second word line signal of the double-word-line memory unit of the selected row are simultaneously started, a first word line signal and a second word line signal of the double-word-line memory unit of the unselected row are closed, and data are written into the double-word-line memory unit through a first bit line signal and a second bit line signal, so that double-end write operation is realized.

In the preferred embodiment, the dual word line memory cell has three operating states, which are: a hold state, a write state, and a read state.

(1) In the hold state, the first word line signal WLL and the second word line signal WLR are both low, and the third NMOS transistor N3 and the fourth NMOS transistor N4 are turned off. The first and second bit line signals BLL and BLR are maintained at the operating voltage VDD regardless of whether data in the dual word line memory cell is '1' or '0'.

(2) In a writing state, at an initial time, both the first word line signal WLL and the second word line signal WLR are at a low level, and the first bit line signal BLL and the second bit line signal BLR are precharged to the operating voltage VDD; subsequently, the charging of the first and second bit line signals BLL and BLR is stopped, and the first and second word line signals WLL and WLR simultaneously become a high level; at this time, the first and second bit line signals BLL and BLR are transmitted to the positive storage signal Q node and the negative storage signal QB node through the third and fourth NMOS transistors N3 and N4, thereby overwriting the memory cell internal data. If '0' is written into the memory cell, the first bit line signal BLL is '0', the second bit line signal BLR is '1', and finally the potential of the positive storage signal Q node is '0', and the potential of the negative storage signal QB node is '1'; when '1' is written into the memory cell, the first bit line signal BLL is '1' and the second bit line signal BLR is '0', and finally the potential of the positive storage signal Q node becomes '1' and the potential of the negative storage signal QB node becomes '0'.

(3) In a reading state, at an initial moment, both the first word line signal WLL and the second word line signal WLR are at a low level, and both the first bit line signal BLL and the second bit line signal BLR are precharged to the working voltage VDD; then, stopping charging the first bit line signal BLL and the second bit line signal BLR, and selecting to turn on the first word line signal WLL or the second word line signal WLR according to the address decoding result; in the continuous reading operation, the first word line signal WLL and the second word line signal WLR are turned on in turn; when the first word line signal WLL is turned on, the third NMOS transistor N3 is turned on, and the fourth NMOS transistor N4 is turned off; if the data in the memory cell is '0', the potential of the first bit line signal BLL is reduced, and the potential of the second bit line signal BLR is kept unchanged at the working voltage VDD; if the data in the memory cell is '1', the potentials of the first bit line signal BLL and the second bit line signal BLR are kept unchanged at VDD; when the second word line signal WLR is turned on, the third NMOS transistor N3 is turned off, and the fourth NMOS transistor N4 is turned on; if the data in the memory cell is '1', the potential of the second bit line signal BLR is reduced, and the potential of the first bit line signal BLL is kept unchanged at the working voltage VDD; if the data in the memory cell is '0', the potentials of the first bit line signal BLL and the second bit line signal BLR are kept unchanged at VDD.

Therefore, the double-word line memory unit is double-end writing and single-end reading, solves the problem of time sequence conflict caused by word line signal overlapping, and is a core module for stable work of the pipeline SRAM.

In particular, the amount of the solvent to be used,

a capacitance-shared replica bit line module which receives a first replica word line signal RWL1, a second replica word line signal RWL2, a first word line selection signal WCX1, a second word line selection signal WCX2, and a chip selection signal LME, and outputs a first read tracking signal RSTCLK1, a second read tracking signal RSTCLK2, a first write tracking signal WSTCLK1, and a second write tracking signal WSTCLK 2;

the capacitance sharing type copy bit line module comprises a write tracking circuit and a read tracking circuit, and the two circuits work independently; for two consecutive read operations, a first read tracking signal is output during the first read operation, and a second read tracking signal is output during the second read operation.

Further, the capacitance-sharing type replica bit line module includes: a write tracking circuit and a read tracking circuit;

as shown in fig. 3, the write tracking circuit includes: the circuit comprises 2n copying units, m redundancy units, a third PMOS (P-channel metal oxide semiconductor) tube, a fourth PMOS tube, a first inverter INV _1 and a second inverter INV _ 2;

the source of a third PMOS tube P3 of the write tracking circuit is connected with the working voltage, the grid is connected with the first pre-charge signal pre1, and the drain is connected with the input end of a first inverter INV _ 1; the source of the fourth PMOS transistor P4 is connected to the working voltage, the gate is connected to the second pre-charge signal pre2, and the drain is connected to the input terminal of the second inverter INV _ 2; the first inverter INV _1 outputs a third replica word line signal RWL3 for controlling the read tracking circuit; the second inverter INV _2 outputs a fourth replica word line signal RWL4 for controlling the read tracking circuit; the control signals for each replica cell in the write tracking circuit are a first replica word line signal RWL1 and a second replica word line signal RWL 2.

As shown in fig. 3, the read tracking circuit includes: the circuit comprises 2n copying units, m redundancy units, a fifth PMOS (P-channel metal oxide semiconductor) tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a first OR gate, a second OR gate, a third phase inverter and a fourth phase inverter.

The source of a fifth PMOS transistor P5 of the read tracking circuit is connected to the working voltage, the gate is connected to the first pre-charge signal pre1, and the drain is connected to the first input terminal of a first OR gate OR2_ 1; the source of the sixth PMOS transistor P6 is connected to the operating voltage, the gate is connected to the second pre-charge signal pre2, and the drain is connected to the first input terminal of the second OR gate OR2_ 2; the source electrode of the fifth NMOS tube N5 is grounded, the grid electrode is connected with the working voltage, and the drain electrode is connected with the source electrode of the seventh NMOS tube N7; the source electrode of the sixth NMOS tube N6 is grounded, the grid electrode is connected with the working voltage, and the drain electrode is connected with the source electrode of the eighth NMOS tube N8; the gate of the seventh NMOS transistor N7 is connected to the first word line enable signal WL _ EN1, and the drain is connected to the first input terminal of the first OR gate OR2_ 1; the gate of the eighth NMOS transistor N8 is connected to the second word line enable signal WL _ EN2, and the drain is connected to the first input terminal of the second OR gate OR2_ 2; the second input of the first OR gate OR2_1 is connected to the positive read write signal LWE, and the output is connected to the first read tracking signal RSTCLK 1; a second input of the second OR gate OR2_2 is connected to the positive read write signal LWE, and an output is connected to the second read tracking signal RSTCLK 2; the control signals of each replica cell in the read tracking circuit are a third replica word line signal RWL3 and a fourth replica word line signal RWL4 output by the write tracking circuit cell.

The source of the ninth NMOS transistor N9 is connected to the first input terminal of the first OR gate OR2_1, the drain is connected to the drain of the seventh PMOS transistor P7, and the gate is connected to the gate of the seventh PMOS transistor P7; the source electrode of the eleventh NMOS tube N11 is grounded, the drain electrode is connected with the input end of the third inverter INV _3, and the grid electrode is connected with the drain electrode of the ninth NMOS tube N9; the source electrode of the seventh PMOS tube P7 is connected with the working voltage, the drain electrode is connected with the drain electrode of the ninth NMOS tube N9, and the grid electrode is connected with the grid electrode of the ninth NMOS tube N9; the source electrode of the ninth PMOS tube P9 is connected with the working voltage, the drain electrode is connected with the drain electrode of the ninth NMOS tube N9, and the grid electrode is connected with the input end of the third inverter INV _ 3; the source electrode of the eleventh PMOS tube P11 is connected with the power voltage, the drain electrode is connected with the input end of the third inverter INV _3, and the grid electrode is connected with the drain electrode of the ninth NMOS tube N9; the output end of the third inverter INV _3 is connected with the first write tracking signal WSTCLK 1; the source of the tenth NMOS transistor N10 is connected to the first input terminal of the second OR gate OR2_2, the drain is connected to the drain of the eighth PMOS transistor P8, and the gate is connected to the gate of the eighth PMOS transistor P8; the source electrode of the twelfth NMOS tube N12 is grounded, the drain electrode is connected with the input end of the fourth inverter INV _4, and the grid electrode is connected with the drain electrode of the tenth NMOS tube N10; the source electrode of the eighth PMOS tube P8 is connected with the working voltage, the drain electrode is connected with the drain electrode of the tenth NMOS tube N10, and the grid electrode is connected with the grid electrode of the tenth NMOS tube N10; the source electrode of the tenth PMOS tube P10 is connected with the power voltage, the drain electrode is connected with the drain electrode of the tenth NMOS tube N10, and the grid electrode is connected with the input end of the fourth inverter INV _ 4; the source electrode of the twelfth PMOS tube P12 is connected with the working voltage, the drain electrode is connected with the input end of the fourth inverter INV _4, and the grid electrode is connected with the drain electrode of the tenth NMOS tube N10; the output terminal of the fourth inverter INV _4 is connected to the second write tracking signal WSTCLK 2.

The first pre-charge signal pre1 is a signal obtained by the bit line pre-charge circuit charging the first bit line during the first read/write operation of the pipelined SRAM, and the second pre-charge signal pre2 is a signal obtained by the bit line pre-charge circuit charging the second bit line during the second read/write operation of the pipelined SRAM.

When the read operation is carried out in the chip, the write operation which is carried out simultaneously does not exist, so that the influence of local process fluctuation on the read tracking circuit can be reduced by utilizing the idle write tracking circuit capacitor during the read operation. The capacitor sharing type copy bit line circuit is divided into a left side and a right side, namely a read-only side and a read-write common side, the two sides work independently, a first read tracking signal RSTCLK1 and a second read tracking signal RSTCLK2 are output to correspond to two times of continuous read operation respectively, and the circuit structures of the two sides are completely the same. The tracking array comprises two 6T units, namely a copy unit and a redundancy unit, wherein the copy unit is used for discharging bit line capacitance, a transmission tube connected with a word line of the redundancy unit is turned off, and the sum of the two 6T units is equal to the number of storage units loaded on the bit line in the real array and used for simulating capacitance on the bit line of the real array. Assuming that the number of discharge cells required in the conventional replica bit line is n, the number of discharge cells on the read-only side and the read-write common side is 2 n. Because the circuits connected with the bit lines on the two sides are completely the same, the left bit line is taken as an example to describe the working principle of the left bit line, when the first copy word line signal RWL1 is turned on, the single bit line on the read-only side starts to discharge, when the discharge reaches the inversion voltage of the inverter, the second copy word line signal RWL2 of the discharge unit on the read-write common side is turned on, the left bit line on the read-write common side starts to discharge, when the bit line discharges to the inversion voltage of the logic circuit connected with the bit line, the read first read tracking signal RSTCLK1 is output, and the read tracking is completed.

In particular, the amount of the solvent to be used,

a first word line control module, which takes the positive read-write signal LWE and the first word line control signal DWL1 as input and takes the first word line signal WLL as output; the second word line control module takes the positive read-write signal LWE and a second word line control signal DWL2 as input and takes a second word line signal WLR as output; for two consecutive read operations, at the time of the first read operation, the address decoding results output by the two address decoders are used as a first word line control signal DWL1, and at the time of the second read operation, the address decoding results output by the two address decoders are used as a second word line control signal DWL 2; when the positive read-write signal is at a high level, the inside of the pipeline SRAM is in a write operation, and when the positive read-write signal is at a low level, the inside of the pipeline SRAM is in a read operation; the positive read-write signal is the signal processed by the read-write enable signal through the register.

Further, the first word line control module and the second word line control module have the same circuit structure and both comprise: a read-write driving circuit and a read driving circuit; wherein the content of the first and second substances,

Further, taking the left circuit structure in any word line control module as an example, as shown in fig. 4, the write driving circuit includes: a first NOR gate NOR2_1, a first TRI-state gate TRI _ 1; the first input end of the first NOR gate NOR2_1 is connected with the second word line control signal DWL2, the second input end is connected with the negative read-write signal LWEB, and the output end is connected with the first write selection signal WS 1; the first TRI-state gate TRI _1 has a first input terminal connected to the first negative word line control signal DWL1B, a second input terminal connected to the first write select signal WS1, and an output terminal connected to the second word line signal WLR.

Further, taking the left circuit structure in any word line control module as an example, as shown in fig. 4, the read/write driving circuit includes: a first NAND gate NAND2_1, a fifth inverter INV _5, and a second TRI-state gate TRI _ 2; the first input of the first NAND gate NAND2_1 is connected to the second word line control signal DWL2, the second input is connected to the positive read write signal LWE, and the output is connected to the first read select signal RWS 1; the input end of the fifth inverter INV _5 is connected to the first word line control signal DWL1, and the output end is connected to the first negative word line control signal DWL 1B; the second TRI-state gate TRI _2 has a first input connected to the first negative word line control signal DWL1B, a second input connected to the first read select signal RWS1, and an output connected to the first word line signal WLL.

In the preferred embodiment, when the SRAM is in the write state, the positive read/write signal LWE is at a high level, and the negative read/write signal LWEB is at a low level. The first word line control signal DWL1 and the second word line control signal DWL2 are left and right decoding results, respectively. When the first word line control signal DWL1 is at a high level and the second word line control signal DWL2 is at a low level, the left write driving circuit pulls up the second word line signal WLR and the right read-write driving circuit pulls up the first word line signal WLL, and the right write driving circuit and the right read-write driving circuit are both in a high-impedance state; when the first word line control signal DWL1 is at a low level and the second word line control signal DWL2 is at a high level, the left write driver circuit and the right read driver circuit are both in a high impedance state, and the right write driver circuit pulls up the first word line signal WLL and the right read driver circuit pulls up the second word line signal WLR.

When the SRAM is in a read state, a positive read-write signal LWE signal is at a low level, and a negative read-write signal LWEB signal is at a high level. When the first word line control signal DWL1 is at a high level and the second word line control signal DWL2 is at a low level, the left write driver circuit is in a high-impedance state, the left read/write driver circuit pulls up the first word line signal WLL, the right write driver circuit is in a high-impedance state, and the right read/write driver circuit pulls down the first word line signal WLR. When the first word line control signal DWL1 is at a low level and the second word line control signal DWL2 is at a high level, the left write driver circuit is in a high impedance state, the left read/write driver circuit pulls the first word line signal WLL low, the right write driver circuit is in a high impedance state, and the right read/write driver circuit pulls the second word line signal WLR high. Therefore, in the write state, the write driving circuit simultaneously turns on the first word line signal WLL and the second word line signal WLR. In the read state, the write driving circuit alternately turns on the first word line signal WLL and the second word line signal WLR according to the states of the first word line control signal DWL1 and the second word line control signal DWL 2.

In particular, the amount of the solvent to be used,

the first timing control module takes a chip selection signal LME, an interrupt signal SWITCH, a first write tracking signal WSTCLK1 and a first read tracking signal RSTCLK1 as input, and takes a first copy word line signal RWL1, a first word line enable signal WL _ EN1 and a first word line selection signal WCX1 as output; the second timing control module takes a chip select signal LME, an interrupt signal SWITCH, a second write tracking signal WSTCLK2 and a second read tracking signal RSTCLK2 as inputs, and takes a second copy word line signal RWL2, a second word line enable signal WL _ EN2 and a second word line select signal WCX2 as outputs; the chip select signal LME is a signal processed by the chip select control signal ME through the register.

The first timing control module and the second timing control module have the same circuit structure, as shown in fig. 5, taking the first timing control module as an example, the first timing control module includes: a thirteenth PMOS transistor P13, a fourteenth PMOS transistor P14, a thirteenth NMOS transistor N13, a fourteenth NMOS transistor N14, a first BUFFER _1, a sixth inverter INV _6, a seventh inverter INV _7, an eighth inverter INV _8, a ninth inverter INV _9, a tenth inverter INV _10, a second NOR gate NOR2_2, a third NOR gate NOR2_3, AND a first AND gate AND2_ 1.

Wherein, the source of the thirteenth PMOS tube P13 is connected to the working voltage VDD, the gate is connected to the first write tracking signal WSTCLK1, and the drain is connected to the internal clock signal Float; the source of the fourteenth PMOS transistor P14 is connected to the operating voltage VDD, the gate is connected to the first read tracking signal RSTCLK1, and the drain is connected to the internal clock signal Float; the source of the thirteenth NMOS transistor N13 is connected to the drain of the fourteenth NMOS transistor N10, the gate of the thirteenth NMOS transistor N13 is connected to the first external clock signal CLK1, and the drain is connected to the internal clock signal Float; the source electrode of the fourteenth NMOS tube N14 is grounded, the grid electrode is connected with the negative clock signal CB, and the drain electrode is connected with the source electrode of the thirteenth NMOS tube N13; the input end of the first BUFFER BUFFER _1 is connected with the first external clock signal CLK1, and the output end of the first BUFFER BUFFER _1 is connected with the input end of the sixth inverter INV _ 6; the output end of the sixth inverter INV _6 is connected to the first input end of the first AND gate AND2_ 1; the input end of the seventh inverter INV _7 is connected to the chip select signal LME, and the output end is connected to the first input end of the second NOR gate NOR2_ 2; a second input terminal of the second NOR gate NOR2_2 is connected to the interrupt signal SWITCH, and an output terminal thereof is connected to the STOP signal STOP; the second input end of the first AND gate AND2_1 is connected with the STOP signal STOP, AND the output end is connected with the negative clock signal CB; the input end of the eighth inverter INV _8 is connected with the internal clock signal Float, and the output end is connected with the positive clock control signal LCLKT; the input end of the ninth inverter INV _9 is connected with the positive clock control signal LCLKT, and the output end is connected with the internal clock signal Float; the input end of the tenth inverter INV _10 is connected with the positive clock control signal LCLKT, and the output end is connected with the negative clock control signal LCLKB; the third NOR gate NOR2_3 has a first input connected to the negative clock control signal LCLKB, a second input connected to the first external clock signal CLK1, and an output connected to the first word line enable signal WL _ EN 1.

In the preferred embodiment, the first timing control module and the second timing control module, wherein the interrupt SWITCH signal is pulled up for a period during the read/write switching, if the STOP signal STOP is high, the clock circuit operates normally, the negative clock signal CB is an inverse signal of the first external clock signal CLK1 and has a time delay compared with the first external clock signal CLK1, whenever a rising edge of the first external clock signal CLK1 arrives, the internal clock signal Float node potential is pulled down, the inverter connected end to end behind the Float node functions to stabilize the internal clock signal Float, when the first external clock signal CLK1 is pulled down, the first word line enable signal WL _ EN1 is pulled up, the decoding result is allowed to be output, when the first write trace signal wstc 1 or the first read trace signal RSTCLK1 is pulled down, the Float node is restored to high level, the first word line enable signal WL _ EN1 is pulled down in advance, representing the completion of the bit line discharge or the memory cell contents having been rewritten at this time. If the STOP signal is at a low level, that is, the STOP signal is not selected by the chip or the current cycle is an idle cycle appointed by the read-then-write operation, the potential of the negative clock signal CB is constantly zero, the potential of the Float node cannot be pulled low, the first word line enable signal WL _ EN1 is always kept at a low level, and the memory array cannot be accessed.

FIG. 6 is a timing diagram of the external read operation of the SRAM in accordance with the preferred embodiment of the present invention. In the figure, the original CLK is the time for a read/write operation of the conventional SRAM, wherein at the end of the first clock cycle, the SRAM outputs data to the external bus once, and the next clock cycle performs this operation. After the pipeline SRAM is adopted, the cost of delaying three beats in the first operation can be used for replacing higher working frequency. The internal mechanism of one-time read operation of the SRAM is divided into three main steps, as shown in the figure (i), (ii) and (iii):

the method comprises the following steps: address input (write operation data input) + address decoding;

secondly, the step of: the word line drives the + bit line to discharge the memory cell (write operation flips the memory cell and precharges);

③: SA detect + output drive + bit line restore precharge (write operation without step three).

The three steps can be respectively carried out in three clock cycles, so that the SRAM can be output only in one cycle except for the time of three clock cycles required by the first operation output of the SRAM, and the throughput rate of the SRAM is improved to a great extent. In order to further optimize the time sequence and further improve the highest main frequency of the SRAM, a step (II) which occupies a relatively long time is allowed, namely the sum of the time of the word line drive and the time of the storage unit discharging the large-capacitance bit line occupies a half period of the operation of the step (I).

Fig. 7 is a timing diagram of a read operation of the pipeline SRAM, before a rising edge of the clock signal CLK arrives, if the chip select signal ME is guaranteed to be 1, and the read/write enable signal WE is 0, in a third clock cycle thereafter, the first data is output after a delay of TC2Q, that is, the first data output has a delay of two clock cycles, and each data output after the first data output only needs a delay time of TC 2Q.

FIG. 8 is a timing diagram of the write operation of the pipeline SRAM, before the rising edge of the clock signal CLK comes, the chip select signal and the read/write enable signal are both high. Unlike the read operation, the write operation consumes relatively short time and does not need to output data, the first operation must be completed before the second operation starts the word line, and the vertical coordinates WLL & R1 are the two-sided word lines of the first selected row, and the vertical coordinates WLL & R2 are the two-sided word lines of the second selected row, which are not overlapped. Ordinate PRE1&2 is the synchronized double-sided bitline precharge control signal.

2. by improving the copy bit line circuit, the delay variation of Sense Amplifier Enable (SAE) is effectively reduced, and the process deviation resistance of the circuit is improved; at 0.6V TT25 ℃, when the K value is 32, the delay variation sigma of SAE is reduced to 518.37ps from 821.38ps of the traditional scheme, and is reduced by 37%.

The above embodiments and examples are specific supports for the technical idea of the pipeline SRAM proposed by the present invention, and the protection scope of the present invention is not limited thereby, and any equivalent changes or equivalent changes made on the basis of the technical solution according to the technical idea proposed by the present invention still belong to the protection scope of the technical solution of the present invention.

Claims

1. A pipeline SRAM adopts a bilateral symmetry circuit structure and comprises two registers, two address decoders, two sense amplifiers, a plurality of data selectors, a plurality of selection switch circuits and a bit line pre-charging circuit; the SRAM takes an external clock signal, a read-write enable signal, a chip selection control signal, an address input signal, a data input signal and an interrupt signal as input signals, and finally outputs a data output signal; wherein the register is used for registering an address input signal and an external clock signal,

2. The pipelined SRAM of claim 1,

3. The pipelined SRAM of claim 2,

when the pipeline SRAM is in a write operation, according to an address decoding result, a first word line signal and a second word line signal of the double-word-line storage unit of the selected row are simultaneously started, a first word line signal and a second word line signal of the double-word-line storage unit of the unselected row are closed, and data are written into the double-word-line storage unit through a first bit line signal and a second bit line signal, so that double-end write operation is realized;

when the pipeline SRAM is in read operation, according to an address decoding result, a first word line signal and a second word line signal of the double word line memory unit of the selected row are turned on in turn, and a first word line signal and a second word line signal of the double word line memory unit of the unselected row are turned off; if the data stored in the memory cell is '0', the first bit line signal is discharged; if the data stored in the memory cell is '1', the second bit line signal is discharged, and thus, the single-ended sensing operation is realized.

4. The pipelined SRAM of claim 1,

in the first word line control module and the second word line control module, when the forward read-write signal is at a low level, that is, when the pipeline SRAM is in read operation, the first word line control signal or the second word line control signal is at a high level, and the first word line signal or the second word line signal is started.

5. The pipelined SRAM of claim 4,

the first word line control module and the second word line control module have the same circuit structure and both comprise: a read-write driving circuit and a read driving circuit; wherein the content of the first and second substances,

6. The pipelined SRAM of claim 1,

the first time sequence control module and the second time sequence control module determine the output of an address decoding result and control the early turn-off of a word line signal according to the chip selection state of the pipeline SRAM and whether the current operation is read-first and then write-operation; meanwhile, the method can also receive a reading tracking signal and a writing tracking signal and carry out self-timing of the reading and writing operation in the SRAM; wherein, the first interrupt signal and the second terminal signal are changed into high level every time when the reading-first and writing-later operation of the pipeline SRAM occurs.

7. The pipelined SRAM of claim 1,

the source of the ninth NMOS transistor N9 is connected to the first input terminal of the first OR gate OR2_1, the drain is connected to the drain of the seventh PMOS transistor P7, and the gate is connected to the gate of the seventh PMOS transistor P7; the source electrode of the eleventh NMOS tube N11 is grounded, the drain electrode is connected with the input end of the third inverter INV _3, and the grid electrode is connected with the drain electrode of the ninth NMOS tube N9; the source electrode of the seventh PMOS tube P7 is connected with the working voltage, the drain electrode is connected with the drain electrode of the ninth NMOS tube N9, and the grid electrode is connected with the grid electrode of the ninth NMOS tube N9; the source electrode of the ninth PMOS tube P9 is connected with the working voltage, the drain electrode is connected with the drain electrode of the ninth NMOS tube N9, and the grid electrode is connected with the input end of the third inverter INV _ 3; the source electrode of the eleventh PMOS tube P11 is connected with the power voltage, the drain electrode is connected with the input end of the third inverter INV _3, and the grid electrode is connected with the drain electrode of the ninth NMOS tube N9; the output end of the third inverter INV _3 is connected with the first write tracking signal WSTCLK 1; the source of the tenth NMOS transistor N10 is connected to the first input terminal of the second OR gate OR2_2, the drain is connected to the drain of the eighth PMOS transistor P8, and the gate is connected to the gate of the eighth PMOS transistor P8; the source electrode of the twelfth NMOS tube N12 is grounded, the drain electrode is connected with the input end of the fourth inverter INV _4, and the grid electrode is connected with the drain electrode of the tenth NMOS tube N10; the source electrode of the eighth PMOS tube P8 is connected with the working voltage, the drain electrode is connected with the drain electrode of the tenth NMOS tube N10, and the grid electrode is connected with the grid electrode of the tenth NMOS tube N10; the source electrode of the tenth PMOS tube P10 is connected with the power voltage, the drain electrode is connected with the drain electrode of the tenth NMOS tube N10, and the grid electrode is connected with the input end of the fourth inverter INV _ 4; the source electrode of the twelfth PMOS tube P12 is connected with the working voltage, the drain electrode is connected with the input end of the fourth inverter INV _4, and the grid electrode is connected with the drain electrode of the tenth NMOS tube N10; the output end of the fourth inverter INV _4 is connected with the second write tracking signal WSTCLK 2;

the first pre-charging signal is obtained by charging the first bit line by the bit line pre-charging circuit during the first read-write operation of the pipeline SRAM, and the second pre-charging signal is obtained by charging the second bit line by the bit line pre-charging circuit during the second read-write operation of the pipeline SRAM.

8. A pipelined SRAM operating method implemented by using a pipelined SRAM as claimed in claims 1 to 7,

the operation method divides an external clock period signal into three internal clock periods, thereby dividing one SRAM read-write operation into three stages to be carried out, and comprises the following steps: