WO2023136078A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2023136078A1
WO2023136078A1 PCT/JP2022/047329 JP2022047329W WO2023136078A1 WO 2023136078 A1 WO2023136078 A1 WO 2023136078A1 JP 2022047329 W JP2022047329 W JP 2022047329W WO 2023136078 A1 WO2023136078 A1 WO 2023136078A1
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WIPO (PCT)
Prior art keywords
metal layer
semiconductor device
area
layer
electrode terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2022/047329
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English (en)
French (fr)
Japanese (ja)
Inventor
瑛典 二井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to DE112022005983.4T priority Critical patent/DE112022005983T5/de
Priority to CN202280088260.1A priority patent/CN118541783A/zh
Priority to JP2023573944A priority patent/JPWO2023136078A1/ja
Publication of WO2023136078A1 publication Critical patent/WO2023136078A1/ja
Priority to US18/771,523 priority patent/US20240363572A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H10W72/07252—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting changes in structures or sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H10W72/07254—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting changes in dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221—Structures or relative sizes
    • H10W72/222—Multilayered bumps, e.g. a coating on top and side surfaces of a bump core
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221—Structures or relative sizes
    • H10W72/222—Multilayered bumps, e.g. a coating on top and side surfaces of a bump core
    • H10W72/223—Multilayered bumps, e.g. a coating on top and side surfaces of a bump core characterised by the structure of the outermost layers, e.g. multilayered coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221—Structures or relative sizes
    • H10W72/227—Multiple bumps having different sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/242—Dispositions, e.g. layouts relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/245—Dispositions, e.g. layouts of outermost layers of multilayered bumps, e.g. bump coating being only on a part of a bump core
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/936—Multiple bond pads having different shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/726—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked lead frame, conducting package substrate or heat sink

Definitions

  • the present disclosure relates to semiconductor devices.
  • a semiconductor device has been proposed in which a plurality of leads and a semiconductor element are bonded in the form of a so-called flip chip.
  • a semiconductor device is disclosed in Patent Document 1, for example.
  • the semiconductor device includes multiple leads, a semiconductor element, a bonding layer, and a sealing resin.
  • the semiconductor element is mounted on the leads with the plurality of first electrodes facing the leads.
  • Each first electrode has a columnar portion protruding toward the lead.
  • the columnar portion is joined to the lead via the joining layer.
  • the bonding layer is formed integrally with the columnar portion by electroplating, and is melted and solidified to bond the columnar portion and the lead.
  • the thickness of each bonding layer varies depending on how each bonding layer spreads at the time of bonding. For example, if the first bonding layer formed on the small-diameter columnar portion and the second bonding layer formed on the large-diameter columnar portion spread to the same extent during bonding, the second bonding layer having a large volume The thickness of the layer is greater than the thickness of the first bonding layer. If there is a difference in the thickness of the bonding layer, the semiconductor element bonded to the lead may tilt. If the semiconductor element is tilted with respect to the leads, problems such as connection failure may occur.
  • An object of the present disclosure is to provide a semiconductor device that is improved over conventional semiconductor devices.
  • an object of the present disclosure is to provide a semiconductor device capable of suppressing tilting of a semiconductor element.
  • a semiconductor device provided by one aspect of the present disclosure includes a semiconductor element, a conductive member, a first metal layer, and a second metal layer.
  • the semiconductor element has an element main surface and an element back surface facing opposite sides in a thickness direction, and a first electrode terminal and a second electrode terminal arranged on the element main surface.
  • the conductive member conducts to the semiconductor element.
  • the first metal layer is formed on the conductive member and joined to the first electrode terminal.
  • the second metal layer is formed on the conductive member and joined to the second electrode terminal.
  • the first electrode terminal has a first bonding surface facing the first metal layer
  • the second electrode terminal has a second bonding surface facing the second metal layer.
  • the first area of the first bonding surface is smaller than the second area of the second bonding surface.
  • the difference between the representative length of the first metal layer and the corresponding representative length of the first joint surface is less than the difference between the representative length of the second metal layer and the corresponding representative length of the second joint surface.
  • “Representative length” indicates the length of a representative portion in the shape of each metal layer and each joint surface. For example, it is the diameter in the case of a circular shape, the major or minor axis in the case of an ellipse, and the length of each side or diagonal in the case of a rectangle or polygon.
  • the difference in representative length is the difference in representative length of corresponding portions of similar shapes, for example, in the case of an elliptical shape, it is the difference between major axes or the difference between minor axes.
  • tilting of the semiconductor element in the semiconductor device can be suppressed.
  • FIG. 1 is a perspective view showing a semiconductor device according to a first embodiment of the present disclosure
  • FIG. FIG. 2 is a plan view showing the semiconductor device of FIG. 1, and is a view through a sealing resin.
  • FIG. 3 is a plan view showing the semiconductor device of FIG. 1, and is a view through a semiconductor element.
  • 4 is a bottom view showing the semiconductor device of FIG. 1.
  • FIG. 7 is a rear view showing the semiconductor device of FIG. 1.
  • FIG. 8 is a right side view of the semiconductor device of FIG. 1.
  • FIG. 9 is a left side view of the semiconductor device of FIG. 1.
  • FIG. 10 is a cross-sectional view taken along line XX of FIG.
  • FIG. 11 is a cross-sectional view along line XI-XI in FIG. 12 is a cross-sectional view along line XII-XII in FIG. 3.
  • FIG. 13 is a cross-sectional view along line XIII-XIII in FIG. 14 is a partially enlarged view of FIG. 10.
  • FIG. 15 is a partially enlarged view of FIG. 10.
  • FIG. 16 is a simplified diagram for explaining a method of flip-chip bonding a semiconductor element to a conductive member.
  • FIG. 17 is a simplified diagram for explaining a method of flip-chip bonding a semiconductor element to a conductive member.
  • FIG. 18 is a simplified diagram for explaining a method of flip-chip bonding a semiconductor element to a conductive member.
  • FIG. 19 is a diagram for comparison with FIG. 18.
  • FIG. FIG. 20 is a diagram for comparison with FIG.
  • FIG. 21 is a plan view showing a semiconductor device according to a second embodiment of the present disclosure, and is a view through a sealing resin and a semiconductor element.
  • 22 is a partially enlarged cross-sectional view showing the semiconductor device of FIG. 21.
  • FIG. 23 is a partially enlarged cross-sectional view taken along line XXIII-XXIII of FIG. 22.
  • FIG. FIG. 24 is a partial plan view showing a semiconductor device according to a third embodiment of the present disclosure, and is a view through a sealing resin and a semiconductor element.
  • First embodiment: 1 to 15 show an example of a semiconductor device according to the present disclosure.
  • a semiconductor device A10 of this embodiment includes first leads 10A, 10B, 10C, a plurality of second leads 21, a pair of third leads 22, a plurality of bonding materials 5, a plurality of metal layers 6, a semiconductor element 30, and a sealing member.
  • a stopper resin 40 is provided.
  • the package format of the semiconductor device A10 is not particularly limited, and in this embodiment, as shown in FIG. 1, it is a QFN (Quad Flat Non-leaded package) type. Further, the usage and function of the semiconductor device A10 are not limited at all.
  • Applications of the semiconductor device A10 include electronic equipment applications, general industrial equipment applications, vehicle applications, and the like.
  • functions of the semiconductor device A10 include, for example, a DC/DC converter, an AC/DC converter, and the like as appropriate.
  • a semiconductor device A10 configured as a DC/DC converter for in-vehicle use will be described as an example.
  • FIG. 1 is a perspective view showing the semiconductor device A10.
  • FIG. 2 is a plan view showing the semiconductor device A10.
  • the outer shape of the sealing resin 40 is shown by an imaginary line (chain double-dashed line) through the sealing resin 40 .
  • FIG. 3 is a plan view showing the semiconductor device A10.
  • the encapsulating resin 40 and the semiconductor element 30 are shown through the encapsulating resin 40 and the semiconductor element 30 by imaginary lines (double-dot chain lines).
  • FIG. 4 is a bottom view showing the semiconductor device A10.
  • FIG. 5 is a plan view showing the semiconductor element 30.
  • FIG. 6 is a front view showing the semiconductor device A10.
  • FIG. 7 is a back view showing the semiconductor device A10.
  • FIG. 8 is a right side view showing the semiconductor device A10.
  • FIG. 9 is a left side view of the semiconductor device A10.
  • 10 is a cross-sectional view taken along line XX of FIG. 3.
  • FIG. 11 is a cross-sectional view along line XI-XI in FIG. 12 is a cross-sectional view along line XII-XII in FIG. 3.
  • FIG. 13 is a cross-sectional view along line XIII-XIII in FIG.
  • FIG. 14 is a partially enlarged view of FIG. 10 (near electrode terminals 36A, which will be described later).
  • FIG. 15 is a partially enlarged view of FIG. 10 (near an electrode terminal 36B, which will be described later).
  • the semiconductor device A10 is plate-shaped, and has a rectangular shape when viewed in the thickness direction (planar view).
  • the thickness direction of the semiconductor device A10 is defined as the z direction
  • the direction along one side of the semiconductor device A10 perpendicular to the z direction (vertical direction in FIGS. 2 to 4) is defined as the x direction, the z direction, and the x direction.
  • the direction orthogonal to the (horizontal direction in FIGS. 2 to 4) is defined as the y direction.
  • the z-direction is an example of the "thickness direction”
  • the y-direction is an example of the "first direction”.
  • the shape and dimensions of the semiconductor device A10 are not limited.
  • the first leads 10A, 10B, 10C, the plurality of second leads 21, and the pair of third leads 22 support the semiconductor element 30 and mount the semiconductor device A10 on the wiring board. terminal.
  • each of the first leads 10A, 10B, 10C, the plurality of second leads 21, and the pair of third leads 22 is partially covered with a sealing resin 40.
  • portions of the first leads 10A, 10B, 10C, the plurality of second leads 21, and the pair of third leads 22 exposed from the sealing resin 40 are Hatching consisting of a plurality of discrete points is attached.
  • conductive member 1 when the first leads 10A, 10B, 10C, the plurality of second leads 21, and the pair of third leads 22 are collectively indicated, they may be referred to as "conductive member 1".
  • the conductive member 1 is formed, for example, by etching a metal plate.
  • the conductive member 1 may be formed by punching or bending a metal plate.
  • the first leads 10A, 10B, 10C, the plurality of second leads 21, and the pair of third leads 22 are arranged apart from each other.
  • a constituent material of the conductive member 1 is, for example, Cu or a Cu alloy, but is not limited thereto.
  • each of the first leads 10A, 10B, 10C has a strip shape extending in the x direction when viewed in the z direction.
  • Each of the first leads 10A, 10B, 10C has a first major surface 101 and a first back surface 102 facing opposite to each other in the z direction.
  • the first main surface 101 faces the z-direction z2 side and faces the semiconductor element 30 .
  • the first major surface 101 is covered with the sealing resin 40 .
  • the first rear surface 102 faces the z-direction z1 side.
  • the first rear surface 102 is exposed from the sealing resin 40 .
  • the semiconductor element 30 is supported on the first main surface 101 in the first leads 10A, 10B, 10C. Also, as shown in FIGS.
  • the area of the first main surface 101 is equal to the area of the first back surface. It is larger than the area of 102.
  • the portions of the first leads 10A, 10B, and 10C where the first main surface 101 does not overlap the first rear surface 102 as viewed in the z direction are formed by half-etching from the first rear surface 102 side, for example. This portion prevents the first leads 10A, 10B, and 10C from dropping off from the bottom surface 42 of the sealing resin 40 by an anchoring effect.
  • the first lead 10A and the first lead 10B receive the DC power (voltage) to be converted in the semiconductor device A10.
  • the first lead 10A is a positive electrode (P terminal).
  • the first lead 10B is a negative electrode (N terminal).
  • the first lead 10C outputs AC power (voltage) converted by a switching circuit 321 of the semiconductor element 30, which will be described later.
  • the first leads 10A, 10B, and 10C are arranged along the y direction from the y1 side to the y2 side in the order of the first lead 10A, the first lead 10C, and the first lead 10B. It is The first lead 10A is positioned between the plurality of second leads 21 and the first lead 10C in the y direction.
  • the first lead 10C is located between the first lead 10A and the first lead 10B in the y direction.
  • each of the first lead 10A and the first lead 10C includes a main portion 11 and a pair of side portions 12. As shown in FIG. The main portion 11 extends in the x direction. The pair of side portions 12 are connected to both ends of the main portion 11 in the x direction, and are smaller in size in the y direction than the main portion 11 . Each of the pair of side portions 12 has a first end surface 121 . As shown in FIG. 11, the first end surface 121 is connected to both the first major surface 101 and the first back surface 102 and faces the x direction. The first end surface 121 is exposed from the sealing resin 40 .
  • the first lead 10B includes a main portion 11, four side portions 12, and a plurality of projecting portions 13.
  • the main portion 11 extends in the x direction.
  • the two side portions 12 are connected to the x-direction x1 side end of the main portion 11 .
  • the other two side portions 12 are connected to the x-direction x2 side end of the main portion 11 .
  • Each of the four sides 12 has a first end surface 121 .
  • the first end surface 121 is connected to both the first major surface 101 and the first back surface 102 and faces the x direction.
  • the first end surface 121 is exposed from the sealing resin 40 .
  • the plurality of protruding portions 13 protrude from the y-direction y2 side of the main portion 11 .
  • a sealing resin 40 is filled between two adjacent protrusions 13 .
  • Each of the plurality of protrusions 13 has a secondary end surface 131 .
  • the secondary end surface 131 is connected to both the first main surface 101 and the first back surface 102 and faces the y direction y2.
  • the secondary end surface 131 is exposed from the sealing resin 40 .
  • the plurality of sub-end faces 131 are arranged at predetermined intervals along the x-direction.
  • First leads 10A, 10B, and 10C are not limited to a shape having main portion 11 and side portion 12 at all.
  • first rear surface 102, pair of first end surfaces 121, and plurality of sub-end surfaces 131 exposed from sealing resin 40 are plated with Sn, for example. may be applied.
  • Sn plating a plurality of metal platings in which Ni, Pd, and Au are laminated in this order, for example, may be adopted.
  • the plurality of second leads 21 are positioned on the y1 side in the y direction with respect to the first lead 10A. Any one of the plurality of second leads 21 is a ground terminal of a control circuit 322 of the semiconductor element 30, which will be described later. Power (voltage) for driving the control circuit 322 or an electric signal for transmission to the control circuit 322 is input to each of the plurality of other second leads 21 . As shown in FIGS. 3 and 4 , each of the plurality of second leads 21 has a second main surface 211 , a second back surface 212 and a second end surface 213 . In addition, the shape of the second lead 21 is not limited at all.
  • the second principal surface 211 faces the same side as the first principal surfaces 101 of the first leads 10A, 10B, and 10C in the z-direction and faces the semiconductor element 30 .
  • the second main surface 211 is covered with the sealing resin 40 .
  • Semiconductor element 30 is supported by second main surface 211 .
  • the second rear surface 212 faces the side opposite to the second major surface 211 .
  • the second rear surface 212 is exposed from the sealing resin 40 .
  • the second end surface 213 is connected to both the second main surface 211 and the second back surface 212 and faces the y-direction y1 side.
  • the second end surface 213 is exposed from the sealing resin 40 .
  • the plurality of second end faces 213 are arranged at predetermined intervals along the x direction.
  • the two second leads 21 arranged at both ends in the x-direction further have fourth end faces 214 .
  • the fourth end face 214 faces the x direction and is exposed from the sealing resin 40 .
  • the area of the second main surface 211 is larger than the area of the second rear surface 212 in each of the plurality of second leads 21 .
  • a portion of each second lead 21 where the second main surface 211 does not overlap the second rear surface 212 when viewed in the z direction is formed by half-etching from the second rear surface 212 side, for example. This portion prevents each second lead 21 from falling off from the bottom surface 42 of the sealing resin 40 by an anchoring effect.
  • the second rear surface 212, the second end surface 213 and the fourth end surface 214 of the plurality of second leads 21 exposed from the sealing resin 40 may be plated with Sn, for example.
  • Sn a plurality of metal platings in which Ni, Pd, and Au are laminated in this order, for example, may be adopted.
  • the pair of third leads 22 are positioned between the first lead 10A and the plurality of second leads 21 in the y direction, as shown in FIG.
  • the pair of third leads 22 are separated from each other in the x direction.
  • An electrical signal or the like for transmission to the control circuit 322 configured in the semiconductor element 30 is input to each of the pair of third leads 22 .
  • each of the pair of third leads 22 has a third main surface 221 , a third rear surface 222 and a third end surface 223 . Note that the shape of the third lead 22 is not limited at all.
  • the third principal surface 221 faces the same side as the first principal surfaces 101 of the first leads 10A, 10B, and 10C in the z-direction and faces the semiconductor element 30 .
  • the third main surface 221 is covered with the sealing resin 40 .
  • Semiconductor element 30 is supported by third main surface 221 .
  • the third rear surface 222 faces the side opposite to the third main surface 221 .
  • the third rear surface 222 is exposed from the sealing resin 40 .
  • the third end surface 223 is connected to both the third main surface 221 and the third back surface 222 and faces the x direction.
  • the third end surface 223 is exposed from the sealing resin 40 .
  • the third end faces 223 are arranged along the y direction together with the first end faces 121 of the first leads 10A, 10B, and 10C.
  • the area of the third main surface 221 is larger than the area of the third back surface 222 in each of the pair of third leads 22 .
  • a portion of each third lead 22 where the third main surface 221 does not overlap the third rear surface 222 as viewed in the z direction is formed by half-etching from the third rear surface 222 side, for example. This portion prevents each third lead 22 from dropping off from the bottom surface 42 of the sealing resin 40 by an anchoring effect.
  • the third rear surface 222 and the third end surface 223 of the pair of third leads 22 exposed from the sealing resin 40 may be plated with Sn, for example.
  • Sn for example.
  • the first leads 10A, 10B, 10C, the plurality of second leads 21, and the pair of third leads 22 may have a plurality of recesses recessed in the z-direction from the respective main surfaces 101, 211, 221.
  • the recesses can be formed, for example, by half-etching from the main surfaces 101, 211, 221 side.
  • the inner surface of the recess is brought into close contact with the sealing resin 40 , thereby improving the adhesion between each lead and the sealing resin 40 .
  • the concave portion can also be used for positioning the semiconductor element 30 in the z direction (positioning in the xy plane).
  • the number, shape, and arrangement of the first leads 10A, 10B, 10C, the second leads 21, and the third leads 22 are not limited.
  • the semiconductor element 30 is arranged in the center of the semiconductor device A10 when viewed in the z direction.
  • the semiconductor element 30 is supported by first leads 10A, 10B, 10C, a plurality of second leads 21, and a pair of third leads 22, as shown in FIGS.
  • the semiconductor element 30 is covered with a sealing resin 40 .
  • the semiconductor element 30 has a semiconductor substrate 31 , a semiconductor layer 32 , a passivation film 33 , an electrode 34 , an insulating layer 35 and a plurality of electrode terminals 36 .
  • the semiconductor element 30 is a flip-chip type LSI in which a circuit is configured.
  • the semiconductor element 30 has a rectangular shape when viewed in the z direction as shown in FIG. 2, and a plate shape as shown in FIGS.
  • the semiconductor element 30 has an element main surface 30a and an element rear surface 30b.
  • the element principal surface 30a includes the first principal surfaces 101 of the first leads 10A, 10B, and 10C, the second principal surfaces 211 of the plurality of second leads 21, and the third principal surfaces 221 of the pair of third leads 22 in the z-direction. facing.
  • the element rear surface 30b faces the side opposite to the element main surface 30a in the z direction.
  • the element main surface 30a includes a first region 301 and a second region 302. As shown in FIG.
  • the first region 301 is a region including portions of the element main surface 30a facing the first main surface 101 of the first leads 10A, 10B, and 10C, and is arranged on the y2 side in the y direction.
  • the second region 302 is a region including portions of the device main surface 30a that face the second main surfaces 211 of the plurality of second leads 21 and the third main surfaces 221 of the pair of third leads 22, and is oriented in the y direction. It is arranged on the y1 side.
  • the semiconductor substrate 31 is provided with a semiconductor layer 32, a passivation film 33, an electrode 34, an insulating layer 35, and a plurality of electrode terminals 36 on the z-direction z1 side.
  • the constituent material of the semiconductor substrate 31 is, for example, Si (silicon) or silicon carbide (SiC).
  • the surface of the semiconductor substrate 31 on the z-direction z2 side constitutes the element back surface 30b.
  • the semiconductor layer 32 is laminated on the semiconductor substrate 31 on the z-direction z1 side.
  • the semiconductor layer 32 includes a plurality of types of p-type semiconductors and n-type semiconductors based on different amounts of doped elements.
  • a switching circuit 321 and a control circuit 322 electrically connected to the switching circuit 321 are formed in the semiconductor layer 32 .
  • the switching circuit 321 is a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), an IGBT (Insulated Gate Bipolar Transistor), or the like.
  • the switching circuit 321 is divided into two regions, a high voltage region (upper arm circuit) and a low voltage region (lower arm circuit). Each region is composed of one n-channel MOSFET.
  • the control circuit 322 includes a gate driver for driving the switching circuit 321, a bootstrap circuit corresponding to the high voltage region of the switching circuit 321, and the like, and performs control for normally driving the switching circuit 321. .
  • a wiring layer (not shown) is further formed in the semiconductor layer 32 . The wiring layer electrically connects the switching circuit 321 and the control circuit 322 to each other.
  • the passivation film 33 covers the surface of the semiconductor layer 32 on the z-direction z1 side.
  • Passivation film 33 has electrical insulation.
  • the passivation film 33 is composed of, for example, a silicon oxide film (SiO 2 ) laminated in contact with the semiconductor layer 32 and a silicon nitride film (Si 3 N 4 ) laminated on the silicon oxide film.
  • the surface of the passivation film 33 on the z-direction z1 side constitutes the element main surface 30a.
  • a plurality of electrodes 34 are formed on the element main surface 30a.
  • the z-direction shape of the plurality of electrodes 34 formed in the first region 301 is, for example, a triangular shape or a rhombus shape, which is long in the y-direction.
  • a plurality of isosceles triangular electrodes 34 with vertices facing the y direction y1 side are arranged side by side at equal intervals in the x direction near the end of the first region 301 on the y direction y2 side.
  • a plurality of other isosceles triangular electrodes 34 are arranged side by side in the x-direction near the end of the first region 301 on the y-direction y1 side with the apex angle facing the y-direction y2 side. .
  • the electrode 34 arranged on the y-direction y2 side and the electrode 34 arranged on the y-direction y1 side are arranged so that their apex angles face each other.
  • a diamond-shaped electrode 34 is arranged in each gap between the plurality of electrodes 34 arranged on the y-direction y2 side and the plurality of electrodes 34 arranged on the y-direction y1 side.
  • the electrodes 34 arranged on the y-direction y2 side are electrically connected to the first lead 10B via electrode terminals 36B.
  • the electrodes 34 arranged on the y-direction y1 side are electrically connected to the first lead 10A via electrode terminals 36B.
  • the electrode 34 arranged in each gap is electrically connected to the first lead 10C via the electrode terminal 36B.
  • the z-direction shape of the plurality of electrodes 34 formed in the second region 302 is, for example, a rectangular shape.
  • a plurality of electrodes 34 are arranged in isolation in the second region 302 .
  • a part of the electrode 34 arranged in the second region 302 is electrically connected to the second lead 21 or the third lead 22 via the electrode terminal 36A.
  • each of the plurality of electrodes 34 when viewed in the z direction are not limited.
  • a slit (gap) is provided between adjacent electrodes 34 .
  • the planar shape of the slit shown in FIG. 5 is linear. Note that the planar shape of the slit is not limited to a linear shape. The planar shape of the slit may be wavy, zigzag, or the like.
  • Each electrode 34 is connected to a wiring layer formed in the semiconductor layer 32 through an opening (not shown) provided in the passivation film 33 . Thereby, the electrode 34 is electrically connected to either the switching circuit 321 or the control circuit 322 of the semiconductor layer 32 .
  • the electrode 34 is composed of a plurality of metal layers laminated from the passivation film 33 toward the z-direction z1 side, and includes a first layer 34a, a second layer 34b, and a third layer 34c. ing.
  • the first layer 34a is in contact with the passivation film 33 and is made of Cu.
  • the second layer 34b is in contact with the first layer 34a and is made of Ni.
  • the third layer 34c is in contact with the second layer 34b and is made of Pd. Note that the configuration of the electrode 34 is not limited.
  • the insulating layer 35 is formed on the element main surface 30a and partially covers the passivation film 33 and the electrodes 34. As shown in FIGS.
  • the insulating layer 35 has electrical insulation.
  • the constituent material of the insulating layer 35 is phenol resin in this embodiment.
  • the constituent material of the insulating layer 35 is not limited, and other insulating materials such as polyimide resin may be used.
  • the insulating layer 35 has a plurality of openings 35a. One of the electrodes 34 is exposed from each of the plurality of openings 35a.
  • the insulating layer 35 is formed, for example, by applying a photolithographic technique to a photosensitive resin material applied by a spin coater.
  • each electrode terminal 36 is arranged on the element main surface 30a and protrude toward the first main surface 101, the second main surface 211 and the third main surface 221. . 14 and 15, each electrode terminal 36 is in contact with one of the electrodes 34 through the opening 35a of the insulating layer 35, respectively. Each electrode terminal 36 is in contact with the electrode 34 at its central portion when viewed in the z-direction, and overlaps the insulating layer 35 at its peripheral portion.
  • the multiple electrode terminals 36 are conductive.
  • each electrode terminal 36 includes a seed layer 361, a first plating layer 362, and a second plating layer 363.
  • the seed layer 361 is in contact with the electrode 34 and the insulating layer 35 and contains Cu.
  • Seed layer 361 is formed, for example, by electroless plating.
  • the constituent material and formation method of the seed layer 361 are not limited.
  • seed layer 361 may be formed by a sputtering method.
  • the first plated layer 362 is laminated on the seed layer 361 and is made of, for example, Cu or a Cu alloy.
  • the first plating layer 362 is formed by electrolytic plating.
  • the constituent material of the first plating layer 362 is not limited.
  • the second plating layer 363 is laminated on the first plating layer 362 .
  • the second plating layer 363 is interposed between the first plating layer 362 and the bonding material 5 and functions to suppress the chemical reaction between the first plating layer 362 and the bonding material 5 .
  • the constituent material of the second plating layer 363 is not particularly limited, and a metal capable of suppressing a chemical reaction is appropriately selected, and examples thereof include Ni and Fe.
  • the first plating layer 362 contains Cu and the bonding material 5 contains Sn, so the second plating layer 363 is made of Ni, for example.
  • the second plating layer 363 is formed by electrolytic plating.
  • the constituent material and formation method of the second plating layer 363 are not limited.
  • Each electrode terminal 36 has a joint surface 365 .
  • the bonding surface 365 is a surface facing away from the electrode 34 (a surface facing the first main surface 101, the second main surface 211, and the third main surface 221), and is connected to the first main surface 365 via the bonding material 5. It is joined to the metal layer 6 formed on the surface 101 , the second principal surface 211 or the third principal surface 221 .
  • the multiple electrode terminals 36 include multiple electrode terminals 36A and multiple electrode terminals 36B. As shown in FIGS. 2 and 5, the plurality of electrode terminals 36A are arranged in the second region 302 of the element main surface 30a. Also, the plurality of electrode terminals 36B are arranged in the first region 301 of the element main surface 30a.
  • the plurality of electrode terminals 36A are electrically connected to the control circuit 322 of the semiconductor layer 32. Further, as shown in FIG. 3, one electrode terminal 36A is conductively connected to the first main surface 101 of the first lead 10A. The other two electrode terminals 36A are conductively connected to the third main surfaces 221 of the pair of third leads 22, respectively. The remaining electrode terminals 36A are conductively connected to the second main surfaces 211 of the plurality of second leads 21, respectively. As a result, the first lead 10A, the pair of third leads 22, and the plurality of second leads 21 are electrically connected to the control circuit 322.
  • the z-direction view shape (planar shape) of the electrode terminal 36A is circular, and the joint surface 365 (365A) of the electrode terminal 36A is also circular.
  • a diameter D1 (see FIG. 14) of the joint surface 365A is not particularly limited, but is, for example, 100 ⁇ m.
  • the plurality of electrode terminals 36B are electrically connected to the switching circuit 321 of the semiconductor layer 32. Also, the plurality of electrode terminals 36B are conductively connected to the first main surfaces 101 of the first leads 10A, 10B, and 10C. As a result, the first leads 10A, 10B and 10C are electrically connected to the switching circuit 321.
  • FIG. The z-direction view shape (planar shape) of the electrode terminal 36B is circular, and the joint surface 365 (365B) of the electrode terminal 36B is also circular.
  • a diameter D2 (see FIG. 15) of the joint surface 365B is not particularly limited, but is larger than the diameter D1, and is, for example, 150 ⁇ m.
  • the area S2 of the joint surface 365B is larger than the area S1 of the joint surface 365A.
  • the area S2 is preferably two to four times the area S1. Since the electrode terminal 36B carries a larger current than the electrode terminal 36A, the area S2 is made larger than the area S1.
  • each first main surface 101 of the first leads 10A, 10B, 10C, each second main surface 211 of the plurality of second leads 21, and each third main surface of the pair of third leads 22 221 are formed with one or more metal layers 6, respectively.
  • Each metal layer 6 is arranged according to the position of the electrode terminal 36 of the semiconductor element 30 .
  • Each metal layer 6, as shown in FIGS. It is interposed between any one of the third main surfaces 221 and the electrode terminal 36 , and the electrode terminal 36 is joined with the joining material 5 .
  • the metal layer 6 suppresses the chemical reaction between the first leads 10A, 10B, 10C, the second leads 21, and the third leads 22 and the bonding material 5, and also prevents the bonding material 5 from reacting with the bonding material 5 when the semiconductor element 30 is bonded. regulate the extent to which
  • the metal layer 6 has a first layer 61, a second layer 62 and a third layer 63, as shown in FIGS.
  • the first layer 61 is in contact with any one of the first main surface 101 of the first leads 10A, 10B, 10C, the second main surface 211 of the plurality of second leads 21, and the third main surface 221 of the third lead 22. are laminated together.
  • the first leads 10A, 10B, 10C, the plurality of second leads 21, and the third leads 22 contain Cu, and the bonding material 5 contains Sn, so the first layer 61 is made of Ni, for example. .
  • the second layer 62 is laminated in contact with the first layer 61 .
  • the constituent material of the second layer 62 is not particularly limited, and includes Pd, for example.
  • the third layer 63 is laminated in contact with the second layer 62 .
  • the third layer 63 is made of a constituent material having relatively good wettability with the bonding material 5 (solder).
  • a constituent material of the third layer 63 is not particularly limited, and includes Au, for example. Note that the method for forming the metal layer 6 is not limited.
  • the multiple metal layers 6 include multiple metal layers 6A and multiple metal layers 6B.
  • each metal layer 6A is arranged on each second main surface 211, each third main surface 221, and the first main surface 101 of the first lead 10A.
  • An electrode terminal 36A of the semiconductor element 30 is joined to each metal layer 6A.
  • the shape of each metal layer 6A as viewed in the z-direction is circular to match the shape of the joint surface 365A of the electrode terminal 36A.
  • the diameter D3 of the metal layer 6A is larger than the diameter D1 of the joint surface 365A.
  • the electrode terminal 36A (joint surface 365A) is included in the metal layer 6A when viewed in the z direction.
  • each metal layer 6B is arranged on each first main surface 101 of the first leads 10A, 10B, 10C. Electrode terminals 36B of the semiconductor element 30 are joined to each metal layer 6B.
  • the shape of each metal layer 6B as viewed in the z-direction is circular to match the shape of the joint surface 365B of the electrode terminal 36B.
  • diameter D4 of metal layer 6B is larger than diameter D2 of bonding surface 365B.
  • the electrode terminal 36B (joint surface 365B) is included in the metal layer 6B when viewed in the z direction.
  • the diameter D2 of the joint surface 365B is n (>1) times the diameter D1 of the joint surface 365A
  • the diameter D4 of the metal layer 6B is n times the diameter D3 of the metal layer 6A. That is, the ratio between the diameter D1 of the joint surface 365A and the diameter D2 of the joint surface 365B is the same as the ratio between the diameter D3 of the metal layer 6A and the diameter D4 of the metal layer 6B.
  • the area S2 of the joint surface 365B is n2 times the area S1 of the joint surface 365A
  • the area S4 of the metal layer 6B is n2 times the area S2 of the metal layer 6A.
  • the ratio between the area S1 of the bonding surface 365A and the area S2 of the bonding surface 365B is the same as the ratio between the area S3 of the metal layer 6A and the area S4 of the metal layer 6B.
  • the formation of the electrode terminals 36 and the metal layer 6 includes manufacturing errors.
  • the ratio of area S3 to area S4 is preferably equal to the ratio of area S1 to area S2, but considering these errors, it is within ⁇ 10% of the ratio of area S1 to area S2.
  • the difference between the diameter D4 of the metal layer 6B and the diameter D2 of the joint surface 365B is n times the difference between the diameter D3 of the metal layer 6A and the diameter D1 of the joint surface 365A. Therefore, the difference between the diameter D3 of the metal layer 6A and the diameter D1 of the joint surface 365A is smaller than the difference between the diameter D4 of the metal layer 6B and the diameter D2 of the joint surface 365B.
  • both the metal layers 6A and 6B and the joint surfaces 365A and 365B are circular, and the diameter of each is an example of the "representative length.”
  • the bonding material 5 has conductivity, is interposed between the electrode terminal 36 and the metal layer 6, and conducts them to each other.
  • the bonding material 5 is made of, for example, solder containing Sn (SnAg, etc.).
  • the constituent material of the bonding material 5 is not limited.
  • the multiple bonding materials 5 include multiple bonding materials 5A and multiple bonding materials 5B.
  • the bonding material 5A is interposed between the bonding surface 365A of the electrode terminal 36A and the metal layer 6A to bond them.
  • the shape of the bonding material 5A is a truncated cone shape in which the upper surface is in contact with the bonding surface 365A and the lower surface is in contact with the metal layer 6A.
  • the bonding material 5B is interposed between the bonding surface 365B of the electrode terminal 36B and the metal layer 6B to bond them.
  • the bonding material 5B has a truncated cone shape in which the upper surface is in contact with the bonding surface 365B and the lower surface is in contact with the metal layer 6B.
  • FIG. 16 to 18 are simplified diagrams for explaining a method of flip-chip bonding the semiconductor element 30 to the conductive member 1.
  • FIG. 16 to 18 are simplified diagrams for explaining a method of flip-chip bonding the semiconductor element 30 to the conductive member 1.
  • the electrode terminal 36A of the semiconductor element 30 has a bonding material 5A formed in advance by electrolytic plating in contact with the bonding surface 365A. Also, the electrode terminal 36B is preliminarily formed with a bonding material 5B that is in contact with the bonding surface 365B by electroplating. Since the joint surfaces 365A and 365B are circular, the joint materials 5A and 5B are cylindrical with a thickness t.
  • FIG. 17 shows a state in which the bonding materials 5A and 5B are melted by reflow.
  • the molten bonding materials 5A and 5B are hemispherical due to surface tension.
  • the semiconductor element 30 is brought close to the conductive member 1, the bonding material 5A is brought into contact with the metal layer 6A, and the bonding material 5B is brought into contact with the metal layer 6B.
  • the third layer 63 of the metal layers 6A and 6B has relatively good solder wettability. Therefore, as shown in FIG. 18, the bonding material 5A spreads over the entire surface of the metal layer 6A so as not to protrude from the metal layer 6A when viewed in the z direction. Also, the bonding material 5B spreads over the entire surface of the metal layer 6B so as not to protrude from the metal layer 6B when viewed in the z direction.
  • the bonding material 5A has a truncated cone shape in which the cross-sectional area perpendicular to the z-direction increases from the electrode terminal 36A toward the metal layer 6A in the z-direction.
  • the bonding material 5B has a truncated cone shape in which the cross-sectional area perpendicular to the z-direction increases from the electrode terminal 36B toward the metal layer 6B in the z-direction.
  • the bonding material 5A is solidified to bond the electrode terminal 36A and the metal layer 6A
  • the bonding material 5B is solidified to bond the electrode terminal 36B and the metal layer 6B.
  • the volume of the bonding material 5A in FIG. 16 is ⁇ (D1/2) 2 ⁇ t.
  • H2 3.D2.sup.2.t /( D2.sup.2 +D2.D4+ D4.sup.2 ) becomes.
  • the height H1 of the bonding material 5A and the height H2 of the bonding material 5B are equal.
  • 19 and 20 are diagrams for comparison with FIG. 18, and are for cases where the diameter D4 of the metal layer 6B is different from that of the semiconductor device A10.
  • FIG. 19 shows the case where the diameter D4 of the metal layer 6B is smaller than n ⁇ D3 and the difference between the diameter D4 and the diameter D2 is equal to the difference between the diameter D3 and the diameter D1.
  • the metal layer 6B restricts the wetting and spreading of the bonding material 5B, and the height H2 of the bonding material 5B becomes larger than that of the semiconductor device A10. Therefore, the height H2 of the bonding material 5B becomes larger than the height H1 of the bonding material 5A, and the semiconductor element 30 is tilted.
  • the inclination of the semiconductor element 30 cannot be prevented.
  • FIG. 20 shows the case where the diameter D4 of the metal layer 6B is larger than n ⁇ D3.
  • the height H2 of the bonding material 5B becomes smaller than that of the semiconductor device A10. Therefore, the height H2 of the bonding material 5B is smaller than the height H1 of the bonding material 5A, and the semiconductor element 30 is tilted.
  • the diameter of each metal layer 6 it is necessary to design the diameter of each metal layer 6 appropriately. Specifically, if the diameter D2 of the joint surface 365B is n times the diameter D1 of the joint surface 365A, the diameter D4 of the metal layer 6B must be n times the diameter D3 of the metal layer 6A. That is, it is necessary to match the ratio of the diameter D3 to the diameter D4 with the ratio of the diameter D1 to the diameter D2.
  • the ratio between the area S3 of the metal layer 6A and the area S4 of the metal layer 6B is the area S1 of the joint surface 365A and the area S1 of the joint surface 365B. It is also to match the ratio with S2.
  • the sealing resin 40 covers the entire semiconductor element 30 and part of each of the first leads 10A, 10B, 10C, the plurality of second leads 21 and the pair of third leads 22 .
  • Sealing resin 40 is made of a material containing, for example, black epoxy resin. Note that the material of the sealing resin 40 is not limited.
  • the sealing resin 40 has a rectangular shape when viewed in the z direction, and has a top surface 41, a bottom surface 42, a pair of first side surfaces 431, and a pair of second side surfaces 432, as shown in FIGS.
  • the top surface 41 faces the same side as the first major surfaces 101 of the first leads 10A, 10B, and 10C in the z direction.
  • the bottom surface 42 faces away from the top surface 41 .
  • the first rear surfaces 102 of the first leads 10A, 10B, and 10C, the second rear surfaces 212 of the plurality of second leads 21, and the third rear surfaces 222 of the pair of third leads 22 are arranged from the bottom surface 42. Exposed.
  • the pair of first side surfaces 431 are connected to both the top surface 41 and the bottom surface 42 and face the x direction.
  • the pair of first side surfaces 431 are separated from each other in the x direction. 6, 7, and 11 to 13, from each of the pair of first side surfaces 431, the first end surface 121 of the first leads 10A, 10B, and 10C and the fourth end surface 214 of the second lead 21 are arranged. , and the third end surface 223 of the third lead 22 are exposed so as to be flush with the first side surface 431 .
  • the pair of second side surfaces 432 are connected to all of the top surface 41, the bottom surface 42 and the pair of first side surfaces 431, and face the y direction.
  • the pair of second side surfaces 432 are separated from each other in the y direction.
  • the second end surfaces 213 of the plurality of second leads 21 are exposed from the second side surface 432 positioned on the y1 side in the y direction so as to be flush with the second side surface 432 .
  • a plurality of sub-end surfaces 131 of the first lead 10B are exposed from the second side surface 432 positioned on the y-direction y2 side so as to be flush with the second side surface 432 .
  • the metal layer 6 is formed on the conductive member 1 so as to match the positions of the electrode terminals 36 of the semiconductor element 30 .
  • Each electrode terminal 36 is joined to the conductive member 1 via the joining material 5 and the metal layer 6, respectively.
  • the bonding material 5 formed and melted on the bonding surface 365 of each electrode terminal 36 spreads over the entire surface of the metal layer 6 so as not to protrude from the metal layer 6 as viewed in the z direction. Since each metal layer 6 can adjust the thickness of each bonding material 5 by adjusting the range where the molten bonding material 5 spreads, the semiconductor device A10 can suppress the occurrence of inclination of the semiconductor element 30 with respect to the conductive member 1 .
  • the semiconductor device A10 can prevent the height H2 from becoming larger than the height H1.
  • the ratio between the area S1 of the joint surface 365A and the area S2 of the joint surface 365B is the same as the ratio between the area S3 of the metal layer 6A and the area S4 of the metal layer 6B. Therefore, as shown in FIGS. 16 to 18, the height H1 of the bonding material 5A and the height H2 of the bonding material 5B are equal. As a result, the semiconductor device A10 can suppress tilting of the semiconductor element 30 with respect to the conductive member 1 . Note that even if the ratio between the areas S1 and S2 and the ratio between the areas S3 and S4 do not completely match due to manufacturing errors, the ratio between the areas S3 and S4 will be the same as the areas S1 and S2. is within ⁇ 10%, it is possible to sufficiently suppress the occurrence of inclination of the semiconductor element 30 with respect to the conductive member 1 .
  • the plurality of electrode terminals 36A are arranged in the second region 302 located on the y-direction y1 side of the element main surface 30a, and the plurality of electrode terminals 36B are arranged in the y-direction y2 of the element main surface 30a. It is arranged in the first region 301 located on the side. Therefore, if there is a difference between the height H1 of the bonding material 5A that bonds the electrode terminal 36A and the height H2 of the bonding material 5B that bonds the electrode terminal 36B, the semiconductor element 30 is likely to tilt. In this embodiment, by appropriately adjusting the areas of the metal layers 6A and 6B, the height H1 and the height H2 can be made equal, so that the semiconductor device A10 can suppress the tilt of the semiconductor element 30 from occurring.
  • the semiconductor element 30 is mounted on the conductive member 1 by so-called flip-chip bonding. Therefore, the semiconductor device A10 can suppress the resistance of the conduction path and can be made low-profile compared to a semiconductor device in which each electrode 34 and each lead are electrically connected by wires. Furthermore, when the sealing resin 40 has the same external size in plan view, the semiconductor device A10 can mount a larger semiconductor element 30 than a semiconductor device that conducts with wires. Moreover, when the same semiconductor element 30 is mounted, the semiconductor device A10 can have a smaller outer shape of the sealing resin 40 than a semiconductor device that conducts with wires.
  • the present invention is not limited to this.
  • the number of layers of the metal layer 6 is not limited, nor is the material of each layer.
  • the semiconductor element 30 is an LSI has been described, but the present invention is not limited to this.
  • the type of semiconductor element 30 is not limited.
  • FIG. 21 is a diagram for explaining a semiconductor device A20 according to the second embodiment of the present disclosure.
  • FIG. 21 is a plan view showing the semiconductor device A20, corresponding to FIG. In FIG. 21 , for convenience of understanding, the encapsulating resin 40 and the semiconductor element 30 are shown through the outlines of the encapsulating resin 40 and the semiconductor element 30 by imaginary lines (two-dot chain lines).
  • FIG. 22 is a partially enlarged cross-sectional view showing the semiconductor device A20, corresponding to FIG. 23 is a partially enlarged cross-sectional view taken along line XXIII-XXIII of FIG. 22.
  • the semiconductor device A20 of this embodiment differs from that of the first embodiment in the shape of the electrode terminal 36B and the metal layer 6B. The configuration and operation of other portions of this embodiment are the same as those of the first embodiment.
  • each electrode terminal 36B is the same elliptical shape. Therefore, the joint surface 365B of each electrode terminal 36B also has the same elliptical shape.
  • the longitudinal direction (the direction of the major diameter) of the joint surface 365B of the electrode terminal 36B is perpendicular to the extending direction of the first leads 10A, 10C, 10B.
  • the relationship between the longitudinal direction of joint surface 365B and the direction in which first leads 10A, 10C, and 10B extend is not limited to this relationship.
  • the dimensions and the like of the joint surface 365B are not particularly limited, but to give an example, the major axis (dimension in the y direction) L1 (see FIG.
  • the area S2 of the joint surface 365B is larger than the area S1 of the joint surface 365A.
  • the area S2 is preferably two to four times the area S1.
  • each metal layer 6B as viewed in the z direction is also an elliptical shape in accordance with the shape of each bonding surface 365B.
  • the major axis (dimension in the y direction) L3 of the metal layer 6B is larger than the major axis L1 of the bonding surface 365B, and as shown in FIG. , larger than the minor axis L2 of the joint surface 365B.
  • the electrode terminal 36B (bonding surface 365B) is included in the metal layer 6B when viewed in the z direction.
  • the ratio between the area S1 of the bonding surface 365A and the area S2 of the bonding surface 365B is the same as the ratio between the area S3 of the metal layer 6A and the area S4 of the metal layer 6B.
  • the formation of the electrode terminals 36 and the metal layer 6 includes manufacturing errors.
  • the ratio of area S3 to area S4 is preferably equal to the ratio of area S1 to area S2, but considering these errors, it is within ⁇ 10% of the ratio of area S1 to area S2.
  • the ratio between the area S1 of the joint surface 365A and the area S2 of the joint surface 365B and the ratio between the area S3 of the metal layer 6A and the area S4 of the metal layer 6B are If the ratio is the same, the height H1 of the bonding material 5A and the height H2 of the bonding material 5B can be made equal.
  • the difference between the diameter D3 of the metal layer 6A and the diameter D1 of the joint surface 365A is smaller than the difference between the major axis L3 of the metal layer 6B and the major axis L1 of the joint surface 365B. Also, the difference between the diameter D3 of the metal layer 6A and the diameter D1 of the bonding surface 365A is smaller than the difference between the minor axis L4 of the metal layer 6B and the minor axis L2 of the bonding surface 365B.
  • the metal layer 6A and the joint surface 365A are circular, their respective diameters are an example of the "representative length.” Also, since the metal layer 6B and the joint surface 365B are elliptical, their major axis or minor axis is an example of the "representative length.”
  • the metal layer 6 is formed on the conductive member 1 so as to match the positions of the electrode terminals 36 of the semiconductor element 30 . Since each metal layer 6 can adjust the thickness of each bonding material 5 by adjusting the range where the molten bonding material 5 spreads, the semiconductor device A20 can suppress the occurrence of tilting of the semiconductor element 30 with respect to the conductive member 1 . Further, in this embodiment, the difference between the diameter D3 and the diameter D1 is smaller than the difference between the major axis L3 and the major axis L1, and smaller than the difference between the minor axis L4 and the minor axis L2. Therefore, the semiconductor device A20 can prevent the height H2 from becoming larger than the height H1.
  • the ratio between the area S1 and the area S2 is the same as the ratio between the area S3 and the area S4. Therefore, height H1 and height H2 are equal.
  • the semiconductor device A20 can suppress the inclination of the semiconductor element 30 with respect to the conductive member 1 . Moreover, the semiconductor device A20 has the same effect as the semiconductor device A10 due to the configuration common to the semiconductor device A10.
  • each electrode terminal 36 is circular or elliptical
  • the shape of the joint surface 365 of each electrode terminal 36 is not limited, and may be rectangular or polygonal.
  • the shape of the metal layer 6 is formed according to the shape of the joint surface 365 of the electrode terminal 36 to be joined. Also, the area of the metal layer 6 is set according to the area of the bonding surface 365 .
  • the ratio between the area S1 of the bonding surface 365A and the area S2 of the bonding surface 365B, the area S3 of the metal layer 6A and the area S4 of the metal layer 6B , the height H1 of the bonding material 5A and the height H2 of the bonding material 5B can be made equal.
  • the length of each side or diagonal line is an example of the "representative length.”
  • the difference in representative length is the difference in the representative length of the corresponding portions of the similar shape, for example, the difference in the lengths of corresponding sides or diagonals of the similar shapes of the joint surface 365 and the metal layer 6 .
  • FIG. 24 is a diagram for explaining a semiconductor device A30 according to the third embodiment of the present disclosure.
  • FIG. 24 is a partial plan view showing the semiconductor device A30, corresponding to FIG. In FIG. 24, for convenience of understanding, the outline of the semiconductor element 30 is shown by an imaginary line (double-dot chain line) through the encapsulation resin 40 and the semiconductor element 30 .
  • the semiconductor device A30 of this embodiment differs from that of the first embodiment in that the semiconductor element 30 is mounted on a wiring substrate instead of leads.
  • the configuration and operation of other portions of this embodiment are the same as those of the first embodiment. Note that each part of the above first and second embodiments may be combined arbitrarily.
  • the semiconductor element 30 is mounted on the first leads 10A, 10B, 10C, the plurality of second leads 21, and the pair of third leads 22, and the electrode terminals 36 are joined to these leads. I explained the case where However, the semiconductor element 30 may be joined to conductive members other than leads.
  • a semiconductor device A30 in which a semiconductor element 30 is mounted on a wiring board and electrode terminals 36 are joined to wirings of the wiring board will be described.
  • the semiconductor device A30 does not have the first leads 10A, 10B, 10C, the second lead 21 and the third lead 22, but has the wiring board 80 instead.
  • the wiring board 80 includes an insulating substrate 81 and a plurality of wirings 82 .
  • Insulating substrate 81 is a rectangular plate member made of an electrically insulating material such as glass epoxy resin or ceramic. The material and shape of insulating substrate 81 are not limited.
  • the wiring 82 is made of Cu, for example, and formed on the insulating substrate 81 . Note that the material and shape of the wiring 82 are not limited.
  • the semiconductor element 30 is flip-chip mounted with the element main surface 30 a facing the wiring board 80 .
  • Each electrode terminal 36A, 36B is joined to one of a plurality of wirings 82 of the wiring substrate 80.
  • One or more metal layers 6 are formed on each wiring 82 .
  • Each metal layer 6 is arranged according to the position of the electrode terminal 36 of the semiconductor element 30 .
  • Each metal layer 6 is interposed between one of the wirings 82 and the electrode terminal 36 , and the electrode terminal 36 is joined by the joining material 5 .
  • the metal layer 6 suppresses the chemical reaction between the wiring 82 and the bonding material 5 and regulates the range over which the bonding material 5 spreads when the semiconductor element 30 is bonded.
  • the multiple metal layers 6 include multiple metal layers 6A and multiple metal layers 6B.
  • An electrode terminal 36A of the semiconductor element 30 is joined to each metal layer 6A.
  • Electrode terminals 36B of the semiconductor element 30 are joined to each metal layer 6B.
  • the entire semiconductor element 30 and at least part of the wiring board 80 are covered with a sealing resin 40 (not shown in FIG. 24).
  • Other electronic components may be mounted on the wiring board 80, and leads for mounting the semiconductor device A30 on the wiring board may be joined.
  • the metal layer 6 is formed on each wiring 82 so as to match the positions of the electrode terminals 36 of the semiconductor element 30 . Since each metal layer 6 can adjust the thickness of each bonding material 5 by adjusting the range where the molten bonding material 5 spreads, the semiconductor device A30 can suppress the occurrence of inclination of the semiconductor element 30 with respect to the wiring board 80 . Also, in this embodiment, the difference between the diameter D3 and the diameter D1 is smaller than the difference between the diameter D4 and the diameter D2. Therefore, the semiconductor device A30 can prevent the height H2 from becoming larger than the height H1. Further, according to the present embodiment, the ratio between the area S1 and the area S2 is the same as the ratio between the area S3 and the area S4.
  • the semiconductor device A30 can suppress tilting of the semiconductor element 30 with respect to the conductive member 1 . Further, the semiconductor device A30 has the same effect as the semiconductor device A10 due to the configuration common to the semiconductor device A10.
  • the semiconductor device according to the present disclosure is not limited to the above-described embodiments.
  • the specific configuration of each part of the semiconductor device according to the present disclosure can be changed in various ways.
  • Appendix 1 It has an element main surface (30a) and an element back surface (30b) facing opposite sides in the thickness direction, and a first electrode terminal (36A) and a second electrode terminal (36B) arranged on the element main surface.
  • the first area (S1) of the first joint surface is smaller than the second area (S2) of the second joint surface, The difference between the representative length of the first metal layer and the corresponding representative length of the first bonding surface is less than the difference between the representative length of the second metal layer and the corresponding representative length of the second bonding surface, semiconductor Device.
  • Appendix 2 The ratio between the third area (S3) of the first metal layer and the fourth area (S4) of the second metal layer is within ⁇ 10% of the ratio between the first area and the second area. 1.
  • the semiconductor device according to Appendix 1. Appendix 3.
  • Appendix 4. 4.
  • the semiconductor device according to any one of appendices 1 to 4, wherein the first bonding surface and the first metal layer are circular, and the second bonding surface and the second metal layer are elliptical.
  • Appendix 6. First embodiment
  • the semiconductor device according to any one of appendices 1 to 4, wherein the first bonding surface and the first metal layer are circular, and the second bonding surface and the second metal layer are circular.
  • Appendix 7. (Fig. 14, Fig. 15)
  • the first metal layer and the second metal layer are a first layer (61) in contact with the conductive member and containing Ni; a second layer (62) in contact with the first layer and containing Pd; a third layer (63) in contact with the second layer and containing Au; 7.
  • Appendix 9. a first bonding material (5A) interposed between the first bonding surface and the first metal layer; a second bonding material (5B) interposed between the second bonding surface and the second metal layer; 9.
  • Appendix 10. The semiconductor device according to appendix 9, wherein the first bonding material and the second bonding material contain solder. Appendix 11.
  • the semiconductor element has a plurality of third electrode terminals having the same shape as the first electrode terminals and a plurality of fourth electrode terminals having the same shape as the second electrode terminals, In the main surface of the element, the first electrode terminal and the plurality of third electrode terminals are arranged on one side in a first direction perpendicular to the thickness direction, and the second electrode terminal and the plurality of fourth electrodes are arranged.
  • the semiconductor device according to any one of appendices 1 to 10, wherein the terminal is arranged on the other side in the first direction.
  • the conductive member includes a first lead (10A), 12.
  • the semiconductor device according to any one of Appendixes 1 to 11, wherein the first metal layer and the second metal layer are formed on the first lead.
  • Appendix 13 The conductive member includes first leads (10A, 10B, 10C) and second leads (21), the first metal layer is formed on the second lead; 12.
  • the semiconductor device according to any one of appendices 1 to 11, wherein the second metal layer is formed on the first lead.
  • Appendix 14. (Third embodiment, FIG. 24) further comprising an insulating substrate (81); 12.
  • the semiconductor device according to any one of appendices 1 to 11, wherein the conductive member is a wiring (82) formed on the insulating substrate.

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
PCT/JP2022/047329 2022-01-14 2022-12-22 半導体装置 Ceased WO2023136078A1 (ja)

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CN202280088260.1A CN118541783A (zh) 2022-01-14 2022-12-22 半导体装置
JP2023573944A JPWO2023136078A1 (https=) 2022-01-14 2022-12-22
US18/771,523 US20240363572A1 (en) 2022-01-14 2024-07-12 Semiconductor device

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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04268739A (ja) * 1991-02-25 1992-09-24 Matsushita Electron Corp 半導体装置の製造方法
JPH07263449A (ja) * 1994-03-18 1995-10-13 Hitachi Ltd 半導体装置及びその製法
JP2002524854A (ja) * 1998-09-01 2002-08-06 ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツング 電子構成素子を支持基板に結合するための方法ならびにこのような結合を検査するための方法
JP2004200194A (ja) * 2002-12-16 2004-07-15 Murata Mfg Co Ltd 表面実装部品の実装構造
JP2007059638A (ja) * 2005-08-25 2007-03-08 Nec Corp 半導体装置およびその製造方法
WO2021177034A1 (ja) * 2020-03-03 2021-09-10 ローム株式会社 半導体装置
WO2021193338A1 (ja) * 2020-03-26 2021-09-30 ローム株式会社 半導体装置

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7231382B2 (ja) 2018-11-06 2023-03-01 ローム株式会社 半導体装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04268739A (ja) * 1991-02-25 1992-09-24 Matsushita Electron Corp 半導体装置の製造方法
JPH07263449A (ja) * 1994-03-18 1995-10-13 Hitachi Ltd 半導体装置及びその製法
JP2002524854A (ja) * 1998-09-01 2002-08-06 ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツング 電子構成素子を支持基板に結合するための方法ならびにこのような結合を検査するための方法
JP2004200194A (ja) * 2002-12-16 2004-07-15 Murata Mfg Co Ltd 表面実装部品の実装構造
JP2007059638A (ja) * 2005-08-25 2007-03-08 Nec Corp 半導体装置およびその製造方法
WO2021177034A1 (ja) * 2020-03-03 2021-09-10 ローム株式会社 半導体装置
WO2021193338A1 (ja) * 2020-03-26 2021-09-30 ローム株式会社 半導体装置

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DE112022005983T5 (de) 2024-10-02

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