WO2023134045A1 - 信号线结构、信号线驱动方法以及信号线电路 - Google Patents

信号线结构、信号线驱动方法以及信号线电路 Download PDF

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Publication number
WO2023134045A1
WO2023134045A1 PCT/CN2022/087463 CN2022087463W WO2023134045A1 WO 2023134045 A1 WO2023134045 A1 WO 2023134045A1 CN 2022087463 W CN2022087463 W CN 2022087463W WO 2023134045 A1 WO2023134045 A1 WO 2023134045A1
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Prior art keywords
signal
driver
level
signal line
input
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PCT/CN2022/087463
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English (en)
French (fr)
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冀康灵
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长鑫存储技术有限公司
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Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to EP22728031.0A priority Critical patent/EP4236075A4/en
Priority to KR1020227026334A priority patent/KR20230110443A/ko
Priority to JP2022543705A priority patent/JP2024507421A/ja
Priority to US17/805,940 priority patent/US20230223053A1/en
Publication of WO2023134045A1 publication Critical patent/WO2023134045A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017509—Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements

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  • the present disclosure relates to the technical field of integrated circuit manufacturing, and in particular, to a signal line structure, a signal line driving method, and a signal line circuit.
  • the purpose of the present disclosure is to provide a signal line structure, a signal line driving method and a signal line circuit, which are used to improve the signal quality on the signal line at least to a certain extent, and save the layout area of parallel signal lines.
  • a signal line structure including: a plurality of parallel signal lines, each of which maintains a driving state at any moment.
  • a signal line driving method which is applied to any one of the above signal line structures, including: controlling a plurality of signal lines arranged in parallel to maintain a driving state at any moment.
  • a signal line circuit including: a first driver, an input end for receiving a first input signal, an enable end connected to a first node, and an output end connected to a signal line; a second driver, an input The terminal is used to receive the second input signal, the enabling terminal is connected to the second node, and the output terminal is connected to the signal line; the input terminal of the inverter is connected to the first node, the output terminal is connected to the second node, and the first node is connected to the output terminal.
  • a node is used to receive a driver enabling signal, the driver enabling signal includes a first level and a second level, and the first level is used to control the first driver to maintain a driving state, and the second driver to maintain In a high-impedance state, the second level is used to control the second driver to maintain a driving state, and the first driver maintains a high-impedance state.
  • FIG. 1 is a schematic diagram of a signal line structure in an exemplary embodiment of the present disclosure.
  • FIG. 2 is a schematic diagram of a driving manner of a signal line in an embodiment of the present disclosure.
  • FIG. 3A is a schematic diagram of crosstalk between two adjacent signal lines in the related art.
  • FIG. 3B is a schematic diagram of crosstalk between two adjacent signal lines in an embodiment of the present disclosure.
  • FIG. 4 is a schematic circuit diagram of a first driver and a second driver of a signal line in an embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram of a connection relationship between the first enable signal and the second enable signal shown in FIG. 4 in an embodiment of the present disclosure.
  • Fig. 6 is a schematic diagram of arrangement of signal lines in an embodiment of the present disclosure.
  • FIG. 7 is a timing diagram of signals corresponding to the arrangement of signal lines shown in FIG. 6 .
  • FIG. 8 is a schematic diagram of a signal line driving method in an embodiment of the present disclosure.
  • Fig. 9 is a schematic diagram of a signal line circuit provided by an exemplary embodiment of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concept of example embodiments to those skilled in the art.
  • the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
  • numerous specific details are provided in order to give a thorough understanding of embodiments of the present disclosure.
  • those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of the specific details being omitted, or other methods, components, devices, steps, etc. may be adopted.
  • well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure.
  • FIG. 1 is a schematic diagram of a signal line structure in an exemplary embodiment of the present disclosure.
  • the signal line structure 100 may include:
  • each signal line maintains a driving state at any moment.
  • FIG. 2 is a schematic diagram of a driving manner of a signal line in an embodiment of the present disclosure.
  • the two ends of the signal line S1 are respectively connected to the first driver 11 and the second driver 12, and at the same time, the first driver 11 and the second driver 12 of the signal line S1 There is one and only one that maintains the driving state.
  • the signal line S2 is adjacent to the signal line S1 in parallel, and the two ends of the signal line S2 are respectively connected to the first driver 21 and the second driver 22. At the same time, there is only one of the first driver 21 and the second driver 22 of the signal line S2. Maintain drive status.
  • the first driver 11 of the signal line S1 maintains the driving state when the first enable signal EN11 is at the first level, and maintains a high impedance when the first enable signal EN11 is at the second level. state; the second driver 12 maintains the driving state when the second enable signal EN12 is at the first level, and maintains the high-impedance state when the second enable signal EN12 is at the second level.
  • the first enable signal EN11 and the second enable signal EN12 are controlled by two levels
  • the first level is, for example, a high level
  • the second level is, for example, a low level.
  • the first level is, for example, a low level
  • the second level is, for example, a high level.
  • the high level is, for example, a state greater than or equal to the power supply voltage
  • the low level is, for example, a state less than or equal to the ground voltage.
  • high level and low level are relative terms, and the specific voltage range included needs to be determined according to specific devices.
  • the high level refers to the gate voltage range that can turn it on
  • the low level refers to the gate voltage range that can turn it off
  • Flat refers to the gate voltage range that enables it to be turned on
  • high level refers to the gate voltage range that enables it to be turned off.
  • the first driver 21 of the signal line S2 maintains the driving state when the first enable signal EN21 is at the first level, and maintains the high-impedance state when the first enable signal EN21 is at the second level; the second driver 22 at the second level The driving state is maintained when the second enable signal EN22 is at the first level, and the high-impedance state is maintained when the second enable signal EN22 is at the second level.
  • FIG. 3A is a schematic diagram of crosstalk between two adjacent signal lines in the related art.
  • FIG. 3B is a schematic diagram of crosstalk between two adjacent signal lines in an embodiment of the present disclosure.
  • the signal line S1 and the signal line S2 are two parallel adjacent signal lines.
  • the first enable signal corresponding to the signal line S1 is EN11, and the second enable signal is EN12; the first enable signal corresponding to the signal line S2 is EN21, and the second enable signal is EN22.
  • the first enable signal EN11 corresponding to the signal line S1 has a high-level pulse, and the signal line S1 is driven by the first driver 11 to appear the signal A.
  • the first driver 21 and the second driver 22 at both ends of the signal line S2 adjacent to and parallel to the line S1 are in a high-impedance state and have no driving capability for the signal line S2.
  • a crosstalk error EA occurs on the signal line S2.
  • the first enable signal EN21 corresponding to the signal line S2 has a high-level pulse, and the signal line S2 is driven by the first driver 21 to appear signal B.
  • crosstalk tends to occur between two parallel adjacent signal lines, resulting in errors in data transmission.
  • only one of the first enable signal EN11 and the second enable signal EN12 of the signal line S1 is at a high level at the same time, and the first enable signal of the signal line S2 is at a high level.
  • One and only one of the EN21 and the second enable signal EN22 is at a high level at the same time.
  • the first enable signal EN21 of the signal line S2 becomes high level
  • the first driver 21 of the signal line S2 becomes the driving state
  • data inversion occurs on the signal line S2 because the signal line S1 at this time
  • the first enable signal EN11 is also at a high level
  • the first driver 11 of the signal line S1 is also in a driving state
  • the data signal on the signal line S1 is less affected by crosstalk (point D).
  • the second enable signal EN12 of the signal line S1 becomes high level
  • the second driver 12 of the signal line S1 becomes a driving state
  • data inversion occurs on the signal line S2
  • the first enable signal EN21 is also at a high level
  • the first driver 21 of the signal line S2 is also in a driving state
  • the data signal on the signal line S2 is less affected by crosstalk (point E).
  • the data signals on the signal line S1 and the signal line S2 are less affected by crosstalk.
  • the signal on the signal line can be reduced from being affected by the data inversion crosstalk of parallel adjacent signal lines, and the signal can be kept stable. That is, using the method provided by the embodiments of the present disclosure to control the driver of the signal line can keep the signal stable without disposing isolation lines and state maintainers between the signal lines, which can greatly save the wiring area.
  • FIG. 4 is a schematic circuit diagram of a first driver and a second driver of a signal line in an embodiment of the present disclosure.
  • the first driver 11 or the second driver 12 of the signal line S1 includes at least one gated inverter.
  • the input terminal of the first gated inverter 111 in the first driver 11 is electrically connected to the first input signal IN11, the enable terminal is connected to the first enable signal EN11, and the output terminal is electrically connected to the signal Line S1.
  • the input terminal of the second gated inverter 121 in the second driver 12 is electrically connected to the second input signal IN12, the enable terminal is connected to the second enable signal EN12, and the output terminal is electrically connected to the signal line S1.
  • the first gated inverter 111 includes a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor M4 connected in sequence, wherein both the first transistor M1 and the second transistor M2 are P-type transistors, The source of the first transistor M1 is connected to the power supply voltage Vcc; the third transistor M3 and the fourth transistor M4 are both N-type transistors, and the source of the fourth transistor M4 is grounded.
  • the gates of the first transistor M1 and the fourth transistor M4 are connected to serve as an input terminal of the first gated inverter 111 and electrically connected to the first input signal IN1.
  • the gate of the second transistor M2 is connected to the output terminal of the inverter INV1, and the input terminal of the inverter INV1 is connected to the gate of the third transistor M3, and the gate of the third transistor M3 serves as the gate of the first gated inverter 111.
  • the enable terminal is connected to the first enable signal EN11.
  • the second gated inverter 121 includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8 connected in sequence, wherein both the fifth transistor M5 and the sixth transistor M6 are P-type transistors, The source of the fifth transistor M5 is connected to the power supply voltage Vcc; both the seventh transistor M7 and the eighth transistor M8 are N-type transistors, and the source of the eighth transistor M8 is grounded.
  • the gates of the fifth transistor M5 and the eighth transistor M8 are connected, and serve as an input terminal of the second gated inverter 121 , electrically connected to the first input signal IN1.
  • the gate of the sixth transistor M6 is connected to the output terminal of the inverter INV2, and the input terminal of the inverter INV2 is connected to the gate of the seventh transistor M7, and the gate of the seventh transistor M7 serves as the gate of the second gated inverter 121.
  • the enable terminal is connected to the second enable signal EN12.
  • both the second transistor M2 and the third transistor M3 in the first gated inverter 111 are turned on, the first gated inverter 111 is in a driving state, and the signal line S1
  • the signal on is changed with the first input signal IN11; when the first enable signal EN11 is at low level, both the second transistor M2 and the third transistor M3 in the first gate inverter 111 are turned off, and the first gate control
  • the inverter 111 is in a high-impedance state, and the signal on the signal line S1 does not change with the first input signal IN11.
  • both the sixth transistor M6 and the seventh transistor M7 in the second gated inverter 121 are turned on, and the second gated inverter 121 is in a driving state.
  • the signal on the signal line S1 changes with the second input signal IN12; when the second enable signal EN12 is at low level, both the sixth transistor M6 and the seventh transistor M7 in the second gated inverter 121 are turned off, and the second The two-gated inverter 121 is in a high-impedance state, and the signal on the signal line S1 does not change with the second input signal IN12.
  • the first enable signal EN11 and the second enable signal EN12 can be obtained by inverting the first enable signal EN11 through an inverter.
  • the number of gated inverters in the first driver 11 and the second driver 12 can be one or more, and FIG. 4 is only an example, and the present disclosure does not make a special limitation thereon.
  • FIG. 5 is a schematic diagram of a connection relationship between the first enable signal and the second enable signal shown in FIG. 4 in an embodiment of the present disclosure.
  • the input end of the first driver 11 is used to receive the first input signal IN11, the enable end is connected to the first node N1, the output end is connected to the signal line S1, and the second driver 11
  • the input end of 12 is used to receive the second input signal IN12, the enable end is connected to the second node N2, the output end is connected to the signal line S1, the first node N1 is used to receive the driver enable signal DRV, the second node N2 and the first node
  • the N1s are connected through an odd number of inverters INV0 (only one is shown in FIG. 5 ).
  • the driving enable signal DRV can control the first driver 11 and the second driver 12 to have one and only one maintaining driving state at the same time when the driving enable signal DRV is in the high level state or the low level state.
  • Fig. 6 is a schematic diagram of arrangement of signal lines in an embodiment of the present disclosure.
  • a plurality of parallel signal lines include odd data lines 61 and even data lines 62 arranged alternately, and the odd data lines 61 are used to transmit odd signals obtained according to odd clock sampling.
  • the even data line 62 is used to transmit the even signal obtained by sampling the even clock, and the phase difference between the odd clock and the even clock is 180 degrees.
  • the phases of the first enable signal EN11 corresponding to the odd data line 61 and the first enable signal EN21 corresponding to the even data line 62 are different, and the phases of the second enable signal EN12 corresponding to the odd data line 61 and the second enable signal EN12 corresponding to the even data line 62 are different.
  • the phases of the enable signal EN22 are different.
  • FIG. 7 is a timing diagram of signals corresponding to the arrangement of signal lines shown in FIG. 6 .
  • the transmission cycle of odd data and even data is T
  • the transmission interval of odd data and even data is T/2, that is, the phase difference between odd data and even data is 180 Spend.
  • the second enable signal EN12 corresponding to the odd data line 61 has a falling edge
  • the first driver 11 corresponding to the odd data line 61 becomes In the driving state
  • the second driver 12 becomes a high-impedance state
  • the signal on the odd data line 61 is controlled by the input signal of the first driver 11
  • the third moment T3 the second enable signal EN12 corresponding to the odd data line 61 appears
  • the rising edge occurs
  • the first enable signal EN11 corresponding to the odd data line 61 has a falling edge
  • the second driver 12 corresponding to the odd data line 61 becomes a driving state
  • the first driver 11 becomes a high-impedance state
  • the odd data line 61 The signal is controlled by the input signal of the second driver 12; at the second time T2, when the first enable signal EN21 corresponding to the even data line 62 has a rising edge, the second enable signal EN22 corresponding to the even data line 62 has a falling
  • the first enable signal EN11 corresponding to the odd data line 61 and the first enable signal EN21 corresponding to the even data line 62 have a phase difference of 180 degrees (T/2), and the second enable signal EN12 corresponding to the odd data line 61 and the even data line
  • the second enable signal EN22 corresponding to the line 62 has a phase difference of 180 degrees (T/2).
  • FIG. 8 is a schematic diagram of a signal line driving method in an embodiment of the present disclosure.
  • the signal line driving method 800 can be applied to the signal line structure shown in any one of the above embodiments.
  • the signal line driving method 800 may include: Step S10 , controlling multiple signal lines arranged in parallel to maintain a driving state at any moment.
  • a first driver and a second driver are respectively provided at both ends of each signal line, and controlling the signal lines arranged in parallel to maintain a driving state at any time includes: controlling the same signal line at the same time There is one and only one of the first drive and the second drive that maintains the drive state.
  • the first driver or the second driver includes at least one gated inverter, the input terminal of the gated inverter is electrically connected to the input signal, and the enable terminal is connected to the first enable signal or The second enabling signal, the output terminal is electrically connected to the signal line, and at the same time, the first driver and the second driver controlling the same signal line have one and only one maintenance driving state, including: inputting the first drive to the enabling terminal of the first driver at the same time A first enable signal of one level enables the first driver to maintain a driving state, and a second enable signal of a second level is input to the enable terminal of the second driver to maintain a high-impedance state of the second driver; or, At the same time, a first enable signal of a second level is input to the enable terminal of the first driver to maintain the first driver in a high-impedance state, and a second enable signal of the first level is input to the enable terminal of the second driver signal to maintain the driving state of the second driver.
  • the input terminal of the first driver is used to receive the first input signal
  • the enable terminal is connected to the first node
  • the output terminal is connected to the signal line
  • the input terminal of the second driver is used to receive the second
  • the input signal, the enable end is connected to the second node, the output end is connected to the signal line
  • the first node is used to receive the driver enable signal
  • the second node and the first node are connected through an odd number of inverters, and the second node is controlled at the same time.
  • a driver and a second driver have and have only one maintenance driving state including: responding to the arrival message of the first input signal, setting the driver enable signal to the first level, so that the first driver maintains the driving state, and the second driver maintains the high-impedance state ; Responding to the arrival message of the second input signal, setting the driver enable signal to the second level, so that the second driver maintains the driving state, and the first driver maintains the high-impedance state.
  • the first level is a high level
  • the second level is a low level.
  • a first driver and a second driver are respectively provided at both ends of each signal line, the plurality of signal lines include odd data lines and even data lines, and control the signal lines arranged in parallel at any time Maintaining the driving state includes: inputting a first enable signal of a first level to the first driver of the same odd data line, and inputting a second enable signal of a second level to the second driver so that the The odd data line maintains the driving state; or a first driver of the same odd data line is input with a first enable signal of a second level, and a second driver is input with a second enable signal of a first level so that The odd data line maintains a driving state; a first enable signal of a first level is input to the first driver of the same even data line, and a second enable signal of a second level is input to the second driver to Maintain the driving state of the even data line; or input the first enable signal of the second level to the first driver of the same even data line, and input the second enable signal of the first level
  • Fig. 9 is a schematic diagram of a signal line circuit provided by an exemplary embodiment of the present disclosure.
  • the signal line circuit 900 includes:
  • the first driver 91 the input end is used to receive the first input signal IN11, the enable end is connected to the first node N1, and the output end is connected to the signal line 90;
  • the second driver 92 the input terminal is used to receive the second input signal IN12, the enable terminal is connected to the second node N2, and the output terminal is connected to the signal line 90;
  • Inverter INV the input end is connected to the first node N1, the output end is connected to the second node N2, the first node is used to receive the driver enable signal DRV, the driver enable signal DRV includes a first level and a second level, the first The level is used to control the first driver 11 to maintain the driving state, and the second driver 12 to maintain the high-impedance state, and the second level is used to control the second driver 12 to maintain the driving state, and the first driver 11 to maintain the high-impedance state.
  • the signal line circuit 900 shown in FIG. 9 can ensure that the first driver 91 and the second driver 92 can maintain one and only one maintained driving state when the driver enable signal DRV is in a high level state or a low level state. Therefore, it is not necessary to provide an isolation track and a state maintainer for the signal line 90 , and the signal line 90 can also be prevented from being affected by level reversals on parallel adjacent signal lines. Thus, the signal line circuit 900 has a smaller wiring area.

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Abstract

一种信号线结构、信号线驱动方法以及信号线电路。信号线结构包括：多条平行的信号线（S1~Sn），每条信号线在任一时刻均维持驱动状态，可以保持信号高速、稳定传输的同时节省布线及相关电路的元件和面积。

Description

信号线结构、信号线驱动方法以及信号线电路
交叉引用
本公开要求于2022年1月11日提交的申请号为202210028112.2、名称为“信号线结构、信号线驱动方法以及信号线电路”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及集成电路制造技术领域，具体而言，涉及一种信号线结构、信号线驱动方法以及信号线电路。
背景技术
在通常的数据通路中，由于数据跳变的方向是随机的，平行相邻的不同信号线之间存在串扰，影响数据时序。在一些情况下，会插入接地的走线做隔离，以保证数据跳变时的时序一致性，此外，有时还需要设置状态保持器(keeper)来降低信号线间的串扰影响。隔离用的走线和状态保持器均会占用额外的线道和布局面积，导致信号线布局面积较大。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于提供一种信号线结构、信号线驱动方法以及信号线电路，用于至少在一定程度上改善信号线上的信号质量，节省平行信号线的布局面积。
根据本公开的第一方面，提供一种信号线结构，包括：多条平行的信号线，每条所述信号线在任一时刻均维持驱动状态。
根据本公开的第二方面，提供一种信号线驱动方法，应用于如上任一项所述的信号线结构，包括：控制平行设置的多条信号线在任一时刻均维持驱动状态。
根据本公开的第三方面，提供一种信号线电路，包括：第一驱动器，输入端用于接收第一输入信号，使能端连接第一节点，输出端连接信号线；第二驱动器，输入端用于接收第二输入信号，使能端连接第二节点，输出端连接所述信号线；反相器，输入端连接所述第一节点，输出端连接所述第二节点，所述第一节点用于接收驱动器使能信号，所述驱动器使能信号包括第一电平和第二电平，所述第一电平用于控制所述第一驱动器维持驱动状态、所述第二驱动器维持高阻状态，所述第二电平用于控制所述第二驱动器维持驱动状态，所述第一驱动器维持高阻状态。
本公开实施例通过设置信号线均维持在驱动状态，可以在并行设置多条信号线时，避免信号线间的串扰造成传输的数据发生错误，且无需设置隔离走线和状态保持器，可以极 大节省信号线的布局占用面积。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开示例性实施例中信号线结构的示意图。
图2是本公开一个实施例中信号线的驱动方式示意图。
图3A是相关技术中相邻两条信号线之间的串扰示意图。
图3B是本公开实施例中相邻两条信号线之间的串扰示意图。
图4是本公开一个实施例中信号线的第一驱动器和第二驱动器的电路示意图。
图5是本公开一个实施例中图4所示第一使能信号和第二使能信号的连接关系示意图。
图6是本公开一个实施例中信号线的设置示意图。
图7是图6所示信号线设置方式对应的信号时序图。
图8是本公开实施例中一种信号线驱动方法的示意图。
图9是本公开示例性实施例提供的一种信号线电路的示意图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施方式使得本公开将更加全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施方式中。在下面的描述中，提供许多具体细节从而给出对本公开的实施方式的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而省略所述特定细节中的一个或更多，或者可以采用其它的方法、组元、装置、步骤等。在其它情况下，不详细示出或描述公知技术方案以避免喧宾夺主而使得本公开的各方面变得模糊。
此外，附图仅为本公开的示意性图解，图中相同的附图标记表示相同或类似的部分，因而将省略对它们的重复描述。附图中所示的一些方框图是功能实体，不一定必须与物理或逻辑上独立的实体相对应。可以采用软件形式来实现这些功能实体，或在一个或多个硬件模块或集成电路中实现这些功能实体，或在不同网络和/或处理器装置和/或微控制器装置中实现这些功能实体。
下面结合附图对本公开示例实施方式进行详细说明。
图1是本公开示例性实施例中信号线结构的示意图。
参考图1，信号线结构100可以包括：
多条平行的信号线S1～Sn，每条信号线在任一时刻均维持驱动状态。
与相关技术相比，多条平行的信号线S1～Sn之间不用设置隔离线道，也无需在传输信号后设置状态保持器(keeper)，可以有效节省布线面积。由于每条信号线在任一时刻均维持驱动状态，平行信号线之间的串扰不会造成信号线的信号翻转，可以有效提高信号稳定程度，避免由于高密度布线导致的串扰增大、信号线上的信号翻转、传输出错。因此，本公开实施例可以在降低高密度布线面积的同时提高信号稳定性。
控制每条信号线在任一时刻均维持驱动状态可以有多种方式，下面通过附图说明一些实施例。
图2是本公开一个实施例中信号线的驱动方式示意图。
参考图2，在本公开的一个示例性实施例中，信号线S1的两端分别连接第一驱动器11和第二驱动器12，在同一时刻信号线S1的第一驱动器11和第二驱动器12中有且只有一个维持驱动状态。信号线S2与信号线S1平行相邻，信号线S2的两端分别连接第一驱动器21和第二驱动器22，在同一时刻信号线S2的第一驱动器21和第二驱动器22中有且只有一个维持驱动状态。
继续参考图2，在一个实施例中，信号线S1的第一驱动器11在第一使能信号EN11为第一电平时维持驱动状态，在第一使能信号EN11为第二电平时维持高阻状态；第二驱动器12在第二使能信号EN12为第一电平时维持驱动状态，在第二使能信号EN12为第二电平时维持高阻状态。在第一使能信号EN11、第二使能信号EN12通过两个电平控制时，第一电平例如为高电平，第二电平例如为低电平。或者，第一电平例如为低电平，第二电平例如为高电平。高电平例如为大于或等于电源电压的状态，低电平例如为小于或等于接地电压的状态。在这里，高电平和低电平是相对而言的，所包含的具体电压范围需要根据具体器件确定。例如，对于N型场效应管，高电平是指能够使其导通的栅极电压范围，低电平是指能够使其关断的栅极电压范围；对于P型场效应管，低电平是指能够使其导通的栅极电压范围，高电平是指能够使其关断的栅极电压范围。
对应的，信号线S2的第一驱动器21在第一使能信号EN21为第一电平时维持驱动状态，在第一使能信号EN21为第二电平时维持高阻状态；第二驱动器22在第二使能信号EN22为第一电平时维持驱动状态，在第二使能信号EN22为第二电平时维持高阻状态。
图3A是相关技术中相邻两条信号线之间的串扰示意图。
图3B是本公开实施例中相邻两条信号线之间的串扰示意图。
在图3A和图3B中，信号线S1和信号线S2为平行相邻的两条信号线。信号线S1对应的第一使能信号为EN11，第二使能信号为EN12；信号线S2对应的第一使能信号为EN21，第二使能信号为EN22。
参考图3A，在相关技术中，在第一时刻T1，信号线S1对应的第一使能信号EN11出现高电平脉冲，信号线S1受第一驱动器11的驱动出现信号A，同时，与信号线S1相邻平行的信号线S2两端的第一驱动器21和第二驱动器22都处于高阻状态，对信号线S2没有驱动能力，受信号A的影响，信号线S2上出现串扰错误EA。在第二时刻T2，信号线S2对应的第一使能信号EN21出现高电平脉冲，信号线S2受第一驱动器21的驱动出现信号B，与此同时，与信号线S2相邻平行的信号线S1两端的第一驱动器11和第二驱动器12都处于高阻状态，对信号线S1没有驱动能力，受信号B的影响，信号线S1上出现串扰错误EB。
同理，在第三时刻T3，当信号线S1对应的第二使能信号EN12出现高电平脉冲，信号线S1受第二驱动器12的驱动出现信号翻转(信号C)，影响信号线S2上信号B的状态，信号线S2上出现串扰错误EC。在第四时刻T4，当信号线S2对应的第二使能信号EN22出现高电平脉冲，信号线S2受第二驱动器22的驱动出现信号翻转，影响信号线S1上信号C的状态，同样出现串扰错误。
因此，在相关技术中，平行相邻的两条信号线之间容易出现串扰，导致数据传输出现错误。
参考图3B，在本公开实施例中，信号线S1的第一使能信号EN11和第二使能信号EN12在同一时刻有且仅有一个为高电平，信号线S2的第一使能信号EN21和第二使能信号EN22在同一时刻有且仅有一个为高电平。
在第二时刻T2，信号线S2的第一使能信号EN21变为高电平，信号线S2的第一驱动器21变为驱动状态，信号线S2上出现数据翻转，由于此时信号线S1的第一使能信号EN11也为高电平，信号线S1的第一驱动器11也为驱动状态，信号线S1上的数据信号受串扰影响较小(D点)。在第三时刻T3，信号线S1的第二使能信号EN12变为高电平，信号线S1的第二驱动器12变为驱动状态，信号线S2上出现数据翻转，由于此时信号线S2的第一使能信号EN21也为高电平，信号线S2的第一驱动器21也处于驱动状态，信号线S2上的数据信号受串扰影响较小(E点)。同理可推导，在第一时刻T1和第四时刻T4，信号线S1和信号线S2上的数据信号受串扰影响也较小。
因此，通过维持信号线两端的驱动器在任意时刻有且仅有一个维持驱动状态，可以减小信号线上的信号受到平行相邻的信号线的数据翻转串扰影响，维持信号稳定。即，使用本公开实施例提供的方法控制信号线的驱动器，无需在信号线之间设置隔离线道和状态维持器即可保持信号稳定，可以极大节省布线面积。
图4是本公开一个实施例中信号线的第一驱动器和第二驱动器的电路示意图。
参考图4，在本公开的一个实施例中，信号线S1的第一驱动器11或第二驱动器12包括至少一个门控反相器。
在图4所示实施例中，第一驱动器11中的第一门控反相器111的输入端电连接第一输入信号IN11，使能端连接第一使能信号EN11，输出端电连接信号线S1。第二驱动器 12中的第二门控反相器121的输入端电连接第二输入信号IN12，使能端连接第二使能信号EN12，输出端电连接信号线S1。
第一门控反相器111包括顺次通过连接的第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4，其中第一晶体管M1和第二晶体管M2均为P型晶体管，第一晶体管M1的源极连接电源电压Vcc；第三晶体管M3和第四晶体管M4均为N型晶体管，第四晶体管M4的源极接地。第一晶体管M1和第四晶体管M4的栅极相连，作为第一门控反相器111的输入端，电连接第一输入信号IN1。第二晶体管M2的栅极连接反相器INV1的输出端，反相器INV1的输入端与第三晶体管M3的栅极相连，第三晶体管M3的栅极作为第一门控反相器111的使能端，连接第一使能信号EN11。
第二门控反相器121包括顺次通过连接的第五晶体管M5、第六晶体管M6、第七晶体管M7、第八晶体管M8，其中第五晶体管M5和第六晶体管M6均为P型晶体管，第五晶体管M5的源极连接电源电压Vcc；第七晶体管M7和第八晶体管M8均为N型晶体管，第八晶体管M8的源极接地。第五晶体管M5和第八晶体管M8的栅极相连，作为第二门控反相器121的输入端，电连接第一输入信号IN1。第六晶体管M6的栅极连接反相器INV2的输出端，反相器INV2的输入端与第七晶体管M7的栅极相连，第七晶体管M7的栅极作为第二门控反相器121的使能端，连接第二使能信号EN12。
当第一使能信号EN11为高电平时，第一门控反相器111中的第二晶体管M2和第三晶体管M3均导通，第一门控反相器111呈驱动状态，信号线S1上的信号随第一输入信号IN11而变；当第一使能信号EN11为低电平时，第一门控反相器111中的第二晶体管M2和第三晶体管M3均截止，第一门控反相器111呈高阻状态，信号线S1上的信号不随第一输入信号IN11变化。
同理，当第二使能信号EN12为高电平时，第二门控反相器121中的第六晶体管M6和第七晶体管M7均导通，第二门控反相器121呈驱动状态，信号线S1上的信号随第二输入信号IN12而变；当第二使能信号EN12为低电平时，第二门控反相器121中的第六晶体管M6和第七晶体管M7均截止，第二门控反相器121呈高阻状态，信号线S1上的信号不随第二输入信号IN12变化。
当设置第一驱动器11和第二驱动器12在同一时刻有且仅有一个维持驱动状态时，可以设置第一使能信号EN11和第二使能信号EN12在同一时刻有且仅有一个为高电平，如图3B所示。在本公开的一个示例性实施例中，第二使能信号EN12可以由第一使能信号EN11经过反相器取反得到。
第一驱动器11和第二驱动器12中的门控反相器数量均可以为一个或多个，图4仅为示例，本公开对此不作特殊限制。
图5是本公开一个实施例中图4所示第一使能信号和第二使能信号的连接关系示意图。
参考图5，在本公开的一个示例性实施例中，第一驱动器11的输入端用于接收第一 输入信号IN11，使能端连接第一节点N1，输出端连接信号线S1，第二驱动器12的输入端用于接收第二输入信号IN12，使能端连接第二节点N2，输出端连接信号线S1，第一节点N1用于接收驱动器使能信号DRV，第二节点N2和第一节点N1之间通过奇数个反相器INV0(图5仅示出一个)连接。
在图5所示实施例中，驱动使能信号DRV在高电平状态或低电平状态时均能够控制第一驱动器11和第二驱动器12在同一时刻有且仅有一个维持驱动状态。
图6是本公开一个实施例中信号线的设置示意图。
参考图6，在本公开的一个示例性实施例中，多条平行的信号线包括交错设置的奇数据线61和偶数据线62，奇数据线61用于传输根据奇时钟采样得到的奇信号，偶数据线62用于传输根据偶时钟采样得到的偶信号，奇时钟和偶时钟的相位差为180度。奇数据线61对应的第一使能信号EN11和偶数据线62对应的第一使能信号EN21相位不同，奇数据线61对应的第二使能信号EN12和偶数据线62对应的第二使能信号EN22相位不同。
图7是图6所示信号线设置方式对应的信号时序图。
参考图7，在本公开的一个示例性实施例中，奇数据和偶数据的传输周期均为T，奇数据和偶数据的传输间隔为T/2，即奇数据和偶数据的相位相差180度。
在第一时刻T1，奇数据线61对应的第一使能信号EN11出现上升沿时，奇数据线61对应的第二使能信号EN12出现下降沿，奇数据线61对应的第一驱动器11变为驱动状态，第二驱动器12变为高阻状态，奇数据线61上的信号受第一驱动器11的输入信号控制；在第三时刻T3，奇数据线61对应的第二使能信号EN12出现上升沿时，奇数据线61对应的第一使能信号EN11出现下降沿，奇数据线61对应的第二驱动器12变为驱动状态，第一驱动器11变为高阻状态，奇数据线61上的信号受第二驱动器12的输入信号控制；在第二时刻T2，偶数据线62对应的第一使能信号EN21出现上升沿时，偶数据线62对应的第二使能信号EN22出现下降沿，偶数据线62对应的第一驱动器21变为驱动状态，第二驱动器22变为高阻状态，偶数据线62上的信号受第一驱动器21的输入信号控制；在第四时刻T4，偶数据线62对应的第二使能信号EN22出现上升沿时，偶数据线62对应的第一使能信号EN21出现下降沿，偶数据线62对应的第二驱动器22变为驱动状态，第一驱动器21变为高阻状态，偶数据线62上的信号受第二驱动器22的输入信号控制。
奇数据线61对应的第一使能信号EN11和偶数据线62对应的第一使能信号EN21相位相差180度(T/2)，奇数据线61对应的第二使能信号EN12和偶数据线62对应的第二使能信号EN22相位相差180度(T/2)。在同一时刻，奇数据线61对应的第一使能信号EN11和第二使能信号EN12有且仅有一个维持高电平；偶数据线62对应的第一使能信号EN21和第二使能信号EN22有且仅有一个维持高电平。
通过控制奇数据线61和偶数据线62在任意时刻均维持驱动状态，可以避免交替传输的奇数据和偶数据之间互相应影响，提高数据可靠性。
图8是本公开实施例中一种信号线驱动方法的示意图。
信号线驱动方法800可以应用于如上任一项实施例所示的信号线结构。
参考图8，信号线驱动方法800可以包括：步骤S10，控制平行设置的多条信号线在任一时刻均维持驱动状态。
在本公开的一个示例性实施例中，每条信号线两端分别设置有第一驱动器和第二驱动器，控制平行设置的信号线在任一时刻均维持驱动状态包括：在同一时刻控制同一信号线的第一驱动器和第二驱动器有且只有一个维持驱动状态。
在本公开的一个示例性实施例中，第一驱动器或第二驱动器包括至少一个门控反相器，门控反相器的输入端电连接输入信号，使能端连接第一使能信号或第二使能信号，输出端电连接信号线，在同一时刻控制同一信号线的第一驱动器和第二驱动器有且只有一个维持驱动状态包括：在同一时刻对第一驱动器的使能端输入第一电平的第一使能信号以使第一驱动器维持驱动状态，对第二驱动器的使能端输入第二电平的第二使能信号平以使第二驱动器维持高阻状态；或者，在同一时刻对第一驱动器的使能端输入第二电平的第一使能信号以使第一驱动器维持高阻状态，对第二驱动器的使能端输入第一电平的第二使能信号以使第二驱动器维持驱动状态。
在本公开的一个示例性实施例中，第一驱动器的输入端用于接收第一输入信号，使能端连接第一节点，输出端连接信号线，第二驱动器的输入端用于接收第二输入信号，使能端连接第二节点，输出端连接信号线，第一节点用于接收驱动器使能信号，第二节点和第一节点之间通过奇数个反相器连接，在同一时刻控制第一驱动器和第二驱动器有且只有一个维持驱动状态包括：响应第一输入信号到达消息，设置驱动器使能信号为第一电平，以使第一驱动器维持驱动状态，第二驱动器维持高阻状态；响应第二输入信号到达消息，设置驱动器使能信号为第二电平，以使第二驱动器维持驱动状态，第一驱动器维持高阻状态。在本公开的一个示例性实施例中，第一电平为高电平，第二电平为低电平。
在本公开的一个示例性实施例中，每条信号线两端分别设置有第一驱动器和第二驱动器，多条信号线包括奇数据线和偶数据线，控制平行设置的信号线在任一时刻均维持驱动状态包括：对同一条所述奇数据线的第一驱动器输入第一电平的第一使能信号，且对第二驱动器输入第二电平的第二使能信号以使所述奇数据线维持驱动状态；或对同一条所述奇数据线的第一驱动器输入第二电平的第一使能信号，且对第二驱动器输入第一电平的第二使能信号以使所述奇数据线维持驱动状态；对同一条所述偶数据线的第一驱动器输入第一电平的第一使能信号，且对第二驱动器输入第二电平的第二使能信号以使所述偶数据线维持驱动状态；或对同一条所述偶数据线的第一驱动器输入第二电平的第一使能信号，且对第二驱动器输入第一电平的第二使能信号以使所述偶数据线维持驱动状态；所述奇数据线对应的所述第一使能信号和所述偶数据线对应的所述第一使能信号相位不同，所述奇数据线对应的所述第二使能信号和所述偶数据线对应的所述第二使能信号相位不同。
信号驱动方法800的相关原理已经在图1～图7所示实施例中进行解释，本公开于此不再赘述。
图9是本公开示例性实施例提供的一种信号线电路的示意图。
参考图9，信号线电路900包括：
第一驱动器91，输入端用于接收第一输入信号IN11，使能端连接第一节点N1，输出端连接信号线90；
第二驱动器92，输入端用于接收第二输入信号IN12，使能端连接第二节点N2，输出端连接信号线90；
反相器INV，输入端连接第一节点N1，输出端连接第二节点N2，第一节点用于接收驱动器使能信号DRV，驱动器使能信号DRV包括第一电平和第二电平，第一电平用于控制第一驱动器11维持驱动状态、第二驱动器12维持高阻状态，第二电平用于控制第二驱动器12维持驱动状态，第一驱动器11维持高阻状态。
图9所示的信号线电路900可以确保驱动器使能信号DRV在高电平状态或低电平状态下，均能维持第一驱动器91和第二驱动器92有且仅有一个维持驱动状态。从而，无需为信号线90设置隔离线道和状态维持器，也能够避免信号线90受到平行相邻的信号线上电平翻转影响。从而，信号线电路900具有较小的布线面积。
应当注意，尽管在上文详细描述中提及了用于动作执行的设备的若干模块或者单元，但是这种划分并非强制性的。实际上，根据本公开的实施方式，上文描述的两个或更多模块或者单元的特征和功能可以在一个模块或者单元中具体化。反之，上文描述的一个模块或者单元的特征和功能可以进一步划分为由多个模块或者单元来具体化。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和构思由权利要求指出。
工业实用性
本公开实施例通过设置信号线均维持在驱动状态，可以在并行设置多条信号线时，避免信号线间的串扰造成传输的数据发生错误，且无需设置隔离走线和状态保持器，可以极大节省信号线的布局占用面积。

Claims (15)

  1. 一种信号线结构，其中，包括：
    多条平行的信号线，每条所述信号线在任一时刻均维持驱动状态。
  2. 如权利要求1所述的信号线结构，其中，每条所述信号线的两端分别连接第一驱动器和第二驱动器，在同一时刻同一所述信号线的所述第一驱动器和所述第二驱动器中有且只有一个维持驱动状态。
  3. 如权利要求2所述的信号线结构，其中，所述第一驱动器在第一使能信号为第一电平时维持驱动状态，在所述第一使能信号为第二电平时维持高阻状态；所述第二驱动器在第二使能信号为所述第一电平时维持驱动状态，在所述第二使能信号为所述第二电平时维持高阻状态。
  4. 如权利要求3所述的信号线结构，其中，所述第一电平为高电平，所述第二电平为低电平。
  5. 如权利要求3所述的信号线结构，其中，所述第二使能信号由所述第一使能信号经过反相器取反得到。
  6. 如权利要求3～5任一项所述的信号线结构，其中，所述第一驱动器或所述第二驱动器包括至少一个门控反相器，所述门控反相器的输入端电连接输入信号，使能端连接所述第一使能信号或所述第二使能信号，输出端电连接所述信号线。
  7. 如权利要求3所述的信号线结构，其中，所述多条平行的信号线包括交错设置的奇数据线和偶数据线，所述奇数据线用于传输根据奇时钟采样得到的奇信号，所述偶数据线用于传输根据偶时钟采样得到的偶信号，所述奇时钟和所述偶时钟的相位差为180度；所述奇数据线对应的所述第一使能信号和所述偶数据线对应的所述第一使能信号相位不同，所述奇数据线对应的所述第二使能信号和所述偶数据线对应的所述第二使能信号相位不同。
  8. 如权利要求7所述的信号线结构，其中，所述奇数据线对应的所述第一使能信号和所述偶数据线对应的所述第一使能信号相位相差180度，所述奇数据线对应的所述第二使能信号和所述偶数据线对应的所述第二使能信号相位相差180度。
  9. 一种信号线驱动方法，其中，应用于如权利要求1～8任一项所述的信号线结构，包括：
    控制平行设置的多条信号线在任一时刻均维持驱动状态。
  10. 如权利要求9所述的信号线驱动方法，其中，每条所述信号线两端分别设置有第一驱动器和第二驱动器，所述控制平行设置的信号线在任一时刻均维持驱动状态包括：
    在同一时刻控制同一所述信号线的所述第一驱动器和所述第二驱动器有且只有一个维持驱动状态。
  11. 如权利要求10所述的信号线驱动方法，其中，所述第一驱动器或所述第二驱动器 包括至少一个门控反相器，所述门控反相器的输入端电连接输入信号，使能端连接第一使能信号或第二使能信号，输出端电连接所述信号线，所述在同一时刻控制同一所述信号线的所述第一驱动器和所述第二驱动器有且只有一个维持驱动状态包括：
    在同一时刻对所述第一驱动器的使能端输入第一电平的第一使能信号以使所述第一驱动器维持驱动状态，对所述第二驱动器的使能端输入第二电平的第二使能信号平以使所述第二驱动器维持高阻状态；或者，在同一时刻对所述第一驱动器的使能端输入第二电平的第一使能信号以使所述第一驱动器维持高阻状态，对所述第二驱动器的使能端输入第一电平的第二使能信号以使所述第二驱动器维持驱动状态。
  12. 如权利要求10所述的信号线驱动方法，其中，所述第一驱动器的输入端用于接收第一输入信号，使能端连接第一节点，输出端连接所述信号线，所述第二驱动器的输入端用于接收第二输入信号，使能端连接第二节点，输出端连接所述信号线，所述第一节点用于接收驱动器使能信号，所述第二节点和所述第一节点之间通过奇数个反相器连接，所述在同一时刻控制所述第一驱动器和所述第二驱动器有且只有一个维持驱动状态包括：
    响应第一输入信号到达消息，设置所述驱动器使能信号为第一电平，以使所述第一驱动器维持驱动状态，所述第二驱动器维持高阻状态；
    响应第二输入信号到达消息，设置所述驱动器使能信号为第二电平，以使所述第二驱动器维持驱动状态，所述第一驱动器维持高阻状态。
  13. 如权利要求11或12所述的信号线驱动方法，其中，所述第一电平为高电平，所述第二电平为低电平。
  14. 如权利要求9所述的信号线驱动方法，其中，每条所述信号线两端分别设置有第一驱动器和第二驱动器，所述多条信号线包括奇数据线和偶数据线，所述控制平行设置的信号线在任一时刻均维持驱动状态包括：
    对同一条所述奇数据线的第一驱动器输入第一电平的第一使能信号，且对第二驱动器输入第二电平的第二使能信号以使所述奇数据线维持驱动状态；或对同一条所述奇数据线的第一驱动器输入第二电平的第一使能信号，且对第二驱动器输入第一电平的第二使能信号以使所述奇数据线维持驱动状态；
    对同一条所述偶数据线的第一驱动器输入第一电平的第一使能信号，且对第二驱动器输入第二电平的第二使能信号以使所述偶数据线维持驱动状态；或对同一条所述偶数据线的第一驱动器输入第二电平的第一使能信号，且对第二驱动器输入第一电平的第二使能信号以使所述偶数据线维持驱动状态；
    所述奇数据线对应的所述第一使能信号和所述偶数据线对应的所述第一使能信号相位不同，所述奇数据线对应的所述第二使能信号和所述偶数据线对应的所述第二使能信号相位不同。
  15. 一种信号线电路，其中，包括：
    第一驱动器，输入端用于接收第一输入信号，使能端连接第一节点，输出端连接信号 线；
    第二驱动器，输入端用于接收第二输入信号，使能端连接第二节点，输出端连接所述信号线；
    反相器，输入端连接所述第一节点，输出端连接所述第二节点，所述第一节点用于接收驱动器使能信号，所述驱动器使能信号包括第一电平和第二电平，所述第一电平用于控制所述第一驱动器维持驱动状态、所述第二驱动器维持高阻状态，所述第二电平用于控制所述第二驱动器维持驱动状态，所述第一驱动器维持高阻状态。
PCT/CN2022/087463 2022-01-11 2022-04-18 信号线结构、信号线驱动方法以及信号线电路 WO2023134045A1 (zh)

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JP2022543705A JP2024507421A (ja) 2022-01-11 2022-04-18 信号線構造、信号線駆動方法及び信号線回路
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