WO2023125202A1 - 一种半导体器件 - Google Patents

一种半导体器件 Download PDF

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Publication number
WO2023125202A1
WO2023125202A1 PCT/CN2022/140732 CN2022140732W WO2023125202A1 WO 2023125202 A1 WO2023125202 A1 WO 2023125202A1 CN 2022140732 W CN2022140732 W CN 2022140732W WO 2023125202 A1 WO2023125202 A1 WO 2023125202A1
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source
along
holes
semiconductor device
rows
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PCT/CN2022/140732
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English (en)
French (fr)
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张乃千
裴轶
孙琳琳
张新川
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苏州能讯高能半导体有限公司
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Publication of WO2023125202A1 publication Critical patent/WO2023125202A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/4175—Source or drain electrodes for field effect devices for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET

Definitions

  • Embodiments of the present invention relate to the technical field of microelectronics, and in particular, to a semiconductor device.
  • Gallium nitride a semiconductor material
  • gallium nitride materials are more suitable for manufacturing high-temperature, high-frequency, high-voltage and high-power semiconductor devices than silicon and gallium arsenide, so gallium nitride-based electronic devices have good application prospects, such as for the preparation of Gallium nitride (GaN) high electron mobility transistor (High Electron Mobility Transistor, HEMT) device.
  • GaN Gallium nitride
  • HEMT High Electron Mobility Transistor
  • a GaN HEMT device is a field-effect transistor that uses two materials with different energy gaps (such as AlGaN/GaN) to form a heterojunction to provide a channel for carriers.
  • two materials with different energy gaps such as AlGaN/GaN
  • a large amount of heat will be generated, which will increase the junction temperature of the device. If the generated heat cannot be dissipated, the junction temperature of the device will become higher and higher. If the maximum junction temperature that can be tolerated is exceeded, the device will be burned.
  • GaN HEMT devices are often designed with a multi-gate structure. Since the heat dissipation rate in the central region of the device is lower than that in the edge region, the junction temperature in the central region is often the highest. If effective heat dissipation is not obtained, the device will burn out in advance, while Increasing the area of the heat dissipation area in the central area will affect the radio frequency characteristics of the device. Therefore, how to ensure the radio frequency characteristics of the semiconductor device while enhancing the heat dissipation capability of the central region of the semiconductor device is an urgent problem to be solved.
  • An embodiment of the present invention provides a semiconductor device to ensure the radio frequency characteristics of the semiconductor device while enhancing the heat dissipation capability of the central region of the semiconductor device.
  • a semiconductor device comprising: an active region and a non-active region surrounding the active region;
  • Semiconductor devices also include:
  • a plurality of sources, a plurality of gates and a plurality of drains are located on the side of the multilayer semiconductor layer away from the substrate and in the active region; in the active region, the sources, gates and drains are arranged along the first The directions are arranged alternately, along the first direction, including two sources closest to the ends of the arrangement, and any gate is located between a source and a drain; the first direction is parallel to the plane where the substrate is located;
  • the length of at least the source electrode located in the center along the first direction is greater than the length of the source electrodes located at both ends along the first direction;
  • the electrode located in the center of the arrangement is the drain
  • At least the two sources closest to the drain have lengths along the first direction greater than the lengths of the sources located at both ends along the first direction, and b rows of through holes are correspondingly provided.
  • the electrode located in the center of the arrangement is the source
  • At least the length of the source electrode along the first direction is greater than the length of the source electrodes at both ends along the first direction, and b rows of through holes are correspondingly provided.
  • the number of through hole rows corresponding to each source is a or b.
  • the number of rows of through holes corresponding to the source near the center of the arrangement is greater than or equal to the number of rows of through holes corresponding to the source far away from the center of the arrangement.
  • the mth source is correspondingly provided with b rows of through holes
  • the length Y m of the mth source electrode along the first direction satisfies Y m ⁇ 3Y h + 2Y c ;
  • Y h is the length of the through hole along the first direction
  • Y c is the distance between the source electrode at both ends and the opposite edge of the through hole in the first direction
  • m is a positive integer greater than 1.
  • the distance L between the two rows of through holes corresponding to the same source in the first direction satisfies L ⁇ Y h ;
  • Y h is the length of the through hole along the first direction.
  • the distance H in the first direction between the source electrode and the opposite edge of the via hole between the source electrodes located at both ends satisfies Y c ⁇ H ⁇ Y h +Y c ;
  • Y h is the length of the through hole along the first direction
  • Y c is the distance between the source electrode at both ends and the opposite edge of the through hole in the first direction.
  • the number of through holes in each row of through holes is equal.
  • a line connecting geometric centers of through holes with the same number of digits is parallel to the first direction.
  • At least the length of the source electrode located in the center along the first direction is greater than the length of the source electrodes located at both ends along the first direction, so that the area of the source electrode located in the center is larger than the area of the source electrodes located at both ends, thereby increasing the The area of the heat dissipation area in the central area of the semiconductor device is increased, and the heat dissipation capacity of the central area of the semiconductor device is improved; at the same time, by setting at least the number of rows of through holes corresponding to the source located at the center is the number of rows of via holes corresponding to the sources located at both ends 2 times that of the device, which can take into account the heat dissipation of the device and at the same time make the current flow path of the central device similar to that of the edge device, improve the symmetry of the overall current flow path, and ensure the radio frequency characteristics of the semiconductor device.
  • FIG. 1 is a schematic cross-sectional structure diagram of a semiconductor device provided by an embodiment of the present invention
  • FIG. 2 is a schematic top view of a semiconductor device provided by an embodiment of the present invention.
  • Fig. 3 is a partial top view structural schematic diagram of a semiconductor device provided by an embodiment of the present invention.
  • FIG. 4 is a partial top view structural diagram of another semiconductor device provided by an embodiment of the present invention.
  • An embodiment of the present invention provides a semiconductor device, including an active region and a non-active region surrounding the active region; the semiconductor device also includes a substrate, multiple semiconductor layers, multiple sources, multiple gates, and multiple drains Pole, the multilayer semiconductor layer is located on one side of the substrate; multiple sources, multiple gates and multiple drains are located on the side of the multilayer semiconductor layer away from the substrate and in the active region; in the active region Inside, the source, gate and drain are arranged alternately along the first direction, including two sources closest to the end of the arrangement along the first direction, and any gate is located between a source and a drain; The first direction is parallel to the plane where the substrate is located; along the first direction, the length of at least the source electrode located in the center along the first direction is greater than the length of the source electrodes located at both ends along the first direction; the semiconductor device also includes a through substrate and a multilayer Multiple rows of through holes in the semiconductor layer; multiple rows of through holes are arranged along the first direction, and the orthographic projection of the source on the substrate overlaps with the
  • Figure 1 is a schematic cross-sectional structure diagram of a semiconductor device provided by an embodiment of the present invention
  • Figure 2 is a schematic top view of a semiconductor device provided by an embodiment of the present invention, see Figures 1 and 2, the semiconductor device provided by an embodiment of the present invention
  • the device 100 includes an active region aa and a non-active region na surrounding the active region aa; the semiconductor device 100 also includes a substrate 10, a multilayer semiconductor layer 20, and a plurality of source electrodes 30 (the numbers after 30 in the figure only represent numbering ), a plurality of gates 40 (numbers after 40 in the figure only represent numbering) and multiple drains 50 (numbers after 50 in the figure only represent numbering), and the multilayer semiconductor layer 20 is located on one side of the substrate 10; A source 30, a plurality of gates 40, and a plurality of drains 50 are located on the side of the multilayer semiconductor layer 20 away from the substrate 10 and in the active region aa; in the active region aa, the source 30, the gate 40
  • the semiconductor device 100 also includes multiple rows of through holes 60 penetrating through the substrate 10 and the multilayer semiconductor layer 20; the multiple rows of through holes 60 are arranged along the first direction y , the orthographic projection of the source 30 on the substrate 10 overlaps the orthographic projection of the through hole 60 on the substrate 10; along the first direction y, the sources at both ends (such as the source 30-1 and the source 30- 3)
  • the semiconductor device provided by the embodiment of the present invention is designed as a multi-gate structure. 1 and 2, in the active region aa, the source 30, the gate 40 and the drain 50 are alternately arranged along the first direction y, and, along the first direction y, any gate 40 is located at one Between the source 30 and a drain 50 , and between any two adjacent gates 40 includes a source 30 or a drain 50 .
  • the arrangement sequence of the source 30, the gate 40 and the drain 50 may be source 30, gate 40, drain 50, gate 40, source 30...source 30, Or it may also be the drain 50 , the gate 40 , the source 30 , the gate 40 , the drain 50 . . . the drain 50 .
  • Figure 1 illustrates the first arrangement as an example. At this time, the two electrodes located at the end of the arrangement are source electrodes 30, and for the second arrangement, the two electrodes located at the end of the arrangement are drain electrodes 50. .
  • the semiconductor device 100 further includes a gate bonding pad 70, a drain bonding pad 80, and multiple rows of through holes 60.
  • the gate bonding pad 70 is located on the multilayer semiconductor layer 20 away from the substrate 10-
  • a plurality of gates 40 are electrically connected to the gate bonding pad 70
  • the drain bonding pad 80 is located in the non-active region na on the side of the multilayer semiconductor layer 20 away from the substrate 10
  • a plurality of drains 50 are electrically connected to the drain bonding pad 80
  • the through hole 60 runs through the substrate 10 and the multilayer semiconductor layer 20, and the orthographic projection of the source 30 on the substrate 10 is the same as that of the through hole 60 on the substrate.
  • the orthographic projections on 10 overlap so that source 30 can be grounded through via 60 .
  • the plurality of gates 40 have equal lengths along the second direction x
  • the plurality of sources 30 have equal lengths along the second direction x
  • the plurality of drains 50 have equal lengths along the second direction x.
  • the second direction x intersects the first direction y and is parallel to the plane where the substrate 10 is located.
  • each row of through holes only needs to include at least one through hole 60 , and the embodiment of the present invention does not limit the number of through holes in a row of through holes.
  • FIG. 2 only shows that the orthographic projection of the source electrode 30 on the substrate 10 covers the orthographic projection of the corresponding through hole 60 on the substrate 10. This structure is not limited, as long as the source electrode 30 is guaranteed to correspond to it.
  • the orthographic projections of the through holes 60 on the substrate 10 overlap.
  • the orthographic projections of the through holes 60 on the source along the second direction x that are close to the edge of the source 30 can extend beyond the edge of the source.
  • the gate 40 is negatively biased, the drain 50 is forward biased, and the source 30 is at zero potential (ground).
  • the semiconductor device when the semiconductor device is in operation, current flows from any drain 50 through the gate 40 on both sides of the drain 50 to the source 30 on both sides of the drain 50 , and then grounded through the through hole 60 .
  • the current flows from the drain 50-1 to the source 30-1 through the gate 40-1, and flows to the source 30-2 through the gate 40-2; at the same time, the current flows from the drain 50-2 through the gate 40-3 flows to the source 30-2, and flows to the source 30-3 through the gate 40-4.
  • the area near the gate 40 is the main area where the device generates heat.
  • the heat dissipation of the device is mainly limited by the distance between adjacent gates 40 along the first direction y. It can be understood that the smaller the distance between the gates 40, the slower the heat dissipation.
  • the source 30 is used as a heat dissipation area, by setting at least the source located in the center (such as the source 30-2) to have a longer length along the first direction y than the sources located at both ends (such as the source 30-1 and the source 30-1) 30-3)
  • the length along the first direction y can increase the distance between the grids in the center of the device (such as the grid 40-2 and the grid 40-3), increase the area of the heat dissipation area in the center of the device, and improve the center of the device.
  • the cooling capacity of the area can be used as a heat dissipation area, by setting at least the source located in the center (such as the source 30-2) to have a longer length along the first direction y than the sources located at both ends (such as the source 30-1 and the source 30-1) 30-3)
  • the length along the first direction y can increase the distance between the grids in the center of the device (such as the grid 40-2 and the grid 40-3), increase the area of the heat dissipation area in the center
  • a plurality of sources 30, a plurality of gates 40 and a plurality of drains 50 are arranged along the first direction y, wherein "a source located in the center” can be understood as being the closest to the arrangement center among the plurality of sources source, and "the source at both ends” means the two sources closest to the ends of the arrangement.
  • the electrodes at the ends of the arrangement can be selected as the source.
  • the sources at both ends are For the two source electrodes located at the end of the arrangement, the following descriptions will be made by taking the electrode at the end of the arrangement as the source electrode as an example. Referring to FIG.
  • a plurality of source electrodes 30, a plurality of gate electrodes 40 and a plurality of drain electrodes 50 may be uniformly and symmetrically distributed along the first direction y in the active region aa, and the plurality of electrodes (i.e. The central point of the electrode (such as the source 30-2) in the center of the arrangement of the source 30, the gate 40 and the drain 50) passes through the central axis X of the active region aa.
  • the "source at the center” can be It is understood as the source closest to the central axis X of the active region aa, wherein the central axis X is perpendicular to the first direction y and passes through the midpoint of the active region aa along the first direction y.
  • the semiconductor device shown in FIG. 1 Exemplarily, in the semiconductor device shown in FIG.
  • three sources are provided in the active region aa, which are source 30-1, source 30-2 and source 30-3, wherein the source 30-1 and the source 30-3 are located at both ends of the active region aa, the source 30-2 is located at the center of the active region aa, and the length of the source 30-2 along the first direction y is greater than that of the source 30-1 and the source 30 -3 The length along the first direction y, so that the area of the heat dissipation area in the center of the device is increased, and the heat dissipation capability of the center area of the device is improved.
  • the arrangement of the number of through hole rows in the arrangement center and the arrangement edge area is generally the same.
  • the length of the source in the center increases along the first direction y, if the source is still provided with the same number of through holes, on the one hand, it will cause the length of the current flow path (the length from the drain to the through hole) to increase, thereby increasing the source.
  • Electrode resistance which affects the radio frequency characteristics of semiconductor devices, such as reducing the key electrical characteristics of the device such as the highest oscillation frequency; Asymmetry will also have a greater impact on the radio frequency characteristics of semiconductor devices.
  • this embodiment increases the length of the source 30 located in the center along the first direction y, and designs the source 30 located in the center.
  • the number b of the through-hole rows is twice the number a of the through-hole rows corresponding to the source electrodes 30 located at both ends, and the through-hole relationship between the end of the arrangement and the center of the arrangement is set so that the current flow path of the center device and the current flow of the edge device The path is approximate, shortening the length of the current flow path, improving the symmetry of the overall current flow path, and ensuring that the device has good radio frequency characteristics.
  • the length of the source electrode 30-2 located in the center increases along the first direction y, and at the same time, the source electrode 30-2 is provided with two rows of through holes 60 correspondingly, and the source electrodes 30-1 located at both ends A row of through holes 60 is provided corresponding to the source electrode 30 - 2 .
  • the current flow path from the drain 50-1 to the source 30-2 is the distance from the drain 50-1 to the through hole 60 closest to the drain 50-1 in the source 30-2, so that the current flow path can be shortened , at the same time, the symmetry of the current flow path from the drain 50-1 to the source 30-1 and the source 30-2 can be improved.
  • the current flow path also has high symmetry, which can ensure that the semiconductor device has good radio frequency characteristics.
  • FIG. 2 only illustrates an example of setting three source electrodes in the active region aa. It can be understood that the number of source electrodes may be greater than three.
  • the length of the source electrode located in the center along the first direction y is the largest, and the length of the source electrode closer to both ends is shorter along the first direction y, so that while improving the heat dissipation capability of the central region of the device, The area of part of the active area aa is saved, so that the area utilization rate of the active area aa is kept high.
  • the current flow path can be shortened, the symmetry of the current flow path can be improved, and the radio frequency characteristics of the semiconductor device can be guaranteed, while avoiding setting too many through holes. Affects the heat dissipation capability of the device.
  • each row of through holes includes at least one through hole 60; the number of through holes in each row of through holes is equal.
  • FIG. 2 only illustrates that each row of through holes includes two through holes 60 as an example.
  • the line connecting the geometric centers of the through holes with the same number of digits is parallel to the first direction y.
  • the semiconductor device can have a high degree of symmetry, thereby ensuring that the semiconductor device has good radio frequency characteristics.
  • the substrate 10 may be one or more of gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, indium phosphide, gallium arsenide, silicon carbide, diamond, sapphire, germanium, silicon species, or any other material capable of growing III-nitrides.
  • the multi-layer semiconductor layer 20 may include a III-V compound based semiconductor material.
  • the multi-layer semiconductor layer 20 may sequentially include a nucleation layer, a buffer layer, a channel layer and a barrier layer from the direction of the substrate 10 .
  • the channel layer and the upper barrier layer together form a heterojunction structure, and the channel layer provides a channel for two-dimensional electron gas movement.
  • the nucleation layer affects parameters such as crystal quality, surface morphology, and electrical properties of the heterojunction material above.
  • the nucleation layer varies with different substrate 10 materials, and mainly plays a role in matching the substrate 10 material and the semiconductor material layer in the heterojunction structure.
  • the buffer layer plays the role of bonding the semiconductor material layer to be grown next, and can protect the material of the substrate 10 from being invaded by some metal ions.
  • the material of the buffer layer may be group III nitride materials such as AlGaN, GaN or AlGaInN.
  • the buffer layer is a gallium nitride layer (Al)GaN with controllable aluminum content.
  • At least the length of the source electrode located in the center along the first direction is greater than the length of the source electrodes located at both ends along the first direction, so that the area of the source electrode located in the center is larger than the area of the source electrodes located at both ends, thereby increasing the The area of the heat dissipation area in the central area of the semiconductor device is increased, and the heat dissipation capacity of the central area of the semiconductor device is improved; at the same time, by setting at least the number of rows of through holes corresponding to the source located at the center is the number of rows of via holes corresponding to the sources located at both ends 2 times that of the source electrode in the center, when the length of the central source along the first direction is increased, the distance between the through hole and the adjacent gate can be kept short, thereby ensuring a short current flow path and ensuring the radio frequency of the semiconductor device characteristic.
  • the number of the source 30, the gate 40 and the drain 50 in the active region aa can be set according to actual needs, and it can be known according to the arrangement of the source 30, the gate 40 and the drain 50, Along the first direction, the electrode located in the center of the arrangement may be the source electrode 30 or the drain electrode 50 .
  • the electrode located in the center of the arrangement is the source (such as the source 30-2) along the first direction y
  • at least the length of the source (30-2) along the first direction y is optionally greater than
  • the source electrodes located at both ends are along the length of the first direction y, and are provided with b rows of through holes 60 correspondingly.
  • FIG. 3 is a partial top view structural diagram of a semiconductor device provided by an embodiment of the present invention, only showing the structure in the active region aa.
  • the electrode located at the center of the arrangement is the drain along the first direction y
  • it is optional that at least the two sources closest to the drain have a length along the first direction y greater than that of the sources located at both ends along the first direction.
  • the length in the direction y, and the b row of through holes 60 are correspondingly provided.
  • the source 30-2 and the source 30-3 are closest to the drain 50-2 in the center of the arrangement, and the length of the two along the first direction y is longer than that of the source 30-1 and the source 30- 4 along the length of the first direction y, and b rows of through holes 60 are correspondingly provided.
  • the optional mth source is correspondingly provided with a b row of through holes 60 .
  • the source is provided with row b of via holes, and the other sources are provided with row a of via holes;
  • the number of through holes on both sides of the central axis X is the same from the sources at the two ends of the arrangement toward the center; wherein, Y h is the length of the through hole 60 along the first direction y , Y c is the distance in the first direction y between the opposite edges of the source electrode 30 and the through hole 60 located at both ends; m is a positive integer greater than 1.
  • the length of each source electrode 30 along the first direction y can be adaptively designed according to the heat dissipation requirements of the region where it is located.
  • the source corresponds to the b row of through holes 60
  • the other sources are when Y m ⁇ 3Y h + 2Y c .
  • a row of through holes is provided.
  • the sources on both sides of the central axis X are arranged symmetrically with respect to the central axis X, and the length of each source along the first direction y is also symmetrical with respect to the central axis X.
  • the through holes on the side are arranged symmetrically with respect to the central axis X; to ensure that the distance between the through holes on each source of the entire device and the adjacent gate is kept as short as possible, and the current flow path of each device is as similar as possible, Furthermore, it is ensured that the current flow paths of all the overall devices are relatively short, so as to prevent the radio frequency characteristics of the semiconductor device from being affected when the size of the source electrode along the first direction y is large.
  • the second source 30-2 and the third source 30-3 are provided with two rows of through holes 60, and the lengths Y 2 and Y 3 of the two in the first direction y need to satisfy The above requirements, namely Y 2 ⁇ 3Y h + 2Y c , Y 3 ⁇ 3Y h + 2Y c , need to be met.
  • the lengths of the first source 30-2 and the fourth source 30-3 in the first direction y are less than 3Y h + 2Y c , the first source 30-2 and the fourth source 30-3
  • the four source electrodes 30-3 are thus provided with a row of through holes.
  • Y c is the distance in the first direction y between the opposite edges of the source electrode 30 and the through hole 60 located at both ends.
  • the source 30-1 (or source 30-4) and its through hole 60 have two sets of opposite edges, specifically, the upper edge of the source 30-1 is opposite to the upper edge of the through hole 60, and the two The distance between them in the first direction y is Y c , the lower edge of the source electrode 30 - 1 is opposite to the lower edge of the through hole 60 , and the distance between them in the first direction y is Y c .
  • the length of the source electrode 30 along the first direction y is usually as small as possible on the premise of meeting performance and production requirements.
  • Yc can be between the source electrode 30 at both ends and the opposite edge of via hole 60.
  • the length Y h of the through hole 60 along the first direction y can be set according to actual requirements, which is not specifically limited in this embodiment of the present invention.
  • the length of the source electrode 30 along the first direction y needs to consider not only the heat dissipation requirements of the corresponding area, but also the radio frequency characteristics of the semiconductor device and the requirements of the production process.
  • FIG. 4 is a partial top view structural schematic diagram of another semiconductor device provided by an embodiment of the present invention, also only showing the structure in the active region aa.
  • the distance L between the two rows of through holes 60 corresponding to the same source (such as the source 30-3) in the first direction y satisfies L ⁇ Y h ; wherein, Y h is the length of the through hole 60 along the first direction y.
  • the source electrode 30 is provided with row b of through holes 60, in order to meet the requirements of the process, it is necessary to ensure that the distance between the two rows of through holes 60 in the first direction y is greater than or equal to the length of the through holes 60 along the first direction y.
  • the distance H between the source electrodes 30 located at both ends and the opposite edges of the through hole 60 in the first direction y satisfies Y c ⁇ H ⁇ Y h +Y c ;
  • Y h is the length of the through hole 60 along the first direction y
  • Y c is the distance between the source electrode 30 at both ends and the opposite edge of the through hole 6 in the first direction y.
  • the distance between the opposite edges of the source electrode 30 and the through hole 60 in the first direction y specifically refers to the source The distance between one edge of the pole 30 and the edge of the through hole 60 closest to the edge.
  • the distance between the opposite edges of the source electrode 30 and the through hole 60 in the first direction y determines the length of the current flow path, therefore, the opposite edges of the source electrode 30 and the through hole 60
  • the distance in the direction y should not be too large, and Y c ⁇ H ⁇ Y h + Y c can be selected.
  • the via hole should be set at the source, but it is not arbitrarily set. It is necessary to ensure that all the source and via holes of the entire device are edge The distance satisfies Y c ⁇ H ⁇ Y h +Y c , so as to ensure that the semiconductor device has good radio frequency characteristics.
  • the current flow path ensures that the current path in the center is the same as the current path in the edge, which improves the radio frequency characteristics of the device.
  • the technical solution of the embodiment of the present invention is generally exemplified.
  • the first source electrode 30 - 1 is located at one end of the active region aa, and its length Y 1 along the first direction y is the smallest.
  • the second source 30-2 is closer to the center of the device than the first source 30-1, therefore, its length Y 2 in the first direction y can be appropriately increased (Y 2 > Y 1 ), and at the same time, when the length of Y 2 does not meet the requirements for designing two rows of through holes 60 (Y 2 ⁇ 3Y h + 2Y c ), it should try to ensure that the opposite edges of the source 30-2 and the through holes 60
  • the spacing H is less than or equal to (Y h +Y c ) and greater than or equal to Y c , so as to increase the heat dissipation capability of this region to a certain extent, and at the same time avoid excessively increasing the distance between the drain electrode 50-1 and the source electrode 30-2.
  • the length of the current flow path reduces the impact on the RF performance of the device.
  • the third source 30-3 is located at the center of the arrangement of electrodes, so that the length Y 3 along the first direction y can satisfy Y 3 ⁇ 3Y h + 2Y c , so as to increase the source 30- 3 to improve the heat dissipation capability of the central region.
  • the length of the source electrode 30-3 along the first direction y meets the requirements for setting two rows of through holes 60, it can avoid the long length of the source electrode 30-3 but only A row of through holes 60 can be provided to avoid affecting the radio frequency performance of the semiconductor device due to increasing the length of the current flow path.
  • the source electrode 30 - 3 is correspondingly provided with two rows of through holes 60 , it is preferable that the distance L between the two rows of through holes 60 is greater than or equal to the length Y h of the through holes 60 along the first direction y.
  • the source 30-4 can be designed symmetrically with the source 30-2, and the source 30-5 can be designed symmetrically with the source 30-1, which will not be elaborated here.
  • the number of rows of via holes corresponding to each source is a or b, so as to ensure the approximation and symmetry of all current flow paths of semiconductor devices, which is extremely high The stability of the semiconductor device; further, among any two nearest neighbor sources, the number of rows of through holes corresponding to the source near the center of the arrangement is greater than or equal to the number of rows of through holes corresponding to the source far away from the center of the arrangement .
  • the source 30-2 is adjacent to the source 30-1, wherein the source 30-2 is closer to the center of the arrangement than the source 30-1, and the source 30-2 is correspondingly provided with a row of through holes, and the source The electrode 30-1 is correspondingly provided with a row of through holes; the source electrode 30-3 is adjacent to the source electrode 30-3, wherein the source electrode 30-3 is closer to the center of the arrangement than the source electrode 30-2, and the source electrode 30-3 is correspondingly provided with two A row of through holes, the source electrode 30-2 is correspondingly provided with a row of through holes.
  • the semiconductor devices include, but are not limited to: high-power gallium nitride high electron mobility transistor (High Electron Mobility Transistor, HEMT) operating in a high-voltage and high-current environment, silicon-on-insulator (Silicon-On- Insulator, referred to as SOI) structure transistors, gallium arsenide (GaAs)-based transistors and metal-oxide-semiconductor field-effect transistors (Metal-Oxide-Semiconductor Field-Effect Transistor, referred to as MOSFET), metal-insulator-semiconductor field-effect transistors (Metal-Oxide-Semiconductor Field-Effect Transistor, referred to as MOSFET) -Semiconductor Field-Effect Transistor (MISFET for short), Double Heterojunction Field-Effect Transistor
  • HEMT high-power gallium nitride high electron mobility transistor
  • SOI silicon-on

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Abstract

本发明实施例公开了一种半导体器件，包括位于有源区的多个源极、多个栅极和多个漏极；在有源区内，源极、栅极和漏极沿第一方向交替排列，沿第一方向，包括两个分别最靠近排列端部的源极，任意一个栅极位于一个源极和一个漏极之间；至少位于中心的源极沿第一方向的长度大于位于两端的源极沿第一方向的长度；半导体器件还包括贯穿衬底以及多层半导体层的多排通孔；多排通孔沿第一方向排列，源极在衬底上的正投影与通孔在衬底上的正投影交叠；沿第一方向，至少位于中心的源极对应设置的通孔排数是位于两端的源极对应设置的通孔排数的2倍。本发明实施例的技术方案可以在增强半导体器件中心区域的散热能力的同时，保证半导体器件的射频特性。

Description

一种半导体器件 技术领域
本发明实施例涉及微电子技术领域，尤其涉及一种半导体器件。
背景技术
半导体材料氮化镓由于具有禁带宽度大、电子饱和漂移速度高、击穿场强高、导热性能好等特点，已经成为目前的研究热点。在电子器件方面，氮化镓材料比硅和砷化镓更适合于制造高温、高频、高压和大功率的半导体器件，因此氮化镓基电子器件具有很好的应用前景，例如用于制备氮化镓(GaN)高电子迁移率晶体管(High Electron Mobility Transistor，HEMT)器件。
GaN HEMT器件是一种场效应晶体管，使用两种具有不同能隙的材料(如AlGaN/GaN)形成异质结，为载流子提供沟道。GaN HEMT器件在实际工作过程中，特别是功率等级较高时，会产生大量的热量，使器件的结温升高，如果产生的热量得不到散发，会使器件结温越来越高，若超出能承受的最高结温，器件将被烧毁。
现有技术中，GaN HEMT器件常设计成多栅结构，由于器件中心区域的热量发散速度低于边缘区域，中心区域的结温往往最高，若得不到有效散热，将导致器件提前烧毁，而增加中心区域散热区的面积，又会影响器件的射频特性。因此，如何在增强半导体器件中心区域的散热能力的同时，保证半导体器件的射频特性是亟待解决的问题。
发明内容
本发明实施例提供一种半导体器件，以在增强半导体器件中心区域的散热能力的同时，保证半导体器件的射频特性。
一种半导体器件，包括：有源区以及围绕有源区的非有源区；
半导体器件还包括：
衬底；
多层半导体层，位于衬底的一侧；
多个源极、多个栅极和多个漏极，位于多层半导体层远离衬底的一侧且位于有源区内；在有源区内，源极、栅极和漏极沿第一方向交替排列，沿第一方向，包括两个分别最靠近排列端部的源极，任意一个栅极位于一个源极和一个漏极之间；第一方向平行于衬底所在平面；
沿第一方向，至少位于中心的源极沿第一方向的长度大于位于两端的源极沿第一方向的长度；
半导体器件还包括贯穿衬底以及多层半导体层的多排通孔；多排通孔沿第一方向排列，源极在衬底上的正投影与通孔在衬底上的正投影交叠；沿第一方向，位于两端的源极对应设置有a排通孔，至少位于中心的源极对应设置有b排通孔，且满足b＝2*a；a和b均为正整数，且a≥1，b≥2。
可选的，沿第一方向，位于排列中心的电极为漏极；
至少距离该漏极最近的两个源极沿第一方向的长度大于位于两端的源极沿第一方向的长度，且对应设置有b排通孔。
可选的，沿第一方向，位于排列中心的电极为源极；
至少该源极沿第一方向的长度大于位于两端的源极沿第一方 向的长度，且对应设置有b排通孔。
可选的，每个源极对应设置的通孔排数为a或者b。
可选的，任意两个最近邻的源极中，靠近排列中心的源极所对应的通孔的排数大于或等于远离排列中心的源极所对应的通孔的排数。
可选的，沿第一方向，自位于一端的第一个源极起，第m个源极对应设置有b排通孔；
第m个源极沿第一方向的长度Y m满足Y m≥3Y h+2Y c；
其中，Y h为通孔沿第一方向的长度，Y c为位于两端的源极和通孔的相对边缘在第一方向上的距离；m为大于1的正整数。
可选的，同一源极对应的两排通孔在第一方向上的距离L满足L≥Y h；
其中，Y h为通孔沿第一方向的长度。
可选的，在位于两端的源极之间的源极和通孔的相对边缘在第一方向上的距离H满足Y c≤H≤Y h+Y c；
其中，Y h为通孔沿所述第一方向的长度，Y c为位于两端的源极和通孔的相对边缘在第一方向上的距离。
可选的，每排通孔内的通孔数量相等。
可选的，各排通孔中，处于相同位数的通孔的几何中心的连线平行于第一方向。
本发明实施例通过设置至少位于中心的源极沿第一方向的长度大于位于两端的源极沿第一方向的长度，使得位于中心的源极的面积大于位于两端的源极的面积，从而增大了半导体器件中心区 域的散热区面积，提升半导体器件中心区域的散热能力；同时，通过设置至少位于中心的源极对应设置的通孔排数是位于两端的源极对应设置的通孔排数的2倍，可以兼顾器件散热的同时，使得中心器件的电流流通路径与边缘器件的电流流通路径近似，提高整体电流流通路径的对称性，保证半导体器件的射频特性。
附图说明
图1是本发明实施例提供的一种半导体器件的剖面结构示意图；
图2是本发明实施例提供的一种半导体器件的俯视结构示意图；
图3是本发明实施例提供的一种半导体器件的局部俯视结构示意图；
图4是本发明实施例提供的另一种半导体器件的局部俯视结构示意图。
具体实施方式
下面结合附图和实施例对本发明作进一步的详细说明。可以理解的是，此处所描述的具体实施例仅仅用于解释本发明，而非对本发明的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与本发明相关的部分而非全部结构，且附图中各元件的形状和大小不反映其真实比例，目的只是示意说明本发明内容。
在不脱离本申请的精神或范围的情况下，在本申请中能进行各种修改和变化，这对于本领域技术人员来说是显而易见的。因而，本申请意在覆盖落入所对应权利要求(要求保护的技术方案)及其等同物范围内的本申请的修改和变化。需要说明的是，本申请实施 例所提供的实施方式，在不矛盾的情况下可以相互组合。
本发明实施例提供一种半导体器件，包括有源区以及围绕有源区的非有源区；半导体器件还包括衬底、多层半导体层、多个源极、多个栅极和多个漏极，多层半导体层位于衬底的一侧；多个源极、多个栅极和多个漏极，位于多层半导体层远离衬底的一侧且位于有源区内；在有源区内，源极、栅极和漏极沿第一方向交替排列，沿第一方向，包括两个分别最靠近排列端部的源极，任意一个栅极位于一个源极和一个漏极之间；第一方向平行于衬底所在平面；沿第一方向，至少位于中心的源极沿第一方向的长度大于位于两端的源极沿第一方向的长度；半导体器件还包括贯穿衬底以及多层半导体层的多排通孔；多排通孔沿第一方向排列，源极在衬底上的正投影与通孔在衬底上的正投影交叠；沿第一方向，位于两端的源极对应设置有a排通孔，至少位于中心的源极对应设置有b排通孔，且满足b＝2*a；a和b均为正整数，且a≥1，b≥2。
采用以上技术方案，既可以兼顾器件散热，提高器件中心区域的散热，还通过排列端部与排列中心的通孔关系设置，使得中心器件的电流流通路径与边缘器件的电流流通路径近似，提高整体电流流通路径的对称性，保证半导体器件的射频特性。
以上是本申请的核心思想，基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下，所获得的所有其他实施例，都属于本申请保护的范围。以下将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。
图1是本发明实施例提供的一种半导体器件的剖面结构示意图，图2是本发明实施例提供的一种半导体器件的俯视结构示意图，参 见图1和图2，本发明实施例提供的半导体器件100包括有源区aa以及围绕有源区aa的非有源区na；半导体器件100还包括衬底10、多层半导体层20、多个源极30(图中30后的数字仅代表编号)、多个栅极40(图中40后的数字仅代表编号)和多个漏极50(图中50后的数字仅代表编号)，多层半导体层20位于衬底10的一侧；多个源极30、多个栅极40和多个漏极50位于多层半导体层20远离衬底10的一侧且位于有源区aa内；在有源区aa内，源极30、栅极40和漏极50沿第一方向y交替排列，沿第一方向y，包括两个分别最靠近排列端部的源极，任意一个栅极40位于一个源极30和一个漏极50之间；第一方向y平行于衬底10所在平面；沿第一方向y，至少位于中心的源极(如源极30-2)沿第一方向y的长度大于位于两端的源极(如源极30-1和源极30-3)沿第一方向y的长度；半导体器件100还包括贯穿衬底10以及多层半导体层20的多排通孔60；多排通孔60沿第一方向y排列，源极30在衬底10上的正投影与通孔60在衬底10上的正投影交叠；沿第一方向y，位于两端的源极(如源极30-1和源极30-3)对应设置有a排通孔60，至少位于中心的源极(如源极30-2)对应设置有b排通孔60，且满足b＝2*a；a和b均为正整数，且a≥1，b≥2。图2以a＝1，b＝2为例进行示意。另外，为便于展示，后续附图均以a＝1，b＝2为例进行示意。
本发明实施例提供的半导体器件设计为多栅结构。如图1和图2所示，在有源区aa内，源极30、栅极40和漏极50沿第一方向y交替排列，并且，沿第一方向y，任意一个栅极40位于一个源极30和一个漏极50之间，且任意两个相邻的栅极40之间包括一个源极 30或一个漏极50。示例性的，沿第一方向，源极30、栅极40和漏极50的排列顺序可以是源极30、栅极40、漏极50、栅极40、源极30……源极30，或者还可以是漏极50、栅极40、源极30、栅极40、漏极50……漏极50。图1以第一种排列方式为例进行示意，此时，位于排列端部的两个电极为源极30，对于第二种排列方式而言，位于排列端部的两个电极为漏极50。
此外，如图2所示，半导体器件100还包括栅极键合盘70、漏极键合盘80以及多排通孔60，栅极键合盘70位于多层半导体层20远离衬底10一侧的非有源区na内，多个栅极40均与栅极键合盘70电连接，漏极键合盘80位于多层半导体层20远离衬底10一侧的非有源区na内，多个漏极50均与漏极键合盘80电连接，通孔60贯穿衬底10以及多层半导体层20，并且源极30在衬底10上的正投影与通孔60在衬底10上的正投影交叠，如此，源极30可以通过通孔60接地。如图2所示，通常，多个栅极40沿第二方向x的长度相等，多个源极30沿第二方向x的长度相等，多个漏极50沿第二方向x的长度相等。其中，第二方向x与第一方向y相交，且平行于衬底10所在平面。
需要说明的是，每排通孔中至少包括一个通孔60即可，本发明实施例对一排通孔中的通孔数量不作限定。此外，图2仅以源极30在衬底10上的正投影覆盖与其对应设置的通孔60在衬底10上的正投影为例进行示意，该结构并非限定，只要保证源极30与其对应的通孔60在衬底10上的正投影交叠即可，示例性的，在其他实施例中，沿第二方向x靠近源极30的边缘的通孔60在该源极上的正投影可以超出该源极的边缘。
通常，栅极40接负向偏压，漏极50接正向偏压，而源极30为零电位(接地)。参照图2，半导体器件在工作时，电流从任一漏极50经过该漏极50两侧的栅极40分别流向该漏极50两侧的源极30，再经通孔60接地。例如，电流从漏极50-1经栅极40-1流向源极30-1，并且经栅极40-2流向源极30-2；同时电流从漏极50-2经栅极40-3流向源极30-2，并且经栅极40-4流向源极30-3。半导体器件在工作时，栅极40下方的附近区域为器件产热的主要区域。在栅极40沿第二方向x的长度一定的情况下，器件的散热主要受限于相邻栅极40沿第一方向y的间距。可以理解的，栅极40之间的间距越小，散热越慢。
本实施例利用源极30作为散热区，通过设置至少位于中心的源极(如源极30-2)沿第一方向y的长度大于位于两端的源极(如源极30-1和源极30-3)沿第一方向y的长度，可以增加器件中心的栅极(如栅极40-2和栅极40-3)之间的间距，增加器件中心的散热区的面积，提升器件中心区域的散热能力。
本实施例中，多个源极30、多个栅极40和多个漏极50沿第一方向y排列，其中，“位于中心的源极”可以理解为多个源极中距离排列中心最近的源极，“位于两端的源极”则表示最靠近排列端部的两个源极，如上所述，可选位于排列端部的电极为源极，此时，位于两端的源极即为位于排列端部的两个源极，后续均以位于排列端部的电极为源极为例进行说明。参照图2，在一具体实施方式中，可选多个源极30、多个栅极40和多个漏极50在有源区aa内沿第一方向y均匀对称分布，多个电极(即源极30、栅极40和漏极50)中位于排列中心的电极(如源极30-2)的中心点经过有源区aa的中 心轴线X，此时，“位于中心的源极”可以理解为距离有源区aa的中心轴线X最近的源极，其中，中心轴线X垂直于第一方向y且经过有源区aa沿第一方向y的中点。示例性的，图2所示半导体器件中，有源区aa内设置有三个源极，分别为源极30-1、源极30-2和源极30-3，其中，源极30-1和源极30-3位于有源区aa的两端，源极30-2位于有源区aa的中心，源极30-2沿第一方向y的长度大于源极30-1和源极30-3沿第一方向y的长度，从而使得器件中心的散热区面积增大，提升了器件中心区域的散热能力。
进一步地，现有技术中，排列中心和排列边缘区域的通孔排数设置一般是相同的。当中心的源极沿第一方向y的长度增加时，若该源极仍设置相同排数通孔，一方面会导致电流流通路径的长度(漏极到通孔的长度)增加，进而增加源极电阻，影响半导体器件的射频特性，例如会降低器件的最高振荡频率等关键电学特性；另一方面还会使同一漏极向两侧源极的电流流通路径长度不等，导致电流流通路径的不对称性，同样会对半导体器件的射频特性带来较大的影响。
为了在解决器件中心区域散热问题的同时，降低对器件射频特性的影响，本实施例在增加位于中心的源极30沿第一方向y的长度的同时，设计位于中心的源极30对应设置的通孔排数b是位于两端的源极30对应设置的通孔排数a的2倍，通过排列端部与排列中心的通孔关系设置，使得中心器件的电流流通路径与边缘器件的电流流通路径近似，缩短电流流通路径的长度，提高整体电流流通路径的对称性，保证器件具有良好的射频特性。
示例性的，参见图2，位于中心的源极30-2沿第一方向y的长 度增加，同时，源极30-2对应设置有两排通孔60，而位于两端的源极30-1和源极30-2则对应设置有一排通孔60。如此，漏极50-1到源极30-2的电流流通路径为漏极50-1到源极30-2中距离漏极50-1最近的通孔60的距离，从而可以缩短电流流通路径，同时可以提高漏极50-1向源极30-1和源极30-2的电流流通路径的对称性，同理，漏极50-2向源极30-2和源极30-3的电流流通路径同样具有较高的对称性，从而可以保证半导体器件具有良好的射频特性。
需要说明的是，图2仅以有源区aa内设置3个源极为例进行示意，可以理解的，源极的数量可以大于3个，此时，除了位于两端的源极以及位于中心的源极以外，其余源极可以根据散热需求选择是否增加该源极沿第一方向y的长度，并且可以根据该源极沿第一方向y的长度确定是否需要设置b排通孔，本发明实施例对此不作限定，在此仅以增加位于中心的源极沿第一方向y的长度，并对应该源极设置b排通孔为例进行说明。在其他实施例中，可选位于中心的源极沿第一方向y的长度最大，越靠近两端的源极沿第一方向y的长度越短，从而可以在提升器件中心区域散热能力的同时，节省部分有源区aa的面积，使有源区aa保持较高的面积利用率。
此外，可选各源极30至多对应设置两排通孔60，如此，可以在缩短电流流通路径，提高电流流通路径的对称性，保证半导体器件的射频特性的同时，避免设置过多通孔而影响器件的散热能力。
可选的，每排通孔包括至少一个通孔60；每排通孔内的通孔数量相等。图2仅以每排通孔包括两个通孔60为例进行示意。进一步的，可选各排通孔中，处于相同位数的通孔的几何中心的连线平行于第一方向y。示例性的，参见图2，沿第二方向x，各排通孔中 的第一个通孔的几何中心的连线平行于第一方向y，各排通孔中的第二个通孔的几何中心的连线平行于第一方向y。如此，可使半导体器件具有高度的对称性，从而可以保证半导体器件具有良好的射频特性。可选的，衬底10可以是氮化镓、铝镓氮、铟镓氮、铝铟镓氮、磷化铟、砷化镓、碳化硅、金刚石、蓝宝石、锗、硅中的一种或多种的组合，或任何其他能够生长III族氮化物的材料。
可选的，多层半导体层20可以包括基于III-V族化合物的半导体材料。具体的，多层半导体层20从衬底10方向可以依次包括成核层、缓冲层、沟道层以及势垒层。其中，沟道层和位于上方的势垒层一起形成异质结结构，该沟道层提供二维电子气运动的沟道。成核层影响上方异质结材料的晶体质量、表面形貌以及电学性质等参数。成核层随着不同的衬底10材料而变化，主要起到匹配衬底10材料和异质结结构中的半导体材料层的作用。缓冲层起到粘合接下来需要生长的半导体材料层的作用，又可以保护衬底10材料不被一些金属离子侵入。缓冲层的材料可以是AlGaN、GaN或AlGaInN等III族氮化物材料。在本发明中，该缓冲层为铝含量可控的氮化镓层(Al)GaN。
本发明实施例通过设置至少位于中心的源极沿第一方向的长度大于位于两端的源极沿第一方向的长度，使得位于中心的源极的面积大于位于两端的源极的面积，从而增大了半导体器件中心区域的散热区面积，提升半导体器件中心区域的散热能力；同时，通过设置至少位于中心的源极对应设置的通孔排数是位于两端的源极对应设置的通孔排数的2倍，可以在中心的源极沿第一方向的长度增加的情况下，使其通孔与相邻的栅极保持较短的距离，进 而保证电流流通路径较短，保证半导体器件的射频特性。
在上述实施例的基础上，有源区aa内源极30、栅极40和漏极50的数量可以根据实际需要设置，按照源极30、栅极40和漏极50的排布规律可知，沿第一方向，位于排列中心的电极可能为源极30，也可能为漏极50。如图2所示，当沿第一方向y，位于排列中心的电极为源极(如源极30-2)时，可选至少该源极(30-2)沿第一方向y的长度大于位于两端的源极沿第一方向y的长度，且对应设置有b排通孔60。图3是本发明实施例提供的一种半导体器件的局部俯视结构示意图，仅示出了有源区aa内的结构。参见图3，当沿第一方向y，位于排列中心的电极为漏极时，可选至少距离该漏极最近的两个源极沿第一方向y的长度大于位于两端的源极沿第一方向y的长度，且对应设置有b排通孔60。示例性的，图3中，源极30-2和源极30-3距离排列中心的漏极50-2最近，二者沿第一方向y的长度大于源极30-1和源极30-4沿第一方向y的长度，且对应设置有b排通孔60。
进一步地，参照图3，沿第一方向y，自位于任意一端的第一个源极(如源极30-1)起，可选第m个源极对应设置有b排通孔60，此时，只要第m个源极沿第一方向y的长度Y m满足Y m≥3Y h+2Y c，则该源极对应设置b排通孔，其余源极则设置a排通孔；一般来说，为了保证优越的射频特性，从两个排列端部的源极向中心方向，中心轴线X两侧的通孔数量是相同的；其中，Y h为通孔60沿第一方向y的长度，Y c为位于两端的源极30和通孔60的相对边缘在第一方向y上的距离；m为大于1的正整数。通过设置对应b排通孔的源极长度要求，保证整个器件的每个源极上通孔与相邻的栅极保持 较短的距离，进而保证所有整体器件的电流流通路径都较短。
具体的，各个源极30沿第一方向y的长度可以根据其所在区域的散热需求做适应性的设计。当第m个源极沿第一方向y的长度Y m≥3Y h+2Y c时，则该源极对应设置b排通孔60，其余源极即当Y m＜3Y h+2Y c时，则设置a排通孔，一般来说，中心轴线X两侧的源极关于中心轴线X对称设置，且每个源极沿第一方向y的长度也关于中心轴线X对称，则中心轴线X两侧的通孔关于中心轴线X对称设置；以保证整个器件的每个源极上通孔与相邻的栅极都尽可能保持较短的距离，且每个器件的电流流通路径尽可能近似，进而保证所有整体器件的电流流通路径都较短，避免该源极沿第一方向y的尺寸较大时对半导体器件的射频特性造成影响。
示例性的，图3中第二个源极30-2和第三个源极30-3设置有两排通孔60，二者在第一方向y上的长度Y 2和Y 3均需满足上述要求，即需要满足Y 2≥3Y h+2Y c，Y 3≥3Y h+2Y c。而图3中第一个源极30-2和第四个源极30-3由于二者在第一方向y上的长度均小于3Y h+2Y c，第一个源极30-2和第四个源极30-3所以设置有一排通孔。
其中，Y c为位于两端的源极30和通孔60的相对边缘在第一方向y上的距离。参照图3，源极30-1(或源极30-4)和其通孔60具有两组相对的边缘，具体的，源极30-1的上边缘与通孔60的上边缘相对，二者在第一方向y上的距离为Y c，源极30-1的下边缘与通孔60的下边缘相对，二者在第一方向y上的距离为Y c。在不考虑散热需求的情况下，为了节约面积，源极30沿第一方向y的长度通常尽量在满足性能和生产要求的前提下做到最小。对于两端的 源极(如图3中源极30-1和源极30-4)，其散热需求最小，因此，Y c可以是两端的源极30与通孔60的相对边缘之间所能允许的最小距离。通孔60沿第一方向y的长度Y h可以根据实际需求进行设置，本发明实施例对此不作特殊限定。
进一步地，源极30沿第一方向y上的长度除了需要考虑对应区域的散热需求以外，还需要综合考量半导体器件的射频特性以及生产工艺的要求。
图4是本发明实施例提供的另一种半导体器件的局部俯视结构示意图，同样仅示出了有源区aa内的结构。参照图4，为了满足工艺的要求，可选的，同一源极(如源极30-3)对应的两排通孔60在第一方向y上的距离L满足L≥Y h；其中，Y h为通孔60沿第一方向y的长度。即，当源极30对应设置b排通孔60时，为了满足工艺的要求，需要保证两排通孔60在第一方向y上的距离大于或等于通孔60沿第一方向y的长度。
继续参见图4，可选的，在位于两端的源极30之间的源极30和通孔60的相对边缘在第一方向y上的距离H满足Y c≤H≤Y h+Y c；其中，Y h为通孔60沿第一方向y的长度，Y c为位于两端的源极30和通孔6的相对边缘在第一方向y上的距离。参照图4，可以理解的，当源极对应设置b排通孔60时(如源极30-3)，源极30和通孔60的相对边缘在第一方向y上的距离具体是指源极30的一个边缘和距离该边缘最近的通孔60的边缘之间的距离。
具体的，根据上文解释可知，源极30和通孔60的相对边缘在第一方向y上的距离决定了电流流通路径的长度，因此，源极30和通孔60的相对边缘在第一方向y上的距离不宜过大，可选 Y c≤H≤Y h+Y c，通孔对应设置在源极，但也不是任意设置的，要保证整个器件的所有源极和通孔是边缘距离满足Y c≤H≤Y h+Y c，以保证半导体器件具有良好的射频特性。另外，当源极对应设置b排通孔时，优选H＝Y c，使得排列中心的通孔到相对源极边缘的距离，和排列边缘的通孔到相对源极边缘的距离相同，以降低电流的流通路径，保证中心的电流路径和边缘的电流路径相同，改善器件射频特性。
综上，以图4所示结构(a＝1，b＝2)为例，对本发明实施例的技术方案做总的示例性说明。图4中，第一个源极30-1位于有源区aa的一端，其沿第一方向y上的长度Y 1最小。沿第一方向y，第二个源极30-2相比第一个源极30-1更加靠近器件的中心，因此，可以适当增加其在第一方向y上的长度Y 2(Y 2＞Y 1)，同时，在Y 2的长度不满足设计两排通孔60的要求(不满足Y 2≥3Y h+2Y c)时，应尽量保证源极30-2与通孔60的相对边缘的间距H小于或等于(Y h+Y c)且大于或等于Y c，以在一定程度上增加该区域的散热能力，同时避免过多地增加漏极50-1到源极30-2的电流流通路径的长度，降低对器件射频性能的影响。继续沿第一方向y，第三个源极30-3位于电极的排列中心，可使其沿第一方向y的长度Y 3满足Y 3≥3Y h+2Y c，以增大源极30-3的面积，提高中心区域的散热能力，同时，由于源极30-3沿第一方向y的长度满足设置两排通孔60的要求，可以避免因源极30-3的长度较长但只能设置一排通孔60的情况，避免因增加电流流通路径的长度而影响半导体器件的射频性能。此外，由于源极30-3对应设置有两排通孔60，因此优选两排通孔60之间的间距L大于或等于通孔60沿第一方向y的长度Y h。此外，对于源极30-3，同样可选源极30-3与通孔60的相对边缘在 第一方向y上的距离H小于或等于(Y h+Y c)且大于或等于Y c(优选H＝Y c)，以避免过多地增加漏极50-2和漏极50-3到源极30-3的电流流通路径的长度，降低对器件射频性能的影响。源极30-4可与源极30-2做对称设计，源极30-5可与源极30-1做对称设计，在此不作过多说明。
最后，结合图2-图4，需要说明的是，本申请中，每个源极对应设置的通孔排数为a或者b，以保证半导体器件所有电流流通路径近似性和对称性，奇高半导体器件的稳定性；进一步的，任意两个最近邻的源极中，靠近排列中心的源极所对应的通孔的排数大于或等于远离排列中心的源极所对应的通孔的排数。以图4为例，源极30-2和源极30-1近邻，其中，源极30-2比源极30-1更加靠近排列中心，源极30-2对应设置一排通孔，源极30-1对应设置一排通孔；源极30-3和源极30-3近邻，其中，源极30-3比源极30-2更加靠近排列中心，源极30-3对应设置两排通孔，源极30-2对应设置一排通孔。
应该理解，本发明实施例是从半导体器件结构设计的角度来改善半导体器件的性能。所述半导体器件包括但不限制于：工作在高电压大电流环境下的大功率氮化镓高电子迁移率晶体管(High Electron Mobility Transistor，简称HEMT)、绝缘衬底上的硅(Silicon-On-Insulator，简称SOI)结构的晶体管、砷化镓(GaAs)基的晶体管以及金属氧化层半导体场效应晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor，简称MOSFET)、金属绝缘层半导体场效应晶体管(Metal-Semiconductor Field-Effect Transistor， 简称MISFET)、双异质结场效应晶体管(Double Heterojunction Field-Effect Transistor，简称DHFET)、结型场效应晶体管(Junction Field-Effect Transistor，简称JFET)，金属半导体场效应晶体管(Metal-Semiconductor Field-Effect Transistor，简称MESFET)，金属绝缘层半导体异质结场效应晶体管(Metal-Semiconductor Heterojunction Field-Effect Transistor，简称MISHFET)或者其他场效应晶体管。
注意，上述仅为本发明的较佳实施例及所运用技术原理。本领域技术人员会理解，本发明不限于这里所述的特定实施例，对本领域技术人员来说能够进行各种明显的变化、重新调整和替代而不会脱离本发明的保护范围。因此，虽然通过以上实施例对本发明进行了较为详细的说明，但是本发明不仅仅限于以上实施例，在不脱离本发明构思的情况下，还可以包括更多其他等效实施例，而本发明的范围由所附的权利要求范围决定。

Claims (10)

  1. 一种半导体器件，包括：有源区以及围绕有源区的非有源区；
    所述半导体器件还包括：
    衬底；
    多层半导体层，位于所述衬底的一侧；
    多个源极、多个栅极和多个漏极，位于所述多层半导体层远离所述衬底的一侧且位于所述有源区内；在所述有源区内，所述源极、所述栅极和所述漏极沿第一方向交替排列，沿所述第一方向，包括两个分别最靠近排列端部的源极，任意一个所述栅极位于一个所述源极和一个所述漏极之间；所述第一方向平行于所述衬底所在平面；
    其特征在于，
    沿所述第一方向，至少位于中心的源极沿所述第一方向的长度大于位于两端的源极沿所述第一方向的长度；
    所述半导体器件还包括贯穿所述衬底以及所述多层半导体层的多排通孔；多排所述通孔沿所述第一方向排列，所述源极在所述衬底上的正投影与所述通孔在所述衬底上的正投影交叠；沿所述第一方向，位于两端的源极对应设置有a排所述通孔，至少位于中心的源极对应设置有b排所述通孔，且满足b＝2*a；a和b均为正整数，且a≥1，b≥2。
  2. 根据权利要求1所述的半导体器件，其特征在于，沿所述第一方向，位于排列中心的电极为漏极；
    至少距离该漏极最近的两个源极沿所述第一方向的长度大于位于两端的源极沿所述第一方向的长度，且对应设置有b排通孔。
  3. 根据权利要求1所述的半导体器件，其特征在于，沿所述第一方向，位于排列中心的电极为源极；
    至少该源极沿所述第一方向的长度大于位于两端的源极沿所述第一方向的长度，且对应设置有b排通孔。
  4. 根据权利要求1所述的半导体器件，其特征在于，每个源极对应设置的通孔排数为a或者b。
  5. 根据权利要求4所述的半导体器件，其特征在于，任意两个最近邻的所述源极中，靠近排列中心的源极所对应的通孔的排数大于或等于远离排列中心的源极所对应的通孔的排数。
  6. 根据权利要求1所述的半导体器件，其特征在于，沿所述第一方向，自位于一端的第一个源极起，第m个源极对应设置有b排通孔；
    所述第m个源极沿所述第一方向的长度Y m满足Y m≥3Y h+2Y c；
    其中，Y h为所述通孔沿所述第一方向的长度，Y c为位于两端的所述源极和所述通孔的相对边缘在第一方向上的距离；m为大于1的正整数。
  7. 根据权利要求1所述的半导体器件，其特征在于，同一源极对应的两排所述通孔在所述第一方向上的距离L满足L≥Y h；
    其中，Y h为所述通孔沿所述第一方向的长度。
  8. 根据权利要求1所述的半导体器件，其特征在于，在位于两端的所述源极之间的所述源极和所述通孔的相对边缘在第一方向上的距离H满足Y c≤H≤Y h+Y c；
    其中，Y h为所述通孔沿所述第一方向的长度，Y c为位于两端的所述源极和所述通孔的相对边缘在第一方向上的距离。
  9. 根据权利要求1所述的半导体器件，其特征在于，每排通孔内的通孔数量相等。
  10. 根据权利要求8所述的半导体器件，其特征在于，各排通孔中，处于相同位数的通孔的几何中心的连线平行于所述第一方向。
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