WO2023124068A1 - 裸片到裸片的互连电路中半导体组件、集成电路封装方法 - Google Patents

裸片到裸片的互连电路中半导体组件、集成电路封装方法 Download PDF

Info

Publication number
WO2023124068A1
WO2023124068A1 PCT/CN2022/109428 CN2022109428W WO2023124068A1 WO 2023124068 A1 WO2023124068 A1 WO 2023124068A1 CN 2022109428 W CN2022109428 W CN 2022109428W WO 2023124068 A1 WO2023124068 A1 WO 2023124068A1
Authority
WO
WIPO (PCT)
Prior art keywords
die
packaging
module
bumps
micro
Prior art date
Application number
PCT/CN2022/109428
Other languages
English (en)
French (fr)
Inventor
冯杰
夏君
Original Assignee
深圳市紫光同创电子有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市紫光同创电子有限公司 filed Critical 深圳市紫光同创电子有限公司
Publication of WO2023124068A1 publication Critical patent/WO2023124068A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout

Definitions

  • the invention relates to the technical field of chip packaging, in particular to a semiconductor assembly in a bare chip to bare chip interconnection circuit, an integrated circuit packaging method, an IP structure and a bare chip.
  • Chiplets have become an increasingly important and extensive solution.
  • the concept of Chiplets is actually very simple, that is, silicon-level reuse. Starting from the system side, firstly, complex functions are decomposed. Then develop a variety of bare chips with a single specific function that can be modularly assembled with each other, such as realizing data storage, computing, signal processing, data flow management and other functions, and finally build a Chiplet chip network based on this.
  • Chiplets need to integrate a die-to-die (referred to as die-die) interconnection circuit.
  • the interconnection circuit is composed of integrated circuits and/or semiconductor devices.
  • the specific connection method can be determined according to actual needs. , the specific components contained in the interconnection circuit and the specific connection methods of the components are different in different actual situations, and an interconnection circuit can be called an IP.
  • Chiplets usually adopt multiple sealing methods such as Multi-chip Module (MCM for short), Fanout Package (FOP for short), and Chip on wafer on package (COWOS for short).
  • MCM Multi-chip Module
  • FOP Fanout Package
  • COWOS Chip on wafer on package
  • the wiring width, the distance between lines, the size of bumps or micro-bumps, and the distance between the centers of two adjacent bumps required by different packaging methods are all different, which requires multiple die- Die interconnect IP to meet the application of different sealing methods, which affects the chip development progress and development cost.
  • the present invention provides a semiconductor component, an integrated circuit packaging method, an IP structure, and a bare chip in a chip-to-bare interconnect circuit. Progress reduces development costs.
  • An embodiment of the present invention provides a method for packaging a semiconductor component and an integrated circuit in a die-to-die interconnection circuit, including:
  • any module in the hard core in the target interconnection circuit if any module uses COWOS or FOP packaging, then any module uses micro-bumps in the packaging process, and any two adjacent modules in the horizontal direction
  • the center-of-sphere distance between the micro-bumps is not less than 40um.
  • the types of the micro-bumps include power terminals, ground terminals, signal terminals and clock signal terminals.
  • the center-of-sphere distance between any two adjacent micro-bumps in the horizontal direction is 40um.
  • the center-of-sphere distance between any two adjacent micro-bumps in the vertical direction is 80um; wherein, the vertical direction is perpendicular to the horizontal direction.
  • any module transmits 52 signals, wherein the 52 signals include 2 differential clock signals.
  • the transmission mode of single data rate is adopted, and the transmission rate is 2.5Gbps.
  • any of the modules uses MCM packaging, then any of the modules transmits 26 signals, and on the basis of COWOS or FOP packaging of any of the modules, several solder balls are set on any of the modules
  • the solder balls are arranged on the corresponding micro-bumps, and the solder balls are connected to the micro-bumps representing signals in the corresponding micro-bumps through rewiring.
  • each solder ball corresponds to a plurality of micro-bumps.
  • the sum of the number of solder balls and the number of remaining micro-bumps representing signals in any module is 26.
  • the distance between the centers of any two solder balls is 160um.
  • the solder balls are flip-chip flip-chip solder balls.
  • the double data rate transmission mode is adopted, and the transmission rate is 5Gbps.
  • any of the modules is composed of semiconductor components and/or integrated circuits.
  • the embodiment of the present invention also provides an IP structure, the IP structure includes a digital control module and a hard core; the hard core is composed of at least one of semiconductor components and integrated circuits; Semiconductor components and integrated circuit packaging methods are packaged in the die-to-die interconnection circuit.
  • the hard core includes a sending module, an IO calibration module and a receiving module; the sending module, the IO calibration module and the receiving module are respectively connected to the digital control module.
  • the embodiment of the present invention also provides a bare chip, the bare chip includes a plurality of the above-mentioned IP structures.
  • the present invention proposes a packaging method for semiconductor components and integrated circuits in a die-to-die interconnection circuit.
  • COWOS or FOP packaging can be realized on the IP without changing the IP structure.
  • the process only needs to do a die-die interconnection IP to meet different packaging methods, reducing chip development progress and development costs.
  • FIG. 1 is a schematic diagram of a die-to-die interconnection circuit structure in an embodiment of the present invention.
  • FIG. 2 is a schematic diagram of COWOS or FOP packaging in an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of the MCM packaging method adopted in the embodiment of the present invention.
  • FIG. 4 is a schematic diagram of a bump pitch when the MCM encapsulation method is adopted in the embodiment of the present invention.
  • FIG. 1 is a schematic diagram of the interconnection circuit structure from die to die in the embodiment of the present invention.
  • hard core 120 comprises sending module 121, IO calibration module 122 and receiving module 123, and sending module, IO calibration module 122 and receiving module 123 are respectively connected with digital control module 110, can be connected with digital control module 110 to communicate.
  • the digital control module 110 is developed and integrated by a chip design project, and the embodiment of the present invention mainly focuses on the packaging method of the hard core 120 .
  • the digital control module 110 and the hard core 120 in the embodiment of the present invention may be a circuit composed of semiconductor components alone, or an integrated circuit die, or a combination of a semiconductor component and an integrated circuit die. become.
  • Fig. 2 is the schematic diagram adopting COWOS or FOP package in the embodiment of the present invention, as shown in Fig. 2, this method comprises:
  • any module in the hard core in the target interconnection circuit if any module uses COWOS or FOP packaging, then any module uses micro-bumps in the packaging process, and any two adjacent modules in the horizontal direction
  • the center-of-sphere distance between the micro-bumps is not less than 40um.
  • the center-of-sphere distance between any two adjacent micro-bumps in the horizontal direction is 40um.
  • the receiving module and the sending module are used as any module for description.
  • the figure shows a schematic diagram of the sending module and the receiving module adopting COWOS packaging or FOP packaging.
  • the bumps used in welding on the sending module and the receiving module are as follows: Micro-bump, the micro-bump is the circle in the figure, and has 4 meanings in total, which respectively represent the power terminal, ground terminal, signal terminal and clock signal terminal.
  • the micro-bump is the micro-bump, in the horizontal direction , the minimum distance between any two adjacent micro-bump pitch centers is 40um, that is, the minimum distance between micro-bump pitches is 40um.
  • COWOS packaging or FOP packaging can be performed on the sending module and receiving module.
  • the micro-bump pitch can be fine-tuned based on the package routing requirements to meet the specification requirements of different projects.
  • the width of the line connecting two micro-bumps in the figure and the distance between lines can be adjusted according to actual needs, which is not limited in this application.
  • the present invention proposes a packaging method for semiconductor components and integrated circuits in a die-to-die interconnection circuit.
  • COWOS or FOP packaging can be realized on the IP without changing the IP structure.
  • the process only needs to do a die-die interconnection IP to meet different packaging methods, which can reduce chip development progress and development costs.
  • the distance between any two adjacent micro-bumps in the vertical direction is 80 um.
  • the vertical direction and the horizontal direction are perpendicular to each other.
  • the center-of-sphere distance between any two adjacent micro-bumps is 80um.
  • any module transmits 52 signals, including 2 differential clock signals.
  • each micro-bump that represents a signal transmits a signal, that is, the white circle in the receiving module or the sending module in the figure, there are 52 white circles in total, and there are 2 micro-bumps to indicate The differential clock signal, that is, the black circle in the receiving module or sending module in the figure.
  • a single data rate transmission mode is adopted, and the transmission rate is 2.5 Gbps.
  • the module uses a single data rate transmission module when performing data transmission, and its transmission rate is 2.5Gbps.
  • FIG 3 is a schematic diagram of the MCM packaging method used in the embodiment of the present invention.
  • the transmission of any module 26 signals on the basis of COWOS or FOP packaging of any module, set several solder balls on any module, the solder balls are set on the corresponding micro-bumps, and the solder balls are connected to the corresponding micro-bumps
  • the micro-bumps representing signals in the bumps are connected by rewiring, and the sum of the number of solder balls and the number of remaining micro-bumps representing signals in any module is 26, and any two tin The distance between the centers of the balls is 160um.
  • the sending module or the receiving module is to use the MCM packaging method, it can be modified directly on the basis of the original COWOS or FOP packaging. Specifically, a certain number of solder balls are added to the module, the white in the figure The big circle is the solder ball, which can be connected to the signal terminal by rewiring, and the number of solder balls plus the number of unconnected signal terminals is 26 in total. Each solder ball and each The unconnected signal end transmits a signal independently, and here, the unconnected signal end refers to the signal end not connected to the solder ball.
  • FIG. 4 is a schematic diagram of the bump pitch when the MCM packaging method is used in the embodiment of the present invention. As shown in FIG. 4, the distance between the centers of any two adjacent solder balls is 160um, that is, the bump pitch in the figure is 160um.
  • each solder ball corresponds to a plurality of micro-bumps.
  • each solder ball can correspond to 4 micro-bumps.
  • the solder balls are flip-chip flip-chip solder balls.
  • the solder ball is flip chip flip soldering solder ball
  • the flip chip flip soldering method is Controlled Collapsed Chip Connection, referred to as C4
  • the solder ball is solder bump
  • the flip chip flip soldering solder ball is C4 solder ball .
  • FANOUT (fan-out) technology is used to expand the bare chip, and rewiring is used to connect the signal terminal and the C4 solder ball.
  • a double data rate transmission mode is adopted, and the transmission rate is 5 Gbps.
  • the bump pitch can be fine-tuned based on the package routing requirements to meet the specification requirements of different projects.
  • IP In order to improve the reliability of high-speed die-die interconnection, IP needs to support and design integrate the following functions:
  • IP supports adjustable IO output impedance gear, and the adjustable range is 20 ⁇ 50ohm.
  • IP supports IO on-chip termination (On Die Termination, referred to as ODT) with adjustable gears, and the adjustable range is 60 ⁇ 480ohm.
  • the IP supports automatic calibration calculations.
  • IP supports Per-bit deskew function, supports thickness adjustment and automatic adjustment.
  • the package wiring is controlled to be equal in length, and the wiring should be as short as possible and the wiring should have fewer vias.
  • SI simulation is required for package routing, and the simulation optimizes the width and spacing of iterative routing to ensure signal quality.
  • Nonvolatile memory can include read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory.
  • Volatile memory can include random access memory (RAM) or external cache memory.
  • RAM is available in many forms such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Chain Synchlink DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.
  • SRAM Static RAM
  • DRAM Dynamic RAM
  • SDRAM Synchronous DRAM
  • DDRSDRAM Double Data Rate SDRAM
  • ESDRAM Enhanced SDRAM
  • SLDRAM Synchronous Chain Synchlink DRAM
  • Rambus direct RAM
  • DRAM direct memory bus dynamic RAM
  • RDRAM memory bus dynamic RAM

Abstract

提出一种裸片到裸片的互连电路中半导体组件、集成电路封装方法、IP结构以及裸片。对于目标互连电路中的硬核中的任一模块，若任一模块使用COWOS或FOP封装，则任一模块在封装过程中使用微凸点，并且水平方向任意两个相邻微凸点之间的球心距离不小于40μm。对于同一个IP，可以在不改变IP结构的前提下，在IP上实现COWOS或FOP封装，一个工艺只需要做一种管芯-管芯互连IP来满足不同封装方式，提高芯片开发进度以及降低开发成本。

Description

裸片到裸片的互连电路中半导体组件、集成电路封装方法
相关申请的交叉引用
本申请要求于2021年12月28日提交中国专利局的申请号为CN2021116300311、名称为“裸片到裸片的互连电路中半导体组件、集成电路封装方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及芯片封装技术领域，尤其涉及一种裸片到裸片的互连电路中半导体组件、集成电路封装方法、IP结构以及裸片。
背景技术
随着进入后摩时代，Chiplet(芯粒)成为一个越来越重要和广泛的解决方案，Chiplet的概念其实很简单，就是硅片级别的重用，从系统端出发，首先将复杂功能进行分解，然后开发出多种具有单一特定功能、可相互进行模块化组装的裸芯片，如实现数据存储、计算、信号处理、数据流管理等功能，并最终以此为基础，建立一个Chiplet的芯片网络。
Chiplet里多颗芯片需要集成裸片到裸片(简称die-die)的互连电路，一般而言，该互连电路由集成电路和/或半导体器件组成，具体连接方式可以根据实际需求进行确定，不同实际情况下互连电路中所包含的具体元器件和元器件的具体连接方式不同，一个互连电路可以称为一个IP。Chiplet通常采用多芯片模块(Multi-chip Module，简称MCM)、扇出封装(Fanout Package，简称FOP)和芯片在晶圆在封装上(Chip on wafer on package，简称COWOS)等多种合封方式，不同封装方式所需要的连线宽度、线与线之间的距离、凸点或微凸点的尺寸以及两个相邻凸点球心之间的间距均不相同，这样需要多颗die-die互连IP来满足不同合封方式应用，影响芯片开发进度和开发成本。
发明内容
本发明提供一种裸片到裸片的互连电路中半导体组件、集成电路封装方法、IP结构以及裸片，其主要目的在于在一个互连电路上实现多种不同的封装方式，提高芯片开发进度降低开发成本。
本发明实施例提供一种裸片到裸片的互连电路中半导体组件、集成电路封装方法，包括：
对于目标互连电路中的硬核中的任一模块，若所述任一模块使用COWOS或FOP封装，则所述任一模块在封装过程中使用微凸点，并且水平方向任意两个相邻微凸点之间的球心距离不小于40um。
优选地，所述微凸点的类型包括电源端、接地端、信号端和时钟信号端。
优选地，水平方向任意两个相邻微凸点之间的球心距离为40um。
优选地，竖直方向任意两个相邻微凸点之间的球心距离为80um；其中，竖直方向与水平方向垂直。
优选地，所述任一模块传输52个信号，其中，52个信号中包括2个差分时钟信号。
优选地，采用单倍数据速率的传输模式，传输速率2.5Gbps。
优选地，若所述任一模块使用MCM封装方式，则所述任一模块传输26个信号，在所述任一模块COWOS或FOP封装基础上，在所述任一模块上设置若干个锡球，所述锡球设置在对应微凸点上面，且所述锡球与对应微凸点中表示信号的微凸点通过再布线连接。
优选地，每个所述锡球对应多个微凸点。
优选地，所述锡球的个数与所述任一模块中剩余表示信号的微凸点个数之和为26。
优选地，所述任意两个锡球球心之间的距离为160um。
优选地，所述锡球为覆晶反扣焊法锡球。
优选地，所述任一模块中有2个差分时钟信号。
优选地，采用双倍数据速率的传输模式，传输速率5Gbps。
优选地，所述任一模块由半导体组件构和/或集成电路构成。
本发明实施例还提供了一种IP结构，所述IP结构包括数字控制模块和硬核；所述硬核采用半导体组件、集成电路中的至少一种组合而成；所述硬核采用上述的裸片到裸片的互连电路中半导体组件、集成电路封装方法封装而成。
优选地，所述硬核包括发送模块、IO校准模块和接收模块；所述发送模块、所述IO校准模块和所述接收模块分别与所述数字控制模块连接。
本发明实施例还提供了一种裸片，所述裸片包括多个上述的IP结构。
本发明提出的一种裸片到裸片的互连电路中半导体组件、集成电路封装方法，对于同一个IP，可以在不改变IP结构的前提下，在该IP上实现COWOS或FOP封装，一个工艺只需要做一种die-die互连IP来满足不同封装方式，降低芯片开发进度以及开发成本。
附图说明
图1为本发明实施例中裸片到裸片的互连电路结构示意图。
图2为本发明实施例中采用COWOS或FOP封装的示意图。
图3为本发明实施例中采用MCM封装方式的示意图。
图4为本发明实施例中采用MCM封装方式时Bump pitch示意图。
本发明目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
具体实施方式
应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
图1为本发明实施例中裸片到裸片的互连电路结构示意图，如图1所示，本发明实施例中，一个裸片包括多个IP结构100，IP结构100包括数字控制模块110和硬核120，硬核120包括发送模块121、IO校准模块122和接收模 块123，发送模块、IO校准模块122和接收模块123均分别与数字控制模块110连接，可以与数字控制模块110之间进行通信。
一般而言，数字控制模块110由芯片设计项目开发集成，本发明实施例中针对的主要是硬核120的封装方式。
需要说明的是，本发明实施例中数字控制模块110和硬核120，可以是单独由半导体组件构成的电路，也可以是集成电路裸片，也可以是由半导体组件和集成电路裸片组合而成。
图2为本发明实施例中采用COWOS或FOP封装的示意图，如图2所示，该方法包括：
对于目标互连电路中的硬核中的任一模块，若所述任一模块使用COWOS或FOP封装，则所述任一模块在封装过程中使用微凸点，并且水平方向任意两个相邻微凸点之间的球心距离不小于40um。
优选地，水平方向任意两个相邻微凸点之间的球心距离为40um。
本发明实施例中以接收模块、发送模块为任一模块进行说明，图中表示发送模块和接收模块的采用COWOS封装或FOP封装的示意图，发送模块和接收模块上在焊接时使用的凸点为微凸点，微凸点即为图中的圈圈，共有4中含义，分别表示电源端、接地端、信号端和时钟信号端，其中，微凸点即为micro-bump，在水平方向上，任意两个相邻的微凸点球心之间的距离最小为40um，即micro-bump pitch的距离最小为40um。只要满足该条件，就能对发送模块、接收模块进行COWOS封装或FOP封装。micro-bump pitch可以基于封装走线要求进行微调，以满足不同项目的规格要求。
还需要说明的是，COWOS封装或FOP封装时，图中连接两个微凸点之间的线的宽度、线和线之间的距离可以根据实际需要进行调整，本申请对此不做限制。
本发明提出的一种裸片到裸片的互连电路中半导体组件、集成电路封装方法，对于同一个IP，可以在不改变IP结构的前提下，在该IP上实现COWOS或FOP封装，一个工艺只需要做一种die-die互连IP来满足不同封装方式，从而可以降低芯片开发进度以及开发成本。
在上述实施例的基础上，优选地，竖直方向任意两个相邻微凸点之间的球心距离为80um。其中，竖直方向与水平方向互相垂直。
在竖直方向上，任意两个相邻的微凸点之间的球心距离为80um。
在上述实施例的基础上，优选地，所述任一模块传输52个信号，其中包括2个差分时钟信号。
参考发送模块和接收模块，每个表示信号的微凸点传输一个信号，也就是图中接收模块或发送模块中白色圈圈，白色圈圈一共有52个，并且其中有2个微凸点表示差分时钟信号，也就是图中接收模块或发送模块中黑色圈圈。
在上述实施例的基础上，优选地，采用单倍数据速率的传输模式，传输速率2.5Gbps。
具体地，模块在进行数据传输时采用单倍数据速率的传输模块，其传输速率是2.5Gbps。
图3为本发明实施例中采用MCM封装方式的示意图，如图3所示，在上述实施例的基础上，优选地，若所述任一模块使用MCM封装方式，则所述任一模块传输26个信号，在所述任一模块COWOS或FOP封装基础上，在所述任一模块上设置若干个锡球，所述锡球设置在对应微凸点上面，且所述锡球与对应微凸点中表示信号的微凸点通过再布线连接，并且，所述锡球的个数与所述任一模块中剩余表示信号的微凸点个数之和为26，所述任意两个锡球球心之间的距离为160um。
本发明实施例中，如果发送模块或接收模块要使用MCM封装方式，则直接在原来的COWOS或FOP封装基础上进行修改即可，具体为在该模块上添加一定数量的锡球，图中白色大圈圈即为锡球，该锡球与信号端可以通过再布线实现连接，并且，锡球的个数加上未连接的信号端个数一共为26个，每个锡球和每个未连接的信号端单独传输一个信号，此处，未连接的信号端是指未与锡球连接的信号端。并且，图4为本发明实施例中采用MCM封装方式时Bump pitch示意图，如图4所示，任意相邻的两个锡球的球心之间的距离为160um，即图中的Bump pitch为160um。
优选地，每个锡球对应多个微凸点。例如，每个锡球可以对应4个微凸 点。
本发明实施例中，当需要实现MCM封装时，只需要在COWOS或FOP封装上添加一定数量和排列符合一定要求的锡球即可，并不需要重新修改IP结构，使得通过一个IP就可以实现常见的COWOS、FOP和MCM封装。
在上述实施例的基础上，优选地，所述锡球为覆晶反扣焊法锡球。
具体地，该锡球为覆晶反扣焊法锡球，覆晶反扣焊法为Controlled Collapsed Chip Connection，简称C4，锡球为solder bump，覆晶反扣焊法锡球即为C4锡球。在具体实施时，采用FANOUT(扇出)技术将裸片扩大，使用再布线连接信号端与C4锡球。
在上述实施例的基础上，优选地，所述任一模块中有2个差分时钟信号。
同样地，该封装方式中也有2个差分时钟信号，即为图中黑色圈圈。
在上述实施例的基础上，优选地，采用双倍数据速率的传输模式，传输速率5Gbps。
本发明实施例中，Bump pitch可以基于封装走线要求进行微调，以满足不同项目的规格要求。
为了提高高速速率die-die互连可靠性，IP需要支持以及设计集成如下功能：
IP支持IO输出阻抗档位可调，可调范围20～50ohm。
IP支持IO片上端接(On Die Termination，简称ODT)档位可调，可调范围60～480ohm。
IP支持自动校准计算。
IP支持Per-bit deskew功能，支持粗细调节以及自动调节。
封装走线进行等长控制，且根据尽量走短线以及走线少过孔。
封装走线需要进行SI仿真，仿真优化迭代走线的宽度和间距，确保信号质量。
本领域普通技术人员可以理解实现上述实施例方法中的全部或部分流程，是可以通过计算机程序来指令相关的硬件来完成，所述的计算机程序可存储于一非易失性计算机可读取存储介质中，该计算机程序在执行时，可包括如 上述各方法的实施例的流程。其中，本申请所提供的各实施例中所使用的对存储器、存储、数据库或其它介质的任何引用，均可包括非易失性和/或易失性存储器。非易失性存储器可包括只读存储器(ROM)、可编程ROM(PROM)、电可编程ROM(EPROM)、电可擦除可编程ROM(EEPROM)或闪存。易失性存储器可包括随机存取存储器(RAM)或者外部高速缓冲存储器。作为说明而非局限，RAM以多种形式可得，诸如静态RAM(SRAM)、动态RAM(DRAM)、同步DRAM(SDRAM)、双数据率SDRAM(DDRSDRAM)、增强型SDRAM(ESDRAM)、同步链路(Synchlink)DRAM(SLDRAM)、存储器总线(Rambus)直接RAM(RDRAM)、直接存储器总线动态RAM(DRDRAM)、以及存储器总线动态RAM(RDRAM)等。
所属领域的技术人员可以清楚地了解到，为了描述的方便和简洁，仅以上述各功能单元、模块的划分进行举例说明，实际应用中，可以根据需要而将上述功能分配由不同的功能单元、模块完成，即将所述装置的内部结构划分成不同的功能单元或模块，以完成以上描述的全部或者部分功能。
以上所述实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的精神和范围，均应包含在本发明的保护范围之内。

Claims (17)

  1. 一种裸片到裸片的互连电路中半导体组件、集成电路封装方法，其特征在于，包括：
    对于目标互连电路中硬核中的任一模块，若所述任一模块使用COWOS或FOP封装，则所述任一模块在封装过程中使用微凸点，并且水平方向任意两个相邻微凸点之间的球心距离不小于40um。
  2. 根据权利要求1所述的裸片到裸片的互连电路中半导体组件、集成电路封装方法，其特征在于，所述微凸点的类型包括电源端、接地端、信号端和时钟信号端。
  3. 根据权利要求1或2所述的裸片到裸片的互连电路中半导体组件、集成电路封装方法，其特征在于，水平方向任意两个相邻微凸点之间的球心距离为40um。
  4. 根据权利要求1至3任一项所述的裸片到裸片的互连电路中半导体组件、集成电路封装方法，其特征在于，竖直方向任意两个相邻微凸点之间的球心距离为80um；其中，所述竖直方向与所述水平方向垂直。
  5. 根据权利要求1至4任一项所述的裸片到裸片的互连电路中半导体组件、集成电路封装方法，其特征在于，所述任一模块传输52个信号，其中，所述52个信号中包括2个差分时钟信号。
  6. 根据权利要求1至5任一项所述的裸片到裸片的互连电路中半导体组件、集成电路封装方法，其特征在于，采用单倍数据速率的传输模式，传输速率2.5Gbps。
  7. 根据权利要求1至6任一项所述的裸片到裸片的互连电路中半导体组件、集成电路封装方法，其特征在于，若所述任一模块使用MCM封装方式，则所述任一模块传输26个信号，在所述任一模块COWOS或FOP封装基础上，在所述任一模块上设置若干个锡球，所述锡球设置在对应微凸点上面，且所述锡球与对应微凸点中表示信号的微凸点通过再布线连接。
  8. 根据权利要求7所述的裸片到裸片的互连电路中半导体组件、集成电 路封装方法，其特征在于，每个所述锡球对应多个微凸点。
  9. 根据权利要求7或8所述的裸片到裸片的互连电路中半导体组件、集成电路封装方法，其特征在于，所述锡球的个数与所述任一模块中剩余表示信号的微凸点个数之和为26。
  10. 根据权利要求9所述的裸片到裸片的互连电路中半导体组件、集成电路封装方法，其特征在于，所述任意两个锡球球心之间的距离为160um。
  11. 根据权利要求10所述的裸片到裸片的互连电路中半导体组件、集成电路封装方法，其特征在于，所述锡球为覆晶反扣焊法锡球。
  12. 根据权利要求10或11所述的裸片到裸片的互连电路中半导体组件、集成电路封装方法，其特征在于，所述任一模块中有2个差分时钟信号。
  13. 根据权利要求10-12任一项所述的裸片到裸片的互连电路中半导体组件、集成电路封装方法，其特征在于，采用双倍数据速率的传输模式，传输速率5Gbps。
  14. 根据权利要求1至13任一项所述的裸片到裸片的互连电路中半导体组件、集成电路封装方法，其特征在于，所述任一模块由半导体组件构和/或集成电路构成。
  15. 一种IP结构，其特征在于，所述IP结构包括数字控制模块和硬核；所述硬核采用半导体组件、集成电路中的至少一种组合而成；所述硬核采用权利要求1至14任一项所述的裸片到裸片的互连电路中半导体组件、集成电路封装方法封装而成。
  16. 根据权利要求15所述的IP结构，其特征在于，所述硬核包括发送模块、IO校准模块和接收模块；所述发送模块、所述IO校准模块和所述接收模块分别与所述数字控制模块连接。
  17. 一种裸片，其特征在于，所述裸片包括多个权利要求15或16所述的IP结构。
PCT/CN2022/109428 2021-12-28 2022-08-01 裸片到裸片的互连电路中半导体组件、集成电路封装方法 WO2023124068A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202111630031.1A CN114446806A (zh) 2021-12-28 2021-12-28 裸片到裸片的互连电路中半导体组件、集成电路封装方法
CN202111630031.1 2021-12-28

Publications (1)

Publication Number Publication Date
WO2023124068A1 true WO2023124068A1 (zh) 2023-07-06

Family

ID=81365272

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/109428 WO2023124068A1 (zh) 2021-12-28 2022-08-01 裸片到裸片的互连电路中半导体组件、集成电路封装方法

Country Status (2)

Country Link
CN (1) CN114446806A (zh)
WO (1) WO2023124068A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117236263A (zh) * 2023-11-15 2023-12-15 之江实验室 一种多芯粒互联仿真方法、装置、存储介质及电子设备

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114446806A (zh) * 2021-12-28 2022-05-06 深圳市紫光同创电子有限公司 裸片到裸片的互连电路中半导体组件、集成电路封装方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201409622A (zh) * 2012-06-18 2014-03-01 Invensas Corp 容忍微電子元件誤置於其中之微電子組件
CN105895623A (zh) * 2015-02-13 2016-08-24 台湾积体电路制造股份有限公司 用于半导体封装件的衬底设计及其形成方法
US9882562B1 (en) * 2016-12-07 2018-01-30 Xilinx, Inc. Rotated integrated circuit die and chip packages having the same
CN112233984A (zh) * 2019-07-15 2021-01-15 台湾积体电路制造股份有限公司 形成半导体器件的方法以及系统
CN113161302A (zh) * 2020-05-01 2021-07-23 台湾积体电路制造股份有限公司 半导体封装结构、半导体封装件及其制造方法
CN113223970A (zh) * 2020-04-29 2021-08-06 台湾积体电路制造股份有限公司 半导体结构及其制造方法
CN114446806A (zh) * 2021-12-28 2022-05-06 深圳市紫光同创电子有限公司 裸片到裸片的互连电路中半导体组件、集成电路封装方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201409622A (zh) * 2012-06-18 2014-03-01 Invensas Corp 容忍微電子元件誤置於其中之微電子組件
CN105895623A (zh) * 2015-02-13 2016-08-24 台湾积体电路制造股份有限公司 用于半导体封装件的衬底设计及其形成方法
US9882562B1 (en) * 2016-12-07 2018-01-30 Xilinx, Inc. Rotated integrated circuit die and chip packages having the same
CN112233984A (zh) * 2019-07-15 2021-01-15 台湾积体电路制造股份有限公司 形成半导体器件的方法以及系统
CN113223970A (zh) * 2020-04-29 2021-08-06 台湾积体电路制造股份有限公司 半导体结构及其制造方法
CN113161302A (zh) * 2020-05-01 2021-07-23 台湾积体电路制造股份有限公司 半导体封装结构、半导体封装件及其制造方法
CN114446806A (zh) * 2021-12-28 2022-05-06 深圳市紫光同创电子有限公司 裸片到裸片的互连电路中半导体组件、集成电路封装方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117236263A (zh) * 2023-11-15 2023-12-15 之江实验室 一种多芯粒互联仿真方法、装置、存储介质及电子设备
CN117236263B (zh) * 2023-11-15 2024-02-06 之江实验室 一种多芯粒互联仿真方法、装置、存储介质及电子设备

Also Published As

Publication number Publication date
CN114446806A (zh) 2022-05-06

Similar Documents

Publication Publication Date Title
WO2023124068A1 (zh) 裸片到裸片的互连电路中半导体组件、集成电路封装方法
US11705398B2 (en) Pitch translation architecture for semiconductor package including embedded interconnect bridge
KR101160405B1 (ko) 고밀도의 범프없는 빌드업 층들 및 더 낮은 밀도의 코어 또는 코어없는 기판을 포함하는 집적회로 패키지들
WO2015184948A1 (zh) 一种芯片堆叠封装结构和电子设备
KR20240010099A (ko) 스케일러블 시스템을 구현하기 위한 시스템들 및 방법들
Chang et al. Ultra high density IO fan-out design optimization with signal integrity and power integrity
JP2011514015A (ja) バンプレス・ビルド・アップ・レイヤ（ｂｂｕｌ）を使用したパッケージオンパッケージ
US20220399321A1 (en) Chipset and manufacturing method thereof
TW202123411A (zh) 用於積體電路封裝體之複合式橋接晶粒至晶粒互連件
WO2016165074A1 (zh) 一种芯片
US20210125932A1 (en) Hybrid core substrate architecture for high speed signaling and fli/sli reliability and its making
KR101903520B1 (ko) 반도체 장치
JP5511823B2 (ja) 半導体装置および電子装置
US20230387090A1 (en) Semiconductor package and stacked package module including the same
Jeng et al. Heterogeneous and Chiplet Integration Using Organic Interposer (CoWoS-R)
US9978735B2 (en) Interconnection of an embedded die
CN115377076A (zh) 一种ddr3存储微模组的布线结构和方法
US20210104486A1 (en) Multi-access memory system and a method to manufacture the system
US20210272905A1 (en) Microelectronic package with substrate cavity for bridge-attach
JP2022027742A (ja) 半導体装置及びその製造方法
US20230176953A1 (en) Failover Methods and Systems in Three-Dimensional Memory Device
WO2022261812A1 (zh) 三维堆叠封装及三维堆叠封装制造方法
US20230100228A1 (en) Physical and electrical protocol translation chiplets
WO2024036724A1 (zh) 一种存储系统及电子设备
US20240055373A1 (en) Semiconductor packages

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22913354

Country of ref document: EP

Kind code of ref document: A1