WO2023115612A1 - 键合系统和键合方法 - Google Patents

键合系统和键合方法 Download PDF

Info

Publication number
WO2023115612A1
WO2023115612A1 PCT/CN2021/142026 CN2021142026W WO2023115612A1 WO 2023115612 A1 WO2023115612 A1 WO 2023115612A1 CN 2021142026 W CN2021142026 W CN 2021142026W WO 2023115612 A1 WO2023115612 A1 WO 2023115612A1
Authority
WO
WIPO (PCT)
Prior art keywords
die
bonding
wafer
deviation value
bonded
Prior art date
Application number
PCT/CN2021/142026
Other languages
English (en)
French (fr)
Inventor
田应超
刘天建
曹瑞霞
汪松
Original Assignee
湖北三维半导体集成创新中心有限责任公司
湖北江城实验室
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 湖北三维半导体集成创新中心有限责任公司, 湖北江城实验室 filed Critical 湖北三维半导体集成创新中心有限责任公司
Priority to EP21946241.3A priority Critical patent/EP4227979A4/en
Publication of WO2023115612A1 publication Critical patent/WO2023115612A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H01L21/681—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment using optical controlling means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67144—Apparatus for mounting on conductive members, e.g. leadframes or conductors on insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6831—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using electrostatic chucks
    • H01L21/6833—Details of electrostatic chucks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/741—Apparatus for manufacturing means for bonding, e.g. connectors
    • H01L24/742—Apparatus for manufacturing bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/98—Methods for disconnecting semiconductor or solid-state bodies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/5442—Marks applied to semiconductor devices or parts comprising non digital, non alphanumeric information, e.g. symbols
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/5448—Located on chip prior to dicing and remaining on chip after dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525—Means for applying energy, e.g. heating means
    • H01L2224/753—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/75301—Bonding head
    • H01L2224/75302—Shape
    • H01L2224/7531—Shape of other parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7565—Means for transporting the components to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/757—Means for aligning
    • H01L2224/75723—Electrostatic holding means
    • H01L2224/75725—Electrostatic holding means in the upper part of the bonding apparatus, e.g. in the bonding head
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/757—Means for aligning
    • H01L2224/75743—Suction holding means
    • H01L2224/75745—Suction holding means in the upper part of the bonding apparatus, e.g. in the bonding head
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/757—Means for aligning
    • H01L2224/75753—Means for optical alignment, e.g. sensors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/759—Means for monitoring the connection process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/7999—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto for disconnecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80009—Pre-treatment of the bonding area
    • H01L2224/8001—Cleaning the bonding area, e.g. oxide removal step, desmearing
    • H01L2224/80013—Plasma cleaning
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8012—Aligning
    • H01L2224/80121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H01L2224/8013—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8012—Aligning
    • H01L2224/80121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H01L2224/80132—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed outside the semiconductor or solid-state body, i.e. "off-chip"
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8034—Bonding interfaces of the bonding area
    • H01L2224/80357—Bonding interfaces of the bonding area being flush with the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80908—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding involving monitoring, e.g. feedback loop
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/98—Methods for disconnecting semiconductor or solid-state bodies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06524—Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06593—Mounting aids permanently on device; arrangements for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75—Apparatus for connecting with bump connectors or layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices

Definitions

  • Embodiments of the present disclosure relate to a bonding system and a bonding method.
  • the three-dimensional integration of semiconductor devices can be realized by using bonding technology.
  • bonding technology By bonding two or more semiconductor structures with the same or different functions, the performance of the chip can be improved, and at the same time, the metal interconnection between the objects to be bonded can be greatly shortened, and heat generation, power consumption and delay can be reduced.
  • the bonding process can be distinguished by bonding object, including wafer to wafer (wafer to wafer) bonding, chip (or called die) to wafer (die to wafer) bonding and chip to chip (die to die) Bond.
  • An embodiment of the present disclosure provides a bonding system, including:
  • a bonding assembly comprising: a bonding head for picking up a first die, and a first optical path passing through the bonding head; wherein, the first end of the first optical path is located at the point where the bonding head picks up a pick-up face of the first die;
  • Wafer carrying table used for carrying wafer
  • the first alignment component located at the second end of the first optical path, is used to determine the distance between the current position of the first die and the first target position according to the detection optical signal transmitted in the first optical path.
  • a second alignment component located on a side of the wafer stage relatively away from the bonding component, for determining a second deviation value between the current position of the second die on the wafer and the second target position;
  • the wafer carrier is further configured to drive the carried wafer to move relative to the pick-up surface according to the first deviation value and the second deviation value, so that the second die is aligned with the the first die;
  • the bonding assembly is also used to bond the first die and the second die;
  • a third alignment component located on a side of the wafer carrier relatively away from the bonding component, for determining the position of the bonded first die and the position of the second die The third deviation value between;
  • the bonding assembly is further configured to debond the first die and the second die when the third deviation value is greater than a preset threshold.
  • the third alignment component is located adjacent to the second alignment component, wherein when the detection field of view of the second alignment component covers the second die, the The detection field of view of the third alignment component covers a third die adjacent to the second die; the third die is a bonded die on the wafer; the third die is Bonding to the fourth die is completed.
  • the wafer stage is further configured to relatively The pick face is moved to align the fourth die with the pick face of the bonding assembly.
  • the bonding assembly is further configured to pick up the fourth die and provide a pulling force to the fourth die when the fourth die is aligned with the pick-up surface, so as to The fourth die is debonded from the third die.
  • the bonding system includes:
  • Two groups of the third alignment components are respectively located at adjacent positions on both sides of the second alignment component; wherein, when the bonding components are bonded along the first direction of die distribution on the wafer , using the third alignment component different from the bonding component for bonding along the second direction of die distribution on the wafer; wherein, the first direction and the second direction are along the Opposite direction of the wafer surface.
  • the third alignment component and the second alignment component are composed of the same set of lens components
  • the lens assembly is used for determining the second deviation value before bonding the first die and the second die, and for bonding the first die and the second die. After combining, the third deviation value is determined.
  • Embodiments of the present disclosure also provide a bonding method, including:
  • the third deviation value is greater than a preset threshold, the first die and the second die are debonded.
  • the bonding method further includes:
  • the step of determining a third offset value between the bonded position of the first die and the position of the second die is performed.
  • the debonding the first die and the second die when the third deviation value is greater than a preset threshold includes:
  • the wafer When the third deviation value is greater than a preset threshold, the wafer is moved in a second direction so that the positions of the first die and the second die are located at a pick-up position; wherein the second The direction is opposite to the first direction; the pick-up position is a corresponding position of the bonding head that picks up the first die;
  • the first die and the second die are debonded.
  • the bonding method also includes:
  • Embodiments of the present disclosure provide a bonding system and a bonding method.
  • the bonding system can determine a first deviation value between a current position of a first die and a first target position by setting a first alignment component. , setting the second alignment component, can determine the second deviation value between the current position of the second die on the wafer and the second target position, and setting the third alignment component, can determine the first a third deviation value between the position of the die and the position of the second die, and debonding the first die and the second die when the third deviation value is greater than a preset threshold. In this way, it is convenient to rework and bond abnormal dies in time, thereby improving the yield rate of die-to-wafer bonding.
  • FIG. 1 is a schematic diagram of a chip-to-wafer provided by an embodiment of the present disclosure
  • Figure 2a is a first schematic diagram of a bonding system according to an embodiment of the present disclosure
  • Fig. 2b is a partial schematic diagram of a bonding system according to an embodiment of the present disclosure
  • Fig. 2c is a second schematic diagram of a bonding system according to an embodiment of the present disclosure.
  • Fig. 2d is a schematic diagram 3 of a bonding system according to an embodiment of the present disclosure.
  • Fig. 2e is a schematic diagram 4 of a bonding system according to an embodiment of the present disclosure.
  • Fig. 2f is a schematic diagram five of a bonding system according to an embodiment of the present disclosure.
  • FIG. 3 is a sixth schematic diagram of a bonding system according to an embodiment of the present disclosure.
  • FIG. 4 is a seventh schematic diagram of a bonding system according to an embodiment of the present disclosure.
  • Fig. 5 is a schematic diagram eight of a bonding system according to an embodiment of the present disclosure.
  • FIG. 6 is a ninth schematic diagram of a bonding system according to an embodiment of the present disclosure.
  • FIG. 7 is a tenth schematic diagram of a bonding system according to an embodiment of the disclosure.
  • FIG. 8 is a schematic flow chart of a bonding method according to an embodiment of the present disclosure.
  • Fig. 9a is a structural schematic diagram corresponding to a bonding method shown according to an embodiment of the present disclosure.
  • Fig. 9b is a structural schematic diagram 2 corresponding to a bonding method according to an embodiment of the present disclosure.
  • Fig. 9c is a schematic structural diagram corresponding to a bonding method according to an embodiment of the present disclosure.
  • Fig. 9d is a fourth structural schematic diagram corresponding to a bonding method shown according to an embodiment of the present disclosure.
  • Hybrid Bonding As an emerging bonding technology, gradually transfers the bonding process from the back-end (Back End) packaging to the front-end (Front End) wafer production, and compares the unevenness of the back-end packaging.
  • Bonding has many advantages, such as simple process, smaller size, higher I/O density, and no electromigration failure problems.
  • Hybrid bonding is more suitable for making chips with high energy consumption and high bandwidth, such as HBM (High Bandwidth Memory, high bandwidth memory), NPU (Neural-network Processing Unit, neural network processor) or AI (Artificial Intelligence, artificial intelligence) chips wait.
  • the basic steps of the hybrid bonding process are: cleaning, plasma activation, hybrid bonding and annealing.
  • the bonding interface is connected by van der Waals force. If a bonding abnormality (for example, displacement deviation) is detected, the debonding operation can be performed and subsequent rework is performed; after annealing, the bonding interface is connected by a covalent If the bonding is performed again, the bonding interface will be directly damaged, resulting in product failure.
  • the wafer-to-wafer hybrid bonding process since the wafer is a whole, the detection of bonding anomalies and the operation of debonding are relatively easy.
  • the wafer is cut into thousands of chips. If all the chips are bonded and then reworked, the bonding time will be longer, and the bonding interface after rework The activation has long been invalid; on the other hand, the number of chips is large, the re-detection takes a long time, and the economic benefit is low.
  • FIG. 1 shows a schematic diagram of a chip-to-wafer bonding structure.
  • a plurality of chips 10 are sequentially bonded to corresponding positions on the wafer 20, and the plurality of chips 10 can be of the same type, that is, all of them are memory chips, control chips or other chips of the same type.
  • the plasma activation operation is performed uniformly.
  • a plurality of chips of the same type are placed in a plasma atmosphere, so that the surface of the chip is activated, thereby facilitating subsequent connection with atoms on the surface of the wafer through van der Waals force.
  • the plasma atmosphere here can be provided by a plasma activation machine. Since the effect of plasma activation is related to factors such as the layout of the chip surface and the type of chip, multiple chips can be effectively activated in a single batch by using the same type of chip to improve the bonding efficiency.
  • FIG. 1 only shows a part of the bonding structure from chip 10 to wafer 20.
  • the number of chips activated and bonded by a single batch of plasma can be much larger than that shown in FIG. 1. chip quantities shown.
  • the next batch of chips of the next type for example, control chips
  • embodiments of the present disclosure provide a bonding system and a bonding method.
  • FIG. 2a to 2f are schematic diagrams of a bonding system 300 according to an embodiment of the present disclosure.
  • the bonding system 300 includes:
  • a bonding assembly comprising: a bonding head 301 for picking up the first die 11, and a first optical path 302 passing through the bonding head 301; wherein, the first end 302a of the first optical path 302 is located at The bonding head 301 picks up the pick-up surface 301b of the first die 11;
  • Wafer carrying table 303 used for carrying wafer 20;
  • the first alignment component 304 located at the second end 302b of the first optical path 302, is used to determine the current position of the first die 11 according to the detection optical signal transmitted in the first optical path 302. a first deviation value between the first target positions;
  • the second alignment component 305 is located on the side of the wafer stage 303 relatively far away from the bonding component, and is used to determine the current position of the second die 21 on the wafer 20 and the first position of the second target position. Two deviation values;
  • the wafer carrier 303 is further configured to drive the carried wafer 20 to move relative to the pick-up surface 301b according to the first deviation value and the second deviation value, so that the second die 21 aligning the first die 11;
  • the bonding assembly is also used for bonding the first die 11 and the second die 21;
  • the third alignment component 306 is located on the side of the wafer carrier 303 that is relatively far away from the bonding component, and is used to determine the position of the first die 11 that has been bonded and the position of the second die a third deviation value between the positions of 21;
  • the bonding assembly is further configured to debond the first die 11 and the second die 21 when the third deviation value is greater than a preset threshold.
  • the bonding head 301 in the embodiment of the present disclosure may be a cylindrical structure as shown in FIG.
  • the first optical path 302 includes a first end 302a and a second end 302b.
  • the first end 302a is used for outputting a detection light signal and receiving a reflected light signal
  • the second end 302b is used for receiving a detection light signal and outputting a reflected light signal.
  • the first optical path 302 allows detection light signals and reflected light signals to pass through, and can be a transparent window set in the bonding head 301, or an optical transmission medium set in the bonding head 301, such as an optical fiber or a waveguide.
  • the inside of the first optical path 302 includes a first mirror 3021, and the first reflective mirror 3021 is located between the first end 302a of the first optical path 302 and the second end 302b of the first optical path 302, for connecting the first
  • the detection optical signal received by the second end 302b of the optical path 302 is reflected to the first end 302a of the first optical path 302, and is also used to reflect the reflected optical signal received by the first end 302a of the first optical path 302 to the first optical path.
  • the second end 302b of the channel 302 is also used to reflect the reflected optical signal received by the first end 302a of the first optical path 302 to the first optical path.
  • the above-mentioned first light path 302 can directly pass through the bonding head 301 along the z direction in FIG.
  • the second end 302b of the passage 302 is correspondingly disposed on the top surface 301a of the bonding head 301 , so that the first optical passage 302 may not be provided with the first reflective mirror 3021 .
  • the bonding head 301 can absorb the first die 11 through vacuum adsorption or electrostatic adsorption.
  • the first die 11 may include a bonding surface and a non-bonding surface oppositely arranged.
  • the pick-up surface 301b picks up the first Die 11.
  • the first die 11 includes: a semiconductor chip, for example, a memory chip, a communication chip, an artificial intelligence chip, an LED (Light-emitting Diode, light-emitting diode) chip, a sensor chip, or a display chip.
  • a semiconductor chip for example, a memory chip, a communication chip, an artificial intelligence chip, an LED (Light-emitting Diode, light-emitting diode) chip, a sensor chip, or a display chip.
  • the first die 11 includes a front side and a back side oppositely arranged along the z direction.
  • the front side of the first die 11 is provided with a functional structure
  • the front side of the first die 11 is a bonding surface
  • the first die 11 is a bonding surface.
  • the back surface of the die 11 is a non-bonding surface.
  • first die 11, the wafer 20 and the second die 21 are not included in the bonding system 300, the first die 11, the wafer 20 and the second die 21 (dotted line (shown) is only a schematic diagram, so as to facilitate the understanding of the positional relationship between the die to be bonded, the bonding head, and the wafer during die-to-wafer bonding.
  • the bonding assembly further includes: a fixed unit 307 and a mobile unit 308, wherein the fixed unit 307 is fixedly connected to the top surface 301a of the bonding head 301 and the mobile unit 308, and the mobile unit 308 is used for opposing the wafer carrier 303 moves the bond head 301 .
  • the wafer carrier 303 may include: a chuck (not shown in the figure), for example, an electrostatic chuck (ESC chuck), used to attract the wafer 20 .
  • a chuck for example, an electrostatic chuck (ESC chuck), used to attract the wafer 20 .
  • ESC chuck electrostatic chuck
  • the table top of the wafer carrier 303 for carrying the wafer 20 itself is not movable, but the wafer carrier 303 includes a lifting pin (Lift pin) that can move relative to the pick-up surface 301b, by driving the loading pin relative to The movement of the pick-up surface 301b can further drive the wafer 20 to move relative to the pick-up surface 301b to realize the position adjustment of the wafer 20 .
  • a vacuum hole may be provided on the loading needle, and the wafer may be sucked by vacuum.
  • the loading needle can move in a plane parallel to the wafer 20 to drive the movement of the wafer 20 so as to adjust the position of the wafer 20 .
  • the electrostatic chuck includes a fixed substrate and loading pins, and the loading needle passes through the fixed substrate along the axial direction of the electrostatic chuck, and can move along the direction perpendicular to the fixed substrate and parallel to the fixed substrate.
  • the direction of the substrate moves.
  • the loading pins may be in contact with the wafer 20 when the electrostatic chuck is carrying the wafer 20 .
  • the loading pin moves toward the pick-up surface 301b along a direction perpendicular to the fixed substrate, the loaded wafer 20 is lifted by the loading pin and separated from the fixed base, and the loaded wafer 20 moves along with the loading pin.
  • the wafer 20 includes a plurality of second dies 21, each second die 21 includes a substrate and a functional structure (for example, a storage array or a functional circuit) on the substrate, and two adjacent second dies 21 There are cutting lines between them.
  • a functional structure for example, a storage array or a functional circuit
  • the first alignment component 304 may include an aligner 3041 and a second optical path 3042, wherein the aligner 3041 is used to send a detection optical signal, receive a reflected optical signal, and determine the first die 11 The first deviation value between the current position of and the first target position.
  • the aligner 3041 emits a detection light signal, and the detection light signal is transmitted to the positioning mark of the first die 11 through the second light path 3042 and the first light path 302 ( FIG. 2b), and form a reflected optical signal, which is transmitted back to the aligner 3041 through the first optical path 302 and the second optical path 3042 .
  • the first alignment component 304 involved in the embodiment of the present disclosure is located on the opposite side of the wafer stage 303 to the bonding component, and determines the first deviation value by detecting optical signals and reflected optical signals.
  • the second alignment assembly 305 and the third alignment assembly 306 are located on the side of the wafer stage 303 opposite to the bonding assembly, that is, the wafer stage 303 is relatively far away from the bonding assembly. side of the component.
  • the second alignment component 305 and the third alignment component 306 involved in the embodiment of the present disclosure may be the same set of alignment components, or may be two sets of alignment components independent of each other.
  • the second alignment component 305 can determine the second deviation value between the current position of the second die 21 and the second target position according to the positioning mark of the second die 21 on the wafer 20, and the third alignment component 306 can The third deviation value is determined according to the positioning marks on the first die 11 and the positioning marks on the second die 21 after the bonding is completed.
  • the bonding assembly can be moved in a horizontal direction (for example, x direction or y direction), and the bonding assembly Adjust to first position.
  • the first position refers to the position where the second end 302 b of the first optical path 302 can receive the detection optical signal emitted by the first alignment component 304 .
  • the first alignment assembly 304 sends a detection optical signal, and the detection optical signal passes through the second end 302b of the first optical path 302 and the second end 302b of the first optical path 302.
  • One end 302a is transmitted to the alignment mark of the first die 11 .
  • the positioning mark here can be a patterned structure composed of metal material or other materials with light reflection ability, so that the detection light signal forms a reflected light signal on the surface of the positioning mark, and the reflected light signal passes through the first optical path 302
  • the one end 302a and the second end 302b are transmitted back to the first alignment assembly 304 .
  • the distance between the coordinate point on , and the coordinate point corresponding to the first target position, and the numerical result has a sign, and the sign here indicates the direction.
  • the result of ⁇ x T in the first deviation value is positive, it means that the coordinate of the first die 11 on the x-axis is located in the positive direction of the first target position along the x-axis, and the distance is the absolute value of ⁇ x T ;
  • the result of ⁇ x T in the first deviation value is negative, it means that the coordinate of the first die 11 on the x-axis is located in the negative direction of the first target position along the x-axis, and the distance is also ⁇ x T the absolute value of .
  • first target position and the second target position have the same position in the horizontal direction and different positions in the vertical direction. That is, x 0 is the same as x 0 ', y 0 is the same as y 0 ', the coordinates in the z direction of the first target position and the second target position are different, and the different reference signs are only for the convenience of distinguishing the first target position and the second target location, and is not intended to limit the disclosure.
  • standard dies can be used to calibrate the positions of the first alignment component, the second alignment component, and the bonding component, so as to ensure that the first alignment component can be aligned with the first alignment component.
  • the second end of the light path is aligned, and the second alignment component is ensured to be aligned with the positioning marks on the surface of the standard die facing the wafer carrier, thereby determining the first target position and the second target position.
  • the first target position represents the position of the standard die after calibration
  • the coordinates in the horizontal direction are marked as (x 0 , y 0 )
  • the position at a preset distance from the first target position in the vertical direction is marked as the second target position
  • the horizontal coordinates of the second target position are marked as (x 0 , y 0 ), where the preset distance is greater than zero.
  • the first die 11 is located on the same level as the first target position, and the second die 21 is located on the same level as the second target position. Therefore, subsequent alignment operations can be performed according to the first offset value ( ⁇ x T , ⁇ y T ) and the second offset value ( ⁇ x B , ⁇ y B ).
  • first die 11 when the first die 11 is at the first target position and the second die 21 is at the second target position, it can be considered that the first die 11 and the second die 21 are aligned, that is, along the vertical line direction, The projection of the first die 11 on the surface of the wafer 20 overlaps with the second die 21 .
  • the current position of the first die 11 represents the actual position of the first die 11 when the bonding assembly is adjusted to the first position, which may deviate from the first target position.
  • the current position of the second die 21 represents the actual position of the second die 21 when the wafer 20 is placed on the wafer stage 303 and the die to be bonded on the wafer 20 is determined to be the second die 21. position, which may be offset from the second target position.
  • the first deviation value and the second deviation value are both zero, and the wafer is moved upwards vertically 20 or move the bonding head 301 vertically downwards to achieve precise alignment bonding of the first die 11 and the second die 21 .
  • the displacement deviation between the first die 11 and the second die 21 can be determined according to the first deviation value and the second deviation value It is: ( ⁇ x T - ⁇ x B , ⁇ y T - ⁇ y B ).
  • the wafer stage 303 drives the wafer 20 to move horizontally ( ⁇ x T - ⁇ x B , ⁇ y T - ⁇ y B ) according to the displacement deviation, so that the first die 11 and the second die 21 are aligned, that is, the first die 11 It is the same as the position of the second die 21 in the horizontal direction.
  • the direction in which the wafer stage 303 drives the wafer 20 to move can be determined according to the positive or negative value of ⁇ xT - ⁇ xB .
  • ⁇ xT - ⁇ xB is a negative value
  • the wafer stage 303 drives the wafer 20 along x
  • the axis moves in the negative direction
  • the moving distance is the absolute value of ( ⁇ x T - ⁇ x B ).
  • ⁇ x T ⁇ x B is a positive value
  • the wafer carrier 303 drives the wafer 20 to move along the positive direction of the x-axis, and the moving distance is ( ⁇ x T ⁇ x B ).
  • the direction in which the wafer stage 303 drives the wafer 20 to move can be determined according to the positive or negative value of ⁇ yT - ⁇ yB .
  • the wafer stage 303 drives the wafer 20 to move along The y-axis moves in the negative direction, and the moving distance is the absolute value of ( ⁇ y T - ⁇ y B ).
  • the wafer stage 303 drives the wafer 20 to move along the positive direction of the y-axis, and the moving distance is ( ⁇ y T ⁇ y B ).
  • a bonding assembly may be used to move relative to the wafer 20 so that the first die 11 is aligned with the second die 11.
  • Die 21 the wafer 20 can be kept fixed (that is, the second die 21 can be kept fixed), and the bonding assembly can be moved horizontally according to the displacement deviation ( ⁇ x T ⁇ x B , ⁇ y T ⁇ y B ), so that the first die 11 and the second die 11 The two dies 21 are aligned.
  • the moving direction of the bonded component can be determined according to the positive or negative value of ⁇ x T - ⁇ x B.
  • ⁇ x T - ⁇ x B is a negative value
  • the bonded component moves along the positive direction of the x-axis, and the moving distance is ( ⁇ x T - the absolute value of ⁇ x B ).
  • ⁇ x T - ⁇ x B is a positive value
  • the bonding assembly moves along the negative direction of the x-axis, and the moving distance is ( ⁇ x T - ⁇ x B ).
  • the moving direction of the bonded component can be determined according to the positive or negative value of ⁇ y T - ⁇ y B , for example, when ⁇ y T - ⁇ y B is negative, the bonded component moves along the positive direction of the y-axis, and the moving distance is ( ⁇ y Absolute value of T - ⁇ y B ).
  • ⁇ y T - ⁇ y B is a positive value, the bonding assembly moves along the negative direction of the y-axis, and the moving distance is ( ⁇ y T - ⁇ y B ).
  • the bonding assembly can drive the bonding head 301 vertically downward along the z-axis (shown by the arrow in the figure) Move to perform bonding operations.
  • the first alignment component 304, the second alignment component 305, and the third alignment component 306 in the embodiment of the present disclosure are arranged outside the keying component, so that the weight of the keying component will not be additionally increased, and the keying component can be made
  • the inertia is small; moreover, it can ensure the high-frequency and high-precision movement of the bonding assembly in the vertical direction, and can improve the bonding efficiency while improving the bonding accuracy.
  • the bonded first die 11 and the second die 21 are connected on the surface of the wafer 20 by van der Waals force.
  • the bonding head 301 moves in the vertical direction, which may cause a displacement deviation. Therefore, the position of the first die 11 and the position of the second die 21 that have been bonded can be determined by the third alignment component 306 The third deviation value between them, and then determine whether the first die 11 and the second die 21 meet the bonding requirements and need to be reworked.
  • FIG. 2 d shows the first die 11 and the second die 21 after the bonding operation is completed according to the embodiment of the present disclosure.
  • the positioning marks of the embodiment of the present disclosure include: a first positioning mark 110 located on the first die 11 , and a second positioning mark 210 located on the second die 21 .
  • both the first positioning mark 110 and the second positioning mark 210 can be patterned structures, and can be made of metal material or other materials with light reflection ability, so that the detection light signal can form a reflected light signal at the positioning mark.
  • the third alignment component 306 is located on the side of the wafer carrier 303 opposite to the bonding component, and can emit a detection light signal.
  • the detection light signal here may be infrared light, which transmits through the silicon material on the wafer 20 , the first die 11 and the second die 21 , but is reflected by the positioning marks.
  • the detection light signal may be sent by a light emitter, such as a light emitting diode or a laser diode; the reflected light signal may be received by a light detector, such as a photodiode or a photomultiplier tube.
  • the light detector can be connected with an image sensor, and the image sensor is used to convert the received reflected light signal into a visualized projection image, and the position of the first die 11 and the position of the second die 21 can be determined according to the projection image.
  • the third deviation value between positions can be provided.
  • the wafer stage 303 may include a transparent window for transmitting the detection light signal sent by the third alignment component 306, or be located outside the light path of the detection light signal, so that the detection light signal can irradiate the wafer.
  • the contact surface of the circle 20 and the wafer carrier 303 may include a transparent window for transmitting the detection light signal sent by the third alignment component 306, or be located outside the light path of the detection light signal, so that the detection light signal can irradiate the wafer.
  • the first positioning mark 110 includes: a light-shielding portion 110a and a light-transmitting portion 110b;
  • the second positioning mark 210 includes: a light-shielding portion 210a and a light-transmitting portion 210b.
  • the light emitter in the third alignment component emits a detection light signal and irradiates it on the second positioning mark 210, wherein part of the detection light signal forms an emission light signal in the light-shielding part 210a, and the rest of the detection light signal continues through the light-transmitting part 210b. Irradiate onto the first positioning mark 110 .
  • the remaining detection light signal forms a reflected light signal on the light-shielding portion 110a of the first positioning mark 110, and is transmitted back to the third alignment component 306 together with the emitted light signal formed on the light-shielding portion 210a of the second positioning mark 210.
  • the projection image corresponding to the first positioning mark 110 and the second positioning mark 210 is finally generated on the image sensor connected to the light detector.
  • Fig. 2e shows two possible first positioning marks 110, second positioning marks 210 and preset patterns.
  • the light-shielding portion 210b of the second positioning mark 210 is also in the shape of a “cross”. If the center of the light-shielding portion 110a and the center of the light-transmitting portion 210b coincide in the projected image, and the distances between the edges of the light-shielding portion 110a and the light-transmitting portion 210b are equal, then it is determined that the third deviation value is smaller than the preset threshold.
  • the coordinate points in the projected image can determine the third deviation value, and when the third deviation value is greater than the preset threshold value, the first A die 11 is debonded and reworked, and the bonding operation is performed again.
  • the first projection of the light-transmitting portion 110 b of the first positioning mark 110 and the second projection of the light-transmitting portion 210 b of the second positioning mark 210 can be obtained on the bonding surface of the first die 11 and the second die 21 . Further, it can be determined whether the bonding condition between the first die 11 and the second die 21 is satisfied by observing whether the pattern formed by the first projection and the second projection satisfies the preset pattern.
  • the light-transmitting portion 110a of the first positioning mark 110 in FIG. 2e may not correspond to the light-shielding portion 210a of the second positioning mark 210, and the scheme of judging the relationship between the third deviation value and the preset threshold value through the projected image should all be It belongs to the scope of protection claimed by the present disclosure.
  • the bonding assembly drives the bonding head 301 to pick up the first die 11 again, and vertically upwards along the positive direction of the z-axis (indicated by the arrow in the figure). shown) to debond the first die 11 from the second die 21 .
  • the bonding, confirming the third deviation value and debonding operations can be performed in sequence. If the second alignment assembly 305 and the third alignment assembly 306 are different sets of alignment assemblies, after bonding the first die 11 and the second die 21, it is necessary to move the wafer carrier 303 to drive the wafer 20 to The second die 21 is aligned with the third alignment assembly 306 and a third offset value is confirmed.
  • next group of dies to be bonded can be bonded, and the bonding of the next group of dies to be bonded is completed, and the third deviation value between the first die 11 and the second die 21 is greater than
  • the threshold is preset, debonding of the first die 11 and the second die 21 is performed.
  • the first deviation value between the current position of the first die 11 and the first target position can be determined, and by setting the second alignment component 305, the wafer can be determined.
  • the second deviation value between the current position of the second die 21 and the second target position, and setting the third alignment component 306 can determine the position of the first die 11 that has been bonded and the second target position.
  • the third alignment component 306 is located adjacent to the second alignment component 305, wherein the detection field of view of the second alignment component 305 covers all When the second die 21 is described, the detection field of view of the third alignment component 306 covers the third die 31 adjacent to the second die 21; The dies that have been bonded; the third die 31 and the fourth die 41 have been bonded.
  • the die-to-wafer bonding in the embodiment of the present disclosure includes sequentially bonding a plurality of plasma-activated dies of the same batch and type to corresponding positions on the wafer 20 .
  • the third die 31 adjacent to the second die 21 in the x-axis direction has been aligned with the corresponding
  • the fourth die 41 is bonded.
  • the third die 31 and the second die 21 are located on the bonding surface of the wafer 20 for hybrid bonding with external chips (for example, the first die 11 and the fourth die 41). structure.
  • the fourth die 41 is a chip of the same type as the first die 11 through plasma activation, including but not limited to semiconductor chips (for example, memory chips or communication chips, etc.), artificial intelligence chips, LED chips, sensor chips or display chip etc.
  • the bonding conditions of the third die 31 and the fourth die 41 can be detected synchronously. Specifically, the detection light signal emitted by the second alignment component 305 is irradiated onto the second die 21, so that the corresponding second positioning mark 210 on the second die 21 is exposed in the detection field of view, so that the first alignment mark 210 before bonding is performed. Determination of the second deviation value.
  • the third alignment component 306 is adjacent to the second alignment component 305 and the third die 31 is adjacent to the second die 21 and includes a third alignment mark.
  • the detection light signal sent by the third alignment component 306 is irradiated on the third die 31, so that the corresponding third positioning mark on the third die 31 can be exposed in the detection field of view, so as to perform the third deviation value after bonding. ok.
  • first alignment mark 110 on the first die 11 corresponds to the second alignment mark 210 on the second die 21
  • fourth alignment mark on the fourth die 41 corresponds to the second alignment mark 210 on the third die 31
  • the positioning marks on the first die 11 and the fourth die 41 can be the same or different, here only the second alignment component 305 and the detection field of view of the third alignment component 306 correspond to each other It is enough to complete the determination of the deviation value by the positioning mark of
  • the first positioning marks 110 may be located at four corners of the first die 11 , and the patterned shape may be a "cross", "L" shape, or a rhombus.
  • the second positioning mark 210 is located on the second die 21, and the detection light signal sent by the second alignment component 305 covers the second positioning mark 210, so that the projection image of the second positioning mark 210 and the projection image of the first positioning mark 110 are formed.
  • a corresponding preset image can be composed.
  • the fourth die 41 is rectangular, and the fourth alignment mark may also be located at four corners of the fourth die 41 , and the patterned shape may be the same as that of the first alignment mark 110 .
  • the detection light signal sent by the third alignment component 306 covers the third positioning mark on the third die, and the formed projection image of the third positioning mark and the projection image of the fourth positioning mark can form a corresponding preset image, And the above two preset images should be the same.
  • the third alignment component 306 adjacent to the second alignment component 305 may have the same structure as the second alignment component 305, that is, the number of lenses, the distance between the lenses, and the position of the lenses are the same. Therefore, the functions of the second alignment component 305 and the third alignment component 306 can be replaced with each other.
  • the detection field of view of the third alignment component 306 covers the second die 21
  • the detection field of view of the second alignment component 305 covers the third die 31 adjacent to the second die 21 , and the bonding of the third die 31 and the fourth die 41 has been completed.
  • the third alignment component 306 in the embodiment of the present disclosure may be located at the adjacent position of the second alignment component 305 in the y-axis direction, or include at least two, respectively located at the second alignment component 305 Adjacent positions in the x-axis and y-axis directions, which need to be determined according to the bonding sequence from the die to the wafer during the actual bonding process.
  • Embodiments of the present disclosure employ adjacent second alignment assemblies 305 and third alignment assemblies 306, one of which is used to align the die currently performing the bonding operation, and synchronously, the other is used to detect completed bonding combined die. In this way, the efficiency of detection and bonding is greatly improved, and the bonding can be released in time, and the dies that do not meet the bonding conditions can be reworked, thereby increasing the yield of products.
  • the wafer carrier 303 is also used for a fourth deviation value between the position of the third die 31 and the position of the fourth die 41 When greater than the preset threshold, move relative to the pick-up surface 301b, so that the fourth die 41 is aligned with the pick-up surface 301b of the bonding assembly.
  • the alignment operation in the embodiment of the present disclosure is performed by moving the wafer carrier 303, specifically, the wafer carrier 303 is used to drive the carried wafer according to the horizontal offset of the first deviation value and the second deviation value 20 moves relative to the pick-up surface 301 b to align the second die 21 with the first die 11 .
  • the size of the wafer 20 is relatively large compared to the size of the bonding head 301.
  • the bonding surface of the wafer 20 is less likely to fluctuate in the horizontal plane, that is, it is less likely to fluctuate with the first tube.
  • the second die 21 bonded to the core 11 is relatively horizontal, which is beneficial to improve the bonding accuracy from the die to the wafer.
  • the bonding operation in the embodiment of the present disclosure is performed by moving the bonding head 301, specifically, the bonding assembly is used to drive the bonding head 301 vertically according to the vertical distance between the first target position and the second target position. straight down, so that the first die 11 picked up by the bonding head 301 is bonded to the second die 21 on the wafer 20 .
  • This is because the size and mass of the bonding head 301 relative to the wafer carrier 303 are relatively small, so the inertia is small, and it can move quickly and at high frequency, which is beneficial to improving the bonding efficiency from the die to the wafer.
  • the fourth deviation between the position of the third die 31 and the position of the fourth die 41 is determined by the third alignment component 306 value.
  • the confirmation method of the fourth deviation value here may be the same as the confirmation method of the third deviation value between the position of the first die 11 and the position of the second die 21 in the above-mentioned embodiment, that is, according to the reflected light signal, the first The projections of the positioning marks on the third die 31 and the fourth die 41 are transformed into visualized images, and the fourth deviation value is determined according to the position coordinates in the projected images.
  • the fourth deviation value is smaller than the preset threshold, it means that the third die 31 and the fourth die 41 meet the bonding conditions, and there is no need to perform a rework operation. If the fourth deviation value is greater than the preset threshold, it indicates that a displacement deviation occurs between the third die 31 and the fourth die 41 , and a rework operation needs to be performed.
  • the rework operation here refers to debonding the third die 31 and the fourth die 41 when the material on the surface of the die is still in a state of plasma activation, and bonding after realignment.
  • the bonding assembly needs to be lifted up to a certain height to prevent the wafer carrier 303 from driving the wafer.
  • the bonding head 301 is in contact with the bonded die.
  • the bonding assembly drives the bonding head 301 to move vertically upward for a certain distance, keep it fixed, and drive the wafer 20 to move relative to the pick-up surface 301b of the bonding head 301 in the direction of the arrow, so that the bonded
  • the fourth die 41 is aligned to the pick face 301b.
  • the bonding assembly, the first alignment assembly 304 , the second alignment assembly 305 and the third alignment assembly 306 remain stationary.
  • the first alignment component 304 can be used again to determine whether the fourth die 41 is aligned with the pick-up surface 301b.
  • the first alignment component 304 uses the aligner 3041 to send out a detection light signal, and the detection light signal is transmitted to the first light path 302 through the second light path 3042 , and from the first light path 302
  • the second end 302b of the first optical path 302 is received, the direction of the optical path is adjusted through the first reflector 3021, and the first end 302a of the first optical path 302 is transmitted to the positioning mark (not shown in the figure) of the fourth die 41, thereby forming reflected light
  • the reflected optical signal is transmitted back to the aligner 3041 through the first optical path 302 and the second optical path 3042 .
  • the fourth die 41 is located at the first target position, it means that the fourth die 41 is aligned with the pick-up surface 301 b of the bonding head 301 , and subsequent debonding operations can be performed.
  • the bonding assembly is also used to pick up the fourth die 41 when the fourth die 41 is aligned with the pick-up surface 301b, and The fourth die 41 provides a pulling force to debond the fourth die 41 from the third die 31 .
  • the bonding assembly drives the bond head 301 to move vertically downward until the pick-up surface 301b of the bond head 301 is aligned with the fourth die.
  • the die 41 is contacted to pick up the fourth die 41 again.
  • the pick-up surface 301 b of the bonding head 301 may include holes or free charges, so that the bonding head 301 can re-attach the fourth die 41 by vacuum adsorption or electrostatic adsorption.
  • the fourth die 41 may include a bonding surface and a non-bonding surface oppositely arranged. During the re-pickup operation, the pick-up surface absorbs the non-bonding surface of the fourth die 41 through 301b, so as to pick up the fourth die 41 again. .
  • the bonding assembly can use the moving unit 308 to drive the bonding head 301 to move vertically upward in the direction of the arrow in FIG. 6 , and make the bonding head 301 apply a pulling force to the fourth die 41 , thereby generating an upward movement tendency.
  • the pulling force applied by the bonding head 301 to the fourth die 41 is greater than the van der Waals force between the fourth die 41 and the third die 31 , the fourth die 41 and the third die 31 are debonded.
  • debonding may be performed on the bonded first die 11 and the second die 21 when the next group of chips to be bonded is bonded.
  • the embodiment of the present disclosure uses a bonding component to apply a pulling force to the bonded die, so as to realize the debonding between the die and the wafer.
  • the debonding operation occurs before the annealing operation, which is convenient and quick, and can reduce the loss of functional structures on the die, thereby improving the efficiency of bonding and rework.
  • the bonding system 300 includes:
  • Two groups of the third alignment components 306 are respectively located at adjacent positions on both sides of the second alignment component 305; wherein, the bonding components are carried out along the first direction of the die distribution on the wafer 20
  • the third alignment component 306 different from that of the bonding component for bonding along the second direction of die distribution on the wafer 20; wherein, the first direction and the second The direction is the opposite direction along the surface of the wafer 20 .
  • a die array may be distributed on a wafer 20 in an embodiment of the present disclosure, that is, a plurality of dies distributed along the x-axis and y-axis directions, including a second die 21 and a third die 31 wait.
  • the external dies eg, the first die 11 or the fourth die 41 , etc.
  • the y-axis direction to achieve the alignment between the dies, and then use the bonding assembly to drive the bonding head 301 to perform the bonding operation.
  • the second alignment component 305 in the embodiment of the present disclosure is used to determine the current position and the second target position of the die to be bonded (for example, the second die 21 in FIG. 7 ) on the current wafer 20 The second deviation value between them, and then align with the chip to be picked up (for example, the first die 11 in FIG. 7 ).
  • the third alignment component 306 in the embodiment of the present disclosure is used to determine the third deviation value between the dies that have been bonded (for example, the third die 31 and the fourth die 41 in FIG. 7 ), and then determine Is it necessary to debond and perform a rework operation.
  • the wafer carrier 303 drives the wafer 20 to move in the direction of the arrow in the figure, for sequentially aligning the third die 31 and the fourth die 41, the first die 11 and the second die 21 , and the next die to be picked up (not shown in the figure) and the next die to be bonded 51 .
  • the direction of the arrow may be the negative direction of the x-axis in the coordinate system. Therefore, the two groups of third alignment components 306 are respectively located at adjacent positions on both sides of the second alignment component 305 in the direction of the x-axis.
  • a plurality of dies on the wafer 20 are sequentially distributed in the negative direction of the x-axis, and are respectively the next die 51 to be bonded, the second die 21 and the third die 31, and the third die 31 and the fourth die 41 have been bonded, and the first die 11 and the second die 21 are currently performing alignment and bonding operations.
  • the third alignment component 306 corresponding to the third die 31 is used to detect whether the bonding condition is satisfied between the third die 31 and the fourth die 41, and simultaneously, the second alignment component 305 is used to A second deviation value between the current position of the second die 21 and the second target position is determined.
  • the die The round carrier 303 drives the wafer 20 to move a certain distance along the negative direction of the x-axis, so that the detection field of view of the second bonding assembly 305 covers the positioning mark on the next die 51 to be bonded, so as to confirm the next die to be bonded
  • the second deviation value between the current position of 51 and the second target position.
  • the bonding assembly can drive the bonding head 301 to pick up a new die to be picked up again (not shown in the figure), and use the first alignment assembly to determine the first deviation value to facilitate subsequent alignment and bonding operations .
  • the third alignment component 306 previously corresponding to the third die 31 can be used to detect whether the bonding condition between the first die 11 and the second die 21 is satisfied.
  • next die 51 to be bonded is the last die of the wafer 20 in this direction, it means that a row of dies on the wafer 20 has been bonded, and the wafer carrier 303 is required to drive the wafer 20 Move a certain distance in the y-axis direction to continue bonding the next row of dies.
  • the bonding order changes from along the negative direction of the x-axis to along the positive direction of the x-axis, that is, the third die 31 and the fourth die 41 that have been bonded are located at 7 , and confirm the third deviation value through the third bonding component 306 corresponding to the next die 51 to be bonded in FIG. 7 .
  • the above operations are repeated until the batch of dies are sequentially bonded to the wafer 20 .
  • the first direction and the second direction are two opposite directions of the x-axis, respectively.
  • two groups of third alignment components 306 may be respectively located at adjacent positions on both sides of the second alignment component 305 along the y-axis direction, where the first direction and the second direction are two directions of the y-axis respectively. in the opposite direction.
  • the x-axis or y-axis direction of the die array distributed along the surface of the wafer 20 can be sequentially bonded, and the movement distance of the wafer 20 can be reduced by using two sets of third alignment components 306, thereby Save steps, reduce displacement deviation, and improve bonding accuracy.
  • the third alignment component 306 and the second alignment component 305 are composed of the same set of lens components
  • the lens assembly is used to determine the second deviation value before the first die 11 and the second die 21 are bonded, and is used to determine the second deviation value between the first die 11 and the second die. After the die 21 is bonded, the third deviation value is determined.
  • the second alignment component 305 and the third alignment component 306 can also determine the second deviation value and the third deviation value respectively through optical alignment.
  • the optical alignment can be achieved through optical lenses, and the optical lenses of the third alignment component 306 and the second alignment component 305 can be the same group of lens components with the same number, the same distance, and the positions corresponding to the positioning marks.
  • the group of lens components may include a light emitter, such as a light emitting diode or a laser diode, for sending out a detection light signal.
  • the set of lens components may also include a photodetector, such as a photodiode or a photomultiplier tube, for receiving reflected light signals.
  • the light detector can be connected with an image sensor, and the image sensor is used to convert the received reflected light signal into a visualized projection image.
  • the above-mentioned light emitter and light detector can also be integrated in the same lens assembly.
  • the detection optical signal sent by the light emitter covers the positioning marks on the die, and in some embodiments, each positioning mark on the die can be provided with one lens assembly.
  • the second alignment component 305 Before the first die 11 and the second die 21 are bonded, the second alignment component 305 sends out a detection light signal, and irradiates the positioning mark on the second die 21 to form a reflected light signal and transmit it back to the second pair of dies.
  • the quasi-assembly 305 is used to confirm the second deviation value between the current position of the second die 21 and the second target position.
  • the wafer stage 303 drives the wafer 20 so that the third alignment component 306 corresponds to the second die 21 .
  • the first alignment component 304 determines the first deviation value between the current position of the next die to be picked and the first target position
  • the second alignment component 305 determines the difference between the current position and the first target position of the next die to be bonded.
  • the third alignment component 306 is used to confirm a third deviation value between the bonded first die 11 and the second die 21 .
  • the third alignment component 306 emits detection light signals (for example, infrared light), and the positioning marks on the second die 21 and the first die 11 respectively form reflected light signals, and the reflected light signals are transmitted back to the third
  • the alignment component 306 converts the reflected light signal into a visualized projection image through the image sensor, and then the third deviation value between the position of the first die 11 and the position of the second die 21 can be determined.
  • the operation steps can be reduced and the bonding efficiency can be improved through the alignment assembly composed of the same group of lens assemblies.
  • a bonding method comprises the following steps:
  • Step S100 determining a first deviation value between the current position of the picked first die and the first target position
  • Step S200 determining a second deviation value between the current position of the second die on the wafer and the second target position
  • Step S300 moving the wafer according to the first deviation value and the second deviation value, so as to align the first die and the second die;
  • Step S400 after the first die and the second die are aligned, bonding the first die and the second die;
  • Step S500 determining a third deviation value between the position of the first die and the position of the second die after bonding
  • Step S600 When the third deviation value is greater than a preset threshold, debond the first die and the second die.
  • step S200 after the first deviation value is determined, the wafer 20 is transferred to the stage 303, and the second alignment component 305 can be used to determine the current position of the second die 21 on the wafer 20 (x 2 , y 2 )
  • first target position and the second target position have the same position in the horizontal direction and different positions in the vertical direction. That is, x 0 is the same as x 0 ', y 0 is the same as y 0 ', the coordinates in the z direction of the first target position and the second target position are different, and the different reference signs are only for the convenience of distinguishing the first target position and the second target location, and is not intended to limit the disclosure.
  • step S300 according to the first deviation value and the second deviation value, it is determined that the displacement deviation between the first die 11 and the second die 21 is ( ⁇ x T - ⁇ x B , ⁇ y T - ⁇ y B ), and the key can be kept
  • the combined assembly is fixed (that is, the first die 11 is kept fixed), and the wafer stage 303 drives the wafer 20 to move horizontally according to the displacement deviation ( ⁇ x T ⁇ x B , ⁇ y T ⁇ y B ), so that the first die 11 and The second die 21 is aligned, that is, the positions of the first die 11 and the second die 21 in the horizontal direction are the same.
  • step S400 as shown in FIG. 2c and FIG. 9b, after the first die 11 and the second die 21 are aligned, the bonding assembly drives the bonding head 301 to move vertically downward to place the first die 11 is bonded to the second die 21 .
  • step S500 as shown in FIG. 2d and FIG. 9c, after the bonding of the first die 11 and the second die 21 is completed, the optical signal can be visualized as a projected image by means of optical alignment, and according to the image The coordinates determine a third deviation value between the first die 11 and the second die 21 , where the third deviation value is a horizontal displacement deviation.
  • step S600 when the third deviation value is greater than the preset threshold, that is, when the horizontal displacement deviation between the first die 11 and the second die 21 is greater than the preset threshold, press the key
  • the bonding assembly drives the bonding head 301 to apply a pulling force to the first die 11, thereby realizing debonding between the die and the wafer.
  • the unbonding is performed.
  • the movable carrier 303 drives the wafer 20 to perform a bonding operation on the next group of chips to be bonded.
  • the bonding process of the next group of chips to be bonded it is confirmed whether the third deviation value between the first die 11 and the second die 21 is greater than the preset threshold, if so, the bonding of the next group of chips to be bonded is completed Afterwards, debonding of the first die 11 and the second die 21 is performed.
  • the first die 11 in the embodiment of the present disclosure is a die that exists independently of the wafer 20 .
  • the first die 11 refers to an independent die formed after cutting the wafer 20 carrying the plurality of dies. It can be understood that the size of the first die 11 is much smaller than the size of the wafer 20 .
  • the present disclosure by determining the first deviation value between the current position of the first die and the first target position, the second deviation value between the current position of the second die on the wafer and the second target position, and the completing the bonding of a third deviation value between the position of the first die and the position of the second die, and when the third deviation value is greater than a preset threshold, unbonding the first die and the second die Describe the second die. In this way, it is convenient to rework the abnormally bonded die in time, thereby improving the yield rate of die-to-wafer bonding.
  • the bonding method further includes:
  • the step of determining a third offset value between the bonded position of the first die and the position of the second die is performed.
  • step S400 the wafer stage 303 drives the wafer 20 to move along the preset bonding direction, so that the bonded first die 11 and the second die 21 are removed, and then aligned with the wafer The next group of dies to be bonded and the next die to be bonded are picked up, and continue to perform the bonding operation.
  • next group of dies to be bonded and the second die 21 on the wafer may be adjacent dies on the wafer 20, and during the bonding operation of the next die to be bonded, it may be performed Step S500 to determine a third deviation value between the first die 11 and the second die 21 .
  • the first direction in the embodiment of the present disclosure is the direction of the actual bonding sequence, and after the dies in the first direction are sequentially bonded, the first direction can be reversed and the bonding operation can be continued.
  • the debonding the first die and the second die when the third deviation value is greater than a preset threshold includes:
  • the wafer When the third deviation value is greater than a preset threshold, the wafer is moved in a second direction so that the positions of the first die and the second die are located at a pick-up position; wherein the second The direction is opposite to the first direction; the pick-up position is a corresponding position of the bonding head that picks up the first die;
  • the first die and the second die are debonded.
  • step S600 if it is detected that the third deviation value is greater than the preset threshold value, the wafer carrier 303 drives the wafer 20 to move in the opposite direction to the actual first direction, that is, the above-mentioned second direction, so as to re-bond the completed
  • the first die 11 and the second die 21 are placed in corresponding positions of the bonding assembly.
  • the first direction is the direction of the actual bonding sequence
  • the second direction is the opposite direction of the actual bonding sequence.
  • the second direction when the first direction is the positive direction of the x-axis, the second direction is the negative direction of the x-axis; when the first direction is the positive direction of the y-axis, the second direction is the negative direction of the y-axis.
  • the bonding head 301 is driven by the bonding assembly to apply a pulling force to the first die 11, so as to realize the alignment between the die and the bonding head 301. Debonding between wafers.
  • the bonding method also includes:
  • the current dies to be bonded are the first die 11 and the second die 21 , then the previously bonded third die 31 and the second die 21 can be detected.
  • the fourth die 41 is used to determine a fourth deviation value between its positions.
  • the fourth deviation value here can also visualize the light signal as a projected image through optical alignment, and be determined according to the coordinates on the image.
  • the bonding head 301 is driven by the bonding assembly to apply Pulling force, so as to realize the debonding between the die and the wafer.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Die Bonding (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

本公开实施例提供一种键合系统和键合方法。所述键合系统包括：键合组件、晶圆承载台、第一对准组件和第二对准组件；晶圆承载台，用于根据第一对准组件确定的第一偏差值和第二对准组件确定的第二偏差值，驱动承载的晶圆移动，以使第二管芯对准第一管芯；键合组件，用于键合第一管芯和第二管芯；该键合系统还包括第三对准组件，位于晶圆承载台相对远离键合组件的一侧，用于确定已完成键合的第一管芯的位置与第二管芯的位置之间的第三偏差值；键合组件，还用于在第三偏差值大于预设阈值时，解键合第一管芯与第二管芯。

Description

键合系统和键合方法
相关申请的交叉引用
本公开基于申请号为202111594258.5，申请日为2021年12月24日，申请名称为“键合系统和键合方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开实施例涉及一种键合系统和键合方法。
背景技术
在半导体制造领域，采用键合技术可实现半导体器件的三维集成。通过将两个或多个功能相同或不同的半导体结构进行键合，可以提高芯片的性能，同时也可以大幅度缩短待键合对象之间的金属互联，减小发热、功耗和延迟。
键合制程可按键合对象区分，包括晶圆到晶圆(wafer to wafer)键合、芯片(或称为管芯)到晶圆(die to wafer)键合以及芯片到芯片(die to die)键合。
发明内容
本公开实施例提供一种键合系统，包括：
键合组件，包括：用于拾取第一管芯的键合头，以及贯穿所述键合头的第一光通路；其中，所述第一光通路的第一端位于所述键合头拾取所述第一管芯的拾取面；
晶圆承载台，用于承载晶圆；
第一对准组件，位于所述第一光通路的第二端，用于根据所述第一光通路内传输的检测光信号，确定所述第一管芯的当前位置与第一目标位置之间的第一偏差值；
第二对准组件，位于所述晶圆承载台相对远离所述键合组件的一侧，用于确定所述晶圆上第二管芯的当前位置与第二目标位置的第二偏差值；
所述晶圆承载台，还用于根据所述第一偏差值和所述第二偏差值，驱动承载的所述晶圆相对所述拾取面移动，以使所述第二管芯对准所述第一管芯；
所述键合组件，还用于键合所述第一管芯和所述第二管芯；
第三对准组件，位于所述晶圆承载台相对远离所述键合组件的一侧，用于确定已完成键合的所述第一管芯的位置与所述第二管芯的位置之间的第三偏差值；
所述键合组件，还用于在所述第三偏差值大于预设阈值时，解键合所述第一管芯与 所述第二管芯。
在一些实施例中，所述第三对准组件，位于所述第二对准组件的相邻位置，其中，所述第二对准组件的检测视野覆盖所述第二管芯时，所述第三对准组件的检测视野覆盖与所述第二管芯相邻的第三管芯；所述第三管芯为所述晶圆上已完成键合的管芯；所述第三管芯与第四管芯已完成键合。
在一些实施例中，所述晶圆承载台，还用于在所述第三管芯的位置与所述第四管芯的位置之间的第四偏差值大于所述预设阈值时，相对所述拾取面移动，以使所述第四管芯对准所述键合组件的所述拾取面。
在一些实施例中，所述键合组件，还用于在所述第四管芯对准所述拾取面时，拾取所述第四管芯，并向所述第四管芯提供拉力，以使所述第四管芯与所述第三管芯解键合。
在一些实施例中，所述键合系统包括：
两组所述第三对准组件，分别位于所述第二对准组件两侧的相邻位置；其中，所述键合组件沿所述晶圆上管芯分布的第一方向进行键合时，与所述键合组件沿所述晶圆上管芯分布的第二方向进行键合时使用不同的所述第三对准组件；其中，所述第一方向与第二方向为沿所述晶圆表面的相反方向。
在一些实施例中，所述第三对准组件与所述第二对准组件由同一组镜头组件构成；
所述镜头组件用于在所述第一管芯与所述第二管芯键合前，确定所述第二偏差值，且用于在所述第一管芯与所述第二管芯键合后，确定所述第三偏差值。
本公开实施例还提供一种键合方法，包括：
确定拾取的第一管芯的当前位置与第一目标位置之间的第一偏差值；
确定晶圆上的第二管芯的当前位置与第二目标位置之间的第二偏差值；
根据所述第一偏差值和所述第二偏差值，移动所述晶圆，以对准所述第一管芯和所述第二管芯；
在所述第一管芯和所述第二管芯对准后，键合所述第一管芯和所述第二管芯；
确定键合后的所述第一管芯的位置和所述第二管芯的位置之间的第三偏差值；
在所述第三偏差值大于预设阈值时，解键合所述第一管芯和所述第二管芯。
在一些实施例中，所述键合所述第一管芯和所述第二管芯后，所述键合方法还包括：
沿第一方向移动所述晶圆，以使晶圆上的下一待键合管芯与拾取的下一待键合管芯位于相对位置；
执行所述确定键合后的所述第一管芯的位置和所述第二管芯的位置之间的第三偏 差值的步骤。
在一些实施例中，所述在所述第三偏差值大于预设阈值时，解键合所述第一管芯和所述第二管芯，包括：
在所述第三偏差值大于预设阈值时，沿第二方向移动所述晶圆，以使所述第一管芯和所述第二管芯的位置位于拾取位置；其中，所述第二方向为所述第一方向的相反方向；所述拾取位置为拾取所述第一管芯的键合头的对应位置；
利用拾取所述第一管芯的键合头，解键合所述第一管芯和所述第二管芯。
在一些实施例中，所述键合方法还包括：
在所述第一管芯与所述第二管芯位于相对位置时，确定所述晶圆上与所述第二管芯相邻的第三管芯的位置、与已键合在所述第三管芯上的第四管芯位置之间的第四偏差值；
在所述第四偏差值大于所述预设阈值时，解键合所述第三管芯和所述第四管芯。
本公开实施例提供了一种键合系统和键合方法，所述键合系统通过设置第一对准组件，可确定第一管芯的当前位置与第一目标位置之间的第一偏差值，设置第二对准组件，可确定晶圆上第二管芯的当前位置与第二目标位置的第二偏差值，以及设置第三对准组件，可确定已完成键合的所述第一管芯的位置与所述第二管芯的位置之间的第三偏差值，并在第三偏差值大于预设阈值时，解键合所述第一管芯与所述第二管芯。这样，便于及时返工键合异常的管芯，进而提升管芯到晶圆键合的良率。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，除非有特别申明，附图中的图不构成比例限制。
图1为本公开实施例提供的一种芯片到晶圆的示意图；
图2a是根据本公开实施例示出的一种键合系统的示意图一；
图2b是根据本公开实施例示出的一种键合系统的局部示意图；
图2c是根据本公开实施例示出的一种键合系统的示意图二；
图2d是根据本公开实施例示出的一种键合系统的示意图三；
图2e是根据本公开实施例示出的一种键合系统的示意图四；
图2f是根据本公开实施例示出的一种键合系统的示意图五；
图3是根据本公开实施例示出的一种键合系统的示意图六；
图4是根据本公开实施例示出的一种键合系统的示意图七；
图5是根据本公开实施例示出的一种键合系统的示意图八；
图6是根据本公开实施例示出的一种键合系统的示意图九；
图7是根据本公开实施例示出的一种键合系统的示意图十；
图8是根据本公开实施例示出的一种键合方法的流程示意图；
图9a是根据本公开实施例示出的一种键合方法对应的结构示意图一；
图9b是根据本公开实施例示出的一种键合方法对应的结构示意图二；
图9c是根据本公开实施例示出的一种键合方法对应的结构示意图三；
图9d是根据本公开实施例示出的一种键合方法对应的结构示意图四。
附图标记：
10—芯片；20—晶圆；11—第一管芯；21—第二管芯；301—键合头；301a—顶面；301b—拾取面；302—第一光通路；302a—第一光通路的第一端；302b—第一光通路的第二端；3021—第一反射镜；303—晶圆承载台；304—第一对准组件；3041—对准器；3042—第二光通路；305—第二对准组件；306—第三对准组件；307—固定单元；308—移动单元；110—第一定位标记；110a—第一定位标记的遮光部分；110b—第一定位标记的透光部分；210—第二定位标记；210a—第二定位标记的遮光部分；210b—第二定位标记的透光部分；31—第三管芯；41—第四管芯；51—下一待键合管芯。
具体实施方式
下面将结合附图和实施例对本公开的技术方案进一步详细阐述。虽然附图中显示了本公开的示例性实施方法，然而应当理解，可以以各种形式实现本公开而不应被这里阐述的实施方式所限制。相反，提供这些实施方式是为了能够更透彻的理解本公开，并且能够将本公开的范围完整的传达给本领域的技术人员。
在下列段落中参照附图以举例方式更具体的描述本公开。根据下面说明和权利要求书，本公开的优点和特征将更清楚。需说明的是，附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本公开实施例的目的。
在本公开实施例中，术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。
需要说明的是，本公开实施例所记载的技术方案之间，在不冲突的情况下，可以任意组合。
在半导体制造领域，混合键合(Hybrid Bonding)作为新兴的键合技术，将键合工序由后段(Back End)封装逐渐转移到前段(Front End)晶圆制作，并较后段封装的凹凸键合(Bump Bonding)有着诸多优势，例如工艺简单、尺寸更小、I/O密度更大、没有电迁移失效问题等。混合键合更加适用于制作高能耗、高带宽的芯片，例如HBM(High Bandwidth Memory，高带宽存储器)、NPU(Neural-network Processing Unit，神经网络处理器)或AI(Artificial Intelligence，人工智能)芯片等。
混合键合制程的基本工序为：清洗、等离子体激活、混合键合以及退火。通常在退火前，键合界面之间通过范德华力连接，若检测到键合异常(例如，位移偏差)，则可执行解键合操作并后续返工；而在退火后，键合界面之间通过共价键连接，若再执行解键合则会直接破坏键合界面，导致产品失效。
在晶圆到晶圆的混合键合工艺中，由于晶圆是一个整体，键合异常的检测以及解键合的操作相对容易。然而在芯片到晶圆混合键合工艺中，晶圆被切割为成千上百颗芯片，若芯片全部键合之后再检测返工，则键合的耗时较长，返工后的键合界面的激活早已失效；另一方面，芯片的数量较多，重新检测的耗时较长，经济效益低。
示例性地，图1示出了一种芯片到晶圆键合结构的示意图。参照图1所示，多个芯片10依次键合到晶圆20上对应位置，多个芯片10之间可以为相同的类型，即都为存储芯片、控制芯片或其他同类型芯片，这样可以在执行混合键合工艺之前，统一地进行等离子体激活操作。
具体地，将多个同类型芯片(例如，存储器芯片)置于等离子体氛围中，以使芯片表面激活，进而便于后续与晶圆表面的原子通过范德华力连接。示例性地，这里的等离子体氛围可以由等离子体激活机提供。由于等离子体激活的效果与芯片表面的布局以及芯片类型等因素相关，因此，采用同类型芯片可以单批次有效地激活多个芯片，提高键合效率。
可以理解的是，图1中仅示出了芯片10到晶圆20键合结构的局部，在实际键合操作中，单批次等离子体激活并执行键合操作的芯片可以远大于图1中所示的芯片数量。进一步地，在当前已激活的芯片被键合到晶圆20上对应位置后，可以继续激活下一批次、下一类型的芯片(例如，控制芯片)，并将其键合到晶圆上。
另一方面，参照图1所示，在完成键合操作后，可以检测已完成键合操作的芯片是否发生键合异常，若检测到该芯片发生位移偏差或局部损坏等键合异常，则执行解键合操作，将该芯片返工。例如，发生位移偏差的芯片需要位置补偿、重新对准并键合；发 生损坏的芯片需要替换并重新键合。这里，本公开不做过多限制。
进一步地，若上述返工是在芯片键合完成后执行，则待键合的芯片数量较多，键合的耗时较长，导致返工后的键合界面的激活早已失效；另一方面，使得检测的耗时也较长，导致键合效率低，经济效益也低。
有鉴于此，本公开实施例提供一种键合系统和键合方法。
图2a至图2f是根据本公开实施例示出的一种键合系统300的示意图，参照图2a所示，所述键合系统300包括：
键合组件，包括：用于拾取第一管芯11的键合头301，以及贯穿所述键合头301的第一光通路302；其中，所述第一光通路302的第一端302a位于所述键合头301拾取所述第一管芯11的拾取面301b；
晶圆承载台303，用于承载晶圆20；
第一对准组件304，位于所述第一光通路302的第二端302b，用于根据所述第一光通路302内传输的检测光信号，确定所述第一管芯11的当前位置与第一目标位置之间的第一偏差值；
第二对准组件305，位于所述晶圆承载台303相对远离所述键合组件的一侧，用于确定所述晶圆20上第二管芯21的当前位置与第二目标位置的第二偏差值；
所述晶圆承载台303，还用于根据所述第一偏差值和所述第二偏差值，驱动承载的所述晶圆20相对所述拾取面301b移动，以使所述第二管芯21对准所述第一管芯11；
所述键合组件，还用于键合所述第一管芯11和所述第二管芯21；
第三对准组件306，位于所述晶圆承载台303相对远离所述键合组件的一侧，用于确定已完成键合的所述第一管芯11的位置与所述第二管芯21的位置之间的第三偏差值；
所述键合组件，还用于在所述第三偏差值大于预设阈值时，解键合所述第一管芯11与所述第二管芯21。
本公开实施例中的键合头301可以为图2a中的圆柱形结构，对应的拾取面301b与顶面301a为圆形，第一光通路302位于圆柱形结构的内部，进而贯穿所述键合头301，这样第一光通路302的第一端302a和第二端302b可以位于键合头301的表面。
第一光通路302包括第一端302a和第二端302b，第一端302a用于输出检测光信号和接收反射光信号，第二端302b用于接收检测光信号和输出反射光信号。第一光通路302允许检测光信号和反射光信号通过，可以是设置于键合头301内的透明窗口，还可 以是设置于键合头301内的光传输介质，例如，光纤或波导等。
在第一光通路302的内部包括第一反射镜3021，第一反射镜3021位于第一光通路302的第一端302a和第一光通路302的第二端302b之间，用于将第一光通路302的第二端302b接收的检测光信号反射至第一光通路302的第一端302a，还用于将第一光通路302的第一端302a接收的反射光信号反射至第一光通路302的第二端302b。
需要说明的是，在另一些实施例中，上述第一光通路302可以沿图2a中z方向，即垂直于拾取面301b与顶面301a的方向，直接贯穿键合头301，则第一光通路302的第二端302b对应地设置在键合头301的顶面301a，这样第一光通路302可不设置第一反射镜3021。
键合头301可通过真空吸附或静电吸附的方式吸附第一管芯11。第一管芯11可包括相对设置的键合面和非键合面，在进行管芯到晶圆键合时，拾取面301b通过吸附第一管芯11的非键合面，以拾取第一管芯11。
第一管芯11包括：半导体芯片，例如，存储芯片，通信芯片、人工智能芯片、LED(Light-emitting Diode，发光二极管)芯片、传感芯片或显示芯片等。参照图2a所示，第一管芯11包括沿z方向相对设置的正面和背面，当第一管芯11的正面设置有功能结构时，第一管芯11的正面为键合面，第一管芯11的背面为非键合面。
需要强调的是，第一管芯11、晶圆20以及第二管芯21并未包括在键合系统300中，图2a中第一管芯11、晶圆20以及第二管芯21(虚线所示)仅为示意，以便于理解在进行管芯到晶圆键合时，待键合管芯与键合头以及晶圆之间的位置关系。
在一些实施例中，键合组件还包括：固定单元307和移动单元308，其中，固定单元307固定连接键合头301的顶面301a和移动单元308，移动单元308用于相对晶圆承载台303移动键合头301。
晶圆承载台303可包括：卡盘(图中未示出)，例如，静电吸盘(ESC chuck)，用于吸附晶圆20。
在一些实施例中，晶圆承载台303用于承载晶圆20的台面本身不可移动，但晶圆承载台303包括能够相对拾取面301b移动的装载针(Lift pin)，通过驱动该装载针相对拾取面301b移动，进而可驱动晶圆20相对拾取面301b移动，实现晶圆20的位置调整。装载针上可设置有真空孔，通过真空吸附晶圆。装载针可在平行于晶圆20的平面内移动，以驱动晶圆20的移动，从而调整晶圆20的位置。
具体地，以晶圆承载台303包括静电吸盘为例，静电吸盘包括固定基板和装载针， 装载针沿静电吸盘的轴向穿过固定基板，且可沿垂直于固定基板的方向和平行于固定基板的方向移动。当静电吸盘承载有晶圆20时，装载针可与该晶圆20接触。当装载针沿垂直于固定基板的方向朝向拾取面301b运动时，承载的晶圆20被装载针顶起进而与固定基板分离，且承载的晶圆20跟随装载针进行运动。
晶圆20包括多个第二管芯21，每个第二管芯21包括衬底和位于衬底上的功能结构(例如，存储阵列或功能电路)，相邻的两个第二管芯21之间设置有切割道。
参照图2b所示，第一对准组件304可以包括对准器3041以及第二光通路3042，其中，对准器3041用于发出检测光信号、接收反射光信号、并确定第一管芯11的当前位置与第一目标位置之间的第一偏差值。示例性地，在键合组件位于第一位置时，对准器3041发出检测光信号，检测光信号经由第二光通路3042和第一光通路302传输至第一管芯11的定位标记(图2b中“十”字型所示)，并形成反射光信号，反射光信号再经由第一光通路302和第二光通路3042传输回对准器3041。
本公开实施例中所涉及的第一对准组件304位于晶圆承载台303与键合组件相对的一侧，并且通过检测光信号与反射光信号来确定第一偏差值。相对地，参照图2a所示，第二对准组件305和第三对准组件306位于晶圆承载台303与键合组件相背的一侧，即晶圆承载台303相对远离所述键合组件的一侧。可以理解的是，本公开实施例中所涉及的第二对准组件305和第三对准组件306可以是同一组对准组件，也可以是相互独立的两组对准组件。
具体地，第二对准组件305可以根据晶圆20上第二管芯21的定位标记确定第二管芯21的当前位置与第二目标位置的第二偏差值，第三对准组件306可以根据完成键合后第一管芯11上的定位标记与第二管芯21上的定位标记来确定第三偏差值。
示例性地，参照图2a所示，在键合组件的键合头301拾取第一管芯11后，可沿水平方向(例如，x方向或y方向)移动键合组件，并将键合组件调整至第一位置。这里，第一位置表示的是第一光通路302的第二端302b能够接收到第一对准组件304发射的检测光信号的位置。
示例性地，参照图2a和图2b所示，在键合组件位于第一位置时，第一对准组件304发送检测光信号，检测光信号经由第一光通路302的第二端302b和第一端302a传输至第一管芯11的定位标记。这里的定位标记可以是由金属材料或其他具有反光能力的材料组成的图案化结构，以使得检测光信号在定位标记的表面形成反射光信号，该反射光信号再经由第一光通路302的第一端302a和第二端302b传输回第一对准组件304。
示例性地，第一对准组件304在接收到反射光信号后，可根据反射光信号确定第一管芯11的当前位置(x 1，y 1)与第一目标位置(x 0，y 0)之间的第一偏差值(Δx T，Δy T)，其中，Δx T＝x 1-x 0，Δy T＝y 1-y 0。需要说明的是，第一偏差值通过光学对准得到，为水平方向的位移偏差，且数值Δx T以及Δy T并不表示坐标值，而是表示第一管芯11分别在x轴以及y轴上的坐标点与第一目标位置对应的坐标点之间的距离，且数值结果具有正负，这里的正负表示方向。例如，若第一偏差值中的Δx T的结果为正，则表示第一管芯11在x轴上的坐标位于第一目标位置沿x轴的正方向上，距离大小为Δx T的绝对值；反之亦然，若第一偏差值中的Δx T的结果为负，则表示第一管芯11在x轴上的坐标位于第一目标位置沿x轴的负方向上，距离大小同样为Δx T的绝对值。
示例性地，参照图2a所示，可利用第二对准组件305确定晶圆20上第二管芯21的当前位置(x 2，y 2)与第二目标位置(x 0’，y 0’)之间的第二偏差值(Δx B，Δy B)，其中，Δx B＝x 2-x 0’，Δy T＝y 2-y 0’。可以理解的是，这里的第二偏差值也为水平方向的位移偏差，且其中的数值Δx B以及Δy B表示的含义与上述第一偏差值中对应数值的含义相同。
需要指出的是，第一目标位置和第二目标位置在水平方向上的位置相同、竖直方向上的位置不同。即x 0与x 0’相同，y 0与y 0’相同，第一目标位置和第二目标位置z方向的坐标不同，不同的附图标记仅是为了便于区分第一目标位置和第二目标位置，而不用于限制本公开。
进一步地，在管芯到晶圆键合前，可利用标准管芯对第一对准组件、第二对准组件以及键合组件的位置进行校正，以保证第一对准组件能够与第一光通路的第二端对准、且保证第二对准组件能够与标准管芯朝向晶圆承载台的表面的定位标记对准，进而确定第一目标位置和第二目标位置。这里，第一目标位置表示的是校正后标准管芯的位置，水平方向的坐标记为(x 0，y 0)，与第一目标位置竖直方向相距预设距离的位置记为第二目标位置，第二目标位置水平方向的坐标记为(x 0，y 0)，这里，预设距离大于零。可以理解的是，第一目标位置和第二目标位置虽然水平方向(x方向和y方向)上的位置相同，但在三维空间内并不是同一位置，即第一目标位置和第二目标位置在竖直方向(z方向)上的位置不同。
可以理解的是，在标准管芯校正后，第一管芯11与第一目标位置位于同一水平面上，第二管芯21与第二目标位置位于同一水平面上。因此，后续的对准操作可根据第一偏差值(Δx T，Δy T)和第二偏差值(Δx B，Δy B)来执行。
进一步地，当第一管芯11位于第一目标位置，第二管芯21位于第二目标位置时，可认为第一管芯11和第二管芯21对准，即沿铅垂线方向，第一管芯11在晶圆20表面的投影与第二管芯21重叠。
需要强调的是，第一管芯11的当前位置表示的是将键合组件调整至第一位置时，第一管芯11的实际位置，其相对于第一目标位置可能存在偏差。第二管芯21的当前位置表示的是将晶圆20置于晶圆承载台303、且确定晶圆20上需要键合的管芯为第二管芯21时，第二管芯21的实际位置，其相对于第二目标位置可能存在偏差。
在第一管芯11的当前位置为第一目标位置、第二管芯21的当前位置为第二目标位置时，第一偏差值和第二偏差值均为零，通过竖直向上移动晶圆20或竖直向下移动键合头301，即可实现第一管芯11与第二管芯21的精准对位键合。
示例性地，若保持键合组件固定(即保持第一管芯11固定)，则根据第一偏差值和第二偏差值可以确定第一管芯11和第二管芯21之间的位移偏差为：(Δx T-Δx B，Δy T-Δy B)。晶圆承载台303根据位移偏差驱动晶圆20水平移动(Δx T-Δx B，Δy T-Δy B)，以使得第一管芯11和第二管芯21对准，即第一管芯11和第二管芯21在水平方向上的位置相同。
这里，可根据Δx T-Δx B的正负确定晶圆承载台303驱动晶圆20移动的方向，例如，在Δx T-Δx B为负值时，晶圆承载台303驱动晶圆20沿x轴负方向移动，移动的距离为(Δx T-Δx B)的绝对值。在Δx T-Δx B为正值时，晶圆承载台303驱动晶圆20沿x轴正方向移动，移动的距离为(Δx T-Δx B)。
类似地，可根据Δy T-Δy B的正负确定晶圆承载台303驱动晶圆20移动的方向，例如，在Δy T-Δy B为负值时，晶圆承载台303驱动晶圆20沿y轴负方向移动，移动的距离为(Δy T-Δy B)的绝对值。在Δy T-Δy B为正值时，晶圆承载台303驱动晶圆20沿y轴正方向移动，移动的距离为(Δy T-Δy B)。
虽然在本示例中，晶圆承载台303驱动晶圆20相对拾取面301b移动，但在其它示例中，可利用键合组件，相对晶圆20移动，以使第一管芯11对准第二管芯21。例如，可保持晶圆20固定(即保持第二管芯21固定)，键合组件根据位移偏差水平移动(Δx T-Δx B，Δy T-Δy B)，以使得第一管芯11和第二管芯21对准。
这里，可根据Δx T-Δx B的正负确定键合组件移动的方向，例如，在Δx T-Δx B为负值时，键合组件沿x轴正方向移动，移动的距离为(Δx T-Δx B)的绝对值。在Δx T-Δx B为正值时，键合组件沿x轴负方向移动，移动的距离为(Δx T-Δx B)。
类似地，可根据Δy T-Δy B的正负确定键合组件移动的方向，例如，在Δy T-Δy B为负值时，键合组件沿y轴正方向移动，移动的距离为(Δy T-Δy B)的绝对值。在Δy T-Δy B为正值时，键合组件沿y轴负方向移动，移动的距离为(Δy T-Δy B)。
示例性地，参照图2c所示，在第一管芯11和第二管芯21对准后，键合组件可以驱动键合头301沿z轴方向竖直向下(图中箭头所示)移动以执行键合操作。
本公开实施例中的第一对准组件304、第二对准组件305以及第三对准组件306设置于键合组件之外，这样不会额外增加键合组件的重量，可使得键合组件的惯性较小；并且，可保证键合组件在竖直方向上高频率、高精度地运动，提高键合精度的同时，还可提高键合效率。
参照图2d所示，键合后的第一管芯11与第二管芯21通过范德华力在晶圆20的表面上连接。键合过程中，键合头301在竖直方向移动，可能产生位移偏差，因此通过第三对准组件306可以确定已完成键合的第一管芯11的位置与第二管芯21的位置之间的第三偏差值，进而确定第一管芯11与第二管芯21是否达到键合要求，需要返工。
示例性地，图2d示出了本公开实施例完成键合操作的第一管芯11与第二管芯21。参照图2e所示，本公开实施例的定位标记包括：位于第一管芯11上的第一定位标记110，和位于第二管芯21上第二定位标记210。这里的第一定位标记110与第二定位标记210都可以是图案化结构，并且可以由金属材料或其他具有反光能力的材料制成，以使得检测光信号能在定位标记处形成反射光信号。
第三对准组件306位于晶圆承载台303与键合组件相背的一侧，可以发射检测光信号。这里的检测光信号可以是红外光，透射晶圆20、第一管芯11以及第二管芯21上的硅材料，却被定位标记反射。
类似地，在定位标记处形成的反射光信号再传输回第三对准组件306，进而获得第一定位标记110与第二定位标记210之间的投影图像。这里，检测光信号可以由光发射器发出，例如，发光二极管或激光二极管等；反射光信号可以由光探测器接收，例如，光电二极管或光电倍增管等。进一步地，光探测器可以与图像传感器连接，该图像传感器用于将接收的反射光信号转化为可视化的投影图像，根据该投影图像可确定第一管芯11的位置与第二管芯21的位置之间的第三偏差值。上述光发射器和光探测器也可以集成在同一电子器件中，本公开在此不做过多限定。
可以理解的是，晶圆承载台303可以包括透明窗口，用于透过第三对准组件306发出的检测光信号，或者位于检测光信号的光路之外，以使检测光信号能照射到晶圆20 与晶圆承载台303的接触面。
具体地，参照图2e所示，第一定位标记110包括：遮光部分110a和透光部分110b；第二定位标记210包括：遮光部分210a和透光部分210b。第三对准组件中的光发射器发出检测光信号，并照射到第二定位标记210上，其中，部分检测光信号在遮光部分210a形成发射光信号，剩余检测光信号通过透光部分210b继续照射到第一定位标记110上。
进一步地，剩余检测光信号在第一定位标记110的遮光部分110a上形成反射光信号，并与在第二定位标记210遮光部分210a上形成的发射光信号一起传输回第三对准组件306的光探测器中，最终在于光探测器连接的图像传感器上生成第一定位标记110与第二定位标记210对应的投影图像。
这里，若投影图像满足预设图案，则可以确定第三偏差值小于预设阈值；若投影图像不满足预设图案，则可以确定第三偏差值大于预设阈值。图2e示出了两种可能的第一定位标记110、第二定位标记210和预设图案。
以第一定位标记110的遮光部分110a为“十”字型为例，第二定位标记210的透光部分210b对应地也为“十”字型。若投影图像中遮光部分110a的中心与透光部分210b的中心重合，且遮光部分110a的各边缘与透光部分210b的各边缘之间的距离相等，则确定第三偏差值小于预设阈值。反之，则说明第一管芯11与第二管芯21之间产生水平位移偏差，投影图像中的坐标点可以确定第三偏差值，且在第三偏差值大于预设阈值时，需要将第一管芯11解键合并返工，重新执行键合操作。
可以在第一管芯11与第二管芯21的键合面上得到第一定位标记110透光部分110b的第一投影，以及第二定位标记210透光部分210b的第二投影。进一步地，观察第一投影与第二投影组成的图案是否满足预设图案，可以确定第一管芯11与第二管芯21之间是否满足键合条件。
可以理解的是，图2e中第一定位标记110的透光部分110a可以不与第二定位标记210的遮光部分210a对应，通过投影图像判断第三偏差值与预设阈值大小关系的方案都应该属于本公开所要求保护的范围。
进一步地，参照图2f所示，在第三偏差值大于预设阈值时，键合组件驱动键合头301重新拾取第一管芯11，并沿z轴正方向竖直向上(图中箭头所示)移动，以使第一管芯11与第二管芯21解键合。
需要指出的是，若第二对准组件305与第三对准组件306为同一组对准组件，则键合、确认第三偏差值以及解键合操作可以依次进行。若第二对准组件305与第三对准组 件306为不同组对准组件，则键合第一管芯11与第二管芯21后，需要移动晶圆承载台303驱动晶圆20，以使第二管芯21与第三对准组件306对准，并确认第三偏差值。同步地，可对下一组待键合管芯进行键合，在下一组待键合管芯的键合完成，且第一管芯11与第二管芯21之间的第三偏差值大于预设阈值时，再执行第一管芯11与第二管芯21的解键合。
本公开实施例中，通过设置第一对准组件304，可确定第一管芯11的当前位置与第一目标位置之间的第一偏差值，设置第二对准组件305，可确定晶圆上第二管芯21的当前位置与第二目标位置的第二偏差值，以及设置第三对准组件306，可确定已完成键合的所述第一管芯11的位置与所述第二管芯21的位置之间的第三偏差值，并在第三偏差值大于预设阈值时，解键合所述第一管芯11与所述第二管芯21。这样，便于及时返工键合异常的管芯，进而提升管芯到晶圆键合的良率。
在一些实施例中，参照图3所示，所述第三对准组件306，位于所述第二对准组件305的相邻位置，其中，所述第二对准组件305的检测视野覆盖所述第二管芯21时，所述第三对准组件306的检测视野覆盖与所述第二管芯21相邻的第三管芯31；所述第三管芯31为所述晶圆上已完成键合的管芯；所述第三管芯31与第四管芯41已完成键合。
本公开实施例中的管芯到晶圆键合包括将多个同批次、同类型等离子体激活的管芯依次键合到晶圆20上对应的位置。参照图3所示，在对第一管芯11和第二管芯21进行键合操作的过程中，在x轴方向上与第二管芯21相邻的第三管芯31已经与对应的第四管芯41完成键合。这里的第三管芯31与第二管芯21都是位于晶圆20的键合面上，用于与外部芯片(例如，第一管芯11和第四管芯41)实现混合键合的结构。第四管芯41是经过等离子体激活，类型与第一管芯11相同的芯片，包括但不限于半导体芯片(例如，存储芯片或通信芯片等)、人工智能芯片、LED芯片、传感芯片或显示芯片等。
在利用键合头301在z轴方向竖直向下移动第一管芯11时，可以同步地对第三管芯31和第四管芯41的键合情况进行检测。具体地，第二对准组件305发出的检测光信号照射到第二管芯21上，以使第二管芯21上对应的第二定位标记210暴露在检测视野内，从而进行键合前第二偏差值的确定。
对应地，第三对准组件306与第二对准组件305相邻，第三管芯31与第二管芯21相邻，并且包括第三定位标记。通过第三对准组件306发出的检测光信号照射到第三管芯31上，可以使得第三管芯31上对应的第三定位标记暴露在检测视野内，从而进行键合后第三偏差值的确定。
可以理解的是，第一管芯11上的第一定位标记110与第二管芯21上的第二定位标记210对应，第四管芯41上的第四定位标记与第三管芯31上的第三定位标记对应，且第一管芯11与第四管芯41上的定位标记可以相同或不同，这里只需第二对准组件305与第三对准组件306的检测视野内覆盖对应的定位标记完成偏差值的确定即可。
示例性地，若第一管芯11为矩形，则第一定位标记110可以位于第一管芯11的四个角，且图案化形状可以为“十”字、“L”型或菱形等。第二定位标记210位于第二管芯21上，第二对准组件305发出的检测光信号覆盖第二定位标记210，形成的第二定位标记210的投影图像与第一定位标记110的投影图像可以组成对应的预设图像。
示例性地，第四管芯41为矩形，且第四定位标记也可以位于第四管芯41的四个角，图案化形状可以与第一定位标记110相同。这样，第三对准组件306发出的检测光信号覆盖第三管芯上的第三定位标记，形成的第三定位标记的投影图像与第四定位标记的投影图像可以组成对应的预设图像，且上述两个预设图像应该相同。
这样，与第二对准组件305相邻的第三对准组件306可以与第二对准组件305的结构相同，即镜头数量、镜头间距和镜头位置等相同。因此，第二对准组件305与第三对准组件306之间的功能可以相互替换。
示例性地，在第三对准组件306的检测视野覆盖所述第二管芯21时，所述第二对准组件305的检测视野覆盖与第二管芯21相邻的第三管芯31，且第三管芯31与第四管芯41已完成键合。
可以理解的是，本公开实施例中的第三对准组件306可以位于第二对准组件305在y轴方向上的相邻位置，或者包括至少两个，分别位于第二对准组件305在x轴和y轴方向上的相邻位置，这需要根据实际键合过程中管芯到晶圆的键合顺序确定。
本公开实施例采用相邻的第二对准组件305与第三对准组件306，其中一组用于对准当前执行键合操作的管芯，同步地，另一组用于检测已完成键合的管芯。这样，大大提高了检测与键合效率，并且可以及时解键合，返工不满足键合条件的管芯，增加产品的良率。
在一些实施例中，参照图4所示，所述晶圆承载台303，还用于在所述第三管芯31的位置与所述第四管芯41的位置之间的第四偏差值大于所述预设阈值时，相对所述拾取面301b移动，以使所述第四管芯41对准所述键合组件的所述拾取面301b。
本公开实施例中的对准操作通过移动晶圆承载台303来执行，具体地，晶圆承载台303，用于根据第一偏差值和第二偏差值的水平偏移，驱动承载的晶圆20相对拾取面 301b移动，以使第二管芯21对准第一管芯11。这是由于本公开实施例中键合头301的尺寸较小，容易发生波动，可能相对水平面倾斜，导致键合头301拾取的管芯倾斜，影响对准，降低键合精度。而晶圆20的尺寸相对键合头301的尺寸较大，在承载台303驱动晶圆20移动的过程中，晶圆20的键合面在水平面发生波动的几率较小，即与第一管芯11键合的第二管芯21较为水平，有利于提高管芯到晶圆的键合精度。
本公开实施例中的键合操作通过移动键合头301来执行，具体地，键合组件，用于根据第一目标位置与第二目标位置之间的竖直距离，驱动键合头301竖直向下移动，以使键合头301拾取的第一管芯11与晶圆20上的第二管芯21键合。这是由于键合头301相对于晶圆承载台303的尺寸与质量都较小，因此惯性较小，可以快速、高频地移动，有利于提供管芯到晶圆的键合效率。
示例性地，在第三管芯31与第四管芯41键合完成后，通过第三对准组件306确定第三管芯31的位置与第四管芯41的位置之间的第四偏差值。这里的第四偏差值的确认方法与上述实施例中第一管芯11的位置与第二管芯21的位置之间的第三偏差值的确认方法可以相同，即根据反射光信号，将第三管芯31和第四管芯41上的定位标记的投影转化为可视化的图像，并根据投影图像中的位置坐标确定第四偏差值。
若第四偏差值小于预设阈值，则说明第三管芯31与第四管芯41满足键合条件，无需执行返工操作。若第四偏差值大于预设阈值，则说明第三管芯31与第四管芯41之间发生位移偏差，需要执行返工操作。这里的返工操作是指在管芯表面材料还处于等离子体激活的状态下，将第三管芯31与第四管芯41解键合，并重新对准后键合。
参照图4所示，键合组件在执行完当前键合操作，即第一管芯11与第二管芯21的键合后，需要向上提升一定高度，以避免晶圆承载台303在驱动晶圆20移动过程中，键合头301与已键合管芯的接触。进一步地，在键合组件驱动键合头301竖直向上移动一定距离后，保持固定不动，沿箭头方向驱动晶圆20相对键合头301的拾取面301b移动，以将已完成键合的第四管芯41对准拾取面301b。
可以理解的是，在晶圆承载台303驱动晶圆20移动的过程中，键合组件、第一对准组件304、第二对准组件305和第三对准组件306保持固定不动。在晶圆20的移动完成后，可以再利用第一对准组件304确定第四管芯41是否与拾取面301b对准。
示例性地，参照图5所示，第一对准组件304利用对准器3041发出检测光信号，检测光信号经由第二光通路3042传输至第一光通路302，并从第一光通路302的第二端302b接收，经由第一反射镜3021调整光路方向，从第一光通路302的第一端302a传输 至第四管芯41的定位标记(图中未示出)，从而形成反射光信号，反射光信号再经由第一光通路302和第二光通路3042传输回对准器3041。当第四管芯41位于第一目标位置时，说明第四管芯41与键合头301的拾取面301b对准，可执行后续的解键合操作。
在一些实施例中，参照图6所示，所述键合组件，还用于在所述第四管芯41对准所述拾取面301b时，拾取所述第四管芯41，并向所述第四管芯41提供拉力，以使所述第四管芯41与所述第三管芯31解键合。
本公开实施例在第四管芯41与键合头301的拾取面301b对准后，键合组件驱动键合头301竖直向下移动，直至键合头301的拾取面301b与第四管芯41接触，以重新拾取第四管芯41。
示例性地，键合头301的拾取面301b上可以包括孔洞或自由电荷，以使键合头301可通过真空吸附或静电吸附的方式重新吸附第四管芯41。第四管芯41可包括相对设置的键合面和非键合面，在进行重新拾取操作时，拾取面通过301b吸附第四管芯41的非键合面，以重新拾取第四管芯41。
进一步地，键合组件可利用移动单元308驱动键合头301沿图6中箭头方向竖直向上移动，并使键合头301向第四管芯41施加拉力，进而产生向上运动的趋势。在键合头301向第四管芯41施加的拉力大于第四管芯41与第三管芯31之间的范德华力时，第四管芯41与第三管芯31发生解键合。
需要强调的是，上述操作是在第一管芯11与第二管芯21键合时，对已键合的第三管芯31与第四管芯41执行解键合。进一步地，本公开实施例还可在下一组待键合芯片键合时，对已键合的第一管芯11与第二管芯21执行解键合。
由于范德华力是微观作用力，其作用相对较弱，因此本公开实施例采用键合组件向已键合管芯施加拉力，从而实现管芯与晶圆之间解键合。该解键合操作发生在退火操作之前，这样既方便快捷，又可以减少对管芯上功能结构的损耗，进而提高键合与返工的效率。
在一些实施例中，参照图7所示，所述键合系统300包括：
两组所述第三对准组件306，分别位于所述第二对准组件305两侧的相邻位置；其中，所述键合组件沿所述晶圆20上管芯分布的第一方向进行键合时，与所述键合组件沿所述晶圆20上管芯分布的第二方向进行键合时使用不同的所述第三对准组件306；其中，所述第一方向与第二方向为沿所述晶圆20表面的相反方向。
参照图1所示，本公开实施例中的晶圆20上可以分布有管芯阵列，即沿x轴和y 轴方向分布的多个管芯，包括第二管芯21和第三管芯31等。在将外部管芯(例如，第一管芯11或第四管芯41等)依次键合到晶圆20上对应管芯的过程中，可以利用晶圆承载台303驱动晶圆20沿x轴方向或y轴方向移动，以实现管芯之间的对准，再利用键合组件驱动键合头301执行键合操作。
需要强调的是，本公开实施例中的第二对准组件305用于确定当前晶圆20上待键合管芯(例如，图7中第二管芯21)的当前位置与第二目标位置之间的第二偏差值，进而与待拾取芯片(例如，图7中第一管芯11)对准。本公开实施例中的第三对准组件306用于确定已完成键合的管芯(例如，图7中第三管芯31和第四管芯41)之间的第三偏差值，进而判断是否需要解键合，并执行返工操作。
参照图7所示，晶圆承载台303驱动晶圆20沿图中箭头方向移动，用于依次对准第三管芯31与第四管芯41，第一管芯11与第二管芯21，以及下一待拾取管芯(图中未示出)与下一待键合管芯51。这里，箭头方向可以是坐标系中x轴的负方向，因此，两组第三对准组件306在x轴方向上分别位于第二对准组件305两侧的相邻位置。
示例性地，晶圆20上的多个管芯依次分布在x轴负方向上，分别为下一待键合管芯51、第二管芯21以及第三管芯31，并且第三管芯31与第四管芯41已完成键合，第一管芯11与第二管芯21在执行当前的对准、键合操作。进一步地，与第三管芯31对应的第三对准组件306用于检测第三管芯31与第四管芯41之间是否满足键合条件，同步地，第二对准组件305用于确定第二管芯21的当前位置与第二目标位置之间的第二偏差值。
示例性地，在第三管芯31与第四管芯41满足键合条件，即第三偏差值小于预设阈值，且第一管芯11与第二管芯21完成键合操作后，晶圆承载台303驱动晶圆20沿x轴负方向移动一定距离，使得第二键合组件305的检测视野覆盖下一待键合管芯51上的定位标记，以确认下一待键合管芯51的当前位置与第二目标位置之间的第二偏差值。同步地，键合组件可以驱动键合头301重新拾取一个新的待拾取管芯(图中未示出)，并利用第一对准组件确定第一偏差值，便于后续对准、键合操作。这里，先前与第三管芯31对应的第三对准组件306可用于检测第一管芯11与第二管芯21之间是否满足键合条件。
示例性地，当下一待键合管芯51为该方向上晶圆20的最后一个管芯时，说明晶圆20上的一行管芯已完成键合，需要晶圆承载台303驱动晶圆20在y轴方向上移动一定距离，以继续键合下一行管芯。
可以理解的是，在键合下一行管芯时，键合顺序由沿x轴负方向变为沿x轴正方向，即已完成键合的第三管芯31与第四管芯41位于图7中下一待键合管芯51的位置，且通过图7中与下一待键合管芯51对应的第三键合组件306来确认第三偏差值。重复上述操作，直至将该批次管芯依次与晶圆20键合。
在上述实施例中，第一方向和第二方向分别为x轴的两个相反方向。
在另一些实施例中，两组第三对准组件306可以沿y轴方向分别位于第二对准组件305两侧的相邻位置，这里，第一方向和第二方向分别为y轴的两个相反方向。
因此，在本公开实施例中，可以沿晶圆20表面分布的管芯阵列的x轴或y轴方向依次键合，利用两组第三对准组件306可以减少晶圆20的移动距离，从而节约步骤，减少位移偏差，提高键合精度。
在一些实施例中，所述第三对准组件306与所述第二对准组件305由同一组镜头组件构成；
所述镜头组件用于在所述第一管芯11与所述第二管芯21键合前，确定所述第二偏差值，且用于在所述第一管芯11与所述第二管芯21键合后，确定所述第三偏差值。
本公开实施例中，与第一对准组件304类似的，第二对准组件305与第三对准组件306也可以通过光学对准来分别确定第二偏差值和第三偏差值。进一步地，可以通过光学镜头来实现光学对准，且第三对准组件306与第二对准组件305的光学镜头可以是数量相同、间距相同以及位置与定位标记对应的同一组镜头组件。
示例性地，这一组镜头组件中可以包括光发射器，例如，发光二极管或激光二极管等，用于发出检测光信号。这一组镜头组件中还可以包括光探测器，例如，光电二极管或光电倍增管等，用于接收反射光信号。进一步地，光探测器可以与图像传感器连接，该图像传感器用于将接收的反射光信号转化为可视化的投影图像。
可以理解的是，上述光发射器和光探测器也可以集成在同一镜头组件中。其中，光发射器发出的检测光信号覆盖管芯上的定位标记，且在一些实施例中，管芯上的每一个定位标记都可对应设置一个上述镜头组件。
示例性地，参照图2a所示，以键合第一管芯11与第二管芯21为例。在第一管芯11与第二管芯21键合前，第二对准组件305发出检测光信号，并照射到第二管芯21上的定位标记，形成反射光信号并传输回第二对准组件305，以确认第二管芯21的当前位置与第二目标位置之间的第二偏差值。
进一步地，在第一管芯11与第二管芯21键合后，晶圆承载台303驱动晶圆20以 使第三对准组件306与第二管芯21对应。这里，第一对准组件304确定下一待拾取管芯的当前位置与第一目标位置之间的第一偏差值，第二对准组件305确定与下一待键合管芯的当前位置与第二目标位置之间的第二偏差值。同步地，第三对准组件306用于确认已完成键合的第一管芯11与第二管芯21之间的第三偏差值。
具体地，第三对准组件306发出检测光信号(例如，红外光)，分别在第二管芯21与第一管芯11上的定位标记形成反射光信号，该反射光信号传输回第三对准组件306，再通过图像传感器将反射光信号转化为可视化的投影图像，进而可以确定第一管芯11的位置与第二管芯21的位置之间的第三偏差值。
本公开实施例，通过由同一组镜头组件构成的对准组件，可以减少操作步骤，提高键合效率。
根据本公开实施例的第二方面，参照图8所示，提供一种键合方法。所述键合方法包括以下步骤：
步骤S100：确定拾取的第一管芯的当前位置与第一目标位置之间的第一偏差值；
步骤S200：确定晶圆上的第二管芯的当前位置与第二目标位置之间的第二偏差值；
步骤S300：根据所述第一偏差值和所述第二偏差值，移动所述晶圆，以对准所述第一管芯和所述第二管芯；
步骤S400：在所述第一管芯和所述第二管芯对准后，键合所述第一管芯和所述第二管芯；
步骤S500：确定键合后的所述第一管芯的位置和所述第二管芯的位置之间的第三偏差值；
步骤S600：在所述第三偏差值大于预设阈值时，解键合所述第一管芯和所述第二管芯。
在步骤S100中，参照图2a、图2b和图9a所示，可利用第一对准组件304确定第一管芯11的当前位置(x 1，y 1)与第一目标位置(x 0，y 0)之间的第一偏差值(Δx T，Δy T)，其中，Δx T＝x 1-x 0，Δy T＝y 1-y 0。
在步骤S200中，在确定第一偏差值后，将晶圆20传输至承载台303上，可利用第二对准组件305确定晶圆20上第二管芯21的当前位置(x 2，y 2)与第二目标位置(x 0’，y 0’)之间的第二偏差值(Δx B，Δy B)，其中，Δx B＝x 2-x 0’，Δy T＝y 2-y 0’。
需要指出的是，第一目标位置和第二目标位置在水平方向上的位置相同、竖直方向上的位置不同。即x 0与x 0’相同，y 0与y 0’相同，第一目标位置和第二目标位置z方向 的坐标不同，不同的附图标记仅是为了便于区分第一目标位置和第二目标位置，而不用于限制本公开。
在步骤S300中，根据第一偏差值和第二偏差值确定第一管芯11和第二管芯21之间的位移偏差为(Δx T-Δx B，Δy T-Δy B)，可保持键合组件固定(即保持第一管芯11固定)，晶圆承载台303驱动晶圆20根据位移偏差水平移动(Δx T-Δx B，Δy T-Δy B)，以使得第一管芯11和第二管芯21对准，即第一管芯11和第二管芯21水平方向上的位置相同。
在步骤S400中，参照图2c和图9b所示，在第一管芯11和第二管芯21对准后，键合组件驱动键合头301竖直向下移动，以将第一管芯11与第二管芯21键合。
在步骤S500中，参照图2d和图9c所示，在第一管芯11与第二管芯21键合完成后，可通过光学对准的方式将光信号可视化为投影图像，并根据图像上坐标确定第一管芯11与第二管芯21之间的第三偏差值，这里的第三偏差值为水平位移偏差。
在步骤S600中，参照图2f和图9d所示，在第三偏差值大于预设阈值，即第一管芯11与第二管芯21之间的水平位移偏差大于预设阈值时，通过键合组件驱动键合头301向第一管芯11施加拉力，从而实现管芯与晶圆之间解键合。
在一些实施例中，第一管芯11与第二管芯21键合完成后，可立即确认第一管芯11与第二管芯21之间的第三偏差值是否大于预设阈值，若是，则执行解键合。
在另一实施例中，第一管芯11与第二管芯21键合完成后，可移动承载台303驱动晶圆20，以对下一组待键合芯片进行键合操作。在下一组待键合芯片键合过程中，确认第一管芯11与第二管芯21之间的第三偏差值是否大于预设阈值，若是，则在下一组待键合芯片键合完成后，执行第一管芯11与第二管芯21的解键合。
需要强调的是，本公开实施例中的第一管芯11是独立于晶圆20存在的管芯。在半导体器件的制作过程中，通常在晶圆20上形成多个管芯，这里，第一管芯11指的是承载有多个管芯的晶圆20切割后形成的独立管芯。可以理解的是，第一管芯11的尺寸远小于晶圆20的尺寸。
本公开实施例中，通过确定第一管芯的当前位置与第一目标位置之间的第一偏差值、晶圆上第二管芯的当前位置与第二目标位置的第二偏差值以及已完成键合的所述第一管芯的位置与所述第二管芯的位置之间的第三偏差值，并在第三偏差值大于预设阈值时，解键合所述第一管芯与所述第二管芯。这样，可便于及时返工键合异常的管芯，进而提升管芯到晶圆键合的良率。
在一些实施例中，所述键合所述第一管芯和所述第二管芯后，所述键合方法还包括：
沿第一方向移动所述晶圆，以使晶圆上的下一待键合管芯与拾取的下一待键合管芯位于相对位置；
执行所述确定键合后的所述第一管芯的位置和所述第二管芯的位置之间的第三偏差值的步骤。
在执行步骤S400之后，晶圆承载台303驱动晶圆20沿预设的键合方向移动，以使已完成键合的第一管芯11与第二管芯21移走，进而对准晶圆上的下一组待键合管芯与拾取的下一待键合管芯，并继续执行键合操作。
这里，晶圆上的下一组待键合管芯与第二管芯21可以是晶圆20上相邻的管芯，在执行下一待键合管芯的键合操作过程中，可以执行步骤S500以确定第一管芯11与第二管芯21之间的第三偏差值。
需要强调的是，本公开实施例中的第一方向为实际键合顺序的方向，在依次键合完第一方向后的管芯后，第一方向可反向，并继续执行键合操作。
在一些实施例中，所述在所述第三偏差值大于预设阈值时，解键合所述第一管芯和所述第二管芯，包括：
在所述第三偏差值大于预设阈值时，沿第二方向移动所述晶圆，以使所述第一管芯和所述第二管芯的位置位于拾取位置；其中，所述第二方向为所述第一方向的相反方向；所述拾取位置为拾取所述第一管芯的键合头的对应位置；
利用拾取所述第一管芯的键合头，解键合所述第一管芯和所述第二管芯。
在步骤S600中，若检测到第三偏差值大于预设阈值，则晶圆承载台303驱动晶圆20沿实际第一方向的反方向，即上述第二方向移动，以重新将已完成键合的第一管芯11与第二管芯21置于键合组件的对应位置。这里的第一方向为实际键合顺序的方向，第二方向为实际键合顺序的反方向。
示例性地，当第一方向为x轴正方向时，第二方向为x轴负方向；当第一方向为y轴正方向时，第二方向为y轴负方向。
进一步地，在调整第二管芯21重新位于与键合头301的拾取面301b对准的位置时，通过键合组件驱动键合头301向第一管芯11施加拉力，从而实现管芯与晶圆之间解键合。
在一些实施例中，所述键合方法还包括：
在所述第一管芯与所述第二管芯位于相对位置时，确定所述晶圆上与所述第二管芯 相邻的第三管芯的位置、与已键合在所述第三管芯上的第四管芯位置之间的第四偏差值；
在所述第四偏差值大于所述预设阈值时，解键合所述第三管芯和所述第四管芯。
本公开实施例中，参照图3至图7所示，若当前待键合管芯为第一管芯11与第二管芯21，则可检测之前已完成键合的第三管芯31与第四管芯41，以确定其位置之间的第四偏差值。
类似地，这里的第四偏差值也可通过光学对准的方式将光信号可视化为投影图像，并根据图像上坐标确定。
在第四偏差值大于预设阈值，即第三管芯31与第四管芯41之间的水平位移偏差大于预设阈值时，通过键合组件驱动键合头301向第四管芯41施加拉力，从而实现管芯与晶圆之间解键合。
需要说明的是，本公开所提供的几个方法或设备实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的方法实施例或设备实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (10)

  1. 一种键合系统，包括：
    键合组件，包括：用于拾取第一管芯的键合头，以及贯穿所述键合头的第一光通路；其中，所述第一光通路的第一端位于所述键合头拾取所述第一管芯的拾取面；
    晶圆承载台，用于承载晶圆；
    第一对准组件，位于所述第一光通路的第二端，用于根据所述第一光通路内传输的检测光信号，确定所述第一管芯的当前位置与第一目标位置之间的第一偏差值；
    第二对准组件，位于所述晶圆承载台相对远离所述键合组件的一侧，用于确定所述晶圆上第二管芯的当前位置与第二目标位置的第二偏差值；
    所述晶圆承载台，还用于根据所述第一偏差值和所述第二偏差值，驱动承载的所述晶圆相对所述拾取面移动，以使所述第二管芯对准所述第一管芯；
    所述键合组件，还用于键合所述第一管芯和所述第二管芯；
    第三对准组件，位于所述晶圆承载台相对远离所述键合组件的一侧，用于确定已完成键合的所述第一管芯的位置与所述第二管芯的位置之间的第三偏差值；
    所述键合组件，还用于在所述第三偏差值大于预设阈值时，解键合所述第一管芯与所述第二管芯。
  2. 根据权利要求1所述的键合系统，其中，
    所述第三对准组件，位于所述第二对准组件的相邻位置，其中，所述第二对准组件的检测视野覆盖所述第二管芯时，所述第三对准组件的检测视野覆盖与所述第二管芯相邻的第三管芯；所述第三管芯为所述晶圆上已完成键合的管芯；所述第三管芯与第四管芯已完成键合。
  3. 根据权利要求2所述的键合系统，其中，
    所述晶圆承载台，还用于在所述第三管芯的位置与所述第四管芯的位置之间的第四偏差值大于所述预设阈值时，相对所述拾取面移动，以使所述第四管芯对准所述键合组件的所述拾取面。
  4. 根据权利要求3所述的键合系统，其中，
    所述键合组件，还用于在所述第四管芯对准所述拾取面时，拾取所述第四管芯，并向所述第四管芯提供拉力，以使所述第四管芯与所述第三管芯解键合。
  5. 根据权利要求2所述的键合系统，还包括：
    两组所述第三对准组件，分别位于所述第二对准组件两侧的相邻位置；其中，所述键合组件沿所述晶圆上管芯分布的第一方向进行键合时，与所述键合组件沿所述晶圆上管芯分布 的第二方向进行键合时使用不同的所述第三对准组件；其中，所述第一方向与第二方向为沿所述晶圆表面的相反方向。
  6. 根据权利要求1所述的键合系统，其中，所述第三对准组件与所述第二对准组件由同一组镜头组件构成；
    所述镜头组件用于在所述第一管芯与所述第二管芯键合前，确定所述第二偏差值，且用于在所述第一管芯与所述第二管芯键合后，确定所述第三偏差值。
  7. 一种键合方法，包括：
    确定拾取的第一管芯的当前位置与第一目标位置之间的第一偏差值；
    确定晶圆上的第二管芯的当前位置与第二目标位置之间的第二偏差值；
    根据所述第一偏差值和所述第二偏差值，移动所述晶圆，以对准所述第一管芯和所述第二管芯；
    在所述第一管芯和所述第二管芯对准后，键合所述第一管芯和所述第二管芯；
    确定键合后的所述第一管芯的位置和所述第二管芯的位置之间的第三偏差值；
    在所述第三偏差值大于预设阈值时，解键合所述第一管芯和所述第二管芯。
  8. 根据权利要求7所述的方法，其中，所述键合所述第一管芯和所述第二管芯后，所述键合方法还包括：
    沿第一方向移动所述晶圆，以使晶圆上的下一待键合管芯与拾取的下一待键合管芯位于相对位置；
    执行所述确定键合后的所述第一管芯的位置和所述第二管芯的位置之间的第三偏差值的步骤。
  9. 根据权利要求8所述的方法，其中，所述在所述第三偏差值大于预设阈值时，解键合所述第一管芯和所述第二管芯，包括：
    在所述第三偏差值大于预设阈值时，沿第二方向移动所述晶圆，以使所述第一管芯和所述第二管芯的位置位于拾取位置；其中，所述第二方向为所述第一方向的相反方向；所述拾取位置为拾取所述第一管芯的键合头的对应位置；
    利用拾取所述第一管芯的键合头，解键合所述第一管芯和所述第二管芯。
  10. 根据权利要求7至9任一所述的方法，还包括：
    在所述第一管芯与所述第二管芯位于相对位置时，确定所述晶圆上与所述第二管芯相邻的第三管芯的位置、与已键合在所述第三管芯上的第四管芯位置之间的第四偏差值；
    在所述第四偏差值大于所述预设阈值时，解键合所述第三管芯和所述第四管芯。
PCT/CN2021/142026 2021-12-24 2021-12-28 键合系统和键合方法 WO2023115612A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP21946241.3A EP4227979A4 (en) 2021-12-24 2021-12-28 CONNECTION SYSTEM AND CONNECTION PROCEDURE

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202111594258.5A CN113990790B (zh) 2021-12-24 2021-12-24 键合系统和键合方法
CN202111594258.5 2021-12-24

Publications (1)

Publication Number Publication Date
WO2023115612A1 true WO2023115612A1 (zh) 2023-06-29

Family

ID=79734269

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/142026 WO2023115612A1 (zh) 2021-12-24 2021-12-28 键合系统和键合方法

Country Status (3)

Country Link
EP (1) EP4227979A4 (zh)
CN (1) CN113990790B (zh)
WO (1) WO2023115612A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116313971B (zh) * 2023-05-17 2023-10-20 拓荆键科(海宁)半导体设备有限公司 通过边缘检测来进行晶圆键合对准的方法
CN116364636B (zh) * 2023-05-31 2023-07-28 广东鸿浩半导体设备有限公司 一种基于红外成像辅助的激光解键合方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5764366A (en) * 1995-11-30 1998-06-09 Lucent Technologies Inc. Method and apparatus for alignment and bonding
CN1983539A (zh) * 2005-12-12 2007-06-20 先进自动器材有限公司 高精度晶粒键合装置
US20090141275A1 (en) * 2007-12-03 2009-06-04 Samsung Electronics Co., Ltd Alignment inspection method and alignment inspection apparatus
CN102275869A (zh) * 2011-08-03 2011-12-14 苏州大学 一种单芯片和晶圆的键合设备及键合方法
CN111668092A (zh) * 2020-04-24 2020-09-15 北京华卓精科科技股份有限公司 晶圆键合的方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7371663B2 (en) * 2005-07-06 2008-05-13 Taiwan Semiconductor Manufacturing Co., Ltd. Three dimensional IC device and alignment methods of IC device substrates
KR102379168B1 (ko) * 2014-09-16 2022-03-29 삼성전자주식회사 반도체 칩 본딩 장치
KR101882395B1 (ko) * 2016-11-16 2018-07-26 주식회사 엠에스텍 기판 위치정렬 방법 및 그 방법을 사용하는 합착기
WO2019087707A1 (ja) * 2017-11-02 2019-05-09 株式会社ニコン 積層基板の製造方法、製造装置、およびプログラム
CN109451763B (zh) * 2018-05-16 2019-11-08 长江存储科技有限责任公司 用于晶圆键合对准补偿的方法和系统
US10636688B2 (en) * 2018-06-22 2020-04-28 Taiwan Semiconductor Manufacturing Co., Ltd. Method for alignment, process tool and method for wafer-level alignment
DE102018115144A1 (de) * 2018-06-23 2019-12-24 Besi Switzerland Ag Stellantrieb für einen Bondkopf
JP7333710B2 (ja) * 2019-05-28 2023-08-25 東京エレクトロン株式会社 接合装置及び接合方法
JP2023517415A (ja) * 2019-12-10 2023-04-26 エーファウ・グループ・エー・タルナー・ゲーエムベーハー 複数の基板の位置合わせをする方法および装置
JP7391733B2 (ja) * 2020-03-17 2023-12-05 キオクシア株式会社 半導体製造装置及び半導体装置の製造方法
KR102446236B1 (ko) * 2020-04-02 2022-09-22 (주)엘트린 기판 접합 장치.
CN112151444B (zh) * 2020-09-28 2023-04-07 武汉新芯集成电路制造有限公司 晶圆的匹配设计方法、晶圆键合结构以及芯片键合结构
CN113314451B (zh) * 2021-06-10 2022-08-02 哈尔滨工业大学 一种基于莫尔条纹的晶圆键合对准系统及方法
CN113681146B (zh) * 2021-10-25 2022-02-08 宁波尚进自动化科技有限公司 一种全自动引线键合机的bto智能校正装置及方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5764366A (en) * 1995-11-30 1998-06-09 Lucent Technologies Inc. Method and apparatus for alignment and bonding
CN1983539A (zh) * 2005-12-12 2007-06-20 先进自动器材有限公司 高精度晶粒键合装置
US20090141275A1 (en) * 2007-12-03 2009-06-04 Samsung Electronics Co., Ltd Alignment inspection method and alignment inspection apparatus
CN102275869A (zh) * 2011-08-03 2011-12-14 苏州大学 一种单芯片和晶圆的键合设备及键合方法
CN111668092A (zh) * 2020-04-24 2020-09-15 北京华卓精科科技股份有限公司 晶圆键合的方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4227979A4 *

Also Published As

Publication number Publication date
EP4227979A1 (en) 2023-08-16
CN113990790B (zh) 2022-03-18
EP4227979A8 (en) 2024-04-10
EP4227979A4 (en) 2024-04-10
CN113990790A (zh) 2022-01-28

Similar Documents

Publication Publication Date Title
WO2023115612A1 (zh) 键合系统和键合方法
WO2023115610A1 (zh) 键合系统和键合补偿方法
JP6712647B2 (ja) チップボンディング装置及び方法
KR102132094B1 (ko) 전자 부품 실장 장치 및 전자 부품 실장 방법
CN107134419B (zh) 倒装芯片键合装置及其键合方法
TW201826427A (zh) 黏晶機
JP2019507504A (ja) フリップチップ接合装置及び接合方法
JP2005114882A (ja) 処理ステージの基板載置方法、基板露光ステージおよび基板露光装置
US20240170318A1 (en) Teaching Substrate for Production and Process-Control Tools
JP2002083827A (ja) 半導体レーザー装置の製造方法および半導体レーザー装置の製造装置
JP3986196B2 (ja) 光半導体装置の製造方法
KR20220078542A (ko) 마이크로 엘이디 제조시스템 및 마이크로 엘이디 제조방법
TW202030041A (zh) 半導體元件雷射焊接裝置及方法
WO2023115615A1 (zh) 键合系统和键合方法
WO2023115614A1 (zh) 键合系统和键合方法
JPH0818164A (ja) 発光デバイスの組立装置
US20220208720A1 (en) Substrate bonding apparatus and substrate bonding method
JP2022079965A (ja) ウェハ接合装置
CN116092957B (zh) 一种键合系统和键合方法
TW202328660A (zh) 含金屬鍍膜半導體元件的檢測系統
JPH06283819A (ja) 光素子のダイボンディング方法及びそのダイボンディング装置
TW202406026A (zh) 調整接合系統的接合工具組件和支撐結構組件之間的傾斜度的方法、以及相關的接合系統
JP2024036204A (ja) 基板処理装置、および位置測定方法
CN117464220A (zh) 一种全自动焊线机的bto智能校准装置及方法
CN116825904A (zh) 巨量转移的系统及方法

Legal Events

Date Code Title Description
ENP Entry into the national phase

Ref document number: 2021946241

Country of ref document: EP

Effective date: 20221226

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21946241

Country of ref document: EP

Kind code of ref document: A1