WO2023109218A1 - 氮化物器件和 cmos 器件集成结构及其制备方法 - Google Patents

氮化物器件和 cmos 器件集成结构及其制备方法 Download PDF

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WO2023109218A1
WO2023109218A1 PCT/CN2022/118855 CN2022118855W WO2023109218A1 WO 2023109218 A1 WO2023109218 A1 WO 2023109218A1 CN 2022118855 W CN2022118855 W CN 2022118855W WO 2023109218 A1 WO2023109218 A1 WO 2023109218A1
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nitride
region
silicon substrate
shaped groove
layer
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PCT/CN2022/118855
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English (en)
French (fr)
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刘胜厚
蔡文必
刘波亭
孙希国
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厦门市三安集成电路有限公司
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Publication of WO2023109218A1 publication Critical patent/WO2023109218A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present application relates to the field of semiconductor technology, in particular, to an integrated structure of a nitride device and a CMOS device and a preparation method thereof.
  • nitride heterojunction has the characteristics of high concentration and high electron mobility, so it has been widely used.
  • nitride semiconductor materials are mainly grown on substrates such as silicon carbide and sapphire.
  • silicon material is widely used in semiconductor devices and CMOS devices.
  • CMOS devices since the crystal plane of the substrate required by the nitride device and the CMOS device is different, the integration of the nitride heterojunction and the CMOS device is limited.
  • the purpose of the present application is to provide an integrated structure of a nitride device and a CMOS device and a preparation method thereof, which can epitaxially grow a high-quality nitride heterojunction on a silicon substrate.
  • an integrated structure of a nitride device and a CMOS device including: a silicon substrate, the silicon substrate includes a first region and a surface It is the second region of the (100) crystal plane; a CMOS device arranged on the (100) crystal plane of the second region of the silicon substrate; a V-shaped groove arranged on the first region of the silicon substrate, and the surface of the V-shaped groove is (111 ) crystal plane; a nitride device with a nitride heterojunction arranged on the (111) crystal plane.
  • a protection layer is further included, the protection layer covers the CMOS device and the nitride device on the silicon substrate, and the protection layer provides a flat top surface.
  • the first interconnection metal extends from the top surface of the protective layer to the nitride device to interconnect with the nitride device metal
  • the second interconnection The metal extends from the top surface of the protection layer to the CMOS device, so as to be interconnected with the metal of the CMOS device.
  • the protective layer includes an insulating layer and a passivation layer arranged in sequence, the insulating layer covers the area of the surface of the CMOS device and the silicon substrate except for the V-shaped groove, and the passivation layer covers the upper surface of the insulating layer and the nitride device .
  • the nitride device further includes a nucleation layer and an electrode, and the nucleation layer, nitride heterojunction and electrode are sequentially arranged on the surface of the V-shaped groove, wherein the nucleation layer covers the V-shaped groove to provide a flat top surface .
  • the CMOS device includes discrete devices and/or circuit structures.
  • Another aspect of the embodiment of the present application provides a method for manufacturing an integrated structure of a nitride device and a CMOS device.
  • the method includes: providing a silicon substrate, and the silicon substrate includes a first region and a second region whose surfaces are both (100) crystal planes. region; CMOS devices are formed in the second region where the surface of the silicon substrate is the (100) crystal plane; V-shaped grooves are formed by wet etching in the first region where the surface of the silicon substrate is the (100) crystal plane, and the V-shaped groove
  • the surface is a (111) crystal plane; a nitride device with a nitride heterojunction is formed on the surface of the V-shaped groove to obtain a prefabricated device.
  • forming the V-shaped groove by wet etching in the first region on the surface of the silicon substrate that is a (100) crystal plane includes: forming an insulating layer on the surface of the silicon substrate, and the insulating layer covers the first region and the first region having a CMOS device. Two areas; the insulating layer is patterned to expose the surface of the silicon substrate in the first area by photolithography; the surface of the silicon substrate exposed in the first area is wet-etched to form at least one V-shaped groove, the V-shaped groove The surface is (111) crystal plane.
  • forming a nitride device with a nitride heterojunction on the surface of the V-shaped groove includes: epitaxially growing a nucleation layer covering the V-shaped groove on the surface of the V-shaped groove, so as to provide a flat top surface through the nucleation layer; A nitride heterojunction and an electrode are sequentially formed on the flat top surface of the nucleation layer to form a nitride device.
  • the method further includes: forming a passivation layer covering the CMOS device and the nitride device on the surface of the prefabricated device; and planarizing the passivation layer processing so that the passivation layer provides a flat top surface; forming a first interconnection hole and a second interconnection hole respectively extending to the nitride device and the CMOS device from the top surface of the passivation layer by etching; respectively passing through the first interconnection The hole and the second interconnect hole form a first interconnect metal interconnected with the nitride device metal and a second interconnect metal interconnected with the CMOS device metal, the first interconnect metal and the second interconnect metal interconnect.
  • the present application provides an integrated structure of a nitride device and a CMOS device and a preparation method thereof, comprising: a silicon substrate, the silicon substrate includes a first region and a second region whose surface is a (100) crystal plane; The CMOS device on the (100) crystal plane of the second region; the V-shaped groove arranged in the first region of the silicon substrate, the surface of the V-shaped groove is a (111) crystal plane; Junction nitride devices.
  • the (111) crystal plane can be formed by performing crystal orientation treatment on the first region of the silicon substrate surface, while retaining the second region of the silicon substrate surface
  • the (100) crystal plane so that the surface of the silicon substrate has both the (111) crystal plane in the first region and the (100) crystal plane in the second region, so that the nitride device made in the first region and the nitride device made in the second region can be made
  • the CMOS devices in the two regions can all have high quality, so as to meet the requirements of high-quality devices, and also realize the integration of nitride devices with nitride heterojunctions and CMOS devices on the surface of the silicon substrate.
  • FIG. 1 is a schematic flow diagram of a method for preparing an integrated structure of a nitride device and a CMOS device provided in an embodiment of the present application;
  • FIG. 2 is one of the schematic diagrams of the preparation state of a nitride device and a CMOS device integrated structure provided in the embodiment of the present application;
  • FIG. 3 is the second schematic diagram of the preparation state of an integrated structure of a nitride device and a CMOS device provided in the embodiment of the present application;
  • Fig. 4 is the third schematic diagram of the preparation state of an integrated structure of a nitride device and a CMOS device provided by the embodiment of the present application;
  • FIG. 5 is the fourth schematic diagram of the preparation state of an integrated structure of a nitride device and a CMOS device provided by the embodiment of the present application;
  • FIG. 6 is the fifth schematic diagram of the preparation state of an integrated structure of a nitride device and a CMOS device provided in the embodiment of the present application;
  • Fig. 7 is the sixth schematic diagram of the preparation state of an integrated structure of a nitride device and a CMOS device provided by the embodiment of the present application;
  • Fig. 8 is the seventh schematic diagram of the preparation state of an integrated structure of a nitride device and a CMOS device provided by the embodiment of the present application;
  • FIG. 9 is the eighth schematic diagram of the preparation state of an integrated structure of a nitride device and a CMOS device provided in the embodiment of the present application.
  • Fig. 10 is the ninth schematic diagram of the preparation state of an integrated structure of a nitride device and a CMOS device provided by the embodiment of the present application;
  • Fig. 11 is a tenth schematic diagram of the preparation state of an integrated structure of a nitride device and a CMOS device provided in the embodiment of the present application;
  • FIG. 12 is a schematic structural diagram of an integrated structure of a nitride device and a CMOS device provided in an embodiment of the present application.
  • Icon 210-silicon substrate; 220-insulating layer; 230-nucleation layer; 240-nitride heterojunction; 260-passivation layer; 271-first interconnection hole; 272-second interconnection hole; 281 - first interconnect metal; 282 - second interconnect metal; 300 - silicon based device; 400 - nitride device.
  • silicon materials are usually used to provide a silicon substrate as a substrate for carrying semiconductor and integrated circuit components, but the surface formed by the silicon substrate is usually (100) crystal
  • the CMOS device can perform good lattice matching with the silicon substrate with the (100) crystal plane on the surface, the lattice matching between the nitride heterojunction and the silicon substrate with the (100) crystal plane on the surface is poor.
  • the quality of the nitride heterojunction epitaxially grown on the silicon substrate of the (100) crystal plane will be poor and cannot Meeting the requirements of high-quality devices also limits the integration of nitride devices with nitride heterojunctions and CMOS devices on the surface of silicon substrates.
  • An aspect of the embodiment of the present application provides an integrated structure of a nitride device and a CMOS device, as shown in FIG. 9 , including: a silicon substrate 210, wherein the upper surface of the silicon substrate 210 includes a first region and a second region , to fabricate the nitride device 400 and the CMOS device respectively.
  • V-shaped grooves are formed in the first region of the surface of the silicon substrate 210 through crystal orientation treatment, and the surface of the V-shaped grooves is a (111) crystal plane, so that the original first region The (100) crystal plane becomes the (111) crystal plane, and then the nitride device 400 is manufactured based on the (111) crystal plane on the surface of the V-shaped groove. Since the nitride heterojunction 240 and the (111) The crystal plane has a good lattice matching degree, therefore, the nitride device 400 fabricated on the surface of the V-shaped groove in the first region can have a higher quality.
  • the second region on the surface of the silicon substrate 210 is a (100) crystal plane.
  • a CMOS device is fabricated on the second region on the surface of the silicon substrate 210, since the CMOS device can be compared with the ( 100) The crystal plane forms a good lattice fit, so that the CMOS device fabricated on the surface of the second region can also have higher quality.
  • the (111) crystal plane can be formed by performing crystal orientation treatment on the first region of the surface of the silicon substrate 210, and at the same time, the silicon substrate
  • the (100) crystal plane of the second region on the surface of the bottom 210 makes the surface of the silicon substrate 210 have both the (111) crystal plane of the first region and the (100) crystal plane of the second region, so that the Both the nitride device 400 and the CMOS device fabricated in the second region can have higher quality, so as to meet the requirements of high-quality devices, and also realize the nitride device 400 with the nitride heterojunction 240 and the CMOS device on silicon Integration of the surface of the substrate 210 .
  • the conductivity type of the silicon substrate 210 may include various forms such as high resistance, N-type conductivity, and P-type conductivity.
  • the nitride device 400 further includes a nucleation layer 230 and an electrode, wherein the nucleation layer 230 is disposed on the surface of the V-shaped groove, and the nitride heterojunction 240 is disposed on the nucleation layer 230 top surface, the electrodes are arranged on the top surface of the nitride heterojunction 240, since the surface of the V-shaped groove is a (111) crystal plane, the epitaxially grown nucleation layer 230 can perform good lattice adaptation with the surface of the silicon substrate 210 matching, so that the nucleation layer 230 has a higher quality, based on the nucleation layer 230, continue to epitaxially grow the nitride heterojunction 240 on the top surface of the nucleation layer 230, because the nitride heterojunction 240 can be combined with the formation
  • the core layer 230 forms better lattice matching, so the quality of the nitride hetero
  • the electrodes fabricated on the surface of the nitride heterojunction 240 can be source S, drain D and gate G, wherein the source S and the drain D can be combined with the nitride
  • the heterojunction 240 forms an ohmic contact
  • the gate G forms a Schottky contact with the nitride heterojunction 240 .
  • the gate G can be a T-shaped gate.
  • the thickness of the nucleation layer 230 is at least greater than or equal to the depth of the V-shaped groove, so that the nucleation layer 230 can cover the V-shaped groove, so that the top surface of the nucleation layer 230 is at the same level.
  • a nucleation layer 230 with a relatively flat top surface can be obtained, which can provide a relatively flat epitaxial plane for the nitride heterojunction 240 , thereby further improving the quality of the nitride heterojunction 240 .
  • the nucleation layer 230 may be a group III-V compound, which has a better crystal lattice with the (111) crystal-plane silicon substrate 210 than the (100) crystal-plane silicon substrate 210 suitability.
  • the CMOS devices may include discrete devices.
  • a CMOS device may include a circuit structure.
  • a CMOS device may include discrete devices and circuit structures.
  • the discrete device may be a silicon-based device 300, a diode, a triode, etc.
  • the circuit structure may be a numerical circuit, an analog circuit, or the like. Taking the silicon-based device 300 as an example, as shown in FIG. 3 , the silicon-based device 300 is fabricated in the second region on the surface of the silicon substrate 210.
  • the silicon-based device 300 includes a well region formed by ion implantation, and a second spacer located in the well region.
  • the first The doped region can serve as the source S of the silicon-based device 300
  • the second doped region can serve as the drain D of the silicon-based device 300 .
  • the doping type of the well region is different from that of the first doping region and the second doping region, for example, the well region is an N-type well region, and the first doping region and the second doping region are The P-type doped region, or the well region is a P-type well region, and the first doped region and the second doped region are N-type doped regions.
  • the integrated structure further includes a protective layer covering the CMOS device and the nitride device 400 on the silicon substrate 210, so that the protective layer can be used to protect the CMOS device and the nitride device.
  • the 400 performs insulation and isolation, and at the same time, the device surface formed with the CMOS device and the nitride device 400 can also be passivated and protected through the protective layer, so as to improve the ability of the device to prevent moisture intrusion.
  • the protective layer includes an insulating layer 220 and a passivation layer 260 arranged in sequence, wherein, as shown in Figures 3 and 4, the insulating layer 220 may be fabricated in the second region After the CMOS device, the entire layer covers the upper surface of the device shown in FIG. 3 , so as to isolate the CMOS device during the process of fabricating the nitride device 400 in the first region and avoid adverse effects on the CMOS device.
  • the insulating layer 220 can also be used as a mask layer when the first region undergoes crystal orientation treatment to form a V-shaped groove. As shown in FIGS. 7 to 9, only the part of the insulating layer 220 located directly above the V-shaped groove is removed, as shown in FIG. In this way, the surface of the substrate 210 can also effectively isolate the nitride device 400 from the CMOS device.
  • the passivation layer 260 can cover the upper surface of the insulating layer 220 and the nitride device 400 after the nitride device 400 and the CMOS device are fabricated in the first region and the second region respectively.
  • the upper surface of the device can be effectively passivated to protect the upper surface of the device structure shown in FIG. 9 and improve the moisture resistance of the entire device.
  • the top surface of the protective layer can be planarized to form a flat top surface, so that the continuity and reliability of the metal wires when wiring on the top surface of the protective layer can be improved.
  • the top layer of the protective layer is a passivation layer 260.
  • the material of the passivation layer 260 is a dielectric material (silicon oxide, silicon nitride, aluminum oxide, silicon oxynitride, etc.), it can be deposited (deposition method) can be PECVD, LPCVD, Sputtering, etc.)
  • the top surface of the passivation layer 260 is planarized using a chemical mechanical polishing process, so that it forms a relatively flat top surface;
  • the top surface of the passivation layer 260 may be planarized by spin coating.
  • the CMOS device and the nitride device 400 may be interconnected, so as to realize predetermined functions.
  • the integrated structure further includes a first interconnection metal 281 and a second interconnection metal 282 , wherein the first interconnection metal 281 extends from the top surface of the protective layer to the nitride device 400 , so as to be compatible with the nitride device 400
  • the second interconnect metal 282 can also extend from the top surface of the protective layer to the CMOS device, so as to perform metal interconnection with the electrodes of the CMOS device.
  • the first interconnect metal 281 and the second interconnect The part of the metal 282 located on the top surface of the protection layer can realize the interconnection between the CMOS device and the nitride device 400 through the connection.
  • Another aspect of the embodiment of the present application provides a method for preparing an integrated structure of a nitride device 400 and a CMOS device, as shown in FIG. 100) The first region and the second region of the crystal plane.
  • a substrate of silicon material is provided, the surface of which includes a first region and a second region, and the surfaces of the two regions are both (100) crystal planes.
  • the conductivity type of the silicon substrate 210 may include various forms such as high resistance, N-type conductivity, and P-type conductivity.
  • S020 forming a CMOS device in a second region where the surface of the silicon substrate 210 is a (100) crystal plane.
  • a CMOS device is fabricated in the second region where the surface of the silicon substrate 210 is a (100) crystal plane. Since the CMOS device can form a good lattice fit with the (100) crystal plane of the second region, the CMOS device fabricated on the surface of the second region can also have higher quality.
  • S030 Form a V-shaped groove by wet etching in the first region of the silicon substrate 210 where the surface is the (100) crystal plane, and the surface of the V-shaped groove is the (111) crystal plane.
  • the etching solution used in wet etching can be an alkaline etching solution (heated KOH or TMAH solution).
  • the corrosion solution is used to process the crystal orientation of the first region of the silicon substrate 210 surface which is the (100) crystal plane, so that pits can be etched on the surface of the first region of the silicon substrate 210, and the corrosion can be stopped at the (111) crystal plane. surface, and then form a V-shaped groove on the surface of the first region of the silicon substrate 210, and the surface of the V-shaped groove is a (111) crystal plane, so as to obtain the device structure as shown in FIG. 7 .
  • S040 forming a nitride device 400 with a nitride heterojunction 240 on the surface of the V-shaped groove to obtain a prefabricated device.
  • a silicon substrate 210 with a (111) crystal plane on the surface of the first region is obtained through S030, and a nitride device 400 with a nitride heterojunction 240 is formed based on the (111) crystal plane on the surface of the V-shaped groove.
  • the nitride heterojunction 240 of the device 400 has a good lattice matching degree with the (111) crystal plane, therefore, the nitride device 400 fabricated on the surface of the V-shaped groove in the first region can be of higher quality, and further obtained as shown in the figure 9 shows the prefabricated device.
  • the (111) crystal plane can be formed by performing crystal orientation treatment on the first region of the surface of the silicon substrate 210, and at the same time, the silicon substrate
  • the (100) crystal plane of the second region on the surface of the bottom 210 makes the surface of the silicon substrate 210 have both the (111) crystal plane of the first region and the (100) crystal plane of the second region, so that the Both the nitride device 400 and the CMOS device fabricated in the second region can have higher quality, so as to meet the requirements of high-quality devices, and also realize the nitride device 400 with the nitride heterojunction 240 and the CMOS device on silicon Integration of the surface of the substrate 210 .
  • the V-shaped groove is formed by wet etching in the first region of the silicon substrate 210 surface being the (100) crystal plane through S030, as shown in FIG.
  • the first region and the second region of the crystal plane form an insulating layer 220 covering the entire layer, that is, the insulating layer 220 covers the surface of the CMOS device in the first region and the second region; as shown in FIG. 5, and then through a photolithography process, the The insulating layer 220 is patterned to form a desired pattern on the insulating layer 220.
  • the patterned insulating layer 220 includes a solid part covering the surface of the first region and a virtual part exposing the surface of the first region; As shown in FIG.
  • the surface of the silicon substrate 210 located in the first region is then subjected to crystal orientation treatment by wet etching, so the etching solution can etch the surface of the silicon substrate 210 exposed in the first region, due to (111)
  • the atomic density of the crystal plane is relatively high, so the corrosion stops at the (111) crystal plane, thereby forming at least one V-shaped groove on the surface of the first region of the silicon substrate 210, and the surface of the V-shaped groove is the (111) crystal plane, and then The insulating layer 220 directly above the V-shaped groove is removed to obtain the device structure as shown in FIG. 7 .
  • the insulating layer 220 can isolate the CMOS device during the crystal orientation treatment of the first region and the process of manufacturing the nitride device 400 , so as to avoid adverse effects on the CMOS device.
  • the insulating layer 220 can also be used as a mask layer when the first region undergoes crystal orientation treatment to form a V-shaped groove. As shown in FIGS. 7 to 9, only the part of the insulating layer 220 located directly above the V-shaped groove is removed, as shown in FIG. In this way, the surface of the substrate 210 can also effectively isolate the nitride device 400 from the CMOS device.
  • the part of the insulating layer 220 to be patterned may include a plurality of sub-mask structures, and the plurality of sub-mask structures Forming a structure arranged in an array, the size of each sub-mask structure is the same, and the distance between two adjacent sub-mask structures is also the same, so that the subsequent V-shaped formation in the first region of the surface of the silicon substrate 210 can be made Grooves have the same structure and size, and can also be arranged in an array, so as to provide a relatively uniform growth environment for the subsequent epitaxial growth of the nucleation layer 230, and facilitate the realization of a nucleation layer 230 with a flat top surface, thereby improving the stability of the epitaxial nucleation layer 230.
  • each sub-mask structure is an elongated structure, and the sub-mask structures of multiple elongated structures are arranged in an array, and the sub-mask structures of each elongated structure have the same size, and The spacing between the sub-mask structures of two adjacent elongated structures is also the same.
  • the distance between two adjacent sub-mask structures determines the area of the (111) crystal plane on which the V-shaped groove is subsequently formed. For example, when the distance increases, the volume of the V-shaped groove increases correspondingly. , the area of the (111) crystal plane also becomes larger, and vice versa.
  • the silicon surface when patterning the entire insulating layer 220 , the silicon surface may be directly exposed by photolithography.
  • the multiple V-shaped grooves are continuous, so that two adjacent V-shaped grooves form a W-shaped structure, so that The surfaces of the first region of the silicon substrate 210 are all (111) crystal planes, so that a high-quality nucleation layer 230 can be epitaxially grown on the surface of the silicon substrate 210 located in the first region.
  • the epitaxially grown nucleation layer 230 can perform good lattice adaptation with the V-shaped groove whose surface of the silicon substrate 210 in the first region is a (111) crystal plane. matching, so that the nucleation layer 230 has a higher quality.
  • the thickness of the nucleation layer 230 is at least greater than or equal to the depth of the V-shaped groove, so that the nucleation layer 230 can cover the V-shaped groove, so that the top surface of the nucleation layer 230 is in the same plane, and is in the same plane as the silicon substrate.
  • the bottom surface of the bottom 210 is parallel to obtain a nucleation layer 230 with a relatively flat top surface.
  • the nitride heterojunction 240 is continued to be epitaxially grown on the top surface of the nucleation layer 230.
  • junction 240 can form better lattice matching with the nucleation layer 230, so the quality of the nitride heterojunction 240 can be improved. 240 provides a flatter epitaxial plane, thereby further improving the quality of the nitride heterojunction 240 . Finally, electrodes are fabricated on the surface of the nitride heterojunction 240 to form the nitride device 400 .
  • the method further includes: as shown in FIG.
  • the passivation layer 260 of the device 400 can effectively passivate and protect the upper surface of the device structure shown in FIG. 9 , and improve the moisture resistance of the entire device.
  • the formed passivation layer 260 can be planarized, so that the top surface of the passivation layer 260 is relatively flat, which can improve the continuity and reliability of metal lines when wiring on the top surface of the passivation layer 260 .
  • the first interconnection hole 271 and the second interconnection hole 272 respectively extend inward from the top surface of the passivation layer 260 through the photolithography plus etching process, wherein the first interconnection hole 271 is formed by the passivation layer.
  • the top surface of the layer 260 extends to the electrodes of the nitride device 400, and the second interconnect hole 272 extends from the top surface of the passivation layer 260 to the electrodes of the CMOS device.
  • the first interconnect metal 281 interconnected with the electrode metal of the nitride device 400 is formed through the first interconnect hole 271
  • the first interconnect metal 281 interconnected with the electrode metal of the CMOS device is formed through the second interconnect hole 272.
  • Two interconnection metals 282 and make the first interconnection metal 281 and the second interconnection metal 282 perform metal interconnection on the top surface of the passivation layer 260 , so as to realize the interconnection between the CMOS device and the nitride device 400 .
  • the first interconnection metal 281 includes a via metal formed in the first interconnection hole 271 by an electroplating process and a via metal located on the top surface of the passivation layer 260 and connected to the via metal.
  • Connection Metal; Second Interconnect Metal 282 Similarly, the first interconnect metal 281 and the second interconnect metal 282 can be metal interconnected through the connection metal on the top surface of the passivation layer 260 . It should be understood that the interconnection between the nitride device 400 and the CMOS device can be connected according to actual needs, for example, as shown in FIG. 12 , the drain D of the nitride device 400 is interconnected with the source S of the silicon-based device 300 .
  • the material of the passivation layer 260 when the material of the passivation layer 260 is a dielectric material (silicon oxide, silicon nitride, aluminum oxide, silicon oxynitride, etc.), it can be deposited (the deposition method can be PECVD, After the passivation layer 260 is formed by LPCVD, Sputtering, etc., the top surface of the passivation layer 260 is planarized by using a chemical mechanical polishing process, so as to form a relatively flat top surface; the material of the passivation layer 260 is insulating organic material, the top surface of the passivation layer 260 may be planarized by spin coating.
  • the deposition method can be PECVD
  • the top surface of the passivation layer 260 is planarized by using a chemical mechanical polishing process, so as to form a relatively flat top surface; the material of the passivation layer 260 is insulating organic material, the top surface of the passivation layer 260 may be planarized by spin coating.
  • nucleation layer 230 when the nucleation layer 230 is epitaxially grown on the (111) crystal plane in the V-shaped groove, multiple layers can be rapidly deposited on the (111) crystal plane in the V-shaped groove a discontinuous island-shaped nucleation point, and then relying on multiple island-shaped nucleation points to form a continuous surface through three-dimensional growth, and finally form a nucleation layer 230 covering the V-shaped groove, so as to obtain a formation with a relatively flat top surface. nuclear layer 230 .
  • the opening width of the V-shaped groove is c, and the depth of the V-shaped groove is h, wherein, the opening width c of the V-shaped groove is 1.43 times the depth h of the V-shaped groove, and the V-shaped groove
  • the included angle between the (111) crystal plane of the sidewall and the horizontal plane is 54.7 degrees, so that the formed V-shaped groove is relatively shallow, which facilitates the epitaxial growth of the nucleation layer 230 to become planar.
  • the depth h of the V-shaped groove may be less than 100 nm, so that it can be completely covered by the nucleation layer 230 that facilitates subsequent epitaxial growth.
  • the nitride heterojunction 240 includes a buffer layer, a channel layer, and a barrier layer sequentially grown on the nucleation layer 230 to form the basic structure of a nitride high electron mobility transistor. structure.
  • the buffer layer, the channel layer and the barrier layer can all be III-V compounds, wherein the buffer layer and the channel layer can be binary or ternary compounds, and the barrier layer can be ternary or quaternary compounds. compound.
  • the buffer layer and the channel layer can be made of the same material, for example, both are GaN, so as to simplify the epitaxy step.
  • the material of the buffer layer is one of GaN and AlxGa1 -xN .
  • the buffer layer can be doped with Fe, C, O and other elements, or undoped.
  • the thickness of the buffer layer may be 20 nm to 8 ⁇ m, which may be reasonably selected according to actual needs when setting it specifically.
  • the material of the channel layer is one of GaN and AlxGa1 -xN .
  • the channel layer may be unintentionally doped or doped with Fe, C, O, etc.
  • the thickness of the channel layer is 10nm to 200nm, which can be reasonably selected according to actual needs.
  • the material of the barrier layer is one of AlN, InN, AlxGa1 -xN , InxAl1 -xN and InxAlyGaN .
  • the thickness of the barrier layer is 1nm to 50nm, which can be reasonably selected according to actual needs when setting.
  • the material of the nucleation layer 230 is AlN.
  • the thickness of the nucleation layer 230 is 10nm to 100nm, which can be reasonably selected according to actual needs during specific setting, but it should be understood that in order to obtain a relatively flat top surface of the nucleation layer 230, therefore, in When the nucleation layer 230 is epitaxially formed, the thickness of the nucleation layer 230 should be greater than the depth of the V-shaped groove, so that the nucleation layer 230 can completely cover the V-shaped groove.

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Abstract

本申请提供一种氮化物器件和CMOS器件集成结构及其制备方法，涉及半导体技术领域，可以根据氮化物器件和CMOS器件各自所需要的不同晶向，通过对硅衬底表面的第一区域进行晶向处理从而形成（111）晶面，同时，保留硅衬底表面第二区域的（100）晶面，使得硅衬底表面同时具有第一区域的（111）晶面和第二区域的（100）晶面，从而能使得制作于第一区域的氮化物器件和制作于第二区域的CMOS器件都能够具有较高的质量，从而满足高质量器件的要求，同时也实现了具有氮化物异质结的氮化物器件与CMOS器件在硅衬底表面的集成。

Description

氮化物器件和CMOS器件集成结构及其制备方法 技术领域
本申请涉及半导体技术领域，具体而言，涉及一种氮化物器件和CMOS器件集成结构及其制备方法。
 背景技术
利用氮化物异质结形成的二维电子气具有高浓度高电子迁移率的特性，因此得到了广泛的应用。目前氮化物半导体材料主要生长在碳化硅、蓝宝石等衬底上。
硅材料作为重要的半导体材料，其广泛应用于半导体器件和CMOS器件。但是由于氮化物器件和CMOS器件所需要的衬底晶面不同，因此，限制了氮化物异质结与CMOS器件的集成。
 技术解决方案
本申请的目的在于，针对上述现有技术中的不足，提供一种氮化物器件和CMOS器件集成结构及其制备方法，能够在硅衬底上外延生长出高质量的氮化物异质结。
为实现上述目的，本申请实施例采用的技术方案如下：本申请实施例的一方面，提供一种氮化物器件和CMOS器件集成结构，包括：硅衬底，硅衬底包括第一区域和表面为（100）晶面的第二区域；设置于硅衬底第二区域（100）晶面上的CMOS器件；设置于硅衬底第一区域的V形槽，V形槽的表面为（111）晶面；设置于（111）晶面上具有氮化物异质结的氮化物器件。
可选的，还包括保护层，保护层覆盖于硅衬底上的CMOS器件和氮化物器件，且保护层提供一平坦顶面。
可选的，还包括互连的第一互连金属和第二互连金属，第一互连金属由保护层顶面延伸至氮化物器件，以与氮化物器件金属互连，第二互连金属由保护层顶面延伸至CMOS器件，以与CMOS器件金属互连。
可选的，保护层包括依次设置的绝缘层和钝化层，绝缘层覆盖于CMOS器件和硅衬底表面除V形槽外的区域，钝化层覆盖于绝缘层和氮化物器件的上表面。
可选的，氮化物器件还包括成核层和电极，成核层、氮化物异质结和电极依次设置于V形槽表面，其中，成核层覆盖于V形槽以提供一平坦顶面。
可选的，CMOS器件包括分立器件和/或电路结构。
本申请实施例的另一方面，提供一种氮化物器件和CMOS器件集成结构制备方法，方法包括：提供硅衬底，硅衬底包括表面均为（100）晶面的第一区域和第二区域；在硅衬底表面为（100）晶面的第二区域内形成CMOS器件；在硅衬底表面为（100）晶面的第一区域通过湿法腐蚀形成V形槽，V形槽的表面为（111）晶面；在V形槽表面形成具有氮化物异质结的氮化物器件，得到预制器件。
可选的，在硅衬底表面为（100）晶面的第一区域通过湿法腐蚀形成V形槽包括：在硅衬底表面形成绝缘层，绝缘层覆盖第一区域和具有CMOS器件的第二区域；通过光刻对绝缘层进行图形化以在第一区域露出硅衬底表面；对在第一区域露出的硅衬底表面进行湿法腐蚀以形成至少一个V形槽，V形槽的表面为（111）晶面。
可选的，在V形槽表面形成具有氮化物异质结的氮化物器件包括：在V形槽表面外延生长覆盖于V形槽的成核层，以通过成核层提供一平坦顶面；在成核层的平坦顶面依次形成氮化物异质结和电极，以形成氮化物器件。
可选的，在V形槽表面形成具有氮化物异质结的氮化物器件之后，方法还包括：在预制器件表面形成覆盖CMOS器件和氮化物器件的钝化层；对钝化层进行平坦化处理以使钝化层提供一平坦顶面；通过刻蚀由钝化层顶面形成分别延伸至氮化物器件和CMOS器件的第一互连孔和第二互连孔；分别通过第一互连孔和第二互连孔形成与氮化物器件金属互连的第一互连金属以及与CMOS器件金属互连的第二互连金属，第一互连金属和第二互连金属互连。
 有益效果
本申请提供了一种氮化物器件和CMOS器件集成结构及其制备方法，包括：硅衬底，硅衬底包括第一区域和表面为（100）晶面的第二区域；设置于硅衬底第二区域（100）晶面上的CMOS器件；设置于硅衬底第一区域的V形槽，V形槽的表面为（111）晶面；设置于（111）晶面上具有氮化物异质结的氮化物器件。如此，可以根据氮化物器件和CMOS器件各自所需要的不同晶向，通过对硅衬底表面的第一区域进行晶向处理从而形成（111）晶面，同时，保留硅衬底表面第二区域的（100）晶面，使得硅衬底表面同时具有第一区域的（111）晶面和第二区域的（100）晶面，从而能使得制作于第一区域的氮化物器件和制作于第二区域的CMOS器件都能够具有较高的质量，从而满足高质量器件的要求，同时也实现了具有氮化物异质结的氮化物器件与CMOS器件在硅衬底表面的集成。
 附图说明
以下附图仅示出了本申请的某些实施例，因此不应被看作是对范围的限定。
图1为本申请实施例提供的一种氮化物器件和CMOS器件集成结构制备方法的流程示意图；
图2为本申请实施例提供的一种氮化物器件和CMOS器件集成结构的制备状态示意图之一；
图3为本申请实施例提供的一种氮化物器件和CMOS器件集成结构的制备状态示意图之二；
图4为本申请实施例提供的一种氮化物器件和CMOS器件集成结构的制备状态示意图之三；
图5为本申请实施例提供的一种氮化物器件和CMOS器件集成结构的制备状态示意图之四；
图6为本申请实施例提供的一种氮化物器件和CMOS器件集成结构的制备状态示意图之五；
图7为本申请实施例提供的一种氮化物器件和CMOS器件集成结构的制备状态示意图之六；
图8为本申请实施例提供的一种氮化物器件和CMOS器件集成结构的制备状态示意图之七；
图9为本申请实施例提供的一种氮化物器件和CMOS器件集成结构的制备状态示意图之八；
图10为本申请实施例提供的一种氮化物器件和CMOS器件集成结构的制备状态示意图之九；
图11为本申请实施例提供的一种氮化物器件和CMOS器件集成结构的制备状态示意图之十；
图12为本申请实施例提供的一种氮化物器件和CMOS器件集成结构的结构示意图。
图标：210-硅衬底；220-绝缘层；230-成核层；240-氮化物异质结；260-钝化层；271-第一互连孔；272-第二互连孔；281-第一互连金属；282-第二互连金属；300-硅基器件；400-氮化物器件。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。
应当理解，虽然术语第一、第二等可以在本文中用于描述各种元件，但是这些元件不应受这些术语的限制。这些术语仅用于区域分一个元件与另一个元件。例如，在不脱离本公开的范围的情况下，第一元件可称为第二元件，并且类似地，第二元件可称为第一元件。如本文所使用，术语“和/或”包括相关联的所列项中的一个或多个的任何和所有组合。
应当理解，当一个元件(诸如层、区域或衬底)被称为“在另一个元件上”或“延伸到另一个元件上”时，其可以直接在另一个元件上或直接延伸到另一个元件上，或者也可以存在介于中间的元件。相反，当一个元件被称为“直接在另一个元件上”或“直接延伸到另一个元件上”时，不存在介于中间的元件。同样，应当理解，当元件(诸如层、区域或衬底)被称为“在另一个元件之上”或“在另一个元件之上延伸”时，其可以直接在另一个元件之上或直接在另一个元件之上延伸，或者也可以存在介于中间的元件。相反，当一个元件被称为“直接在另一个元件之上”或“直接在另一个元件之上延伸”时，不存在介于中间的元件。还应当理解，当一个元件被称为“连接”或“耦接”到另一个元件时，其可以直接连接或耦接到另一个元件，或者可以存在介于中间的元件。相反，当一个元件被称为“直接连接”或“直接耦接”到另一个元件时，不存在介于中间的元件。
硅材料在半导体器件和集成电路的应用中，通常用于提供一种硅衬底，从而作为承载半导体和集成电路元器件的基材，但硅衬底所形成的表面通常均为（100）晶面，虽然CMOS器件能够和表面为（100）晶面的硅衬底进行良好的晶格适配，但是氮化物异质结与表面为（100）晶面硅衬底的晶格匹配度较差，因此，直接在（100）晶面的硅衬底上外延生长氮化物异质结时，会使得外延生长于（100）晶面的硅衬底上的氮化物异质结质量较差，无法满足高质量器件的要求，也因此限制了具有氮化物异质结的氮化物器件与CMOS器件在硅衬底表面的集成。
本申请实施例的一方面，提供一种氮化物器件和CMOS器件集成结构，如图9所示，包括：硅衬底210，其中，硅衬底210的上表面包括第一区域和第二区域，用以分别制作氮化物器件400和CMOS器件。
如图4至图9所示，通过晶向处理，在硅衬底210表面的第一区域形成V形槽，并且V形槽的表面为（111）晶面，从而能够将原本第一区域的（100）晶面变为（111）晶面，然后以V形槽表面的（111）晶面为依托，制作氮化物器件400，由于氮化物器件400的氮化物异质结240与（111）晶面具有良好的晶格匹配度，因此，能够使得制作于第一区域V形槽表面的氮化物器件400具有较高质量。
如图2至图3所示，硅衬底210表面的第二区域为（100）晶面，在硅衬底210表面的第二区域制作CMOS器件时，由于CMOS器件能够与第二区域的（100）晶面形成良好的晶格适配，从而使得制作于第二区域表面的CMOS器件也能够具有较高质量。
综上所述，可以根据氮化物器件400和CMOS器件各自所需要的不同晶向，通过对硅衬底210表面的第一区域进行晶向处理从而形成（111）晶面，同时，保留硅衬底210表面第二区域的（100）晶面，使得硅衬底210表面同时具有第一区域的（111）晶面和第二区域的（100）晶面，从而能使得制作于第一区域的氮化物器件400和制作于第二区域的CMOS器件都能够具有较高的质量，从而满足高质量器件的要求，同时也实现了具有氮化物异质结240的氮化物器件400与CMOS器件在硅衬底210表面的集成。在一些实施方式中，硅衬底210的导电类型可以包括高阻、N型导电、P型导电等多种形式。
可选的，如图7至图9所示，氮化物器件400还包括成核层230和电极，其中，成核层230设置于V形槽表面，氮化物异质结240设置于成核层230顶面，电极设置于氮化物异质结240顶面，由于V形槽表面为（111）晶面，因此，外延生长的成核层230能够与硅衬底210表面进行良好的晶格适配，从而使得成核层230具有较高的质量，以该成核层230为基础，继续在成核层230顶面外延生长氮化物异质结240，由于氮化物异质结240能够与成核层230形成较好的晶格匹配，因此，能够提高氮化物异质结240的质量，最后在氮化物异质结240表面制作电极。
在一些实施方式中，如图9所示，在氮化物异质结240表面制作的电极可以是源极S、漏极D和栅极G，其中，源极S和漏极D能够与氮化物异质结240形成欧姆接触，栅极G与氮化物异质结240形成肖特基接触。为进一步提高器件性能，栅极G可以是T型栅。
在一些实施方式中，如图9所示，成核层230的厚度至少大于或等于V形槽的深度，从而使得成核层230能够覆盖V形槽，使得成核层230的顶面处于同一平面内，进而获得一个顶面较为平坦的成核层230，能够对氮化物异质结240提供较为平整的外延平面，从而进一步的提高氮化物异质结240的质量。在一些实施方式中，成核层230可以是三五族化合物，三五族化合物相比于（100）晶面硅衬底210，与（111）晶面硅衬底210具有更好的晶格匹配度。
在一些实施方式中，CMOS器件可以包括分立器件。在一些实施方式中，CMOS器件可以包括电路结构。在一些实施方式中，CMOS器件可以包括分立器件和电路结构。需要说明的是，分立器件可以是硅基器件300、二极管、三极管等，电路结构可以是数值电路、模拟电路等。以硅基器件300为例，如图3所示，在硅衬底210表面的第二区域制作硅基器件300，硅基器件300包括通过离子注入形成的阱区、间隔位于阱区内的第一掺杂区和第二掺杂区、在第一掺杂区和第二掺杂区之间的衬底表面形成的介质层以及位于介质层上的栅极G，应当理解的是，第一掺杂区可以作为硅基器件300的源极S，第二掺杂区可以作为硅基器件300的漏极D。需要说明的是，阱区的掺杂类型与第一掺杂区和第二掺杂区的掺杂类型不同，例如阱区为N型阱区，第一掺杂区和第二掺杂区为P型掺杂区，或，阱区为P型阱区，第一掺杂区和第二掺杂区为N型掺杂区。
可选的，如图10至图12所示，集成结构还包括保护层，保护层覆盖于硅衬底210上的CMOS器件和氮化物器件400，从而能够利用保护层对CMOS器件和氮化物器件400进行绝缘隔离，同时，还能够通过保护层对形成有CMOS器件和氮化物器件400的器件表面进行钝化保护，提高器件的防水汽侵入的能力。
可选的，如图10至图12所示，保护层包括依次设置的绝缘层220和钝化层260，其中，如图3和图4所示，绝缘层220可以是在第二区域制作完CMOS器件后，整层覆盖于图3所示的器件上表面，从而在第一区域制作氮化物器件400的过程中，隔离CMOS器件，避免对CMOS器件造成不利影响。同时，如图5和图6所示，绝缘层220还能够作为第一区域进行晶向处理形成V形槽时的掩膜层。如图7至图9所示，仅去除位于V形槽正上方绝缘层220的部分，如图9所示，使得剩余部分的绝缘层220覆盖CMOS器件上表面以及覆盖除V形槽外的硅衬底210表面，如此，也能够对氮化物器件400和CMOS器件进行有效的绝缘隔离。
如图9和图10所示，钝化层260可以是在第一区域和第二区域分别制作完氮化物器件400和CMOS器件后，整层覆盖于绝缘层220的上表面以及氮化物器件400的上表面，从而能够对图9所示的器件结构的上表面进行有效的钝化保护，提高整个器件的防水汽侵入能力。
可选的，可以通过平坦化处理使得保护层的顶面形成一平坦顶面，如此，能够提高金属线在保护层顶面布线时的连续性和可靠性。例如图10所示，保护层的顶层为钝化层260，在钝化层260的材质为介质材料（氧化硅、氮化硅、氧化铝、氮氧化硅等）时，可以通过沉积（沉积方式可以是PECVD、LPCVD、Sputtering等）形成钝化层260后，利用化学机械研磨工艺对钝化层260的顶面进行平坦化处理，从而使其形成较为平坦的顶面；在钝化层260的材质为绝缘有机材料时，可以采用旋转涂布的方式实现钝化层260顶面的平坦化。
可选的，在同一硅衬底210上集成CMOS器件和氮化物器件400后，可以对CMOS器件和氮化物器件400进行互连，从而实现预定功能。例如图12所示，集成结构还包括第一互连金属281和第二互连金属282，其中，第一互连金属281由保护层顶面延伸至氮化物器件400，从而与氮化物器件400的电极进行金属互连，同理，第二互连金属282也可以由保护层顶面延伸至CMOS器件，从而与CMOS器件的电极进行金属互连，第一互连金属281和第二互连金属282位于保护层顶面的部分可以通过连接实现CMOS器件和氮化物器件400的互连。
本申请实施例的另一方面，提供一种氮化物器件400和CMOS器件集成结构制备方法，如图1所示，方法包括：S010：提供硅衬底210，硅衬底210包括表面均为（100）晶面的第一区域和第二区域。
如图2所示，提供一硅材料的衬底，其表面包括第一区域和第二区域，两个区域的表面均为（100）晶面。在一些实施方式中，硅衬底210的导电类型可以包括高阻、N型导电、P型导电等多种形式。
S020：在硅衬底210表面为（100）晶面的第二区域内形成CMOS器件。
如图3所示，在硅衬底210表面为（100）晶面的第二区域内制作CMOS器件。由于CMOS器件能够与第二区域的（100）晶面形成良好的晶格适配，从而使得制作于第二区域表面的CMOS器件也能够具有较高质量。
S030：在硅衬底210表面为（100）晶面的第一区域通过湿法腐蚀形成V形槽，V形槽的表面为（111）晶面。
对S010提供的硅衬底210表面为（100）晶面的第一区域进行湿法腐蚀，湿法腐蚀时所采用的腐蚀液可以是碱性腐蚀液（加热的KOH或TMAH溶液），通过碱性腐蚀液对硅衬底210表面为（100）晶面的第一区域进行晶向处理，从而能够在硅衬底210的第一区域表面腐蚀出凹坑，并且腐蚀能够停止于（111）晶面，进而在硅衬底210的第一区域的表面形成V形槽，且V形槽的表面为（111）晶面，得到如图7所示的器件结构。
S040：在V形槽表面形成具有氮化物异质结240的氮化物器件400，得到预制器件。
通过S030获得一个第一区域表面为（111）晶面的硅衬底210，以V形槽表面的（111）晶面为依托形成具有氮化物异质结240的氮化物器件400，由于氮化物器件400的氮化物异质结240与（111）晶面具有良好的晶格匹配度，因此，能够使得制作于第一区域V形槽表面的氮化物器件400具有较高质量，进而得到如图9所示的预制器件。
综上所述，可以根据氮化物器件400和CMOS器件各自所需要的不同晶向，通过对硅衬底210表面的第一区域进行晶向处理从而形成（111）晶面，同时，保留硅衬底210表面第二区域的（100）晶面，使得硅衬底210表面同时具有第一区域的（111）晶面和第二区域的（100）晶面，从而能使得制作于第一区域的氮化物器件400和制作于第二区域的CMOS器件都能够具有较高的质量，从而满足高质量器件的要求，同时也实现了具有氮化物异质结240的氮化物器件400与CMOS器件在硅衬底210表面的集成。
可选的，通过S030在硅衬底210表面为（100）晶面的第一区域通过湿法腐蚀形成V形槽时，如图4所示，可以先在硅衬底210的表面为（100）晶面的第一区域和第二区域形成整层覆盖的绝缘层220，即绝缘层220覆盖第一区域和第二区域的CMOS器件表面；如图5所示，然后通过光刻工艺，使绝缘层220图形化，从而在绝缘层220上形成所需要的图案，应当理解的是，具有图案的绝缘层220包括覆盖第一区域表面的实体部分和露出第一区域表面的虚体部分；如图6所示，接着通过湿法腐蚀对硅衬底210位于第一区域的表面进行晶向处理，因此，腐蚀液能够对露出于第一区域的硅衬底210表面进行腐蚀，由于（111）晶面的原子密度较高，故腐蚀停止于（111）晶面，从而在硅衬底210第一区域的表面形成至少一个V形槽，且V形槽的表面为（111）晶面，然后去除位于V形槽正上方的绝缘层220，得到如图7所示的器件结构。绝缘层220能够在第一区域进行晶向处理和制作氮化物器件400的过程中，隔离CMOS器件，避免对CMOS器件造成不利影响。同时，如图5和图6所示，绝缘层220还能够作为第一区域进行晶向处理形成V形槽时的掩膜层。如图7至图9所示，仅去除位于V形槽正上方绝缘层220的部分，如图9所示，使得剩余部分的绝缘层220覆盖CMOS器件上表面以及覆盖除V形槽外的硅衬底210表面，如此，也能够对氮化物器件400和CMOS器件进行有效的绝缘隔离。
需要说明的是，如图5和图6所示，通过光刻工艺在绝缘层220上形成图案后，可以使得被图形化处理的绝缘层220部分包括多个子掩膜结构，多个子掩膜结构形成阵列排布的结构形式，每个子掩膜结构的尺寸相同，且相邻两个子掩膜结构之间的间距也相同，如此，能够使得后续形成于硅衬底210表面第一区域的V形槽结构、尺寸相同，且也能够阵列排布，从而为后续外延生长成核层230时，提供较为均匀的生长环境，便于实现顶面平整的成核层230，从而提高外延成核层230的质量。例如图5所示，每子掩膜结构均为长条形结构，且多个长条形结构的子掩膜结构阵列排布，每个长条形结构的子掩膜结构的尺寸相同，且相邻两个长条形结构的子掩膜结构之间的间距也相同。
还需要说明的是，相邻两个子掩膜结构之间的间距决定了后续形成V形槽的（111）晶面的面积，例如，当间距增大时，对应的，V形槽容积变大，（111）晶面的面积也变大，反之亦然。
在一些实施方式中，如图5所示，在对整层绝缘层220进行图形化时，可以直接通过光刻的方式将硅表面露出。
在一些实施方式中，如图6所示，当形成的V形槽为多个，且多个V形槽之间连续，从而使得相邻两个V形槽形成W形结构，如此，能够使得硅衬底210第一区域的表面均为（111）晶面，从而能够便于在硅衬底210位于第一区域的表面外延生长出高质量的成核层230。
可选的，通过S040在V形槽表面形成具有氮化物异质结240的氮化物器件400时，如图8所示，先在具有V形槽的第一区域的表面外延生长成核层230，由于V形槽表面为（111）晶面，因此，外延生长的成核层230能够与硅衬底210位于第一区域的表面为（111）晶面的V形槽进行良好的晶格适配，使得成核层230具有较高的质量。应当理解的是，成核层230的厚度至少大于或等于V形槽的深度，从而使得成核层230能够覆盖V形槽，使得成核层230的顶面处于同一平面内，且与硅衬底210的底面平行，进而获得一个顶面较为平坦的成核层230，以该成核层230为基础，继续在成核层230顶面外延生长氮化物异质结240，由于氮化物异质结240能够与成核层230形成较好的晶格匹配，因此，能够提高氮化物异质结240的质量，同时，由于成核层230顶面较为平坦，因此，能够对氮化物异质结240提供较为平整的外延平面，从而进一步的提高氮化物异质结240的质量。最后在氮化物异质结240表面制作电极，从而形成氮化物器件400。
可选的，通过S040在V形槽表面形成具有氮化物异质结240的氮化物器件400之后，方法还包括：如图10所示，在预制器件表面上整层形成覆盖CMOS器件和氮化物器件400的钝化层260，从而能够对图9所示的器件结构的上表面进行有效的钝化保护，提高整个器件的防水汽侵入能力。
如图10 所示，形成的钝化层260可以进行平坦化处理，从而使得钝化层260的顶面较为平坦，能够提高金属线在钝化层260顶面布线时的连续性和可靠性。
如图11所示，通过光刻加刻蚀工艺由钝化层260顶面分别向内延伸的第一互连孔271和第二互连孔272，其中，第一互连孔271由钝化层260顶面延伸至氮化物器件400的电极，第二互连孔272由钝化层260顶面延伸至CMOS器件的电极。
如图12所示，通过第一互连孔271形成与氮化物器件400的电极金属互连的第一互连金属281，通过第二互连孔272形成与CMOS器件的电极金属互连的第二互连金属282，并且使得第一互连金属281和第二互连金属282在钝化层260顶面进行金属互连，实现CMOS器件和氮化物器件400的互连。
在一些实施方式中，如图12所示，第一互连金属281包括通过电镀工艺形成于第一互连孔271内的通孔金属和位于钝化层260顶面且与通孔金属连接的连接金属；第二互连金属282同理，第一互连金属281和第二互连金属282在钝化层260顶面可以通过连接金属进行金属互连。应当理解的是，氮化物器件400和CMOS器件的互连可以根据实际需求进行连接，例如图12所示，氮化物器件400的漏极D与硅基器件300的源极S互连。
在一些实施方式中，如图10所示，在钝化层260的材质为介质材料（氧化硅、氮化硅、氧化铝、氮氧化硅等）时，可以通过沉积（沉积方式可以是PECVD、LPCVD、Sputtering等）形成钝化层260后，利用化学机械研磨工艺对钝化层260的顶面进行平坦化处理，从而使其形成较为平坦的顶面；在钝化层260的材质为绝缘有机材料时，可以采用旋转涂布的方式实现钝化层260顶面的平坦化。
在一些实施方式中，如图8所示，在V形槽内的（111）晶面上外延生长成核层230时，可以在V形槽内的（111）晶面上先快速沉积形成多个不连续的岛状成核点，然后依托多个岛状成核点通过三维生长形成连续的面，并最终形成覆盖V形槽的成核层230，以此获得一个顶面较为平整的成核层230。
可选的，如图7所示，V形槽的开口宽度为c，V形槽的深度为h，其中，V形槽的开口宽度c为V形槽的深度h的1.43倍，V形槽侧壁的（111）晶面与水平面的夹角为54.7度，如此，形成的V形槽较浅，便于成核层230外延生长成为平面型。
在一些实施方式中，如图7和图8所示，V形槽的深度h可以小于100nm，如此，能够便于后续外延生长的成核层230将其完全覆盖。
在一些实施方式中，如图9所示，氮化物异质结240包括依次生长于成核层230上的缓冲层、沟道层和势垒层，以便形成氮化物高电子迁移率晶体管的基本结构。应当理解的是，缓冲层、沟道层和势垒层可以均为三五族化合物，其中，缓冲层和沟道层可以是二元、三元化合物，势垒层可以是三元、四元化合物。在一些实施方式中，缓冲层和沟道层可以是同种材质，例如均为GaN，从而简化外延步骤。
在一些实施方式中，缓冲层的材质为GaN和Al xGa 1-xN中的一种。缓冲层可以掺杂Fe、C、O等元素，或者无掺杂。
在一些实施方式中，缓冲层的厚度可以为20nm至8μm，具体设置时，可以根据实际需求合理选择。
在一些实施方式中，沟道层的材质为GaN和Al xGa 1-xN中的一种。沟道层可以非故意掺杂或者掺杂Fe、C、O等。
在一些实施方式中，沟道层的厚度为10nm至200nm，具体设置时，可以根据实际需求合理选择。
在一些实施方式中，势垒层的材质AlN、InN、Al xGa 1-xN、In xAl 1-xN和In xAl yGaN中的一种。
在一些实施方式中，势垒层的厚度为1nm至50nm，具体设置时，可以根据实际需求合理选择。
在一些实施方式中，成核层230的材质为AlN。
在一些实施方式中，成核层230的厚度为10nm至100nm，具体设置时，可以根据实际需求合理选择，但应当理解的是，为便于获得顶面较为平整的成核层230，因此，在外延成核层230时，应当使得成核层230的厚度大于V形槽的深度，使得成核层230能够完全覆盖V形槽。
以上所述仅为本申请的优选实施例而已，并不用于限制本申请，对于本领域的技术人员来说，本申请可以有各种更改和变化。凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (10)

  1. 一种氮化物器件和CMOS器件集成结构，其特征在于，包括：硅衬底，所述硅衬底包括第一区域和表面为（100）晶面的第二区域；设置于所述硅衬底第二区域（100）晶面上的CMOS器件；设置于所述硅衬底第一区域的V形槽，所述V形槽的表面为（111）晶面；设置于所述（111）晶面上具有氮化物异质结的氮化物器件。
  2. 如权利要求1所述的集成结构，其特征在于，还包括保护层，所述保护层覆盖于所述硅衬底上的CMOS器件和氮化物器件，且所述保护层提供一平坦顶面。
  3. 如权利要求2所述的集成结构，其特征在于，还包括互连的第一互连金属和第二互连金属，所述第一互连金属由所述保护层顶面延伸至所述氮化物器件，以与所述氮化物器件金属互连，所述第二互连金属由所述保护层顶面延伸至所述CMOS器件，以与所述CMOS器件金属互连。
  4. 如权利要求2所述的集成结构，其特征在于，所述保护层包括依次设置的绝缘层和钝化层，所述绝缘层覆盖于所述CMOS器件和所述硅衬底表面除所述V形槽外的区域，所述钝化层覆盖于所述绝缘层和所述氮化物器件的上表面。
  5. 如权利要求1所述的集成结构，其特征在于，所述氮化物器件还包括成核层和电极，所述成核层、所述氮化物异质结和所述电极依次设置于所述V形槽表面，其中，所述成核层覆盖于所述V形槽以提供一平坦顶面。
  6. 如权利要求1所述的集成结构，其特征在于，所述CMOS器件包括分立器件和/或电路结构。
  7. 一种氮化物器件和CMOS器件集成结构制备方法，其特征在于，所述方法包括：提供硅衬底，所述硅衬底包括表面均为（100）晶面的第一区域和第二区域；在所述硅衬底表面为（100）晶面的第二区域内形成CMOS器件；在所述硅衬底表面为（100）晶面的第一区域通过湿法腐蚀形成V形槽，所述V形槽的表面为（111）晶面；在所述V形槽表面形成具有氮化物异质结的氮化物器件，得到预制器件。
  8. 如权利要求7所述的制备方法，其特征在于，所述在所述硅衬底表面为（100）晶面的第一区域通过湿法腐蚀形成V形槽包括：在所述硅衬底表面形成绝缘层，所述绝缘层覆盖所述第一区域和具有所述CMOS器件的第二区域；通过光刻对所述绝缘层进行图形化以在所述第一区域露出所述硅衬底表面；对在所述第一区域露出的硅衬底表面进行湿法腐蚀以形成至少一个V形槽，所述V形槽的表面为（111）晶面。
  9. 如权利要求7所述的制备方法，其特征在于，所述在所述V形槽表面形成具有氮化物异质结的氮化物器件包括：在所述V形槽表面外延生长覆盖于所述V形槽的成核层，以通过所述成核层提供一平坦顶面；在所述成核层的平坦顶面依次形成氮化物异质结和电极，以形成所述氮化物器件。
  10. 如权利要求7所述的制备方法，其特征在于，在所述V形槽表面形成具有氮化物异质结的氮化物器件之后，所述方法还包括：在所述预制器件表面形成覆盖所述CMOS器件和所述氮化物器件的钝化层；对所述钝化层进行平坦化处理以使所述钝化层提供一平坦顶面；通过刻蚀由所述钝化层顶面形成分别延伸至所述氮化物器件和所述CMOS器件的第一互连孔和第二互连孔；分别通过所述第一互连孔和所述第二互连孔形成与所述氮化物器件金属互连的第一互连金属以及与所述CMOS器件金属互连的第二互连金属，所述第一互连金属和所述第二互连金属互连。
PCT/CN2022/118855 2021-12-13 2022-09-15 氮化物器件和 cmos 器件集成结构及其制备方法 WO2023109218A1 (zh)

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