WO2023108398A1 - 环栅器件及其后栅单扩散隔断工艺方法以及器件制备方法 - Google Patents

环栅器件及其后栅单扩散隔断工艺方法以及器件制备方法 Download PDF

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WO2023108398A1
WO2023108398A1 PCT/CN2021/137775 CN2021137775W WO2023108398A1 WO 2023108398 A1 WO2023108398 A1 WO 2023108398A1 CN 2021137775 W CN2021137775 W CN 2021137775W WO 2023108398 A1 WO2023108398 A1 WO 2023108398A1
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gate
source
drain
dummy
stress
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French (fr)
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刘桃
张卫
徐敏
汪大伟
孙新
潘哲成
吴春蕾
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Fudan University
Shanghai IC Manufacturing Innovation Center Co Ltd
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Fudan University
Shanghai IC Manufacturing Innovation Center Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]

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  • the present invention relates to the field of semiconductors, and in particular to a gate-around device, a post-gate single-diffusion isolation process method, and a device preparation method.
  • Transistor devices can be understood as switch structures made of semiconductor materials. With the development of semiconductor technology, transistor devices have developed from planar transistors to FinFET transistors, and then to ring-gate transistors.
  • the gate-around transistor can also be understood as a GAA transistor or GAAFET. Among them, the full name of GAA is: Gate-All-Around, which means a full-surround gate technology.
  • the N-type transistor and the P-type transistor there is a difference in the carrier mobility, so that the current capability of the N-type transistor and the P-type transistor is different under the same size.
  • the electron mobility of N-type transistors is almost twice that of P-type transistors.
  • the way to solve this problem is to use the source-drain silicon germanium (SiGe) stress technology of planar transistors.
  • SiGe source-drain silicon germanium
  • the electron mobility of the N-type transistor has been greatly improved, while the hole mobility of the P-type transistor has been reduced, resulting in the carrier mobility of the N-type GAA transistor and the P-type GAA transistor.
  • single diffusion break SDB
  • DDB double diffusion break
  • the invention provides a ring-gate device, a back-gate single-diffusion isolation process method and a device preparation method, so as to reduce stress relaxation in the single-diffusion isolation process and improve device performance.
  • a gate-all-around device single-diffusion isolation process method including:
  • a plurality of fin structures are formed on the substrate structure, the plurality of fin structures are arranged on the substrate structure along a first direction, and shallow trench isolation structures are arranged between adjacent fin structures;
  • Each of the plurality of fin structures includes alternately stacked sacrificial layers and channel layers;
  • a plurality of dummy gate structures are formed along the second direction on each fin structure, and the dummy gate structures straddle the corresponding fin structures; the dummy gate structures include dummy dummy gates and active dummy gates; The second direction is perpendicular to the first direction;
  • Source/drain layers in the source/drain cavity to form source/drain regions
  • a diffusion isolation layer is formed in the single diffusion isolation cavity.
  • the forming a plurality of fin structures on the substrate structure specifically includes:
  • the stack comprising alternately stacked sacrificial layers and channel layers;
  • the fin structure is etched on the stack to form the fin structure.
  • the method before performing source/drain etching on the fin structure by using the gate structure as a mask to form a source/drain cavity, the method further includes: depositing a spacer layer on the dummy gate structure.
  • the epitaxial source/drain layer in the source/drain cavity, before forming the source/drain region further includes:
  • An inner spacer layer is formed in the recessed area.
  • the epitaxial source/drain layer is formed in the source/drain cavity and the source/drain region is formed, it further includes:
  • An interlayer dielectric is deposited on the substrate structure, the interlayer dielectric covering the source/drain regions.
  • the forming the active metal gate specifically includes:
  • a metal gate is deposited on the high-k dielectric.
  • a method for manufacturing a gate-all-around device including the above-mentioned gate-all-around device single-diffusion isolation process method.
  • the manufacturing method of the gate-all-around device further includes: forming a device contact.
  • a gate-all-around device is also provided, which is manufactured by using the above-mentioned method for manufacturing a gate-all-around device.
  • the etching of the dummy dummy gate used to form the single-diffusion isolation cavity is carried out after the active metal gate of the GAA device is prepared.
  • the source/drain region will apply stress to the fin structures on both sides (the fin structure corresponding to the active dummy gate and the fin structure corresponding to the dummy dummy gate); after the channel is released, the fin structure corresponding to the active dummy gate Only the channel layer is left, so the stress of the source/drain region will be concentrated on the channel layer, so that the stress of the channel layer is enhanced.
  • the dummy gate and its corresponding fin structure have not been processed at this time, it will also transfer stress to the channel layer of the GAA device, so that the stress of the channel layer of the GAA device reaches the maximum; at the same time, due to the dummy gate Before the etching of the dummy gate, the channel layer of the GAA device has been wrapped by the active metal gate. Since the high dielectric constant dielectric material in the active metal gate is not easily deformed, the stress on the channel layer is generated. The confinement effect minimizes the effect of relaxation on the stress of the channel layer of the GAA device after subsequent dummy gate etching. The stress relaxation problem in the existing single-diffusion isolation process is effectively solved.
  • Fig. 1 is a schematic flow diagram 1 of a gate-all-around device single-diffusion isolation process method provided by an embodiment of the present invention
  • Fig. 2 is a schematic flow diagram II of a gate-all-around device single-diffusion isolation process method provided by an embodiment of the present invention
  • 3-15 are partial schematic diagrams of the device structure corresponding to each step of the gate-all-around device single-diffusion isolation process method provided by an embodiment of the present invention.
  • 16 is a stress simulation effect diagram of each step of the gate-last single-diffusion isolation process method of the present invention, the traditional single-diffusion isolation process and the self-aligned single-diffusion isolation process for P-type GAA devices;
  • FIG. 17 is a schematic structural diagram of a complete device fabricated by a gate-last single-diffusion isolation process.
  • first and second are only used for description purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Thus, a feature defined as “first” and “second” may explicitly or implicitly include one or more of these features.
  • a plurality means a plurality, such as two, three, four, etc., unless otherwise specifically defined.
  • connection and other terms should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral body; it can be a mechanical connection , can also be electrically connected or can communicate with each other; it can be directly connected or indirectly connected through an intermediary, and it can be the internal communication of two components or the interaction relationship between two components.
  • connection and other terms should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral body; it can be a mechanical connection , can also be electrically connected or can communicate with each other; it can be directly connected or indirectly connected through an intermediary, and it can be the internal communication of two components or the interaction relationship between two components.
  • the applicant Before proposing the present invention, the applicant has fully studied the single-diffusion isolation process of GAA devices at advanced nodes.
  • the single-diffusion isolation process for GAA devices is mainly:
  • Epitaxial fin structure stacks on the substrate structure (sacrificial layer/channel layer arranged alternately);
  • this process puts the step of forming the single-diffusion isolation cavity between the step of forming the interlayer dielectric and the step of removing the dummy gate, and other process steps are similar to the traditional process.
  • the stress of the source/drain region on the channel layer is very important to the performance of the device.
  • the applicant finds that there will be different degrees of stress relaxation.
  • the applicant conducted a series of stress simulations and found that the stress of the above two processes will relax to different degrees after the formation of the single-diffusion isolation cavity, so that the stress of the final channel layer maintains at lower level.
  • FIG. 1 Schematic flow chart 1 of the gate-all-around device single-diffusion isolation process method provided by an embodiment of the invention
  • Figures 3 to 15 show the steps corresponding to each step of the gate-all-around device single-diffusion isolation process method provided by an embodiment of the invention
  • Schematic diagram of the device structure wherein, Fig. 4 is a schematic cross-sectional view of Fig. 3 taken from the cross-section line B-B, and Fig. 5 is a schematic cross-sectional view of Fig. 3 taken from the cross-section line A-A, and Fig. 6-Fig. 15 is shown on the basis of Fig. 5 Schematic diagram of the device structure under different process steps.
  • the gate-all-around device single-diffusion isolation process method includes the following steps:
  • the substrate structure 101 may be a silicon substrate or a strain-relaxed buffer layer (SRB, Strain Relaxed Buffer), and of course it may also be other substrates. As long as the substrate structure meets the requirements of the GAA device, it is within the protection scope of the present invention.
  • SRB strain-relaxed buffer layer
  • S2 Form a plurality of fin structures 110 on the substrate structure 101, and the plurality of fin structures 110 are arranged along a first direction on the substrate structure 101, as shown in FIG. 3; the first in FIG. 3 One direction can be understood as a direction perpendicular to the channel direction of the final GAA device, and the second direction can be understood as a direction along the channel of the final GAA device, so the first direction is perpendicular to the second direction.
  • a shallow trench isolation (STI, Shallow Trench Isolation) structure 120 is arranged between each adjacent fin structure 110, and each fin structure 110 in the plurality of fin structures includes alternately stacked sacrificial layers 111 and channel layers 112, as shown in Figure 4.
  • STI Shallow Trench Isolation
  • FIG. 3 and FIG. 4 Four fin structures are shown in FIG. 3 and FIG. 4 as an example. In fact, after this step is completed, multiple fin structures will be formed on the underlying structure. The number is not limited to four, and can be other numbers.
  • the forming a plurality of fin structures on the substrate structure further includes:
  • the stack includes alternately stacked sacrificial layers 111 and channel layers 112;
  • the fin structure is etched on the stack to form the fin structure 110 .
  • the adjacent fin structures 110 are isolated by the shallow trench isolation structure 120 .
  • S3 Form a plurality of dummy gate structures along the second direction on each fin structure, and the dummy gate structures straddle the corresponding fin structures; the dummy gate structures include dummy dummy gates 132 and active dummy gates Pole 131, as shown in FIG. 6 .
  • step S3 may include the following sub-steps:
  • a plurality of dummy gate stacks 130 are formed along the second direction on each fin structure, as shown in FIG. the top and sides of the fin structure;
  • the dummy gate stack 105 is etched to form a plurality of dummy gate structures, as shown in FIG. 6 ; wherein, the plurality of dummy gate structures are distributed along the second direction in sequence.
  • the dummy gate structure can be divided into a dummy dummy gate 132 and an active dummy gate 131 according to its function, wherein the dummy dummy gate 132 will be etched eventually to form a single diffusion isolation cavity; The gate 131 will eventually be etched to form an active metal gate.
  • the dummy gate structure can use metal gate materials, specifically, different metal gate materials can be used according to the type of ions doped in the corresponding regions.
  • a step S31 is also included: depositing a spacer layer 140 on the dummy gate structures.
  • a schematic diagram of the device structure after this step is shown in FIG. 7.
  • step S4 also includes step S41: forming an inner spacer; specifically, step S41 includes the following sub-steps:
  • An inner spacer layer 141 is formed in the recessed region; a schematic diagram of the device structure after this step is shown in FIG. 9 .
  • S5 Epitaxial source/drain layers in the source/drain cavity 150 to form source/drain regions 151 .
  • a step S51 is further included: depositing an interlayer dielectric 160; specifically including:
  • the deposited interlayer dielectric 160 is planarized, specifically, chemical mechanical polishing may be performed to planarize the deposited interlayer dielectric 160 .
  • a schematic diagram of the device structure after this step is completed is shown in FIG. 10 .
  • this step includes the following sub-steps:
  • the sacrificial layer 111 in the corresponding fin structure is removed, and the schematic diagram of the device structure after this step is shown in FIG. 12 ; wherein, the sacrificial layer 111 can be removed by an etching process.
  • This step specifically includes:
  • a metal gate (not shown) is deposited on the high-k dielectric 170 .
  • the high-permittivity dielectric 170 can be a conventional high-permittivity dielectric material.
  • a diffusion isolation layer 180 is formed in the single diffusion isolation cavity; a schematic diagram of the device structure after this step is shown in FIG. 15 .
  • the diffusion isolation layer 180 may specifically be an insulating layer, such as silicon dioxide or the like.
  • the etching of the dummy dummy gate used to form the single-diffusion isolation cavity is carried out after the active metal gate of the GAA device is prepared.
  • the source/drain region will apply stress to the fin structures on both sides (the fin structure corresponding to the active dummy gate and the fin structure corresponding to the dummy dummy gate); after the channel is released, the fin structure corresponding to the active dummy gate Only the channel layer is left, so the stress of the source/drain region will be concentrated on the channel layer, so that the stress of the channel layer is enhanced.
  • the dummy gate and its corresponding fin structure have not been processed at this time, it will also transfer stress to the channel layer of the GAA device, so that the stress of the channel layer of the GAA device reaches the maximum; at the same time, due to the dummy gate Before the etching of the dummy gate, the channel layer of the GAA device has been wrapped by the active metal gate. Since the high dielectric constant dielectric material in the active metal gate is not easily deformed, the stress on the channel layer is generated. The confinement effect minimizes the effect of relaxation on the stress of the channel layer of the GAA device after subsequent dummy gate etching. The stress relaxation problem in the existing single-diffusion isolation process is effectively solved.
  • the applicant also carried out the stress simulation of each process step, using the gate-last single diffusion isolation process method of the present invention, the channel stress is increased to about +3.2GPa. It has also been significantly improved.
  • Fig. 3-Fig. 15 only illustrate the structural diagrams of partial devices prepared by the gate-around device on the back gate single diffusion isolation process of the present invention.
  • the single diffusion isolation The process usually has one or more active dummy gates between two dummy dummy gates.
  • a schematic illustration is made of the situation that there is an active dummy gate between two dummy dummy gates.
  • FIG. 17 The local device repeatable unit 1 in FIG. 15 schematically illustrates the structure.
  • the complete repeatable unit shown in FIG. 17 is a structure in which there is an active dummy gate between two dummy dummy gates; wherein, the partial device repeatable unit 1 is half of the complete repeatable unit.
  • a method for manufacturing a gate-all-around device including the above-mentioned gate-all-around device single-diffusion isolation process method.
  • the manufacturing method of the gate-all-around device further includes: forming a device contact.
  • a gate-all-around device is also provided, which is manufactured by using the above-mentioned method for manufacturing a gate-all-around device.

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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本发明提供了一种环栅器件上后栅单扩散隔断工艺方法，其用于形成单扩散隔断空腔的虚设伪栅极的刻蚀是在GAA器件的有源金属栅极制备完成后才进行，由于源/漏区会向两侧的鳍结构施加应力；而在沟道释放后，有源伪栅极对应的鳍结构中只剩下了沟道层，因而源/漏区的应力会集中到沟道层上，使得沟道层的应力得到增强。并且由于此时虚设伪栅极及其对应的鳍结构还未进行处理，其也会向GAA器件的沟道层传递应力，使得GAA器件的沟道层的应力达到最大；同时，由于在进行虚设伪栅极的刻蚀前，GAA器件的沟道层已经被有源金属栅极包裹，其对沟道层的应力产生禁锢作用，使得在后续虚设伪栅极刻蚀后，GAA器件的沟道层的应力因弛豫带来的影响降到最低。

Description

环栅器件及其后栅单扩散隔断工艺方法以及器件制备方法 技术领域
本发明涉及领域半导体领域，尤其涉及一种环栅器件及其后栅单扩散隔断工艺方法以及器件制备方法。
背景技术
晶体管器件，可理解为用半导体材料制作的开关结构。随着半导体技术的发展，晶体管器件从平面晶体管发展到FinFET晶体管，再发展到环栅晶体管。环栅晶体管也可理解为GAA晶体管、GAAFET。其中，GAA的全称为：Gate-All-Around，表示一种全环绕式栅极技术。
对于N型晶体管与P型晶体管而言，其载流子的迁移率存在差异，从而使得N型晶体管与P型晶体管在相同尺寸下的电流能力存在差异。其中对于平面晶体管而言，N型晶体管的电子迁移率比P型晶体管的空穴迁移率大了几乎一倍，解决这一问题的方式为通过平面晶体管的源漏锗硅(SiGe)应力技术来调节N型晶体管沟道和P型晶体管沟道的载流子迁移率。发展到FinFE晶体管时，N型晶体管与P型晶体管的载流子迁移率相差不大。而发展到GAA晶体管时，N型晶体管的电子迁移率有了很大的提高，而P型晶体管的空穴迁移率反而降低了，导致N型GAA晶体管和P型GAA晶体管的载流子迁移率相差很大。从而当把N型GAA晶体管和P型GAA晶体管进行集成时，电流匹配问题非常突出。同时，空穴迁移率对应力的敏感度增加，电子迁移率对应力的敏感度降低，这使得在GAA晶体管上对应力的需求增大。
在7nm技术节点以下，单扩散隔断(Single diffusion break，SDB)已经取代了双扩散隔断(Double diffusion break，DDB)以进一步增加晶体管密度。传统的SDB和自对准SDB(self-aligned SDB，SA-SDB)方案都会不同程度造成沟道应力弛豫。
因而，如何解决单扩散隔断工艺中的应力弛豫问题，已经成为业界亟需解决的技术问题。
发明内容
本发明提供一种环栅器件及其后栅单扩散隔断工艺方法以及器件制备方法，以降低单扩散隔断工艺中的应力弛豫，提高器件性能。
根据本发明的第一方面，提供给了一种环栅器件上后栅单扩散隔断工艺方法，包括：
提供一衬底结构；
在所述衬底结构上形成多个鳍结构，所述多个鳍结构在所述衬底结构上沿第一方向排布，各相邻鳍结构之间设置有浅沟槽隔离结构；所述多个鳍结构中的每个鳍结构包括交替层叠的牺牲层与沟道层；
在每个鳍结构上沿第二方向形成多个伪栅极结构，所述伪栅极结构横跨对应的鳍结构；所述伪栅极结构包括虚设伪栅极与有源伪栅极；所述第二方向与所述第一方向垂直；
以所述伪栅极结构为掩模，对所述鳍结构进行源/漏刻蚀，形成源/漏空腔；
在所述源/漏空腔内外延源/漏层，形成源/漏区；
去除所述有源伪栅极及所述有源伪栅极对应的鳍结构中的牺牲层，进行沟道释放；
形成有源金属栅极；
对所述虚设伪栅极及其覆盖的鳍结构进行刻蚀，直至刻蚀掉部分衬底结构，形成单扩散隔断空腔；以及
在所述单扩散隔断空腔中形成扩散隔离层。
可选的，所述在衬底结构上形成多个鳍结构具体包括：
在所述衬底结构上形成堆叠件，所述堆叠件包括交替层叠的牺牲层与沟道层；
对堆叠件进行鳍结构刻蚀，形成鳍结构。
可选的，在所述以栅极结构为掩模，对所述鳍结构进行源/漏刻蚀，形成源/漏空腔之前，还包括：在所述伪栅极结构上沉积间隔层。
可选的，在所述源/漏空腔内外延源/漏层，形成源/漏区之前还包括：
对源漏刻蚀后暴露在表面的牺牲层进行刻蚀，使其部分凹陷；
在凹陷区域形成内间隔层。
可选的，在所述源/漏空腔内外延源/漏层，形成源/漏区之后还包括：
在所述衬底结构上淀积层间电介质，所述层间电介质覆盖所述源/漏区。
可选的，所述形成有源金属栅极具体包括：
在所述释放沟道后的沟道层上淀积高介电常数电介质；以及
在所述高介电常数电介质上淀积金属栅极。
根据本发明的第二方面，还提供了一种环栅器件的制备方法，包括上述的环栅器件上后栅单扩散隔断工艺方法。
可选的，该环栅器件的制备方法在单扩散隔断空腔中形成扩散隔离层之后还包括：形成器件接触。
根据本发明的第三方面，还提供了一种环栅器件，采用上述的环栅器件的制备方法制备而成。
本发明提供的环栅器件上后栅单扩散隔断工艺方法，其用于形成单扩散隔断空腔的虚设伪栅极的刻蚀是在GAA器件的有源金属栅极制备完成后才进行，由于源/漏区会向两侧的鳍结构(有源伪栅极对应的鳍结构和虚设伪栅极对应的鳍结构)施加应力；而在沟道释放后，有源伪栅极对应的鳍结构中只剩下了沟道层，因而源/漏区的应力会集中到沟道层上，使得沟道层的应力得到增强。并且由于此时虚设伪栅极及其对应的鳍结构还未进行处理，其也会向GAA器件的沟道层传递应力，使得GAA器件的沟道层的应力达到最大；同时，由于在进行虚设伪栅极的刻蚀前，GAA器件的沟道层已经被有源金属栅极包裹，由于有源金属栅极中的高介电常数电介质材料不容易形变，因而其对沟道层的应力产生禁锢作用，使得在后续虚设伪栅极刻蚀后，GAA器件的沟道层的应力因弛豫带来的影响降到最低。有效地解决了现有的单扩散隔断工艺中的应力弛豫问题。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1是本发明一实施例提供的环栅器件上后栅单扩散隔断工艺方法的流程示意图一；
图2是本发明一实施例提供的环栅器件上后栅单扩散隔断工艺方法的流程示意图二；
图3-图15是本发明一实施例提供的环栅器件上后栅单扩散隔断工艺方法各步骤对应的器件结构的局部示意图。
图16是针对P型GAA器件本发明的后栅单扩散隔断工艺方法与传统的单扩散隔断工艺以及自对准单扩散隔断工艺的各步骤的应力仿真效果图；
图17为后栅单扩散隔断工艺方法制备的完整器件的结构示意图。
附图标记说明：
1-局部器件可重复单元；
101-衬底结构；
110-鳍结构；
111-牺牲层；
112-沟道层；
130-伪栅极堆叠件；
131-有源伪栅极；
132-虚设伪栅极；
140-间隔层；
150-源/漏空腔；
141-内间隔层；
151-源/漏层；
160-层间电介质；
170-高K栅介质；
180-扩散隔离层；
A-A、B-B-横剖面线；
a-传统的单扩散隔断工艺各步骤对应的应力仿真曲线；
b-自对准单扩散隔断工艺各步骤对应的应力仿真曲线；
c-本发明的后栅单扩散隔断工艺方法各步骤对应的应力仿真曲线。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行 清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
在本发明说明书的描述中，需要理解的是，术语“上部”、“下部”、“上端”、“下端”、“下表面”、“上表面”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。
在本发明说明书的描述中，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。
在本发明的描述中，“多个”的含义是多个，例如两个，三个，四个等，除非另有明确具体的限定。
在本发明说明书的描述中，除非另有明确的规定和限定，术语“连接”等术语应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或成一体；可以是机械连接，也可以是电连接或可以互相通讯；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本发明中的具体含义。
下面以具体的实施例对本发明的技术方案进行详细说明。下面这几个具体的实施例可以相互结合，对于相同或相似的概念或过程可能在某些实施例不再赘述。
在提出本发明之前，申请人对于先进节点的GAA器件的单扩散隔断工艺进行了充分研究，目前针对GAA器件的单扩散隔断工艺主要为：
一、传统的单扩散隔断工艺
该工艺的具体流程为：
a.在衬底结构上外延鳍结构堆叠件(牺牲层/沟道层交替排列)；
b.将鳍结构堆叠件图形化；
c.鳍结构刻蚀以及鳍结构截断，形成鳍结构以及单扩散隔断空腔；
d.填充隔离层，形成STI以及扩散隔离层；
e.在鳍结构上形成伪栅极；
f.源/漏刻蚀以及形成源/漏区；
g.形成层间电介质；
h.去除伪栅极；
i.去除牺牲层，释放沟道；
j.形成高K栅介质；
k.形成金属接触。
二、自对准单扩散隔断工艺
该工艺相对于传统工艺而言，将形成单扩散隔断空腔的步骤放到形成层间电介质这一步骤与去除伪栅极这一步骤之间，其它工艺步骤与传统工艺类似。
对于GAA器件而言，源/漏区对于沟道层的应力对器件的性能影响至关重要。而对于上述两种工艺，申请人发现都会存在不同程度的应力弛豫。为了弄清楚应力弛豫的缘由，申请人进行了一系列的应力仿真，发现上述两种工艺在形成单扩散隔断空腔后，应力都会发生不同程度的弛豫，使得最终沟道层的应力维持在较低的水平。
申请人通过进一步跟踪各个工艺步骤的应力仿真并研究分析后，发现上述两种工艺造成应力弛豫的原因是：上述两种工艺在形成单扩散隔断空腔时都会造成沟道层两端形成自由表面，应力由自由表面的通道造成松弛，从而使得最终沟道层的应力较低。
基于此，申请人针对GAA器件的需要，创造性地提出了一种新的环栅器件上后栅单扩散隔断工艺方法，请参考图1，并结合图3至图15，其中，图1为本发明一实施例提供的环栅器件上后栅单扩散隔断工艺方法的流程示意图一；图3-图15为本发明一实施例提供的环栅器件上后栅单扩散隔断工艺方法各步骤对应的器件结构示意图。其中，图4是从横剖面线B-B截取的图3的横剖面示意图，图5是从横剖面线A-A截取的图3的横剖面示意图，图6-图15是在图5的基础上示出的不同工艺步骤下的器件结构示意图。
结合图1、图3-图15，本发明实施例提供的环栅器件上后栅单扩散隔断工艺方法包括以下步骤：
S1:提供一衬底结构101。
其中，该衬底结构101可以为硅衬底或者应变弛豫的缓冲层(SRB，Strain Relaxed Buffer)，当然也可以为其他衬底。只要满足GAA器件要求的衬底结构均在本发明的保护范围之内。
S2:在所述衬底结构101上形成多个鳍结构110，所述多个鳍结构110在所述衬底结构101上沿第一方向排布，如图3所示；图3中的第一方向可以理解为与最终GAA器件的沟道方向垂直的方向，第二方向可以理解为沿最终GAA器件的沟道的方向，因而第一方向与第二方向垂直。
其中，各相邻鳍结构110之间设置有浅沟槽隔离(STI，Shallow Trench Isolation)结构120，所述多个鳍结构中的每个鳍结构110包括交替层叠的牺牲层111与沟道层112，如图4所示。
图3和图4中示出四个鳍结构作为示例，事实上该步骤完成后，会在底层结构上形成多个鳍结构，数量并不限于四个，可以为其它数量。
在一个具体实施方式中，所述在衬底结构上形成多个鳍结构进一步包括：
在所述衬底结构101上形成堆叠件，该堆叠件包括交替层叠的牺牲层111与沟道层112；
对堆叠件进行鳍结构刻蚀，形成鳍结构110。并且相邻鳍结构110之间通过浅沟槽隔离结构120进行隔离。
S3：在每个鳍结构上沿第二方向形成多个伪栅极结构，所述伪栅极结构横跨对应的鳍结构；所述伪栅极结构包括虚设伪栅极132与有源伪栅极131，如图6所示。
具体地，步骤S3可包括以下子步骤：
先在每个鳍结构上沿第二方向形成多个伪栅极堆叠件130，如图5所示；伪栅极堆叠件130横跨对应的鳍结构，具体地，伪栅极堆叠件130覆盖鳍结构的顶部及两侧；
接着对伪栅极堆叠件105进行刻蚀，形成多个伪栅极结构，如图6所示；其中，多个伪栅极结构沿第二方向依次分布。其中，伪栅极结构依据其作用可以分为虚设伪栅极132与有源伪栅极131，其中的虚设伪栅极132最终会被刻蚀而形成单扩散隔断空腔；其中的有源伪栅极131最终会被刻蚀而形成有源金属栅极。伪栅极结构可采用金属栅材料，具体的，可以根据对应区掺 杂的离子的类型，采用不同的金属栅材料。
作为一优选实施方式，如图2所示，在形成多个伪栅极结构后，还包括步骤S31：在所述伪栅极结构上沉积间隔层140，该步骤完成后的器件结构示意图如图7所示。
S4：以所述伪栅极结构为掩模，对所述鳍结构进行源/漏刻蚀，形成源/漏空腔150；刻蚀后的器件结构如图8所示。
作为一优选实施方式，如图2所示，在步骤S4后还包括步骤S41:形成内间隔层；具体地，步骤S41包括以下子步骤：
对源漏刻蚀后暴露在表面的牺牲层111进行刻蚀，使其部分凹陷；
在凹陷区域形成内间隔层141；该步骤完成后的器件结构示意图如图9所示。
S5：在所述源/漏空腔150内外延源/漏层，形成源/漏区151。
作为一优选实施方式，如图2所示，在形成源/漏区151后还包括步骤S51：淀积层间电介质160；具体地包括：
在所述衬底结构上淀积层间电介质160，所述层间电介质160覆盖所述源/漏区151；
对淀积的层间电介质160进行平坦化，具体地，可进行化学机械抛光，使得淀积的层间电介质160平坦化。该步骤完成后的器件结构示意图如图10所示。
S6：去除有源伪栅极131及有源伪栅极131对应的鳍结构中的牺牲层111，进行沟道释放。具体地，该步骤包括以下子步骤：
去除有源伪栅极131，该步骤完成后的器件结构示意图如图11所示；其中，可通过刻蚀工艺去除有源伪栅极131；
去除对应鳍结构中的牺牲层111，该步骤完成后的器件结构示意图如图12所示；其中，可通过刻蚀工艺去除牺牲层111。
S7：形成有源金属栅极。该步骤具体包括：
在所述释放沟道后的沟道层112上淀积高介电常数电介质170；该步骤完成后的器件结构示意图如图13所示；以及
在所述高介电常数电介质170上淀积金属栅极(未示出)。
其中的高介电常数电介质170可以采用常规的高介电常数电介质材料。
S8：对所述虚设伪栅极132及其覆盖的鳍结构进行刻蚀，直至刻蚀掉部分衬底结构，形成单扩散隔断空腔；该步骤完成后的器件结构示意图如图14所示；以及
在所述单扩散隔断空腔中形成扩散隔离层180；该步骤完成后的器件结构示意图如图15所示。其中的扩散隔离层180具体可以为绝缘层，例如二氧化硅等。
本发明提供的环栅器件上后栅单扩散隔断工艺方法，其用于形成单扩散隔断空腔的虚设伪栅极的刻蚀是在GAA器件的有源金属栅极制备完成后才进行，由于源/漏区会向两侧的鳍结构(有源伪栅极对应的鳍结构和虚设伪栅极对应的鳍结构)施加应力；而在沟道释放后，有源伪栅极对应的鳍结构中只剩下了沟道层，因而源/漏区的应力会集中到沟道层上，使得沟道层的应力得到增强。并且由于此时虚设伪栅极及其对应的鳍结构还未进行处理，其也会向GAA器件的沟道层传递应力，使得GAA器件的沟道层的应力达到最大；同时，由于在进行虚设伪栅极的刻蚀前，GAA器件的沟道层已经被有源金属栅极包裹，由于有源金属栅极中的高介电常数电介质材料不容易形变，因而其对沟道层的应力产生禁锢作用，使得在后续虚设伪栅极刻蚀后，GAA器件的沟道层的应力因弛豫带来的影响降到最低。有效地解决了现有的单扩散隔断工艺中的应力弛豫问题。
为了与现有的单扩散隔断工艺进行比对，申请人针对各工艺方法对对应的各步骤进行了应力仿真跟踪，请参考图16，其中，曲线a为传统的单扩散隔断工艺各步骤对应的应力仿真曲线；曲线b为自对准单扩散隔断工艺各步骤对应的应力仿真曲线；曲线c为本发明的后栅单扩散隔断工艺方法各步骤对应的应力仿真曲线；图16的纵坐标表征应力大小，其横坐标表征各工艺步骤；图中的SDB代表的是单扩散隔断步骤(即形成单扩散隔断空腔)。由图16可知，对于P型GAA器件而言，曲线a中在形成SDB后，其应力大小在1.5GPa左右，并且后续沟道层的应力大小维持在-1GPa左右；曲线b中在形成SDB后，其应力大小在1GPa左右，并且后续沟道层的应力大小维持在0GPa左右；曲线c中在形成SDB后，其应力大小在-4.4GPa左右，并且后续沟道层的应力大小维持在-4.4GPa左右。因而可以得出，采用本发明的后栅单扩散隔断工艺方法，其沟道应力得到显著的提升。
同样的，对于N型GAA器件，申请人也进行了各工艺步骤的应力仿真，采用本发明的后栅单扩散隔断工艺方法，其沟道应力提高至+3.2GPa左右。同样得到了显著的提升。
需要说明的是，图3-图15仅以示意出了本发明环栅器件上后栅单扩散隔断工艺方法制备的局部器件的结构示意图，实际情况中，在沿沟道长度方向，单扩散隔断工艺通常是两个虚设伪栅极之间存在有一个或多个有源伪栅极。本申请中是以两个虚设伪栅极之间存在有一个有源伪栅极的情况进行示意说明，请参照图17所示，图17中的局部器件可重复单元1即为图3-图15示意出的结构。图17所示的完整的可重复单元是两个虚设伪栅极之间存在有一个有源伪栅极的结构；其中，局部器件可重复单元1是完整的可重复单元的一半。
根据本发明的第二方面，还提供了一种环栅器件的制备方法，包括上述的环栅器件上后栅单扩散隔断工艺方法。并且，该环栅器件的制备方法在单扩散隔断空腔中形成扩散隔离层之后还包括：形成器件接触。
根据本发明的第三方面，还提供了一种环栅器件，采用上述的环栅器件的制备方法制备而成。
在本说明书的描述中，参考术语“一种实施方式”、“一种实施例”、“具体实施过程”、“一种举例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本发明的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
最后应说明的是：以上各实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述各实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。

Claims (9)

  1. 一种环栅器件上后栅单扩散隔断工艺方法，其特征在于，包括：
    提供一衬底结构；
    在所述衬底结构上形成多个鳍结构，所述多个鳍结构在所述衬底结构上沿第一方向排布，各相邻鳍结构之间设置有浅沟槽隔离结构；所述多个鳍结构中的每个鳍结构包括交替层叠的牺牲层与沟道层；
    在每个鳍结构上沿第二方向形成多个伪栅极结构，所述伪栅极结构横跨对应的鳍结构；所述伪栅极结构包括虚设伪栅极与有源伪栅极；所述第二方向与所述第一方向垂直；
    以所述伪栅极结构为掩模，对所述鳍结构进行源/漏刻蚀，形成源/漏空腔；
    在所述源/漏空腔内外延源/漏层，形成源/漏区；
    去除所述有源伪栅极及所述有源伪栅极对应的鳍结构中的牺牲层，进行沟道释放；
    形成有源金属栅极；
    对所述虚设伪栅极及其覆盖的鳍结构进行刻蚀，直至刻蚀掉部分衬底结构，形成单扩散隔断空腔；以及
    在所述单扩散隔断空腔中形成扩散隔离层。
  2. 根据权利要求1所述的环栅器件上后栅单扩散隔断工艺方法，其特征在于，所述在衬底结构上形成多个鳍结构具体包括：
    在所述衬底结构上形成堆叠件，所述堆叠件包括交替层叠的牺牲层与沟道层；
    对堆叠件进行鳍结构刻蚀，形成鳍结构。
  3. 根据权利要求1所述的环栅器件上后栅单扩散隔断工艺方法，其特征在于，在所述以栅极结构为掩模，对所述鳍结构进行源/漏刻蚀，形成源/漏空腔之前，还包括：在所述伪栅极结构上沉积间隔层。
  4. 根据权利要求1所述的环栅器件上后栅单扩散隔断工艺方法，其特征在于，在所述源/漏空腔内外延源/漏层，形成源/漏区之前还包括：
    对源漏刻蚀后暴露在表面的牺牲层进行刻蚀，使其部分凹陷；
    在凹陷区域形成内间隔层。
  5. 根据权利要求1所述的环栅器件上后栅单扩散隔断工艺方法，其特征 在于，在所述源/漏空腔内外延源/漏层，形成源/漏区之后还包括：
    在所述衬底结构上淀积层间电介质，所述层间电介质覆盖所述源/漏区。
  6. 根据权利要求5所述的环栅器件上后栅单扩散隔断工艺方法，其特征在于，所述形成有源金属栅极具体包括：
    在所述释放沟道后的沟道层上淀积高介电常数电介质；以及
    在所述高介电常数电介质上淀积金属栅极。
  7. 一种环栅器件的制备方法，包括权利要求1至6任一项所述的环栅器件上后栅单扩散隔断工艺方法。
  8. 根据权利要求7所述的环栅器件的制备方法，其特征在于，所述在单扩散隔断空腔中形成扩散隔离层之后还包括：
    形成器件接触。
  9. 一种环栅器件，其特征在于，采用权利要求7所述的环栅器件的制备方法制备而成。
PCT/CN2021/137775 2021-12-14 2021-12-14 环栅器件及其后栅单扩散隔断工艺方法以及器件制备方法 Ceased WO2023108398A1 (zh)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180175194A1 (en) * 2016-12-15 2018-06-21 Commissariat A L'energie Atomique Et Aux Energies Alternatives Method for making a semiconductor device with a compressive stressed channel
CN113394295A (zh) * 2021-06-10 2021-09-14 上海集成电路制造创新中心有限公司 P型环栅器件堆叠结构及增强p型环栅器件沟道应力方法
CN113497036A (zh) * 2020-03-19 2021-10-12 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180175194A1 (en) * 2016-12-15 2018-06-21 Commissariat A L'energie Atomique Et Aux Energies Alternatives Method for making a semiconductor device with a compressive stressed channel
CN113497036A (zh) * 2020-03-19 2021-10-12 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
CN113394295A (zh) * 2021-06-10 2021-09-14 上海集成电路制造创新中心有限公司 P型环栅器件堆叠结构及增强p型环栅器件沟道应力方法

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