WO2023108398A1

WO2023108398A1 - Gate-all-around device and gate-last single diffusion break process method therefor, and preparation method for device

Info

Publication number: WO2023108398A1
Application number: PCT/CN2021/137775
Authority: WO
Inventors: 刘桃; 张卫; 徐敏; 汪大伟; 孙新; 潘哲成; 吴春蕾
Original assignee: 复旦大学; 上海集成电路制造创新中心有限公司
Priority date: 2021-12-14
Filing date: 2021-12-14
Publication date: 2023-06-22

Abstract

Provided in the present invention is a gate-last single diffusion break process method on a gate-all-around (GAA) device. By means of the method, the etching of dummy gates for forming a single diffusion break cavity is performed after the preparation of an active metal gate of a GAA device is completed; and source/drain regions may apply stress to fin structures on two sides, and after channel release, only channel layers are left in the fin structures corresponding to an active dummy gate, such that the stress of the source/drain regions is concentrated in the channel layers, and the stress of the channel layers is enhanced. In addition, the dummy gates and the fin structures corresponding thereto are not processed at this time and same may also transmit the stress to the channel layers of the GAA device, such that the stress of the channel layers of the GAA device reaches the maximum; moreover, the channel layers of the GAA device are wrapped by the active metal gate before the etching of the dummy gates is performed, and the active metal gate has a confinement effect on the stress of the channel layers, such that after the dummy gates are subsequently etched, the influence caused by the relaxation of the stress of the channel layers of the GAA device is minimized.

Description

Gate-all-around device, gate-back single-diffusion isolation process method and device preparation method

technical field

The present invention relates to the field of semiconductors, and in particular to a gate-around device, a post-gate single-diffusion isolation process method, and a device preparation method.

Background technique

Transistor devices can be understood as switch structures made of semiconductor materials. With the development of semiconductor technology, transistor devices have developed from planar transistors to FinFET transistors, and then to ring-gate transistors. The gate-around transistor can also be understood as a GAA transistor or GAAFET. Among them, the full name of GAA is: Gate-All-Around, which means a full-surround gate technology.

For the N-type transistor and the P-type transistor, there is a difference in the carrier mobility, so that the current capability of the N-type transistor and the P-type transistor is different under the same size. Among them, for planar transistors, the electron mobility of N-type transistors is almost twice that of P-type transistors. The way to solve this problem is to use the source-drain silicon germanium (SiGe) stress technology of planar transistors. The carrier mobility of the N-type transistor channel and the P-type transistor channel is adjusted. When developing to FinFE transistors, the carrier mobility of N-type transistors and P-type transistors is not much different. When developing to the GAA transistor, the electron mobility of the N-type transistor has been greatly improved, while the hole mobility of the P-type transistor has been reduced, resulting in the carrier mobility of the N-type GAA transistor and the P-type GAA transistor. A big difference. Therefore, when the N-type GAA transistor and the P-type GAA transistor are integrated, the current matching problem is very prominent. Simultaneously, the sensitivity of hole mobility to stress increases, and the sensitivity of electron mobility to stress decreases, which makes the demand for stress increase on the GAA transistor.

Below the 7nm technology node, single diffusion break (SDB) has replaced double diffusion break (DDB) to further increase transistor density. Traditional SDB and self-aligned SDB (self-aligned SDB, SA-SDB) schemes will cause channel stress relaxation to varying degrees.

Therefore, how to solve the stress relaxation problem in the single-diffusion isolation process has become an urgent technical problem in the industry.

Contents of the invention

The invention provides a ring-gate device, a back-gate single-diffusion isolation process method and a device preparation method, so as to reduce stress relaxation in the single-diffusion isolation process and improve device performance.

According to the first aspect of the present invention, there is provided a gate-all-around device single-diffusion isolation process method, including:

providing a substrate structure;

A plurality of fin structures are formed on the substrate structure, the plurality of fin structures are arranged on the substrate structure along a first direction, and shallow trench isolation structures are arranged between adjacent fin structures; Each of the plurality of fin structures includes alternately stacked sacrificial layers and channel layers;

A plurality of dummy gate structures are formed along the second direction on each fin structure, and the dummy gate structures straddle the corresponding fin structures; the dummy gate structures include dummy dummy gates and active dummy gates; The second direction is perpendicular to the first direction;

Using the dummy gate structure as a mask, performing source/drain etching on the fin structure to form a source/drain cavity;

Epitaxial source/drain layers in the source/drain cavity to form source/drain regions;

removing the active dummy gate and the sacrificial layer in the fin structure corresponding to the active dummy gate to release the channel;

forming an active metal gate;

Etching the dummy dummy gate and its covered fin structure until part of the substrate structure is etched away to form a single-diffusion isolation cavity; and

A diffusion isolation layer is formed in the single diffusion isolation cavity.

Optionally, the forming a plurality of fin structures on the substrate structure specifically includes:

forming a stack on the substrate structure, the stack comprising alternately stacked sacrificial layers and channel layers;

The fin structure is etched on the stack to form the fin structure.

Optionally, before performing source/drain etching on the fin structure by using the gate structure as a mask to form a source/drain cavity, the method further includes: depositing a spacer layer on the dummy gate structure.

Optionally, the epitaxial source/drain layer in the source/drain cavity, before forming the source/drain region, further includes:

Etching the sacrificial layer exposed on the surface after source and drain etching to make it partially recessed;

An inner spacer layer is formed in the recessed area.

Optionally, after the epitaxial source/drain layer is formed in the source/drain cavity and the source/drain region is formed, it further includes:

An interlayer dielectric is deposited on the substrate structure, the interlayer dielectric covering the source/drain regions.

Optionally, the forming the active metal gate specifically includes:

depositing a high-k dielectric on the channel layer after releasing the channel; and

A metal gate is deposited on the high-k dielectric.

According to the second aspect of the present invention, there is also provided a method for manufacturing a gate-all-around device, including the above-mentioned gate-all-around device single-diffusion isolation process method.

Optionally, after forming the diffusion isolation layer in the single diffusion isolation cavity, the manufacturing method of the gate-all-around device further includes: forming a device contact.

According to the third aspect of the present invention, a gate-all-around device is also provided, which is manufactured by using the above-mentioned method for manufacturing a gate-all-around device.

In the gate-all-around device single-diffusion isolation process method provided by the present invention, the etching of the dummy dummy gate used to form the single-diffusion isolation cavity is carried out after the active metal gate of the GAA device is prepared. The source/drain region will apply stress to the fin structures on both sides (the fin structure corresponding to the active dummy gate and the fin structure corresponding to the dummy dummy gate); after the channel is released, the fin structure corresponding to the active dummy gate Only the channel layer is left, so the stress of the source/drain region will be concentrated on the channel layer, so that the stress of the channel layer is enhanced. And since the dummy gate and its corresponding fin structure have not been processed at this time, it will also transfer stress to the channel layer of the GAA device, so that the stress of the channel layer of the GAA device reaches the maximum; at the same time, due to the dummy gate Before the etching of the dummy gate, the channel layer of the GAA device has been wrapped by the active metal gate. Since the high dielectric constant dielectric material in the active metal gate is not easily deformed, the stress on the channel layer is generated. The confinement effect minimizes the effect of relaxation on the stress of the channel layer of the GAA device after subsequent dummy gate etching. The stress relaxation problem in the existing single-diffusion isolation process is effectively solved.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. For those skilled in the art, other drawings can also be obtained according to these drawings without any creative effort.

Fig. 1 is a schematic flow diagram 1 of a gate-all-around device single-diffusion isolation process method provided by an embodiment of the present invention;

Fig. 2 is a schematic flow diagram II of a gate-all-around device single-diffusion isolation process method provided by an embodiment of the present invention;

3-15 are partial schematic diagrams of the device structure corresponding to each step of the gate-all-around device single-diffusion isolation process method provided by an embodiment of the present invention.

16 is a stress simulation effect diagram of each step of the gate-last single-diffusion isolation process method of the present invention, the traditional single-diffusion isolation process and the self-aligned single-diffusion isolation process for P-type GAA devices;

FIG. 17 is a schematic structural diagram of a complete device fabricated by a gate-last single-diffusion isolation process.

Explanation of reference signs:

1- Partial device repeatable unit;

101 - substrate structure;

110 - fin structure;

111 - sacrificial layer;

112 - channel layer;

130 - a dummy gate stack;

131 - active dummy gate;

132 - dummy dummy gate;

140-interval layer;

150 - source/drain cavity;

141 - inner compartment layer;

151 - source/drain layer;

160 - interlayer dielectric;

170-high K gate dielectric;

180-diffusion isolation layer;

A-A, B-B-cross-section line;

a- Stress simulation curves corresponding to each step of the traditional single-diffusion isolation process;

b-The stress simulation curve corresponding to each step of the self-aligned single diffusion isolation process;

c- Stress simulation curves corresponding to each step of the gate-last single-diffusion isolation process method of the present invention.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

In the description of the specification of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "upper part", "lower part", "upper end", "lower end", "lower surface" and "upper surface" are based on the drawings The orientations or positional relationships shown are only for the convenience of describing the present invention and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be construed as an important aspect of the present invention. limits.

In the description of the specification of the present invention, the terms "first" and "second" are only used for description purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Thus, a feature defined as "first" and "second" may explicitly or implicitly include one or more of these features.

In the description of the present invention, "a plurality" means a plurality, such as two, three, four, etc., unless otherwise specifically defined.

In the description of the specification of the present invention, unless otherwise clearly stipulated and limited, the term "connection" and other terms should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral body; it can be a mechanical connection , can also be electrically connected or can communicate with each other; it can be directly connected or indirectly connected through an intermediary, and it can be the internal communication of two components or the interaction relationship between two components. Those of ordinary skill in the art can understand the specific meanings of the above terms in the present invention according to specific situations.

The technical solution of the present invention will be described in detail below with specific examples. The following specific embodiments may be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments.

Before proposing the present invention, the applicant has fully studied the single-diffusion isolation process of GAA devices at advanced nodes. Currently, the single-diffusion isolation process for GAA devices is mainly:

1. Traditional single diffusion partition process

The specific flow of the process is:

a. Epitaxial fin structure stacks on the substrate structure (sacrificial layer/channel layer arranged alternately);

b. patterning the fin structure stack;

c. Fin structure etching and fin structure truncation to form fin structure and single diffusion isolation cavity;

d. Fill the isolation layer to form STI and diffusion isolation layer;

e. forming a dummy gate on the fin structure;

f. Source/drain etching and formation of source/drain regions;

g. forming an interlayer dielectric;

h. Remove the dummy gate;

i. Remove the sacrificial layer and release the channel;

j. Forming a high-K gate dielectric;

k. Forming metal contacts.

2. Self-aligned single diffusion isolation process

Compared with the traditional process, this process puts the step of forming the single-diffusion isolation cavity between the step of forming the interlayer dielectric and the step of removing the dummy gate, and other process steps are similar to the traditional process.

For GAA devices, the stress of the source/drain region on the channel layer is very important to the performance of the device. For the above two processes, the applicant finds that there will be different degrees of stress relaxation. In order to clarify the cause of the stress relaxation, the applicant conducted a series of stress simulations and found that the stress of the above two processes will relax to different degrees after the formation of the single-diffusion isolation cavity, so that the stress of the final channel layer maintains at lower level.

After the applicant further traced the stress simulation of each process step and researched and analyzed, it was found that the reason for the stress relaxation caused by the above two processes is that the above two processes will cause free surface, the stress is relaxed by the channels in the free surface, resulting in a lower stress in the final channel layer.

Based on this, the applicant creatively proposed a new single-diffusion isolation process method for gate-all-around devices based on the needs of GAA devices. Please refer to Figure 1, combined with Figures 3 to 15. Schematic flow chart 1 of the gate-all-around device single-diffusion isolation process method provided by an embodiment of the invention; Figures 3 to 15 show the steps corresponding to each step of the gate-all-around device single-diffusion isolation process method provided by an embodiment of the invention Schematic diagram of the device structure. Wherein, Fig. 4 is a schematic cross-sectional view of Fig. 3 taken from the cross-section line B-B, and Fig. 5 is a schematic cross-sectional view of Fig. 3 taken from the cross-section line A-A, and Fig. 6-Fig. 15 is shown on the basis of Fig. 5 Schematic diagram of the device structure under different process steps.

Referring to Fig. 1, Fig. 3-Fig. 15, the gate-all-around device single-diffusion isolation process method provided by the embodiment of the present invention includes the following steps:

S1: Provide a substrate structure 101.

Wherein, the substrate structure 101 may be a silicon substrate or a strain-relaxed buffer layer (SRB, Strain Relaxed Buffer), and of course it may also be other substrates. As long as the substrate structure meets the requirements of the GAA device, it is within the protection scope of the present invention.

S2: Form a plurality of fin structures 110 on the substrate structure 101, and the plurality of fin structures 110 are arranged along a first direction on the substrate structure 101, as shown in FIG. 3; the first in FIG. 3 One direction can be understood as a direction perpendicular to the channel direction of the final GAA device, and the second direction can be understood as a direction along the channel of the final GAA device, so the first direction is perpendicular to the second direction.

Wherein, a shallow trench isolation (STI, Shallow Trench Isolation) structure 120 is arranged between each adjacent fin structure 110, and each fin structure 110 in the plurality of fin structures includes alternately stacked sacrificial layers 111 and channel layers 112, as shown in Figure 4.

Four fin structures are shown in FIG. 3 and FIG. 4 as an example. In fact, after this step is completed, multiple fin structures will be formed on the underlying structure. The number is not limited to four, and can be other numbers.

In a specific implementation manner, the forming a plurality of fin structures on the substrate structure further includes:

forming a stack on the substrate structure 101, the stack includes alternately stacked sacrificial layers 111 and channel layers 112;

The fin structure is etched on the stack to form the fin structure 110 . And the adjacent fin structures 110 are isolated by the shallow trench isolation structure 120 .

S3: Form a plurality of dummy gate structures along the second direction on each fin structure, and the dummy gate structures straddle the corresponding fin structures; the dummy gate structures include dummy dummy gates 132 and active dummy gates Pole 131, as shown in FIG. 6 .

Specifically, step S3 may include the following sub-steps:

First, a plurality of dummy gate stacks 130 are formed along the second direction on each fin structure, as shown in FIG. the top and sides of the fin structure;

Next, the dummy gate stack 105 is etched to form a plurality of dummy gate structures, as shown in FIG. 6 ; wherein, the plurality of dummy gate structures are distributed along the second direction in sequence. Among them, the dummy gate structure can be divided into a dummy dummy gate 132 and an active dummy gate 131 according to its function, wherein the dummy dummy gate 132 will be etched eventually to form a single diffusion isolation cavity; The gate 131 will eventually be etched to form an active metal gate. The dummy gate structure can use metal gate materials, specifically, different metal gate materials can be used according to the type of ions doped in the corresponding regions.

As a preferred implementation manner, as shown in FIG. 2, after forming a plurality of dummy gate structures, a step S31 is also included: depositing a spacer layer 140 on the dummy gate structures. A schematic diagram of the device structure after this step is shown in FIG. 7.

S4: Using the dummy gate structure as a mask, perform source/drain etching on the fin structure to form a source/drain cavity 150; the device structure after etching is shown in FIG. 8 .

As a preferred embodiment, as shown in Figure 2, after step S4, also includes step S41: forming an inner spacer; specifically, step S41 includes the following sub-steps:

Etching the sacrificial layer 111 exposed on the surface after source and drain etching to partially recess it;

An inner spacer layer 141 is formed in the recessed region; a schematic diagram of the device structure after this step is shown in FIG. 9 .

S5: Epitaxial source/drain layers in the source/drain cavity 150 to form source/drain regions 151 .

As a preferred implementation manner, as shown in FIG. 2, after forming the source/drain region 151, a step S51 is further included: depositing an interlayer dielectric 160; specifically including:

depositing an interlayer dielectric 160 on the substrate structure, the interlayer dielectric 160 covering the source/drain region 151;

The deposited interlayer dielectric 160 is planarized, specifically, chemical mechanical polishing may be performed to planarize the deposited interlayer dielectric 160 . A schematic diagram of the device structure after this step is completed is shown in FIG. 10 .

S6: removing the active dummy gate 131 and the sacrificial layer 111 in the fin structure corresponding to the active dummy gate 131 to perform channel release. Specifically, this step includes the following sub-steps:

Removing the active dummy gate 131, the schematic diagram of the device structure after this step is shown in Figure 11; wherein, the active dummy gate 131 can be removed by an etching process;

The sacrificial layer 111 in the corresponding fin structure is removed, and the schematic diagram of the device structure after this step is shown in FIG. 12 ; wherein, the sacrificial layer 111 can be removed by an etching process.

S7: forming an active metal gate. This step specifically includes:

Depositing a high dielectric constant dielectric 170 on the channel layer 112 after releasing the channel; the schematic diagram of the device structure after this step is shown in FIG. 13 ; and

A metal gate (not shown) is deposited on the high-k dielectric 170 .

The high-permittivity dielectric 170 can be a conventional high-permittivity dielectric material.

S8: Etching the dummy dummy gate 132 and its covered fin structure until part of the substrate structure is etched away to form a single-diffusion isolation cavity; the schematic diagram of the device structure after this step is shown in FIG. 14 ; as well as

A diffusion isolation layer 180 is formed in the single diffusion isolation cavity; a schematic diagram of the device structure after this step is shown in FIG. 15 . The diffusion isolation layer 180 may specifically be an insulating layer, such as silicon dioxide or the like.

In order to compare with the existing single-diffusion isolation process, the applicant carried out stress simulation tracking for each process method, please refer to Figure 16, where curve a is the stress corresponding to each step of the traditional single-diffusion isolation process Stress simulation curve; curve b is the stress simulation curve corresponding to each step of the self-aligned single-diffusion isolation process; curve c is the stress simulation curve corresponding to each step of the rear gate single-diffusion isolation process method of the present invention; the ordinate in Figure 16 represents the stress The abscissa represents each process step; the SDB in the figure represents the single-diffusion block step (that is, the formation of a single-diffusion block cavity). It can be seen from Figure 16 that for a P-type GAA device, after the SDB is formed in curve a, the stress is about 1.5GPa, and the stress of the subsequent channel layer is maintained at about -1GPa; in curve b, after the SDB is formed , the stress is about 1GPa, and the stress of the subsequent channel layer is maintained at about 0GPa; in curve c, after the SDB is formed, the stress is about -4.4GPa, and the stress of the subsequent channel layer is maintained at -4.4 Around GPa. Therefore, it can be concluded that by using the gate-last single-diffusion isolation process method of the present invention, the channel stress is significantly improved.

Similarly, for the N-type GAA device, the applicant also carried out the stress simulation of each process step, using the gate-last single diffusion isolation process method of the present invention, the channel stress is increased to about +3.2GPa. It has also been significantly improved.

It should be noted that Fig. 3-Fig. 15 only illustrate the structural diagrams of partial devices prepared by the gate-around device on the back gate single diffusion isolation process of the present invention. In actual situations, along the channel length direction, the single diffusion isolation The process usually has one or more active dummy gates between two dummy dummy gates. In this application, a schematic illustration is made of the situation that there is an active dummy gate between two dummy dummy gates. Please refer to FIG. 17. The local device repeatable unit 1 in FIG. 15 schematically illustrates the structure. The complete repeatable unit shown in FIG. 17 is a structure in which there is an active dummy gate between two dummy dummy gates; wherein, the partial device repeatable unit 1 is half of the complete repeatable unit.

According to the second aspect of the present invention, there is also provided a method for manufacturing a gate-all-around device, including the above-mentioned gate-all-around device single-diffusion isolation process method. In addition, after the formation of the diffusion isolation layer in the single diffusion isolation cavity, the manufacturing method of the gate-all-around device further includes: forming a device contact.

In the description of this specification, descriptions referring to terms such as "one embodiment", "an embodiment", "a specific implementation process", "an example" mean specific features described in conjunction with the embodiment or example, A structure, material or characteristic is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than limiting them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: It is still possible to modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the various embodiments of the present invention. scope.

Claims

A gate-all-round device single-diffusion isolation process method, characterized in that it includes:

providing a substrate structure;

A plurality of fin structures are formed on the substrate structure, the plurality of fin structures are arranged on the substrate structure along a first direction, and shallow trench isolation structures are arranged between adjacent fin structures; Each of the plurality of fin structures includes alternately stacked sacrificial layers and channel layers;

A plurality of dummy gate structures are formed along the second direction on each fin structure, and the dummy gate structures straddle the corresponding fin structures; the dummy gate structures include dummy dummy gates and active dummy gates; The second direction is perpendicular to the first direction;

Using the dummy gate structure as a mask, performing source/drain etching on the fin structure to form a source/drain cavity;

Epitaxial source/drain layers in the source/drain cavity to form source/drain regions;

removing the active dummy gate and the sacrificial layer in the fin structure corresponding to the active dummy gate to release the channel;

forming an active metal gate;

Etching the dummy dummy gate and its covered fin structure until part of the substrate structure is etched away to form a single-diffusion isolation cavity; and

A diffusion isolation layer is formed in the single diffusion isolation cavity.
The gate-all-around device single-diffusion isolation process method according to claim 1, wherein said forming a plurality of fin structures on the substrate structure specifically comprises:

forming a stack on the substrate structure, the stack comprising alternately stacked sacrificial layers and channel layers;

The fin structure is etched on the stack to form the fin structure.
The process method for gate-last single-diffusion isolation on a gate-around device according to claim 1, characterized in that, using the gate structure as a mask, performing source/drain etching on the fin structure to form source/drain spaces Before the cavity, it also includes: depositing a spacer layer on the dummy gate structure.
According to claim 1, the isolation process method of single-diffusion on the gate-all-around device, characterized in that, before the source/drain layer is epitaxially formed in the source/drain cavity and the source/drain region is formed, it further includes:

Etching the sacrificial layer exposed on the surface after source and drain etching to make it partially recessed;

An inner spacer layer is formed in the recessed area.
According to claim 1, the gate-all-around device single-diffusion isolation process method is characterized in that, after the epitaxial source/drain layer is formed in the source/drain cavity and the source/drain region is formed, it also includes:

An interlayer dielectric is deposited on the substrate structure, the interlayer dielectric covering the source/drain regions.
The gate-all-around device single-diffusion isolation process method according to claim 5, wherein said forming an active metal gate specifically comprises:

depositing a high-k dielectric on the channel layer after releasing the channel; and

A metal gate is deposited on the high-k dielectric.
A method for manufacturing a gate-all-around device, comprising the single-diffusion isolation process method on a gate-all-around device according to any one of claims 1 to 6.
The method for preparing a gate-all-around device according to claim 7, further comprising:

Form device contacts.
A gate-all-around device, characterized in that it is manufactured by the method for preparing a gate-all-around device according to claim 7.