CN113497036A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN113497036A
CN113497036A CN202010196421.1A CN202010196421A CN113497036A CN 113497036 A CN113497036 A CN 113497036A CN 202010196421 A CN202010196421 A CN 202010196421A CN 113497036 A CN113497036 A CN 113497036A
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forming
fin
gate
layer
opening
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CN113497036B (en
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王楠
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
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    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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    • H01L21/8232—Field-effect technology
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    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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Abstract

A semiconductor structure and a method of forming the same, wherein the method comprises: forming a first dummy gate structure on the first region and crossing the first initial fin structure; etching one or more first initial nanowires, and forming grooves on one side or two side walls of the first initial nanowires; after the groove is formed, removing the first initial fin part structures on two sides of the first pseudo gate structure, and forming a first fin part structure on the first region, so that the first initial nanowire forms a first nanowire, wherein two sides of the first fin part structure in the extension direction are provided with a first source drain opening, the side wall of the first source drain opening is exposed out of the groove, and the side wall of the first nanowire where the groove is located is recessed relative to the side wall of the first nanowire at the bottom of the groove; and forming an isolation structure in the groove, wherein the isolation structure is positioned between one or a plurality of first nanowires and the first source drain opening. The method can change the number of channels in the semiconductor structure, thereby meeting performance requirements.

Description

Semiconductor structure and forming method thereof
Technical Field
The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure and a method for forming the same.
Background
With the development of information technology, the amount of stored information has increased dramatically. The increase in the amount of stored information has promoted the rapid development of memories, and also has made higher demands on the stability of memories.
A basic Static Random Access Memory (SRAM) relies on six transistors that form two cross-coupled inverters. Each inverter includes: one pull-up transistor, one pull-down transistor, and one access transistor.
In order to obtain sufficient anti-interference capability and read stability, the transistors used to form the memory may be gate-all-around (GAA) structure transistors. The volume of the channel gate surrounding structure transistor used as a channel region is increased, and the working current of the channel gate surrounding structure transistor is further increased, so that the application of the channel gate surrounding structure transistor in a memory can improve the data storage stability and the integration level of the memory.
However, the performance of the semiconductor device formed by the existing static memory still needs to be improved.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which are used for forming semiconductor devices with different channel numbers so as to meet specific process requirements.
To solve the above technical problem, an embodiment of the present invention provides a semiconductor structure, including: a substrate comprising a first region and a second region; the first fin portion structure is positioned on the first area and comprises a plurality of first nanowires which are arranged along the normal direction of the surface of the substrate and are mutually separated; the first fin structure is positioned in the first region and transversely crosses the first fin structure, first source-drain openings are formed in the first fin structures on two sides of the first gate structure, grooves are formed in the side walls of the first source-drain openings on one side or two sides, the surfaces of one or more first nanowire side walls are exposed out of the grooves, and the side walls of the first nanowires where the grooves are located are recessed relative to the first nanowire side walls at the bottom of the grooves; an isolation structure located within the recess.
Optionally, the first gate structure includes: the first fin portion structure comprises a first gate dielectric layer crossing the first fin portion structure, a first gate electrode layer located on the surface of the first gate dielectric layer, and first side walls located on the surfaces of the side walls of the first gate dielectric layer and the first gate electrode layer.
Optionally, the isolation structure sidewall is flush with the first sidewall surface.
Optionally, the method further includes: the second fin portion structure is positioned on the second area and comprises a plurality of second nanowires which are arranged along the normal direction of the surface of the substrate and are mutually separated; a second gate structure located across the second fin structure in the second region.
Optionally, the second fin structures on two sides of the second gate structure have second source-drain openings therein.
Optionally, the method further includes: the first source-drain doping layer is positioned in the first source-drain opening and covers the surface of the side wall of the isolation structure; and the second source-drain doping layer is positioned in the second source-drain opening.
Optionally, the second gate structure includes: the second gate dielectric layer stretches across the second fin portion structure, the second gate electrode layer is located on the surface of the second gate dielectric layer, and the second side wall is located on the surfaces of the side walls of the second gate dielectric layer and the second gate electrode layer.
Optionally, a first fin recess and a first isolation layer located in the first fin recess are formed between adjacent first nanowires.
Optionally, a second fin recess and a second isolation layer located in the second fin recess are formed between adjacent second nanowires.
Optionally, the method further includes: a dielectric layer located on the substrate, wherein a first gate opening is formed in the dielectric layer, and the first gate opening exposes part of the top surface and the side wall surface of the first fin structure; the first gate structure is located within the first gate opening.
Optionally, a second gate opening is further formed in the dielectric layer, and the second gate opening exposes a portion of the top surface and the sidewall surface of the second fin structure; the second gate structure is located within the second gate opening.
Optionally, the method further includes: a first additional opening between adjacent first nanowires, the first gate opening exposing the first additional opening; the first gate structure is also located within the first additional opening and surrounds each of the first nanowires.
Optionally, the method further includes: a second additional opening between adjacent second nanowires, the second gate opening exposing the second additional opening; the second gate structure is also located in the second additional opening, and the second gate structure surrounds each of the second nanowires.
Correspondingly, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a first area and a second area, the first area is provided with a first initial fin part structure, and the first initial fin part structure comprises a plurality of first sacrificial layers overlapped along the normal direction of the surface of the substrate and first initial nanowires positioned on the surface of the first sacrificial layers; forming a first dummy gate structure on the first region and crossing the first initial fin structure; etching one or more first initial nanowires, and forming grooves on one side or two side walls of the first initial nanowires; after the groove is formed, removing the first initial fin part structures on two sides of the first pseudo gate structure, and forming a first fin part structure on the first region, so that the first initial nanowire forms a first nanowire, wherein two sides of the first fin part structure in the extension direction are provided with a first source drain opening, the side wall of the first source drain opening is exposed out of the groove, and the side wall of the first nanowire where the groove is located is recessed relative to the side wall of the first nanowire at the bottom of the groove; and forming an isolation structure in the groove, wherein the isolation structure is positioned between one or a plurality of first nanowires and the first source drain opening.
Optionally, a second initial fin structure is disposed on the substrate of the second region, and the second initial fin structure includes a plurality of second sacrificial layers overlapped along a normal direction of the substrate surface and a second initial nanowire located on a surface of the second sacrificial layer.
Optionally, the method further includes: forming a second dummy gate structure on the second region and crossing the second initial fin structure.
Optionally, the method for etching a plurality of the first initial nanowires includes: forming a mask layer on the first initial fin portion structure, the second initial fin portion structure, the first dummy gate structure and the second dummy gate structure, wherein the mask layer is internally provided with a mask opening, and the mask opening exposes the surface of the first initial fin portion structure; and etching the one or a plurality of first initial nanowires exposed from the mask opening by taking the mask layer as a mask until the surface of the first sacrificial layer is exposed, and forming the grooves on the side walls of the one or a plurality of first initial nanowires.
Optionally, the process of etching the one or more first initial nanowires exposed by the mask opening is a wet etching process; the parameters of the wet etching process comprise: the adopted etching solution comprises a tetramethylammonium hydroxide solution, and the concentration of the tetramethylammonium hydroxide solution is 3-20%.
Optionally, the mask opening exposes a side of the first initial fin structure away from the second region; and etching the plurality of first initial nanowires exposed from the mask opening by taking the mask layer as a mask, and forming the grooves on one sides of the plurality of first initial nanowires.
Optionally, the method further includes: and removing the second initial fin part structures on two sides of the second pseudo gate structure to enable the second initial nanowire to form a second nanowire, and forming a second fin part structure on the second region, wherein two sides of the second fin part structure in the extension direction are provided with second source drain openings.
Optionally, the method further includes: forming a first source drain doping layer in the first source drain opening, wherein the first source drain doping layer covers the surface of the side wall of the isolation structure; and forming a second source-drain doping layer in the second source-drain opening.
Optionally, the method further includes: after the first source drain opening and the second source drain opening are formed and before the first source drain doping layer and the second source drain doping layer are formed, a first fin portion groove is formed between adjacent first nanowires; forming a second fin portion groove between adjacent second nanowires; forming a first isolation layer in the first fin portion groove; forming a second isolation layer in the second fin portion groove; and after the first isolation layer and the second isolation layer are formed, forming a first source drain doping layer and a second source drain doping layer, wherein the first source drain doping layer covers the surface of the side wall of the first isolation layer, and the second source drain doping layer covers the surface of the side wall of the second isolation layer.
Optionally, the method for forming the first fin recess includes: etching part of the first sacrificial layer to form a first correcting sacrificial layer, wherein the side wall of the first correcting sacrificial layer is sunken relative to the side wall of the first nanowire, and a first fin part groove is formed between the adjacent first nanowires; the method for forming the second fin recess includes: and etching part of the second sacrificial layer to form a second correcting sacrificial layer, wherein the side wall of the second correcting sacrificial layer is sunken relative to the side wall of the second nanowire, and a second fin part groove is formed between the adjacent second nanowires.
Optionally, the isolation structure and the first and second isolation layers are formed in the same process.
Optionally, the method for forming the isolation structure and the first and second isolation layers includes: forming an isolation material film on the surface of the substrate, in the groove, in the first fin part groove, in the second fin part groove, on the top surface and the side wall surface of the first pseudo gate structure, on the top surface and the side wall surface of the second pseudo gate structure, and on the side wall surfaces of the first nanowire and the second nanowire; and etching the isolating material film back until the surface of the substrate, the surface of the side wall of the first nanowire and the surface of the side wall of the second nanowire are exposed, forming an isolating structure in the groove, forming the first isolating layer in the groove of the first fin part, and forming the second isolating layer in the groove of the second fin part.
Optionally, the top surface of the first initial fin structure and the top surface of the second initial fin structure further have a protective layer.
Optionally, the method for forming the first initial fin structure and the second initial fin structure includes: forming a fin material film on the substrate, wherein the fin material film comprises a plurality of sacrificial material films overlapped along the normal direction of the surface of the substrate and a nano material film positioned on the surface of the sacrificial material film; forming a protective film on the surface of the fin material film; forming a patterned layer on the surface of the protective film; and etching the fin material film and the protective film by taking the patterning layer as a mask until the surface of the substrate is exposed, so that the protective film forms a protective layer, a first sacrificial layer and a first initial nanowire positioned on the surface of the first sacrificial layer are formed on the first area, and a second sacrificial layer and a second initial nanowire positioned on the surface of the second sacrificial layer are formed on the second area.
Optionally, the method further includes: after the first source-drain doping layer and the second source-drain doping layer are formed, a dielectric layer is formed on the substrate and covers the first source-drain doping layer, the second source-drain doping layer, the first pseudo gate structure and the side wall surface of the second pseudo gate structure; forming a first gate opening and a second gate opening in the dielectric layer; forming a first additional opening between adjacent first nanowires exposed by the first gate opening; forming a second additional opening between adjacent second nanowires exposed by the second gate opening; forming first gate structures in the first gate openings and the first additional openings, wherein the first gate structures surround the first nanowires; and forming a second gate structure in the second gate opening and the second additional opening, wherein the second gate structure surrounds each second nanowire.
Optionally, the method for forming the first gate opening includes: removing the first pseudo gate structure, and forming a first gate opening in the dielectric layer; the forming method of the second gate opening comprises the following steps: and removing the second pseudo gate structure, and forming a second gate opening in the dielectric layer.
Optionally, the method for forming the first additional opening includes: removing the first sacrificial layer exposed by the first gate opening, and forming a first additional opening between the adjacent first nanowires; the method for forming the second additional opening comprises the following steps: and removing the second sacrificial layer exposed by the second gate opening, and forming a second additional opening between the adjacent second nano-phases.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
in the semiconductor structure provided by the technical scheme of the invention, the side wall of the first source drain opening at one side or two sides is provided with a groove, the groove exposes the surface of one or more side walls of the first nanowire, the side wall of the first nanowire where the groove is located is sunken relative to the side wall of the first nanowire at the bottom of the groove, and meanwhile, the side wall of the groove is exposed by the first source drain opening. The first source-drain doping layer is arranged in the first source-drain opening, and the isolation structure is arranged in the groove, namely, the isolation structure is positioned on the first source-drain doping layer and the first nanowire, so that the isolation structure can effectively isolate the first source-drain doping layer from the first nanowire, one or a plurality of first nanowires can not play a role of providing channels between the first source-drain doping layer, and the number of the channels in the semiconductor device can be changed.
Furthermore, the second nanowires on the second region can all function to provide channels between the second source-drain doped layers, so that the number of channels for forming semiconductor devices on the first region is less than that of channels for forming semiconductor devices on the second region, that is, the semiconductor devices on the first region and the second region have different channel numbers, and thus, specific process requirements can be met.
In the method for forming the semiconductor structure provided by the technical scheme of the invention, one or a plurality of first initial nanowires are etched, and grooves are formed on one side or two side walls of the first initial nanowires on the first region; and forming first source drain openings at two sides of the extending direction of the first fin structure, wherein the side walls of the first source drain openings are exposed out of the grooves, and the side walls of the first nanowires where the grooves are located are sunken relative to the side walls of the first nanowires at the bottom of the grooves. The isolation structure is formed in the groove and located between one or a plurality of first nanowires and the first source-drain opening, and the isolation structure can effectively isolate the first source-drain doping layer and the first nanowires which are formed in the first source-drain opening in a follow-up mode, so that one or a plurality of first nanowires cannot play a role of providing channels between the first source-drain doping layers, and the number of the channels in the semiconductor device can be changed.
Furthermore, the second nanowires on the second region can all function to provide channels between the second source-drain doped layers, so that the number of channels for forming semiconductor devices on the first region is less than that of channels for forming semiconductor devices on the second region, that is, the semiconductor devices on the first region and the second region have different channel numbers, and thus, specific process requirements can be met.
Furthermore, because the first pseudo gate structure in the second region easily affects one side of the first initial fin portion structure, when the mask opening exposes one side of the first initial fin portion structure far away from the second region, in the process of etching the one or the plurality of first initial nanowires, on one hand, the process difficulty of forming the groove is favorably reduced, and on the other hand, the second initial fin portion structure close to the first region is not easily affected, so that the appearance of the formed groove is good, the quality of the isolation structure formed in the groove is guaranteed, the isolation structure can effectively isolate the first source drain doping layer, semiconductor devices formed in the first region and the second region contain different channel numbers, and specific process requirements can be met.
Drawings
FIG. 1 is a schematic diagram of a semiconductor structure;
fig. 2 to 15 are schematic structural diagrams of steps of a semiconductor structure forming method according to an embodiment of the invention.
Detailed Description
As described in the background, the conventional semiconductor structure does not satisfy the process requirements, and is described in detail below with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a semiconductor structure.
Referring to fig. 1, a semiconductor structure includes: a substrate 100, the substrate 100 comprising a first region I and a second region II; the first fin structure 110 is located on the first region I, and the first gate structure 120 crosses the first fin structure 110, where the first fin structure 110 includes a plurality of first nanowires 111 arranged along a normal direction of a surface of the substrate 100 and separated from each other; the second fin structure 130 is located on the second region II, and the second gate structure 140 crosses the second fin structure 130, where the second fin structure 140 includes a plurality of second nanowires 131 arranged along the normal direction of the surface of the substrate 100 and separated from each other; the first source-drain doping layers 160 are located on two sides of the first fin structure 110 in the extending direction on the first region I; and the second source-drain doping layers 170 are positioned on the second region II and on two sides of the extending direction of the second fin structure 140.
In the above structure, the first nanowire 111 is used to provide a channel, the second nanowire 131 is used to provide a channel, the first gate structure 120 surrounds the first nanowire 111, and the second gate structure 140 surrounds the second nanowire 131, so that the device in the first region I is a channel gate surrounding structure transistor, and the device in the second region II is a channel gate surrounding structure transistor, so that the gating capability of the formed semiconductor structure is enhanced.
However, since the number of the first nanowires 111 in the first fin structure 110 and the number of the second nanowires 131 in the second fin structure 130 are the same, the semiconductor device on the first region I has the same number of channels as the semiconductor device on the second region II, and the semiconductor structure cannot satisfy specific process requirements.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
To solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: etching one or more first initial nanowires, and forming grooves on one side or two side walls of the first initial nanowires; after the groove is formed, removing the first initial fin part structures on two sides of the first pseudo gate structure, and forming a first fin part structure on the first region, so that the first initial nanowire forms a first nanowire, wherein two sides of the first fin part structure in the extension direction are provided with a first source drain opening, the side wall of the first source drain opening is exposed out of the groove, and the side wall of the first nanowire where the groove is located is recessed relative to the side wall of the first nanowire at the bottom of the groove; and forming an isolation structure in the groove, wherein the isolation structure is positioned between one or a plurality of first nanowires and the first source drain opening. The method can fulfill the need of changing the number of channels in the semiconductor device.
Fig. 2 to 15 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the invention.
Referring to fig. 2 and fig. 3, fig. 3 is a schematic cross-sectional view of fig. 2 taken along a line a-a1 and a line a2-A3, providing a substrate 200, where the substrate 200 includes a first region I and a second region II, the first region I has a first initial fin structure 210 thereon, and the first initial fin structure 210 includes a plurality of first sacrificial layers 211 overlapping along a normal direction of a surface of the substrate 200 and first initial nanowires 212 on a surface of the first sacrificial layers 211.
In this embodiment, the substrate 200 in the second region II has a second initial fin structure 220, and the second initial fin structure 220 includes a plurality of second sacrificial layers 221 overlapped along a normal direction of the surface of the substrate 200 and second initial nanowires 222 located on the surface of the second sacrificial layers 221.
The substrate 200 is made of silicon; in other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide; in other embodiments, the base may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
The first preliminary fin structure 210 and the second preliminary fin structure 220 also have a first protection layer 213 on top surfaces thereof.
The method for forming the first initial fin structure 210 and the second initial fin structure 220 includes: forming a fin material film (not shown in the figure) on the substrate 200, wherein the fin material film comprises a plurality of sacrificial material films overlapped along the normal direction of the surface of the substrate 200 and a nano material film positioned on the surface of the sacrificial material film; forming a protective film on the surface of the fin material film; forming a patterned layer on the surface of the protective film; and etching the fin material film and the protective film by using the patterned layer as a mask until the surface of the substrate 200 is exposed, so that the protective film forms a first protective layer 213, a first sacrificial layer 211 and a first initial nanowire 212 positioned on the surface of the first sacrificial layer 211 are formed on the first region I, and a second sacrificial layer 221 and a second initial nanowire 222 positioned on the surface of the second sacrificial layer 212 are formed on the second region II.
The first protection layer 213 is used to protect the surfaces of the first initial fin structure 210 and the second initial fin structure 220 from being affected by the subsequent processes, which may result in consumption of the first initial fin structure 210 and the second initial fin structure 220.
The material of the first protection layer 213 is different from the material of the fin material film.
The material of the first protective layer 213 includes: silicon oxide or silicon nitride
In this embodiment, the material of the first protection layer 213 is silicon nitride.
With continued reference to fig. 2 and 3, after the first and second initial fin structures 210 and 220 are formed, an insulating layer (not labeled) is formed on the surface of the substrate 200, the insulating layer covers the sidewall surfaces of the first and second initial fin structures 210 and 220, and the top surface of the insulating layer is lower than the top surfaces of the first and second initial fin structures 210 and 220.
The insulating layer is used for realizing electric isolation among different devices.
Referring to fig. 4 and 5, fig. 4 is a schematic view based on fig. 2, and fig. 5 is a schematic view based on fig. 3, wherein a first dummy gate structure 230 is formed on the first region I and crosses over the first initial fin structure 210.
In this embodiment, the method for forming a semiconductor structure further includes: a second dummy gate structure 240 is formed on the second region II, crossing the second initial fin structure 220.
The first dummy gate structure 230 is used in a gate last process, so as to subsequently form a first gate structure; the second dummy gate structure 240 is used in a gate last process to subsequently form a second gate structure.
In this embodiment, the first dummy gate structure 230 and the second dummy gate structure 240 are formed in the same process. In other embodiments, the first dummy gate structure and the second dummy gate structure are formed sequentially.
The method for forming the first dummy gate structure 230 and the second dummy gate structure 240 includes: forming a dummy gate dielectric film on the substrate 200 to cover the surfaces of the first initial fin structure 210 and the second initial fin structure 220; forming a pseudo gate electrode film on the surface of the pseudo gate dielectric film; patterning the layers of the dummy gate electrode film and the dummy gate dielectric film until the surface of the insulating layer is exposed, forming a first dummy gate structure 230 crossing the first initial fin structure 210 on the first region I, and forming a second dummy gate structure 240 crossing the second initial fin structure 220 on the second region II.
In this embodiment, the method for forming a semiconductor structure further includes: forming a first sidewall 231 on a sidewall surface of the first dummy gate structure 230; a second sidewall 232 is formed on the sidewall surface of the second dummy gate structure 240.
The first side wall 231 and the second side wall 232 are used for protecting the side wall surface of the first dummy gate structure 230 and the side wall surface of the second dummy gate structure 240, so that the first gate structure and the second gate structure formed subsequently are prevented from appearance defects, and the electrical performance of the semiconductor structure is prevented from being influenced.
In this embodiment, the method for forming a semiconductor structure further includes: forming a second protection layer (not shown) on the top surface of the first dummy gate structure 230; a third passivation layer (not shown) is formed on the top surface of the second dummy gate structure 240.
The second protection layer and the third protection layer are used for protecting the top surface of the first dummy gate structure 230 and the top surface of the second dummy gate structure 240 when the first source-drain doping layer and the second source-drain doping layer are formed in the subsequent process, so that the influence on the heights of the first gate structure and the second gate structure caused by the subsequent removal of the first dummy gate structure 230 to form the first gate structure and the removal of the second dummy gate structure 240 to form the second gate structure is avoided.
Then, one or more of the first initial nanowires 212 are etched, and a groove is formed on one or two side walls of the first initial nanowires 212.
In this embodiment, one of the first initial nanowires 212 is etched, and the groove is formed on one side of the first initial nanowire 212, and for a specific process of etching the first initial nanowire, refer to fig. 6 to 9.
Referring to fig. 6 and 7, fig. 6 is a schematic view based on fig. 4, and fig. 7 is a schematic view based on fig. 5, wherein a mask layer 250 is formed on the first initial fin structure 210, the second initial fin structure 230, the first dummy gate structure 230, and the second dummy gate structure 240, and the mask layer 250 has a mask opening 251 therein, and the mask opening 251 exposes the first initial fin structure 210.
The mask layer 250 is used as a mask for forming a recess by subsequently etching the first initial fin structure 210.
In the present embodiment, the mask opening 251 exposes one side of the first initial fin structure 210.
Specifically, the mask opening 251 exposes a side of the first initial fin structure 210 away from the second region II.
The material of the mask layer 250 includes: a photoresist material.
Since the first dummy gate structure 230 of the second region II is likely to affect one side of the first initial fin structure 210, when the mask opening 251 exposes one side of the first initial fin structure 210 away from the second region II, in the process of etching the one or the plurality of first initial nanowires 212, on one hand, the process difficulty of subsequently forming a groove is facilitated to be reduced, and on the other hand, the second initial fin structure 220 adjacent to the first region II is not likely to be affected, so that the morphology of the formed groove is better, the quality of an isolation structure subsequently formed in the groove is ensured, the isolation structure can effectively isolate the first source-drain doping layer, semiconductor devices formed on the first region I and the second region II contain different numbers of channels, and specific process requirements can be met.
Referring to fig. 8 and 9, fig. 8 is a schematic diagram based on fig. 6, fig. 9 is a schematic diagram based on fig. 7, the mask layer 250 is used as a mask, the one or more first initial nanowires 212 exposed by the mask opening 251 are etched until the surface of the first sacrificial layer 211 is exposed, and the groove 260 is formed on the sidewall of the one or more first initial nanowires 212.
The recess 260 provides a space for the subsequent formation of an isolation structure.
In this embodiment, the one of the first initial nanowires 212 is etched, and the groove 260 is formed on one side of the one of the first initial nanowires 212.
In other embodiments, two or more first initial nanowires may be etched, and the groove may be formed on one side of the two or more first initial nanowires.
In other embodiments, one of the first initial nanowires may be etched, and the grooves may be formed on both sides of the one of the first initial nanowires.
In other embodiments, two or more first initial nanowires may be etched, and the grooves may be formed on two sides of the two or more first initial nanowires.
The process of etching the one or several first initial nanowires 212 exposed by the mask opening 251 comprises: one or two of the dry etching process and the wet etching process are combined.
The process of etching the one or more first initial nanowires 212 exposed by the mask opening 251 is a wet etching process; the parameters of the wet etching process comprise: the adopted etching solution comprises a tetramethylammonium hydroxide solution, and the concentration of the tetramethylammonium hydroxide solution is 3-20%.
The wet etching process is an isotropic etching process, so that the formed groove 260 is also etched along the extending direction of the first initial fin structure 210, that is, the first initial fin structure 210 located at the bottom of the first dummy gate structure 230 is etched, which is helpful for making the sidewall of the first nanowire where the subsequent groove 260 is located be recessed relative to the sidewall of the first nanowire opposite to the bottom of the groove 260 when the first initial nanowire 212 is subsequently etched to form the first nanowire.
Specifically, in the present embodiment, the sidewall of the first initial nanowire 212 where the groove 260 is located is recessed with respect to the sidewall of the first sidewall 231.
In this embodiment, after the groove 260 is formed, the mask layer 250 is removed.
Referring to fig. 10, fig. 10 is a schematic diagram based on fig. 8, after the groove 260 is formed, the first initial fin structures 210 on two sides 230 of the first dummy gate structure are removed, and a first fin structure (not labeled in the figure) is formed on the first region I, so that the first initial nanowire 212 forms the first nanowire 216, two sides of the first fin structure in the extending direction have first source-drain openings 241, sidewalls of the first source-drain openings 241 expose the groove 260, and a sidewall of the first nanowire 216 where the groove 260 is located is recessed relative to a sidewall of the first nanowire 216 at the bottom of the groove 260.
In this embodiment, the method for forming a semiconductor structure further includes: removing the second initial fin structures 220 on two sides of the second dummy gate structure 240, so that the second initial nanowire 222 forms a second nanowire 226, and a second fin structure (not shown in the figure) is formed on the second region II, where two sides of the second fin structure in the extending direction have second source-drain openings 242.
The first source-drain opening 241 is used for providing a space for the subsequent formation of a first source-drain doping layer, and the second source-drain opening 242 is used for providing a space for the subsequent formation of the first source-drain doping layer.
In this embodiment, the first source-drain opening 241 and the second source-drain opening 232 are formed in the same process.
In this embodiment, specifically, the first initial fin structure 210 is etched to form a first fin structure, the first source/drain opening 241 is formed in the first fin structure, the second initial fin structure 220 is etched to form a second fin structure, and the second source/drain opening 242 is formed in the second fin structure, with the first dummy gate structure 221 and the second dummy gate structure 222 as masks, respectively.
In this embodiment, the first source drain opening 241 and the second source drain opening 232 are adjacent to each other and are communicated with each other.
In other embodiments, the first source drain opening and the second source drain opening may not be adjacent.
The process of etching the first initial fin structure 210 and the second initial fin structure 220 includes: one or two of the dry etching process and the wet etching process are combined.
In this embodiment, the process of etching the first initial fin structure 210 and the second initial fin structure 220 is a dry etching process, and the dry etching process is beneficial to forming the first fin structure and the second fin structure with better appearances.
With continued reference to fig. 10, after the first source drain opening 241 and the second source drain opening 242 are formed, a first fin recess 218 is formed between adjacent first nanowires 216.
In this embodiment, the forming of the semiconductor structure further includes: second fin recesses 228 are formed between adjacent second nanowires 226.
The first fin recess 218 provides space for a first isolation layer to be subsequently formed, and the second fin recess 228 provides space for a second isolation layer to be subsequently formed.
The method of forming the first fin recess 218 includes: portions of the first sacrificial layer 211 are etched to form first modified sacrificial layer 215, sidewalls of the first modified sacrificial layer 215 are recessed with respect to sidewalls of the first nanowires 216, forming first fin recesses 218 between adjacent first nanowires 216.
The method of forming the second fin recess 228 includes: a portion of the second sacrificial layer 221 is etched to form a second modified sacrificial layer 225, sidewalls of the second modified sacrificial layer 225 are recessed with respect to sidewalls of the second nanowires 226, and second fin recesses 228 are formed between adjacent second nanowires 226.
In the present embodiment, the first fin recess 218 and the second fin recess 228 are formed in the same process.
The process of etching a portion of the first sacrificial layer 211 and etching a portion of the second sacrificial layer 221 includes: one or two of the dry etching process and the wet etching process are combined.
In this embodiment, the process of etching a portion of the first sacrificial layer 211 and a portion of the second sacrificial layer 221 is a wet etching process, which is beneficial to etching the first sacrificial layer 212 between adjacent first nanowires 216 and the second sacrificial layer 222 between adjacent second nanowires 226.
Referring to fig. 11, fig. 11 is a schematic diagram based on fig. 10, and an isolation structure 281 is formed in the groove 260, where the isolation structure 281 is located between one or more first nanowires 216 and the first source-drain opening 241 (shown in fig. 10).
In this embodiment, the method for forming a semiconductor structure further includes: a first isolation layer 282 is formed within the first fin recess 218.
In this embodiment, the method for forming a semiconductor structure further includes: a second isolation layer 283 is formed within the second fin recess 228.
In this embodiment, the isolation structure 281 and the first and second isolation layers 282 and 283 are formed in the same process.
The forming method of the isolation structure 281 and the first and second isolation layers 282 and 283 includes: forming a film of isolation material (not shown) on the surface of the substrate 200, in the recess 260, in the first fin recess 218, in the second fin recess 228, on the top surface and on the sidewall surface of the first dummy gate structure 230, on the top surface and on the sidewall surface of the second dummy gate structure 240, and on the sidewall surfaces of the first nanowire 216 and the second nanowire 226; the isolation material film is etched back until the surface of the substrate 200, the surface of the sidewall of the first nanowire 216, and the surface of the sidewall of the second nanowire 216 are exposed, an isolation structure 281 is formed in the recess 260, the first isolation layer 282 is formed in the first fin recess 218, and the second isolation layer 283 is formed in the second fin recess 228.
The isolating material film is made of an insulating material. The insulating material includes: silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon oxycarbonitride or silicon oxynitride.
In the present embodiment, the isolation material film is made of silicon nitride, and accordingly, the isolation structures 281, the first isolation layer 282, and the second isolation layer 283 are formed of silicon nitride.
Referring to fig. 12, fig. 12 is a schematic view based on fig. 11, a first source-drain doping layer 243 is formed in the first source-drain opening 241, and the first source-drain doping layer 243 covers the sidewall surface of the isolation structure 281.
In this embodiment, the method for forming a semiconductor structure further includes: a second source drain doped layer 244 is formed within the second source drain opening 242.
In this embodiment, the first source-drain doping layer 243 further covers the first isolation layer 282 and the sidewall surface of the first nanowire 216; the second source-drain doping layer 244 also covers the second isolation layer 283 and the sidewall surface of the first nanowire 226.
Specifically, after the isolation structure 281, the first isolation layer 282, and the second isolation layer 283 are formed, the first source-drain doping layer 243 is formed in the first source-drain opening 241 and the second source-drain doping layer 244 is formed in the second source-drain opening 242 through an in-situ epitaxial growth process.
Source and drain ions are further doped in the first source and drain doping layer 243 and the second source and drain doping layer 244, and the source and drain ions include: p-type ions, e.g. boron or BF2+Or N-type ions, including: phosphorus ions, arsenic ions or antimony ions.
The process of doping source and drain ions in the first source and drain doped layer 243 and the second source and drain doped layer 244 includes: an ion implantation process or an in-situ doping process.
Forming a groove 260 on one side or two side walls of the first initial nanowire 212 on the first region I by etching the one or a plurality of first initial nanowires 212; first source-drain openings 241 are formed on two sides of the extending direction of the first fin structure, the side walls of the first source-drain openings 241 are exposed out of the groove 260, and the side wall of the first nanowire 216 where the groove 260 is located is recessed relative to the side wall of the first nanowire 216 at the bottom of the groove 260. By forming the isolation structure 281 in the groove 260, the isolation structure 281 is located between one or a plurality of first nanowires 216 and the first source-drain opening 241, and the isolation structure 281 can effectively isolate the first source-drain doping layer 243 located in the first source-drain opening 242 from the first nanowires 216, so that the one or a plurality of first nanowires 216 cannot provide a channel between the first source-drain doping layers 216, and the number of channels in the semiconductor device can be changed.
Meanwhile, the second nanowires 226 on the second region II can all function to provide channels between the second source-drain doping layers 244, and therefore, the number of channels for forming semiconductor devices on the first region I is less than that of channels for forming semiconductor devices on the second region II, that is, the semiconductor devices on the first region I and the second region II have different channel numbers, so that specific process requirements can be met.
Referring to fig. 13, fig. 13 is a schematic diagram based on fig. 12, in which a dielectric layer 290 is formed on the substrate 200, and the dielectric layer 290 covers the surface of the first source-drain doping layer 243, the surface of the second source-drain doping layer 244, the surface of the sidewall of the first dummy gate structure, and the surface of the sidewall of the second dummy gate structure; forming a first gate opening 291 and a second gate opening 292 in the dielectric layer 290; forming a first additional opening 2911 between the adjacent first nanowires 216 exposed by the first gate opening 291; second additional openings 2921 are formed between adjacent second nanowires 226 exposed by the second gate opening 292.
The first opening 291 and the first additional opening 2911 are used for the subsequent formation of a first gate structure, and the second opening 292 and the second additional opening 2921 are used for the subsequent formation of a second gate structure.
The method for forming the first gate opening 291 and the second gate opening 292 in the dielectric layer 290 includes: removing the first dummy gate structure 230, and forming the first opening 291 in the dielectric layer 290; the second dummy gate structure 240 is removed, and the second opening 292 is formed in the dielectric layer 290.
In this embodiment, the removal of the first dummy gate structure 230 and the second dummy gate structure 240 is performed in the same process.
The process of removing the first dummy gate structure 230 and the second dummy gate structure 240 includes: one or two of the dry etching process and the wet etching process are combined.
Specifically, the first opening 291 exposes a portion of the top surface and sidewall surface of the first fin structure and the surface of the isolation layer; the second opening 2921 exposes a portion of the top and sidewall surfaces of the first fin structure and the surface of the isolation layer.
The first additional opening 2911 forming method includes: the first modified sacrificial layer 215 between adjacent first nanowires 216 exposed by the first opening 291 is removed, and the first additional opening 2911 is formed between the adjacent first nanowires 216.
The method of forming the second additional opening 2921 includes: the second modified sacrificial layer 225 between the adjacent second nanowires 226 exposed by the second opening 291 is removed, and the second additional opening 2921 is formed between the adjacent second nanowires 226.
Referring to fig. 14 and 15, fig. 14 is a schematic diagram based on fig. 13, the view directions of fig. 15 and 9 are the same, a first gate structure 293 is formed in the first gate opening 291 and the first additional opening 2911, and the first gate structure 293 surrounds each of the first nanowires 216; a second gate structure 294 is formed within the second gate opening 292 and the second additional opening 2921, the second gate structure 294 surrounding each of the second nanowires 226.
In the present embodiment, the first gate structure 293 and the second gate structure 294 are formed in the same process.
The method for forming the first gate structure 293 and the second gate structure 294 includes: forming a gate dielectric film (not shown) in the first and second openings 291 and 292, on the surfaces of the first and second additional openings 2911 and 2921, and on the surface of the dielectric layer 290; forming a gate electrode film (not shown) on the surface of the gate dielectric film, wherein the gate electrode film fills the first and second openings 291 and 292, and the first and second additional openings 2911 and 2921; planarizing the gate electrode film and the gate dielectric film until the surface of the dielectric layer 290 is exposed, forming the gate dielectric layer from the gate dielectric film, forming the gate electrode layer from the gate electrode film, forming the first gate structure 293 in the first opening 291 and the first additional opening 2911, and forming the second gate connection port 294 in the second opening 292 and the second additional opening 2921.
The first sidewalls 231 are located on both sidewalls of the first gate structure 293.
The second sidewalls 232 are located on both sidewalls of the second gate structure 294.
Accordingly, an embodiment of the present invention provides a semiconductor structure, please continue to refer to fig. 11, which includes: a substrate 200, the substrate 200 comprising a first region I and a second region II; a first fin structure located on the first region I, the first fin structure including a plurality of first nanowires 216 arranged along a surface normal direction of the substrate 200 and separated from each other; the first gate structure 293 is located in the first region I and crosses the first fin structure, the first fin structure on two sides of the first gate structure 293 is provided with a first source drain opening 241 (shown in fig. 10), a groove 260 (shown in fig. 10) is formed on the sidewall of the first source drain opening 241 on one or two sides, the groove 260 exposes the sidewall surface of one or more first nanowires 216, and the sidewall of the first nanowire 216 where the groove 260 is located is recessed relative to the sidewall of the first nanowire 216 at the bottom of the groove 260; a spacer structure 281 located within the recess 260.
Because the sidewall of the first source-drain opening 241 on one side or both sides is provided with the groove 260, the groove 260 exposes the sidewall surface of one or a plurality of first nanowires 216, the sidewall of the first nanowire 216 where the groove 260 is located is recessed relative to the sidewall of the first nanowire 216 at the bottom of the groove 260, and meanwhile, the sidewall of the groove 260 is exposed by the first source-drain opening 241. The first source-drain doping layer 243 is arranged in the first source-drain opening 241, the isolation structure 281 is arranged in the groove 260, that is, the isolation structure 281 is located in the first source-drain doping layer 243 and the first nanowire 216, so that the isolation structure 281 can effectively isolate the first source-drain doping layer 243 from the first nanowire 216, one or a plurality of first nanowires 216 cannot provide channels between the first source-drain doping layers 243, and the number of the channels in the semiconductor device can be changed.
The following detailed description is made with reference to the accompanying drawings.
The first gate structure 293 includes: the first fin structure includes a first gate dielectric layer (not shown) crossing the first fin structure, a first gate electrode layer first gate dielectric layer (not shown) located on a surface of the first gate dielectric layer, and a first sidewall 231 located on a sidewall surface of the first gate dielectric layer and a sidewall surface of the first gate electrode layer.
In this embodiment, the sidewall of the isolation structure 281 is flush with the sidewall surface of the first sidewall 231.
The semiconductor structure further includes: a second fin structure located on the second region II, the second fin structure including a plurality of second nanowires 226 arranged along the normal direction of the surface of the substrate 200 and separated from each other; a second gate structure 294 located across the second fin structure in the second region II.
The second fin structures on two sides of the second gate structure 294 have second source/drain openings 242 therein.
The semiconductor structure further includes: a first source-drain doping layer 243 located in the first source-drain opening 241, and the first source-drain doping layer 243 covers the sidewall surface of the isolation structure 281; a second source drain doped layer 244 located within the second source drain opening 244.
The second gate structure 294 includes: a second gate dielectric layer (not shown) crossing the second fin structure, a second gate electrode layer (not shown) on the surface of the second gate dielectric layer, and a second sidewall 232 on the sidewall surfaces of the second gate dielectric layer and the second gate electrode layer.
A first fin recess 218 and a first isolation layer 281 in the first fin recess 218 are disposed between adjacent first nanowires 216.
A second fin recess 228 and a second isolation layer 283 are disposed between adjacent second nanowires 226 in the second fin recess 229.
The semiconductor structure further includes: a dielectric layer 290 located on the substrate 200, wherein the dielectric layer 290 has a first gate opening 291 therein, and the first gate opening 291 exposes a portion of the top surface and the sidewall surface of the first fin structure; the first gate structure 293 is located in the first gate opening 291.
A second gate opening 292 is further formed in the dielectric layer 290-, and the second gate opening 292 exposes a portion of the top surface and the sidewall surface of the second fin structure; the second gate structure 294 is located in the second gate opening 292.
The semiconductor structure further includes: a first additional opening 2911 between adjacent first nanowires 216, the first gate opening 291 exposing the first additional opening 2911; the first gate structure 293 is also located in the first additional opening 2911, and the first gate structure 293 surrounds each of the first nanowires 216.
The semiconductor structure further includes: second additional openings 2921 between adjacent second nanowires 226, the second gate openings 292 exposing the second additional openings 2921; the second gate structure 294 is also located within the second additional opening 2921, and the second gate structure 294 surrounds each of the second nanowires 226.
Further, the second nanowires 226 in the second region II can all function to provide channels between the second source-drain doping layers 244, and therefore, the number of channels used for forming semiconductor devices in the first region I is less than the number of channels used for forming semiconductor devices in the second region II, that is, the semiconductor devices in the first region I and the second region II have different numbers of channels, so that specific process requirements can be met.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (30)

1. A semiconductor structure, comprising:
a substrate comprising a first region and a second region;
the first fin portion structure is positioned on the first area and comprises a plurality of first nanowires which are arranged along the normal direction of the surface of the substrate and are mutually separated;
the first fin structure is positioned in the first region and transversely crosses the first fin structure, first source-drain openings are formed in the first fin structures on two sides of the first gate structure, grooves are formed in the side walls of the first source-drain openings on one side or two sides, the surfaces of one or more first nanowire side walls are exposed out of the grooves, and the side walls of the first nanowires where the grooves are located are recessed relative to the first nanowire side walls at the bottom of the grooves;
an isolation structure located within the recess.
2. The semiconductor structure of claim 1, wherein the first gate structure comprises: the first fin portion structure comprises a first gate dielectric layer crossing the first fin portion structure, a first gate electrode layer located on the surface of the first gate dielectric layer, and first side walls located on the surfaces of the side walls of the first gate dielectric layer and the first gate electrode layer.
3. The semiconductor structure of claim 2, wherein the isolation structure sidewall is flush with the first sidewall surface.
4. The semiconductor structure of claim 1, further comprising: the second fin portion structure is positioned on the second area and comprises a plurality of second nanowires which are arranged along the normal direction of the surface of the substrate and are mutually separated; a second gate structure located across the second fin structure in the second region.
5. The semiconductor structure of claim 4, wherein the second fin structure on both sides of the second gate structure has a second source drain opening therein.
6. The semiconductor structure of claim 5, further comprising: the first source-drain doping layer is positioned in the first source-drain opening and covers the surface of the side wall of the isolation structure; and the second source-drain doping layer is positioned in the second source-drain opening.
7. The semiconductor structure of claim 4, wherein the second gate structure comprises: the second gate dielectric layer stretches across the second fin portion structure, the second gate electrode layer is located on the surface of the second gate dielectric layer, and the second side wall is located on the surfaces of the side walls of the second gate dielectric layer and the second gate electrode layer.
8. The semiconductor structure of claim 1, wherein a first fin recess is between adjacent first nanowires, and a first isolation layer is in the first fin recess.
9. The semiconductor structure of claim 4, wherein a second fin recess is between adjacent second nanowires, and a second isolation layer is in the second fin recess.
10. The semiconductor structure of claim 9, further comprising: a dielectric layer located on the substrate, wherein a first gate opening is formed in the dielectric layer, and the first gate opening exposes part of the top surface and the side wall surface of the first fin structure; the first gate structure is located within the first gate opening.
11. The semiconductor structure of claim 10, further comprising a second gate opening in the dielectric layer, the second gate opening exposing a portion of the top surface and sidewall surfaces of the second fin structure; the second gate structure is located within the second gate opening.
12. The semiconductor structure of claim 11, further comprising: a first additional opening between adjacent first nanowires, the first gate opening exposing the first additional opening; the first gate structure is also located within the first additional opening and surrounds each of the first nanowires.
13. The semiconductor structure of claim 12, further comprising: a second additional opening between adjacent second nanowires, the second gate opening exposing the second additional opening; the second gate structure is also located in the second additional opening, and the second gate structure surrounds each of the second nanowires.
14. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a first area and a second area, the first area is provided with a first initial fin part structure, and the first initial fin part structure comprises a plurality of first sacrificial layers overlapped along the normal direction of the surface of the substrate and first initial nanowires positioned on the surface of the first sacrificial layers;
forming a first dummy gate structure on the first region and crossing the first initial fin structure;
etching one or more first initial nanowires, and forming grooves on one side or two side walls of the first initial nanowires;
after the groove is formed, removing the first initial fin part structures on two sides of the first pseudo gate structure, and forming a first fin part structure on the first region, so that the first initial nanowire forms a first nanowire, wherein two sides of the first fin part structure in the extension direction are provided with a first source drain opening, the side wall of the first source drain opening is exposed out of the groove, and the side wall of the first nanowire where the groove is located is recessed relative to the side wall of the first nanowire at the bottom of the groove;
and forming an isolation structure in the groove, wherein the isolation structure is positioned between one or a plurality of first nanowires and the first source drain opening.
15. The method of claim 14, wherein the second region has a second initial fin structure on the substrate, and the second initial fin structure comprises a plurality of second sacrificial layers overlapping in a direction normal to the surface of the substrate and a plurality of second initial nanowires on the surface of the second sacrificial layers.
16. The method of forming a semiconductor structure of claim 15, further comprising: forming a second dummy gate structure on the second region and crossing the second initial fin structure.
17. The method of forming a semiconductor structure of claim 16, wherein etching the plurality of first initial nanowires comprises: forming a mask layer on the first initial fin portion structure, the second initial fin portion structure, the first dummy gate structure and the second dummy gate structure, wherein the mask layer is internally provided with a mask opening, and the mask opening exposes the surface of the first initial fin portion structure; and etching the one or a plurality of first initial nanowires exposed from the mask opening by taking the mask layer as a mask until the surface of the first sacrificial layer is exposed, and forming the grooves on the side walls of the one or a plurality of first initial nanowires.
18. The method for forming a semiconductor structure of claim 17, wherein the process of etching the one or more first initial nanowires exposed by the mask opening is a wet etching process; the parameters of the wet etching process comprise: the adopted etching solution comprises a tetramethylammonium hydroxide solution, and the concentration of the tetramethylammonium hydroxide solution is 3-20%.
19. The method of forming a semiconductor structure of claim 17, wherein the mask opening exposes a side of the first initial fin structure away from the second region; and etching the plurality of first initial nanowires exposed from the mask opening by taking the mask layer as a mask, and forming the grooves on one sides of the plurality of first initial nanowires.
20. The method of forming a semiconductor structure of claim 16, further comprising: and removing the second initial fin part structures on two sides of the second pseudo gate structure to enable the second initial nanowire to form a second nanowire, and forming a second fin part structure on the second region, wherein two sides of the second fin part structure in the extension direction are provided with second source drain openings.
21. The method of forming a semiconductor structure of claim 20, further comprising: forming a first source drain doping layer in the first source drain opening, wherein the first source drain doping layer covers the surface of the side wall of the isolation structure; and forming a second source-drain doping layer in the second source-drain opening.
22. The method of forming a semiconductor structure of claim 21, further comprising: after the first source drain opening and the second source drain opening are formed and before the first source drain doping layer and the second source drain doping layer are formed, a first fin portion groove is formed between adjacent first nanowires; forming a second fin portion groove between adjacent second nanowires; forming a first isolation layer in the first fin portion groove; forming a second isolation layer in the second fin portion groove; and after the first isolation layer and the second isolation layer are formed, forming a first source drain doping layer and a second source drain doping layer, wherein the first source drain doping layer covers the surface of the side wall of the first isolation layer, and the second source drain doping layer covers the surface of the side wall of the second isolation layer.
23. The method of forming a semiconductor structure of claim 22, wherein the method of forming the first fin recess comprises: etching part of the first sacrificial layer to form a first correcting sacrificial layer, wherein the side wall of the first correcting sacrificial layer is sunken relative to the side wall of the first nanowire, and a first fin part groove is formed between the adjacent first nanowires; the method for forming the second fin recess includes: and etching part of the second sacrificial layer to form a second correcting sacrificial layer, wherein the side wall of the second correcting sacrificial layer is sunken relative to the side wall of the second nanowire, and a second fin part groove is formed between the adjacent second nanowires.
24. The method of forming a semiconductor structure of claim 23, wherein the isolation structure and the first and second isolation layers are formed in a same process.
25. The method of forming a semiconductor structure of claim 24, wherein the method of forming the isolation structure and the first and second isolation layers comprises: forming an isolation material film on the surface of the substrate, in the groove, in the first fin part groove, in the second fin part groove, on the top surface and the side wall surface of the first pseudo gate structure, on the top surface and the side wall surface of the second pseudo gate structure, and on the side wall surfaces of the first nanowire and the second nanowire; and etching the isolating material film back until the surface of the substrate, the surface of the side wall of the first nanowire and the surface of the side wall of the second nanowire are exposed, forming an isolating structure in the groove, forming the first isolating layer in the groove of the first fin part, and forming the second isolating layer in the groove of the second fin part.
26. The method of forming a semiconductor structure of claim 15, wherein the first initial fin structure top surface and the second initial fin structure top surface further comprise a protective layer.
27. The method of forming a semiconductor structure of claim 26, wherein the first and second initial fin structures are formed by a method comprising: forming a fin material film on the substrate, wherein the fin material film comprises a plurality of sacrificial material films overlapped along the normal direction of the surface of the substrate and a nano material film positioned on the surface of the sacrificial material film; forming a protective film on the surface of the fin material film; forming a patterned layer on the surface of the protective film; and etching the fin material film and the protective film by taking the patterning layer as a mask until the surface of the substrate is exposed, so that the protective film forms a protective layer, a first sacrificial layer and a first initial nanowire positioned on the surface of the first sacrificial layer are formed on the first area, and a second sacrificial layer and a second initial nanowire positioned on the surface of the second sacrificial layer are formed on the second area.
28. The method of forming a semiconductor structure of claim 21, further comprising: after the first source-drain doping layer and the second source-drain doping layer are formed, a dielectric layer is formed on the substrate and covers the first source-drain doping layer, the second source-drain doping layer, the first pseudo gate structure and the side wall surface of the second pseudo gate structure; forming a first gate opening and a second gate opening in the dielectric layer; forming a first additional opening between adjacent first nanowires exposed by the first gate opening; forming a second additional opening between adjacent second nanowires exposed by the second gate opening; forming first gate structures in the first gate openings and the first additional openings, wherein the first gate structures surround the first nanowires; and forming a second gate structure in the second gate opening and the second additional opening, wherein the second gate structure surrounds each second nanowire.
29. The method of forming a semiconductor structure of claim 28, wherein the method of forming the first gate opening comprises: removing the first pseudo gate structure, and forming a first gate opening in the dielectric layer; the forming method of the second gate opening comprises the following steps: and removing the second pseudo gate structure, and forming a second gate opening in the dielectric layer.
30. The method of forming a semiconductor structure of claim 29, wherein the method of forming the first additional opening comprises: removing the first sacrificial layer exposed by the first gate opening, and forming a first additional opening between the adjacent first nanowires; the method for forming the second additional opening comprises the following steps: and removing the second sacrificial layer exposed by the second gate opening, and forming a second additional opening between the adjacent second nano-phases.
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