CN113497036B - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN113497036B
CN113497036B CN202010196421.1A CN202010196421A CN113497036B CN 113497036 B CN113497036 B CN 113497036B CN 202010196421 A CN202010196421 A CN 202010196421A CN 113497036 B CN113497036 B CN 113497036B
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forming
fin
nanowires
layer
gate
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CN113497036A (en
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王楠
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
    • B—PERFORMING OPERATIONS; TRANSPORTING
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    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region

Abstract

A semiconductor structure and a method of forming the same, wherein the method comprises: forming a first dummy gate structure on the first region that spans the first initial fin structure; etching one or a plurality of first initial nanowires, and forming grooves on side walls of one side or two sides of the first initial nanowires; after the grooves are formed, removing first initial fin structures on two sides of the first pseudo gate structure, forming first fin structures on a first region, enabling the first initial nanowires to form first nanowires, wherein first source drain openings are formed on two sides of the extending direction of the first fin structures, the side walls of the first source drain openings expose the grooves, and the side walls of the first nanowires where the grooves are located are sunken relative to the side walls of the first nanowires at the bottoms of the grooves; and forming an isolation structure in the groove, wherein the isolation structure is positioned between one or a plurality of first nanowires and the first source drain opening. The method can change the number of channels in the semiconductor structure so as to meet the performance requirement.

Description

Semiconductor structure and forming method thereof
Technical Field
The present disclosure relates to semiconductor manufacturing technology, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the development of information technology, the amount of stored information has increased dramatically. The increase in the amount of stored information has prompted the rapid development of memory, while also placing higher demands on the stability of memory.
Basic static memory (Static Random Access Memory, SRAM) relies on six transistors that constitute two cross-coupled inverters. Each inverter includes: a pull-up transistor, a pull-down transistor, and an access transistor.
In order to obtain sufficient anti-disturb capability and read stability, the transistor used to form the memory may be a channel gate-all-around (GAA) structure transistor. The volume of the channel gate surrounding structure transistor serving as a channel region is increased, so that the working current of the channel gate surrounding structure transistor is further increased, and the application of the channel gate surrounding structure transistor in a memory can improve the data storage stability and the integration level of the memory.
However, the performance of the semiconductor device constituted by the existing static memory has yet to be improved.
Disclosure of Invention
The invention solves the technical problem of providing a semiconductor structure and a forming method thereof so as to form semiconductor devices with different channel numbers, thereby meeting specific process requirements.
In order to solve the above technical problems, the present invention provides a semiconductor structure, including: a substrate comprising a first region and a second region; the first fin structure is positioned on the first region and comprises a plurality of first nanowires which are arranged along the normal direction of the surface of the substrate and are mutually separated; the first grid structure is positioned on the first region and spans the first fin structure, first source drain openings are formed in the first fin structures at two sides of the first grid structure, grooves are formed in the side walls of the first source drain openings at one side or two sides of the first fin structures, the grooves expose the surface of one or a plurality of first nanowire side walls, and the side walls of the first nanowires where the grooves are positioned are sunken relative to the side walls of the first nanowire at the bottom of the grooves; and the isolation structure is positioned in the groove.
Optionally, the first gate structure includes: the first side wall is positioned on the side wall surfaces of the first gate dielectric layer and the first gate electrode layer.
Optionally, the isolation structure sidewall is flush with the first sidewall surface.
Optionally, the method further comprises: the second fin structure is positioned on the second region and comprises a plurality of second nanowires which are arranged along the normal direction of the surface of the substrate and are mutually separated; and the second grid structure is positioned on the second region and spans the second fin structure.
Optionally, a second source-drain opening is formed in the second fin structure at two sides of the second gate structure.
Optionally, the method further comprises: the first source-drain doping layer is positioned in the first source-drain opening and covers the side wall surface of the isolation structure; and the second source-drain doping layer is positioned in the second source-drain opening.
Optionally, the second gate structure includes: the second side wall is positioned on the side wall surfaces of the second gate dielectric layer and the second gate electrode layer.
Optionally, a first fin groove and a first isolation layer located in the first fin groove are arranged between the adjacent first nanowires.
Optionally, a second fin groove and a second isolation layer located in the second fin groove are arranged between the adjacent second nanowires.
Optionally, the method further comprises: the dielectric layer is positioned on the substrate and is provided with a first gate opening, and part of the top surface and the side wall surface of the first fin structure are exposed out of the first gate opening; the first gate structure is located within the first gate opening.
Optionally, a second gate opening is further formed in the dielectric layer, and the second gate opening exposes a part of top surface and sidewall surface of the second fin structure; the second gate structure is located within the second gate opening.
Optionally, the method further comprises: a first additional opening between adjacent first nanowires, the first gate opening exposing the first additional opening; the first gate structure is also located within the first additional opening, and the first gate structure surrounds each of the first nanowires.
Optionally, the method further comprises: a second additional opening between adjacent second nanowires, the second gate opening exposing the second additional opening; the second gate structure is also located within the second additional opening, and the second gate structure surrounds each of the second nanowires.
Accordingly, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a first region and a second region, the first region is provided with a first initial fin structure, and the first initial fin structure comprises a plurality of first sacrificial layers overlapped along the normal direction of the surface of the substrate and first initial nanowires positioned on the surface of the first sacrificial layers; forming a first dummy gate structure on the first region that spans the first initial fin structure; etching one or a plurality of first initial nanowires, and forming grooves on side walls of one side or two sides of the first initial nanowires; after the grooves are formed, removing first initial fin structures on two sides of the first pseudo gate structure, forming first fin structures on a first region, enabling the first initial nanowires to form first nanowires, wherein first source drain openings are formed on two sides of the extending direction of the first fin structures, the side walls of the first source drain openings expose the grooves, and the side walls of the first nanowires where the grooves are located are sunken relative to the side walls of the first nanowires at the bottoms of the grooves; and forming an isolation structure in the groove, wherein the isolation structure is positioned between one or a plurality of first nanowires and the first source drain opening.
Optionally, the substrate of the second region is provided with a second initial fin structure, and the second initial fin structure comprises a plurality of second sacrificial layers overlapped along the normal direction of the surface of the substrate and second initial nanowires positioned on the surface of the second sacrificial layers.
Optionally, the method further comprises: a second dummy gate structure is formed on the second region across the second initial fin structure.
Optionally, the method for etching the plurality of first initial nanowires includes: forming a mask layer on the first initial fin structure, the second initial fin structure, the first pseudo gate structure and the second pseudo gate structure, wherein a mask opening is formed in the mask layer, and the mask opening exposes the surface of the first initial fin structure; and etching one or a plurality of first initial nanowires exposed by the mask opening by taking the mask layer as a mask until the surface of the first sacrificial layer is exposed, and forming the grooves on the side walls of the one or a plurality of first initial nanowires.
Optionally, the process of etching the one or several first initial nanowires exposed by the mask opening is a wet etching process; the parameters of the wet etching process include: the adopted etching solution comprises a tetramethyl ammonium hydroxide solution, and the concentration of the tetramethyl ammonium hydroxide solution is 3-20%.
Optionally, the mask opening exposes a side of the first initial fin structure away from the second region; and etching the first initial nanowires exposed by the mask openings by taking the mask layer as a mask, and forming the grooves on one sides of the first initial nanowires.
Optionally, the method further comprises: and removing the second initial fin structures at two sides of the second pseudo gate structure, forming a second nanowire by the second initial nanowire, and forming a second fin structure on a second region, wherein two sides of the extending direction of the second fin structure are provided with second source and drain openings.
Optionally, the method further comprises: forming a first source-drain doping layer in the first source-drain opening, wherein the first source-drain doping layer covers the side wall surface of the isolation structure; and forming a second source-drain doping layer in the second source-drain opening.
Optionally, the method further comprises: forming a first fin groove between adjacent first nanowires after forming the first source-drain opening and the second source-drain opening and before forming the first source-drain doping layer and the second source-drain doping layer; forming a second fin groove between adjacent second nanowires; forming a first isolation layer in the first fin portion groove; forming a second isolation layer in the second fin portion groove; after the first isolation layer and the second isolation layer are formed, the first source-drain doping layer and the second source-drain doping layer are formed, the first source-drain doping layer covers the surface of the side wall of the first isolation layer, and the second source-drain doping layer covers the surface of the side wall of the second isolation layer.
Optionally, the forming method of the first fin portion groove includes: etching part of the first sacrificial layer to form a first modified sacrificial layer, wherein the side wall of the first modified sacrificial layer is sunken relative to the side wall of the first nanowire, and a first fin groove is formed between adjacent first nanowires; the forming method of the second fin portion groove comprises the following steps: and etching part of the second sacrificial layer to form a second modified sacrificial layer, wherein the side wall of the second modified sacrificial layer is sunken relative to the side wall of the second nanowire, and a second fin groove is formed between adjacent second nanowires.
Optionally, the isolation structure, the first isolation layer and the second isolation layer are formed in the same process.
Optionally, the forming method of the isolation structure and the first and second isolation layers includes: forming an isolation material film on the substrate surface, the groove, the first fin groove, the second fin groove, the top surface and the side wall surface of the first pseudo gate structure, the top surface and the side wall surface of the second pseudo gate structure, and the side wall surfaces of the first nanowire and the second nanowire; and etching the isolation material film until the substrate surface, the first nanowire side wall surface and the second nanowire side wall surface are exposed, forming an isolation structure in the groove, forming a first isolation layer in the first fin groove, and forming a second isolation layer in the second fin groove.
Optionally, the top surface of the first initial fin structure and the top surface of the second initial fin structure further have a protective layer.
Optionally, the forming method of the first initial fin structure and the second initial fin structure includes: forming a fin material film on the substrate, wherein the fin material film comprises a plurality of sacrificial material films overlapped along the normal direction of the surface of the substrate and a nano material film positioned on the surface of the sacrificial material film; forming a protective film on the surface of the fin part material film; forming a patterned layer on the surface of the protective film; and etching the fin material film and the protective film by taking the patterned layer as a mask until the surface of the substrate is exposed, forming a protective layer by the protective film, forming a first sacrificial layer and a first initial nanowire positioned on the surface of the first sacrificial layer on the first region, and forming a second sacrificial layer and a second initial nanowire positioned on the surface of the second sacrificial layer on the second region.
Optionally, the method further comprises: forming a dielectric layer on the substrate after forming the first source-drain doping layer and the second source-drain doping layer, wherein the dielectric layer covers the side wall surfaces of the first source-drain doping layer, the second source-drain doping layer, the first pseudo gate structure and the second pseudo gate structure; forming a first gate opening and a second gate opening in the dielectric layer; forming first additional openings between adjacent first nanowires exposed by the first gate openings; forming a second additional opening between adjacent second nanowires exposed by the second gate opening; forming a first gate structure within the first gate opening and the first additional opening, the first gate structure surrounding each of the first nanowires; forming a second gate structure within the second gate opening and the second additional opening, the second gate structure surrounding each of the second nanowires.
Optionally, the method for forming the first gate opening includes: removing the first pseudo gate structure and forming a first gate opening in the dielectric layer; the second gate opening forming method comprises the following steps: and removing the second pseudo gate structure, and forming a second gate opening in the dielectric layer.
Optionally, the forming method of the first additional opening includes: removing the first sacrificial layer exposed by the first gate opening, and forming a first additional opening between adjacent first nanowires; the forming method of the second additional opening comprises the following steps: and removing the second sacrificial layer exposed by the second gate opening, and forming the second additional opening between adjacent second nanophase.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
In the semiconductor structure provided by the technical scheme of the invention, the side wall of the first source drain opening at one side or two sides is provided with the groove, the groove exposes one or a plurality of surfaces of the side wall of the first nanowire, the side wall of the first nanowire where the groove is positioned is sunken relative to the side wall of the first nanowire at the bottom of the groove, and meanwhile, the side wall of the groove is exposed by the first source drain opening. The first source-drain doping layer is arranged in the first source-drain opening, and the isolation structure is arranged in the groove, namely, the isolation structure is arranged between the first source-drain doping layer and the first nanowire, so that the isolation structure can effectively isolate the first source-drain doping layer from the first nanowire, one or a plurality of first nanowires cannot play a role in providing channels between the first source-drain doping layers, and the number of channels in the semiconductor device can be changed.
Further, the second nanowires on the second region can all serve to provide channels between the second source-drain doped layers, so that the number of channels used for forming semiconductor devices on the first region is smaller than that of channels used for forming semiconductor devices on the second region, that is, the semiconductor devices on the first region and the second region contain different channel numbers, thereby being capable of meeting specific process requirements.
In the method for forming the semiconductor structure provided by the technical scheme of the invention, the grooves are formed on the side wall of one side or two sides of the first initial nanowire on the first region by etching the one or a plurality of first initial nanowires; and forming first source and drain openings at two sides of the extending direction of the first fin structure, wherein the side walls of the first source and drain openings expose the grooves, and the side walls of the first nanowires where the grooves are positioned are sunken relative to the side walls of the first nanowires at the bottoms of the grooves. By forming the isolation structure in the groove, the isolation structure is located between one or a plurality of first nanowires and the first source-drain openings, and the isolation structure can effectively isolate the first source-drain doping layers formed in the first source-drain openings and the first nanowires, so that one or a plurality of first nanowires cannot play a role in providing channels between the first source-drain doping layers, and the number of channels in the semiconductor device can be changed.
Further, the second nanowires on the second region can all serve to provide channels between the second source-drain doped layers, so that the number of channels used for forming semiconductor devices on the first region is smaller than that of channels used for forming semiconductor devices on the second region, that is, the semiconductor devices on the first region and the second region contain different channel numbers, thereby being capable of meeting specific process requirements.
Further, since the first dummy gate structure of the second region easily affects one side of the first initial fin structure, when the mask opening exposes one side of the first initial fin structure away from the second region, in the process of etching the one or more first initial nanowires, on one hand, the process difficulty of forming the grooves is reduced, on the other hand, the second initial fin structure adjacent to the first region is not easily affected, and therefore the morphology of the formed grooves is good, the quality of an isolation structure formed in the grooves is ensured, the isolation structure can effectively isolate the first source-drain doped layers, and semiconductor devices formed on the first region and the second region contain different channel numbers, so that specific process requirements can be met.
Drawings
FIG. 1 is a schematic diagram of a semiconductor structure;
fig. 2 to 15 are schematic structural views illustrating steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
As described in the background, the existing semiconductor structure cannot meet the process requirements, and the following detailed description is given with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a semiconductor structure.
Referring to fig. 1, a semiconductor structure includes: a substrate 100, the substrate 100 comprising a first region I and a second region II; a first fin structure 110 located on the first region I and a first gate structure 120 crossing the first fin structure 110, wherein the first fin structure 110 includes a plurality of first nanowires 111 aligned along a surface normal direction of the substrate 100 and separated from each other; a second fin structure 130 located on the second region II and a second gate structure 140 crossing the second fin structure 130, wherein the second fin structure 140 includes a plurality of second nanowires 131 aligned along a surface normal direction of the substrate 100 and separated from each other; the first source-drain doped layers 160 are located on two sides of the extending direction of the first fin structure 110 on the first region I; the second source-drain doped layer 170 is located on two sides of the second region II in the extending direction of the second fin structure 140.
In the above structure, the first nanowire 111 is used to provide a channel, the second nanowire 131 is used to provide a channel, the first gate structure 120 surrounds the first nanowire 111, the second gate structure 140 surrounds the second nanowire 131, so that the devices on the first region I are channel gate surrounding structure transistors, and the devices on the second region II are channel gate surrounding structure transistors, so that the gate control capability of the formed semiconductor structure is enhanced.
However, since the number of the first nanowires 111 in the first fin structure 110 and the number of the second nanowires 131 of the second fin structure 130 are the same, the semiconductor device on the first region I has the same number of channels as the semiconductor device on the second region II, which cannot meet specific process requirements.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
In order to solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: etching one or a plurality of first initial nanowires, and forming grooves on side walls of one side or two sides of the first initial nanowires; after the grooves are formed, removing first initial fin structures on two sides of the first pseudo gate structure, forming first fin structures on a first region, enabling the first initial nanowires to form first nanowires, wherein first source drain openings are formed on two sides of the extending direction of the first fin structures, the side walls of the first source drain openings expose the grooves, and the side walls of the first nanowires where the grooves are located are sunken relative to the side walls of the first nanowires at the bottoms of the grooves; and forming an isolation structure in the groove, wherein the isolation structure is positioned between one or a plurality of first nanowires and the first source drain opening. The method can realize the requirement of changing the number of channels in the semiconductor device.
Fig. 2 to 15 are schematic structural views illustrating steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 2 and 3, fig. 3 is a schematic cross-sectional view taken along line A-A1 and line A2-A3 in fig. 2, a substrate 200 is provided, the substrate 200 includes a first region I and a second region II, the first region I has a first initial fin structure 210 thereon, and the first initial fin structure 210 includes a plurality of first sacrificial layers 211 overlapping along a normal direction of a surface of the substrate 200 and first initial nanowires 212 located on the surface of the first sacrificial layers 211.
In this embodiment, the substrate 200 of the second region II has a second initial fin structure 220 thereon, and the second initial fin structure 220 includes a plurality of second sacrificial layers 221 overlapping along a surface normal direction of the substrate 200 and second initial nanowires 222 located on a surface of the second sacrificial layers 221.
The material of the substrate 200 is silicon; in other embodiments, the substrate material may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide; in other embodiments, the base may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
The top surface of the first initial fin structure 210 and the top surface of the second initial fin structure 220 also have a first protection layer 213.
The method for forming the first initial fin structure 210 and the second initial fin structure 220 includes: forming a fin material film (not shown in the figure) on the substrate 200, wherein the fin material film comprises a plurality of sacrificial material films overlapped along the normal direction of the surface of the substrate 200 and a nano material film positioned on the surface of the sacrificial material film; forming a protective film on the surface of the fin part material film; forming a patterned layer on the surface of the protective film; etching the fin material film and the protective film by using the patterned layer as a mask until the surface of the substrate 200 is exposed, forming a first protective layer 213 by the protective film, forming a first sacrificial layer 211 and a first initial nanowire 212 positioned on the surface of the first sacrificial layer 211 on the first region I, and forming a second sacrificial layer 221 and a second initial nanowire 222 positioned on the surface of the second sacrificial layer 212 on the second region II.
The first protection layer 213 is used to protect the surfaces of the first initial fin structure 210 and the second initial fin structure 220 from being affected by the subsequent process, so that the first initial fin structure 210 and the second initial fin structure 220 are consumed.
The material of the first protection layer 213 is different from the material of the fin material film.
The materials of the first protective layer 213 include: silicon oxide or silicon nitride
In this embodiment, the material of the first protection layer 213 is silicon nitride.
With continued reference to fig. 2 and 3, after forming the first initial fin structure 210 and the second initial fin structure 220, an insulating layer (not labeled in the drawing) is formed on the surface of the substrate 200, where the insulating layer covers sidewall surfaces of the first initial fin structure 210 and the second initial fin structure 220, and a top surface of the insulating layer is lower than top surfaces of the first initial fin structure 210 and the second initial fin structure 220.
The insulating layer is used for realizing electrical isolation between different devices.
Referring to fig. 4 and 5, fig. 4 is a schematic view based on fig. 2, fig. 5 is a schematic view based on fig. 3, and a first dummy gate structure 230 is formed on the first region I and spans the first initial fin structure 210.
In this embodiment, the method for forming a semiconductor structure further includes: a second dummy gate structure 240 is formed on the second region II across the second initial fin structure 220.
The first dummy gate structure 230 is used in a post gate process to subsequently form a first gate structure; the second dummy gate structure 240 is used in a post gate process to subsequently form a second gate structure.
In this embodiment, the first dummy gate structure 230 and the second dummy gate structure 240 are formed in the same process. In other embodiments, the first dummy gate structure and the second dummy gate structure are formed sequentially.
The forming method of the first dummy gate structure 230 and the second dummy gate structure 240 includes: forming a dummy gate dielectric film on the substrate 200, wherein the dummy gate dielectric film covers the surfaces of the first initial fin structure 210 and the second initial fin structure 220; forming a pseudo gate electrode film on the surface of the pseudo gate dielectric film; patterning the dummy gate electrode film and the dummy gate dielectric film until the surface of the insulating layer is exposed, forming a first dummy gate structure 230 crossing the first initial fin structure 210 on the first region I, and forming a second dummy gate structure 240 crossing the second initial fin structure 220 on the second region II.
In this embodiment, the method for forming a semiconductor structure further includes: forming a first sidewall 231 on a sidewall surface of the first dummy gate structure 230; a second sidewall 232 is formed on a surface of the sidewall of the second dummy gate structure 240.
The first side wall 231 and the second side wall 232 are used for protecting the sidewall surfaces of the first dummy gate structure 230 and the second dummy gate structure 240, so as to avoid appearance defects of the subsequently formed first gate structure and second gate structure and influence the electrical performance of the semiconductor structure.
In this embodiment, the method for forming a semiconductor structure further includes: forming a second protective layer (not shown) on the top surface of the first dummy gate structure 230; a third protective layer (not shown) is formed on the top surface of the second dummy gate structure 240.
The second protection layer and the third protection layer are used for protecting the top surface of the first dummy gate structure 230 and the top surface of the second dummy gate structure 240 when the first source-drain doped layer and the second source-drain doped layer are subsequently formed, so as to avoid influencing the heights of the first gate structure and the second gate structure when the first dummy gate structure 230 is subsequently removed to form the first gate structure and the second dummy gate structure 240 is subsequently removed to form the second gate structure.
Next, one or several of the first initial nanowires 212 are etched, and grooves are formed on one or both side walls of the first initial nanowires 212.
In this embodiment, the first initial nanowire 212 is etched, the recess is formed on one side of the first initial nanowire 212, and the process of etching the first initial nanowire is specifically described with reference to fig. 6 to 9.
Referring to fig. 6 and 7, fig. 6 is a schematic diagram based on fig. 4, and fig. 7 is a schematic diagram based on fig. 5, wherein a mask layer 250 is formed on the first initial fin structure 210, the second initial fin structure 230, the first dummy gate structure 230, and the second dummy gate structure 240, the mask layer 250 has a mask opening 251 therein, and the mask opening 251 exposes the first initial fin structure 210.
The mask layer 250 serves as a mask for subsequently etching the first initial fin structure 210 to form a recess.
In this embodiment, the mask opening 251 exposes one side of the first initial fin structure 210.
Specifically, the mask opening 251 exposes a side of the first initial fin structure 210 away from the second region II.
The mask layer 250 comprises the following materials: a photoresist material.
Because the first dummy gate structure 230 of the second region II easily affects one side of the first initial fin structure 210, when the mask opening 251 exposes one side of the first initial fin structure 210 away from the second region II, in the process of etching the one or more first initial nanowires 212, on one hand, the process difficulty of subsequently forming the grooves is reduced, on the other hand, the second initial fin structure 220 adjacent to the first region II is not easily affected, so that the formed grooves have better morphology, the quality of isolation structures subsequently formed in the grooves is ensured, and the isolation structures can effectively isolate the first source-drain doped layers, so that semiconductor devices formed on the first region I and the second region II contain different channel numbers, and specific process requirements can be met.
Referring to fig. 8 and 9, fig. 8 is a schematic diagram based on fig. 6, and fig. 9 is a schematic diagram based on fig. 7, in which the mask layer 250 is used as a mask, one or several first initial nanowires 212 exposed by the mask opening 251 are etched until the surface of the first sacrificial layer 211 is exposed, and the grooves 260 are formed on the sidewalls of the one or several first initial nanowires 212.
The grooves 260 provide space for the subsequent formation of isolation structures.
In this embodiment, the one first preliminary nanowire 212 is etched, and the groove 260 is formed at one side of the one first preliminary nanowire 212.
In other embodiments, more than two of the first initial nanowires may be etched, and the grooves may be formed at one side of the more than two of the first initial nanowires.
In other embodiments, one of the first initial nanowires may be etched, and the grooves may be formed on both sides of the one of the first initial nanowires.
In other embodiments, more than two first initial nanowires may be etched, and the grooves may be formed on both sides of the more than two first initial nanowires.
The process of etching the one or several first initial nanowires 212 exposed by the mask openings 251 comprises: one or a combination of both of a dry etching process and a wet etching process.
The process of etching the one or several first initial nanowires 212 exposed by the mask opening 251 is a wet etching process; the parameters of the wet etching process include: the adopted etching solution comprises a tetramethyl ammonium hydroxide solution, and the concentration of the tetramethyl ammonium hydroxide solution is 3-20%.
The wet etching process is an isotropic etching process, so that the formed groove 260 is also etched along the extending direction of the first initial fin structure 210, that is, the first initial fin structure 210 located at the bottom of the first dummy gate structure 230 is etched, which is helpful for the subsequent etching of the first initial nanowire 212 to form the first nanowire, so that the sidewall of the first nanowire where the subsequent groove 260 is located is recessed relative to the sidewall of the first nanowire opposite to the bottom of the groove 260.
Specifically, in this embodiment, the sidewall of the first initial nanowire 212 where the groove 260 is located is recessed with respect to the sidewall of the first sidewall 231.
In this embodiment, after the recess 260 is formed, the mask layer 250 is removed.
Referring to fig. 10, fig. 10 is a schematic diagram of fig. 8, after the recess 260 is formed, the first initial fin structures 210 on both sides 230 of the first dummy gate structure are removed, a first fin structure (not labeled in the drawing) is formed on the first region I, so that the first initial nanowire 212 forms a first nanowire 216, both sides of the first fin structure in the extending direction have first source/drain openings 241, the sidewalls of the first source/drain openings 241 expose the recess 260, and the sidewalls of the first nanowire 216 where the recess 260 is located are recessed with respect to the sidewalls of the first nanowire 216 on the bottom of the recess 260.
In this embodiment, the method for forming a semiconductor structure further includes: the second initial fin structures 220 at two sides of the second dummy gate structure 240 are removed, so that the second initial nanowire 222 forms a second nanowire 226, and a second fin structure (not shown in the figure) is formed on the second region II, where two sides of the extending direction of the second fin structure have second source-drain openings 242.
The first source-drain opening 241 is used for providing space for forming a first source-drain doped layer subsequently, and the second source-drain opening 242 is used for providing space for forming the first source-drain doped layer subsequently.
In this embodiment, the first source-drain opening 241 and the second source-drain opening 232 are formed in the same process.
In this embodiment, specifically, the first dummy gate structure 221 and the second dummy gate structure 222 are used as masks, the first initial fin structure 210 is etched to form a first fin structure, the first source-drain opening 241 is formed in the first fin structure, the second initial fin structure 220 is etched to form a second fin structure, and the second source-drain opening 242 is formed in the second fin structure.
In this embodiment, the first source drain opening 241 and the second source drain opening 232 are adjacent to and communicate with each other.
In other embodiments, the first source-drain opening and the second source-drain opening may not be adjacent.
The process of etching the first initial fin structure 210 and the second initial fin structure 220 includes: one or a combination of both of a dry etching process and a wet etching process.
In this embodiment, the process of etching the first initial fin structure 210 and the second initial fin structure 220 is a dry etching process, and the dry etching process is favorable for forming the first fin structure and the second fin structure with good morphology.
With continued reference to fig. 10, after forming the first source-drain openings 241 and the second source-drain openings 242, first fin recesses 218 are formed between adjacent first nanowires 216.
In this embodiment, the forming of the semiconductor structure further includes: a second fin recess 228 is formed between adjacent second nanowires 226.
The first fin recess 218 provides space for a subsequent formation of a first isolation layer, and the second fin recess 228 provides space for a subsequent formation of a second isolation layer.
The method for forming the first fin recess 218 includes: portions of the first sacrificial layer 211 are etched to form first modified sacrificial layers 215, sidewalls of the first modified sacrificial layers 215 are recessed relative to sidewalls of the first nanowires 216, and first fin recesses 218 are formed between adjacent first nanowires 216.
The method for forming the second fin recess 228 includes: portions of the second sacrificial layer 221 are etched to form second modified sacrificial layers 225, sidewalls of the second modified sacrificial layers 225 are recessed relative to sidewalls of the second nanowires 226, and second fin recesses 228 are formed between adjacent second nanowires 226.
In this embodiment, the first fin recess 218 and the second fin recess 228 are formed in the same process.
The process of etching a portion of the first sacrificial layer 211 and a portion of the second sacrificial layer 221 includes: one or a combination of both of a dry etching process and a wet etching process.
In the present embodiment, the process of etching part of the first sacrificial layer 211 and etching part of the second sacrificial layer 221 is a wet etching process, which is advantageous for etching the first sacrificial layer 212 between adjacent first nanowires 216 and the second sacrificial layer 222 between adjacent second nanowires 226.
Referring to fig. 11, fig. 11 is a schematic view of fig. 10, an isolation structure 281 is formed in the recess 260, and the isolation structure 281 is located between one or several first nanowires 216 and the first source-drain openings 241 (shown in fig. 10).
In this embodiment, the method for forming a semiconductor structure further includes: a first isolation layer 282 is formed within the first fin recess 218.
In this embodiment, the method for forming a semiconductor structure further includes: a second isolation layer 283 is formed in the second fin recess 228.
In this embodiment, the isolation structures 281 and the first and second isolation layers 282 and 283 are formed in the same process.
The forming method of the isolation structure 281 and the first isolation layer 282, the second isolation layer 283 includes: forming an isolation material film (not shown) on the substrate 200 surface, the recess 260, the first fin recess 218, the second fin recess 228, the top surface and sidewall surface of the first dummy gate structure 230, the top surface and sidewall surface of the second dummy gate structure 240, and the sidewall surfaces of the first nanowire 216 and the second nanowire 226; the isolation material film is etched back until the surface of the substrate 200, the surface of the sidewall of the first nanowire 216, and the surface of the sidewall of the second nanowire 216 are exposed, an isolation structure 281 is formed in the recess 260, the first isolation layer 282 is formed in the first fin recess 218, and the second isolation layer 283 is formed in the second fin recess 228.
The isolating material film is made of insulating material. The insulating material includes: silicon oxide, silicon nitride, silicon carbide nitride, silicon boride nitride, silicon oxycarbide oxide, or silicon oxynitride.
In this embodiment, the material of the isolation material film is silicon nitride, and correspondingly, the materials of the isolation structure 281, the first isolation layer 282, and the second isolation layer 283 are uniform silicon nitride.
Referring to fig. 12, fig. 12 is a schematic view of fig. 11, a first source-drain doped layer 243 is formed in the first source-drain opening 241, and the first source-drain doped layer 243 covers the sidewall surface of the isolation structure 281.
In this embodiment, the method for forming a semiconductor structure further includes: a second source-drain doped layer 244 is formed within the second source-drain openings 242.
In this embodiment, the first source-drain doped layer 243 also covers the first isolation layer 282 and the sidewall surface of the first nanowire 216; the second source drain doped layer 244 also covers the second isolation layer 283 and the first nanowire 226 sidewall surfaces.
Specifically, after the isolation structures 281, the first isolation layer 282, and the second isolation layer 283 are formed, the first source-drain doped layer 243 is formed in the first source-drain opening 241 and the second source-drain doped layer 244 is formed in the second source-drain opening 242 by an in-situ epitaxial growth process.
Source-drain ions are further doped in the first source-drain doped layer 243 and the second source-drain doped layer 244, and the source-drain ions include: p-type ions, such as boron ions or BF 2+, or N-type ions, include: phosphorus ions, arsenic ions or antimony ions.
The process of doping source and drain ions in the first source and drain doping layer 243 and the second source and drain doping layer 244 includes: an ion implantation process or an in-situ doping process.
Forming a groove 260 on one side or two side walls of the first initial nanowire 212 on the first region I by etching the one or a plurality of first initial nanowires 212; a first source-drain opening 241 is formed at two sides of the extending direction of the first fin structure, the sidewall of the first source-drain opening 241 exposes the recess 260, and the sidewall of the first nanowire 216 where the recess 260 is located is recessed relative to the sidewall of the first nanowire 216 at the bottom of the recess 260. By forming the isolation structures 281 within the recess 260, the isolation structures 281 are located between the one or several first nanowires 216 and the first source-drain openings 241, the isolation structures 281 are capable of effectively isolating between the first source-drain doped layer 243 located within the first source-drain openings 242 and the first nanowires 216, such that the one or several first nanowires 216 cannot function to provide channels between the first source-drain dopings 216, thereby enabling a change in the number of channels in the semiconductor device.
At the same time, the second nanowires 226 on the second region II can each function to provide channels between the second source-drain doped layers 244, so that the number of channels used to form semiconductor devices on the first region I is smaller than the number of channels used to form semiconductor devices on the second region II, i.e., the semiconductor devices on the first region I and the second region II have different numbers of channels, thereby being capable of meeting specific process requirements.
Referring to fig. 13, fig. 13 is a schematic diagram of fig. 12, a dielectric layer 290 is formed on the substrate 200, and the dielectric layer 290 covers the surface of the first source/drain doped layer 243, the surface of the second source/drain doped layer 244, the surface of the first dummy gate structure and the surface of the sidewall of the second dummy gate structure; forming a first gate opening 291 and a second gate opening 292 in the dielectric layer 290; forming first additional openings 2911 between adjacent first nanowires 216 exposed by the first gate openings 291; a second additional opening 2921 is formed between adjacent second nanowires 226 exposed by the second gate opening 292.
The first opening 291 and the first additional opening 2911 are used to subsequently form a first gate structure, and the second opening 292 and the second additional opening 2921 are used to subsequently form a second gate structure.
The forming method for forming the first gate opening 291 and the second gate opening 292 in the dielectric layer 290 includes: removing the first dummy gate structure 230, forming the first opening 291 in the dielectric layer 290; the second dummy gate structure 240 is removed and the second opening 292 is formed in the dielectric layer 290.
In this embodiment, the removal of the first dummy gate structure 230 and the second dummy gate structure 240 is performed in the same process.
The process of removing the first and second dummy gate structures 230 and 240 includes: one or a combination of both of a dry etching process and a wet etching process.
Specifically, the first opening 291 exposes a portion of the top surface and the sidewall surface of the first fin structure, and the surface of the isolation layer; the second opening 2921 exposes a portion of the top and sidewall surfaces of the first fin structure, as well as the spacer surface.
The first additional opening 2911 is formed by: the first sacrificial layer 215 between adjacent first nanowires 216 exposed by the first openings 291 is removed, and the first additional openings 2911 are formed between the adjacent first nanowires 216.
The forming method of the second additional opening 2921 includes: the second sacrificial layer 225 between adjacent second nanowires 226 exposed by the second openings 291 is removed, and the second additional openings 2921 are formed between the adjacent second nanowires 226.
Referring to fig. 14 and 15, fig. 14 is a schematic view based on fig. 13, and the directions of the views in fig. 15 and 9 are the same, a first gate structure 293 is formed in the first gate opening 291 and the first additional opening 2911, and the first gate structure 293 surrounds each of the first nanowires 216; a second gate structure 294 is formed within the second gate opening 292 and the second additional opening 2921, the second gate structure 294 surrounding each of the second nanowires 226.
In this embodiment, the first gate structure 293 and the second gate structure 294 are formed in the same process.
The forming method of the first gate structure 293 and the second gate structure 294 includes: forming a gate dielectric film (not shown) in the first and second openings 291 and 292, on the surfaces of the first and second additional openings 2911 and 2921, and on the surface of the dielectric layer 290; forming a gate electrode film (not shown) on the surface of the gate dielectric film, the gate electrode film filling the first and second openings 291 and 292 and the first and second additional openings 2911 and 2921; the gate electrode film and the gate dielectric film are planarized until the surface of the dielectric layer 290 is exposed, the gate dielectric film is formed into a gate dielectric layer, the gate electrode film is formed into a gate electrode layer, the first gate structure 293 is formed in the first opening 291 and the first additional opening 2911, and the second gate electrode coupler 294 is formed in the second opening 292 and the second additional opening 2921.
The first side walls 231 are located on two side walls of the first gate structure 293.
The second side walls 232 are located on two side walls of the second gate structure 294.
Accordingly, an embodiment of the present invention provides a semiconductor structure, please continue to refer to fig. 11, including: a substrate 200, the substrate 200 comprising a first region I and a second region II; a first fin structure located on the first region I, the first fin structure including a plurality of first nanowires 216 aligned along a surface normal direction of the substrate 200 and separated from each other; a first gate structure 293 located on the first region I and crossing the first fin structure, wherein a first source-drain opening 241 (shown in fig. 10) is formed in the first fin structure at two sides of the first gate structure 293, a groove 260 is formed on one or two sides of the sidewall of the first source-drain opening 241 (shown in fig. 10), the surface of the sidewall of one or several first nanowires 216 is exposed by the groove 260, and the sidewall of the first nanowire 216 where the groove 260 is located is recessed relative to the sidewall of the first nanowire 216 at the bottom of the groove 260; isolation structures 281 are located within the recess 260.
Because the sidewalls of the first source-drain openings 241 on one side or both sides have the grooves 260, the grooves 260 expose the sidewall surfaces of one or several first nanowires 216, and the sidewalls of the first nanowires 216 where the grooves 260 are located are recessed with respect to the sidewalls of the first nanowires 216 at the bottom of the grooves 260, and at the same time, the sidewalls of the grooves 260 are exposed by the first source-drain openings 241. The first source-drain opening 241 has a first source-drain doped layer 243 therein, and the recess 260 has an isolation structure 281 therein, that is, the isolation structure 281 is located between the first source-drain doped layer 243 and the first nanowire 216, so that the isolation structure 281 can effectively isolate the first source-drain doped layer 243 from the first nanowire 216, so that one or several first nanowires 216 cannot function to provide channels between the first source-drain dopings 243, thereby changing the number of channels in the semiconductor device.
The following detailed description refers to the accompanying drawings.
The first gate structure 293 includes: the first gate dielectric layer (not shown) spans the first fin structure, the first gate electrode layer first gate dielectric layer (not shown) located on the surface of the first gate dielectric layer, and the first sidewall 231 located on the sidewall surfaces of the first gate dielectric layer and the first gate electrode layer.
In this embodiment, the sidewall of the isolation structure 281 is flush with the sidewall surface of the first sidewall 231.
The semiconductor structure further includes: a second fin structure located on the second region II, the second fin structure including a plurality of second nanowires 226 arranged along a surface normal direction of the substrate 200 and separated from each other; a second gate structure 294 is located on the second region II across the second fin structure.
The second fin structure at two sides of the second gate structure 294 has second source-drain openings 242 therein.
The semiconductor structure further includes: the first source-drain doped layer 243 is located in the first source-drain opening 241, and the first source-drain doped layer 243 covers the surface of the sidewall of the isolation structure 281; a second source-drain doped layer 244 located within second source-drain opening 244.
The second gate structure 294 includes: the second fin structure comprises a second gate dielectric layer (not shown) crossing the second fin structure, a second gate electrode layer (not shown) located on the surface of the second gate dielectric layer, and a second sidewall 232 located on the surfaces of the second gate dielectric layer and the sidewall of the second gate electrode layer.
A first fin recess 218 and a first isolation layer 281 located in the first fin recess 218 are located between adjacent first nanowires 216.
A second fin recess 228 and a second isolation layer 283 in the second fin recess 229 are disposed between adjacent second nanowires 226.
The semiconductor structure further includes: a dielectric layer 290 on the substrate 200, wherein a first gate opening 291 is formed in the dielectric layer 290, and a part of top surface and sidewall surface of the first fin structure are exposed by the first gate opening 291; the first gate structure 293 is located within the first gate opening 291.
The dielectric layer 290-also has a second gate opening 292 therein, and the second gate opening 292 exposes a portion of a top surface and a sidewall surface of the second fin structure; the second gate structure 294 is located within the second gate opening 292.
The semiconductor structure further includes: a first additional opening 2911 located between adjacent first nanowires 216, the first gate opening 291 exposing the first additional opening 2911; the first gate structure 293 is also located within the first additional opening 2911, and the first gate structure 293 surrounds each of the first nanowires 216.
The semiconductor structure further includes: a second additional opening 2921 located between adjacent second nanowires 226, the second gate opening 292 exposing the second additional opening 2921; the second gate structure 294 is also located within the second additional opening 2921, and the second gate structure 294 surrounds each of the second nanowires 226.
Further, the second nanowires 226 on the second region II can each function to provide a channel between the second source-drain doped layers 244, so that the number of channels used to form semiconductor devices on the first region I is less than the number of channels used to form semiconductor devices on the second region II, i.e., the semiconductor devices on the first region I and the second region II have different numbers of channels, thereby being capable of meeting specific process requirements.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (30)

1. A semiconductor structure, comprising:
a substrate comprising a first region and a second region;
The first fin structure is positioned on the first region and comprises a plurality of first nanowires which are arranged along the normal direction of the surface of the substrate and are mutually separated;
The first grid structure is positioned on the first region and spans the first fin structure, first source drain openings are formed in the first fin structures at two sides of the first grid structure, grooves are formed in the side walls of the first source drain openings at one side or two sides of the first fin structures, the grooves expose the surface of one or a plurality of first nanowire side walls, and the side walls of the first nanowires where the grooves are positioned are sunken relative to the side walls of the first nanowire at the bottom of the grooves;
and the isolation structure is positioned in the groove.
2. The semiconductor structure of claim 1, wherein the first gate structure comprises: the first side wall is positioned on the side wall surfaces of the first gate dielectric layer and the first gate electrode layer.
3. The semiconductor structure of claim 2, wherein the isolation structure sidewall is flush with the first sidewall surface.
4. The semiconductor structure of claim 1, further comprising: the second fin structure is positioned on the second region and comprises a plurality of second nanowires which are arranged along the normal direction of the surface of the substrate and are mutually separated; and the second grid structure is positioned on the second region and spans the second fin structure.
5. The semiconductor structure of claim 4, wherein a second fin structure on both sides of the second gate structure has a second source drain opening therein.
6. The semiconductor structure of claim 5, further comprising: the first source-drain doping layer is positioned in the first source-drain opening and covers the side wall surface of the isolation structure; and the second source-drain doping layer is positioned in the second source-drain opening.
7. The semiconductor structure of claim 4, wherein the second gate structure comprises: the second side wall is positioned on the side wall surfaces of the second gate dielectric layer and the second gate electrode layer.
8. The semiconductor structure of claim 1, wherein a first fin recess and a first isolation layer within the first fin recess are provided between adjacent first nanowires.
9. The semiconductor structure of claim 4, wherein a second fin recess and a second isolation layer within the second fin recess are provided between adjacent second nanowires.
10. The semiconductor structure of claim 9, further comprising: the dielectric layer is positioned on the substrate and is provided with a first gate opening, and part of the top surface and the side wall surface of the first fin structure are exposed out of the first gate opening; the first gate structure is located within the first gate opening.
11. The semiconductor structure of claim 10, further having a second gate opening in the dielectric layer, the second gate opening exposing a portion of a top surface and a sidewall surface of the second fin structure; the second gate structure is located within the second gate opening.
12. The semiconductor structure of claim 11, further comprising: a first additional opening between adjacent first nanowires, the first gate opening exposing the first additional opening; the first gate structure is also located within the first additional opening, and the first gate structure surrounds each of the first nanowires.
13. The semiconductor structure of claim 12, further comprising: a second additional opening between adjacent second nanowires, the second gate opening exposing the second additional opening; the second gate structure is also located within the second additional opening, and the second gate structure surrounds each of the second nanowires.
14. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a first region and a second region, the first region is provided with a first initial fin structure, and the first initial fin structure comprises a plurality of first sacrificial layers overlapped along the normal direction of the surface of the substrate and first initial nanowires positioned on the surface of the first sacrificial layers;
forming a first dummy gate structure on the first region that spans the first initial fin structure;
Etching one or a plurality of first initial nanowires, and forming grooves on side walls of one side or two sides of the first initial nanowires;
after the grooves are formed, removing first initial fin structures on two sides of the first pseudo gate structure, forming first fin structures on a first region, enabling the first initial nanowires to form first nanowires, wherein first source drain openings are formed on two sides of the extending direction of the first fin structures, the side walls of the first source drain openings expose the grooves, and the side walls of the first nanowires where the grooves are located are sunken relative to the side walls of the first nanowires at the bottoms of the grooves;
and forming an isolation structure in the groove, wherein the isolation structure is positioned between one or a plurality of first nanowires and the first source drain opening.
15. The method of claim 14, wherein a substrate of the second region has a second initial fin structure thereon, the second initial fin structure including a plurality of second sacrificial layers overlapping along a normal direction of a surface of the substrate and second initial nanowires on a surface of the second sacrificial layers.
16. The method of forming a semiconductor structure of claim 15, further comprising: a second dummy gate structure is formed on the second region across the second initial fin structure.
17. The method of forming a semiconductor structure of claim 16, wherein the method of etching a plurality of the first initial nanowires comprises: forming a mask layer on the first initial fin structure, the second initial fin structure, the first pseudo gate structure and the second pseudo gate structure, wherein a mask opening is formed in the mask layer, and the mask opening exposes the surface of the first initial fin structure; and etching one or a plurality of first initial nanowires exposed by the mask opening by taking the mask layer as a mask until the surface of the first sacrificial layer is exposed, and forming the grooves on the side walls of the one or a plurality of first initial nanowires.
18. The method of claim 17, wherein the process of etching the one or more first initial nanowires exposed by the mask opening is a wet etching process; the parameters of the wet etching process include: the adopted etching solution comprises a tetramethyl ammonium hydroxide solution, and the concentration of the tetramethyl ammonium hydroxide solution is 3-20%.
19. The method of claim 17, wherein the mask opening exposes a side of the first initial fin structure away from the second region; and etching the first initial nanowires exposed by the mask openings by taking the mask layer as a mask, and forming the grooves on one sides of the first initial nanowires.
20. The method of forming a semiconductor structure of claim 16, further comprising: and removing the second initial fin structures at two sides of the second pseudo gate structure, forming a second nanowire by the second initial nanowire, and forming a second fin structure on a second region, wherein two sides of the extending direction of the second fin structure are provided with second source and drain openings.
21. The method of forming a semiconductor structure of claim 20, further comprising: forming a first source-drain doping layer in the first source-drain opening, wherein the first source-drain doping layer covers the side wall surface of the isolation structure; and forming a second source-drain doping layer in the second source-drain opening.
22. The method of forming a semiconductor structure of claim 21, further comprising: forming a first fin groove between adjacent first nanowires after forming the first source-drain opening and the second source-drain opening and before forming the first source-drain doping layer and the second source-drain doping layer; forming a second fin groove between adjacent second nanowires; forming a first isolation layer in the first fin portion groove; forming a second isolation layer in the second fin portion groove; after the first isolation layer and the second isolation layer are formed, the first source-drain doping layer and the second source-drain doping layer are formed, the first source-drain doping layer covers the surface of the side wall of the first isolation layer, and the second source-drain doping layer covers the surface of the side wall of the second isolation layer.
23. The method of forming a semiconductor structure of claim 22, wherein the method of forming a first fin recess comprises: etching part of the first sacrificial layer to form a first modified sacrificial layer, wherein the side wall of the first modified sacrificial layer is sunken relative to the side wall of the first nanowire, and a first fin groove is formed between adjacent first nanowires; the forming method of the second fin portion groove comprises the following steps: and etching part of the second sacrificial layer to form a second modified sacrificial layer, wherein the side wall of the second modified sacrificial layer is sunken relative to the side wall of the second nanowire, and a second fin groove is formed between adjacent second nanowires.
24. The method of forming a semiconductor structure of claim 23, wherein said isolation structure and said first and second isolation layers are formed in the same process.
25. The method of forming a semiconductor structure of claim 24, wherein the forming of the isolation structure and the first and second isolation layers comprises: forming an isolation material film on the substrate surface, the groove, the first fin groove, the second fin groove, the top surface and the side wall surface of the first pseudo gate structure, the top surface and the side wall surface of the second pseudo gate structure, and the side wall surfaces of the first nanowire and the second nanowire; and etching the isolation material film until the substrate surface, the first nanowire side wall surface and the second nanowire side wall surface are exposed, forming an isolation structure in the groove, forming a first isolation layer in the first fin groove, and forming a second isolation layer in the second fin groove.
26. The method of claim 15, wherein the first initial fin structure top surface and the second initial fin structure top surface further have a protective layer.
27. The method of forming a semiconductor structure of claim 26, wherein the forming of the first initial fin structure and the second initial fin structure comprises: forming a fin material film on the substrate, wherein the fin material film comprises a plurality of sacrificial material films overlapped along the normal direction of the surface of the substrate and a nano material film positioned on the surface of the sacrificial material film; forming a protective film on the surface of the fin part material film; forming a patterned layer on the surface of the protective film; and etching the fin material film and the protective film by taking the patterned layer as a mask until the surface of the substrate is exposed, forming a protective layer by the protective film, forming a first sacrificial layer and a first initial nanowire positioned on the surface of the first sacrificial layer on the first region, and forming a second sacrificial layer and a second initial nanowire positioned on the surface of the second sacrificial layer on the second region.
28. The method of forming a semiconductor structure of claim 21, further comprising: forming a dielectric layer on the substrate after forming the first source-drain doping layer and the second source-drain doping layer, wherein the dielectric layer covers the side wall surfaces of the first source-drain doping layer, the second source-drain doping layer, the first pseudo gate structure and the second pseudo gate structure; forming a first gate opening and a second gate opening in the dielectric layer; forming first additional openings between adjacent first nanowires exposed by the first gate openings; forming a second additional opening between adjacent second nanowires exposed by the second gate opening; forming a first gate structure within the first gate opening and the first additional opening, the first gate structure surrounding each of the first nanowires; forming a second gate structure within the second gate opening and the second additional opening, the second gate structure surrounding each of the second nanowires.
29. The method of forming a semiconductor structure of claim 28, wherein the method of forming a first gate opening comprises: removing the first pseudo gate structure and forming a first gate opening in the dielectric layer; the second gate opening forming method comprises the following steps: and removing the second pseudo gate structure, and forming a second gate opening in the dielectric layer.
30. The method of forming a semiconductor structure of claim 29, wherein the method of forming the first additional opening comprises: removing the first sacrificial layer exposed by the first gate opening, and forming a first additional opening between adjacent first nanowires; the forming method of the second additional opening comprises the following steps: and removing the second sacrificial layer exposed by the second gate opening, and forming the second additional opening between adjacent second nanophase.
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