WO2023103031A1 - 一种显示面板及其制备方法 - Google Patents

一种显示面板及其制备方法 Download PDF

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Publication number
WO2023103031A1
WO2023103031A1 PCT/CN2021/139032 CN2021139032W WO2023103031A1 WO 2023103031 A1 WO2023103031 A1 WO 2023103031A1 CN 2021139032 W CN2021139032 W CN 2021139032W WO 2023103031 A1 WO2023103031 A1 WO 2023103031A1
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Prior art keywords
substrate
capacitive
medium
electrode
layer
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PCT/CN2021/139032
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English (en)
French (fr)
Inventor
马倩
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深圳市华星光电半导体显示技术有限公司
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Priority to US17/622,804 priority Critical patent/US20240032341A1/en
Publication of WO2023103031A1 publication Critical patent/WO2023103031A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor

Definitions

  • the present application relates to the field of display technology, in particular to a display panel and a manufacturing method thereof.
  • OLED full name in English: Organic Light-Emitting Diode, Chinese: Organic Light-Emitting Display Device
  • OLED is also known as an organic electro-laser display device and an organic light-emitting semiconductor device.
  • OLED has become the most important One of the display technologies.
  • the current OLED generally adopts LTPO (English full name: Low Temperature Polycrystalline Oxide, Chinese: low temperature polycrystalline oxide) substrate.
  • the LTPO substrate contains IGZO (English full name: Indium Gallium Zinc Oxide, Chinese: Indium Gallium Zinc Oxide) TFT (English full name: Thin Film Transistor, Chinese: Thin Film Transistor) and LTPS (Low Temperature Poly-Silicon, low temperature polysilicon) TFT two TFT structures.
  • IGZO Indium Gallium Zinc Oxide
  • TFT Indium Gallium Zinc Oxide
  • LTPS Low Temperature Poly-Silicon, low temperature polysilicon
  • the gate of the LTPS TFT is generally used as the first capacitor electrode of the storage capacitor, and then a capacitor medium is arranged on the first capacitor electrode, and then a second gate is arranged on the capacitor medium as the second capacitor electrode of the storage capacitor.
  • the thickness of the current capacitor medium ranges from 1000 angstroms to 3000 angstroms, and the thickness of the capacitor medium is relatively large; the material of the current capacitor medium is generally SiOx or SiNx, and its dielectric constant is small, so the capacitance value of the storage capacitor formed thereby is relatively high. Small, unable to meet the needs of the display panel's charge and discharge and charge retention capabilities.
  • the light-shielding unit of the IGZO TFT is also defined, and then an insulating layer is set on the second capacitor electrode, and then the IGZO TFT is defined on the insulating layer . Therefore, the current LTPO substrate requires three gate masks (the gate of the LTPS TFT, the second capacitor electrode of the storage capacitor, and the gate of the IGZO TFT), and the preparation process is cumbersome.
  • the thickness of the insulating layer on the second capacitor electrode ranges from 2000 angstroms to 10000 angstroms, which is relatively thick, resulting in a thick film thickness of the LTPO substrate, which cannot meet the development requirements of ultra-thin display technology.
  • the purpose of the present invention is to provide a display panel and a preparation method thereof, which can solve the problem that the storage capacitor existing in the existing display panel has a relatively small capacitance value and cannot meet the requirements of the display panel's charge and discharge and charge retention capabilities, and the film thickness is relatively thick. Unable to meet the development needs of ultra-thin display technology and other issues.
  • the present invention provides a display panel, which includes a substrate and a plurality of pixel units arranged on the substrate; each of the pixel units includes: a driving area and a switching area; each of the pixel Each unit includes: a storage capacitor located in the drive area, which includes: a first capacitor electrode disposed on the substrate in the drive area; a first capacitor medium disposed on the first capacitor electrode away from the substrate on the surface of one side of the substrate, and extend to cover the substrate; the second capacitive electrode is arranged on the surface of the first capacitive medium away from the substrate, and is arranged correspondingly to the first capacitive electrode The second capacitor medium is arranged on the surface of the second capacitor electrode away from the substrate, and extends to cover the first capacitor medium; the interlayer insulating layer is arranged on the second capacitor medium on the surface of the side away from the substrate; and a third capacitive electrode disposed on the surface of the interlayer insulating layer away from the substrate and corresponding to the second capacitive electrode.
  • each of the pixel units includes: a driving thin film transistor located in the driving area, which includes: a first active layer disposed between the substrate and the first capacitor electrode; a first insulating layer , arranged between the first active layer and the first capacitor electrode, and extending to cover the substrate; a first gate, which is the same film layer as the first capacitor electrode; and a first source
  • the drain layer is disposed on the surface of the interlayer insulating layer away from the substrate, and is disposed on the same layer as the third capacitance electrode.
  • each of the pixel units includes: a switch thin film transistor located in the switch region, which includes: a second active layer disposed between the first capacitor medium and the interlayer insulating layer, and It is arranged on the same layer as the second capacitor electrode; the second insulating layer is arranged between the second active layer and the interlayer insulating layer; the second gate is arranged between the second insulating layer and the interlayer insulating layer. between the interlayer insulating layers; the second source and drain layer is disposed on the surface of the interlayer insulating layer away from the substrate, and is disposed on the same layer as the third capacitance electrode.
  • each of the pixel units further includes: a light-shielding unit disposed between the first insulating layer and the first capacitor medium, corresponding to the second active layer, and connected to the first A capacitor electrode is arranged on the same layer.
  • the second capacitive medium partially covers the second active layer; there are gaps between both sides of the second insulating layer and the second capacitive medium.
  • the material of the second capacitor medium is Al 2 O 3 .
  • the thickness of the second capacitor medium ranges from 50 angstroms to 100 angstroms.
  • the present invention also provides a method for manufacturing a display panel, which includes the following steps: providing a substrate, and preparing a plurality of pixel units on the substrate, and each pixel unit includes: a driving region and Switching area; the preparation step of each pixel unit includes: preparing a storage capacitor in the driving area, which includes: preparing a first capacitor electrode on the substrate in the driving area; Prepare a first capacitor medium on the surface of one side of the substrate, and the first capacitor medium extends to cover the substrate; prepare a second capacitor on the surface of the first capacitor medium away from the substrate electrode, the second capacitance electrode is arranged corresponding to the first capacitance electrode; a second capacitance medium is prepared on the surface of the second capacitance electrode away from the substrate, and the second capacitance medium extends to cover the On the first capacitor medium; preparing an interlayer insulating layer on the surface of the second capacitor medium away from the substrate; and preparing an interlayer insulating layer on the surface of the side away from the substrate A
  • the following steps are further included: preparing a light-shielding unit on the substrate of the switch region; The light-shielding unit is prepared and formed simultaneously with the first capacitor electrode.
  • the following steps are further included: on the surface of the first capacitor electrode on the side away from the substrate preparing a second active layer on the second active layer; preparing and forming the second active layer and the second capacitive electrode at the same time; preparing a second insulating layer on the surface of the second active layer away from the substrate; and preparing a second grid on the surface of the second insulating layer on the side away from the substrate.
  • the present application prepares the first gate of the driving thin film transistor while forming the light-shielding unit, while forming the second active layer of the switching thin film transistor, forms the second capacitor electrode of the storage capacitor, and forms the driving
  • the third capacitor electrode of the storage capacitor is formed at the same time as the first source and drain layers of the thin film transistor, thereby saving a gate mask plate, improving production efficiency and saving production cost.
  • the present invention adopts the first capacitance electrode, the first capacitance medium, the second capacitance electrode, the second capacitance medium and the third capacitance electrode to form a sandwich capacitance, because the thickness of the second capacitance medium is relatively thin, and the dielectric constant of the second capacitance medium Therefore, the capacitance value of the entire storage capacitor can be increased to meet the requirements of the display panel's charge and discharge and charge retention capabilities.
  • the thickness of the second capacitor medium is relatively thin, which can reduce the thickness of the display panel, thereby meeting the development requirements of ultra-thin display technology.
  • FIG. 1 is a schematic plan view of a display panel of the present invention
  • FIG. 2 is a schematic structural view of a display panel of the present invention
  • FIG. 3 is a schematic diagram of forming a second buffer layer, an electrostatic shielding layer, a third buffer layer and a barrier layer on a substrate;
  • FIG. 4 is a schematic diagram of forming a first active layer semi-finished product and a Vss wiring semi-finished product on the barrier layer;
  • FIG. 5 is a schematic diagram of preparing a first metal thin film on a first insulating layer
  • FIG. 6 is a schematic diagram of forming a first capacitive electrode and a light-shielding unit by patterning the first metal thin film
  • FIG. 7 is a schematic diagram of forming a first capacitor medium on a first capacitor electrode, a light-shielding unit and a first insulating layer;
  • FIG. 8 is a schematic diagram of forming a second capacitor electrode semi-finished product and a second active layer semi-finished product on the first capacitor medium;
  • FIG. 9 is a schematic diagram of preparing a second insulating layer semi-finished product on the second capacitor electrode semi-finished product, the second active layer semi-finished product and the first capacitor medium, and preparing a second metal film on the second insulating layer semi-finished product;
  • Fig. 10 is a schematic diagram after etching the semi-finished product of the second insulating layer and the second metal film by using the photoresist pattern
  • Fig. 11 is a schematic diagram of depositing an aluminum layer on the basis of Fig. 10;
  • Fig. 12 is a schematic diagram after stripping and removing the photoresist and annealing the aluminum layer
  • Fig. 13 is a schematic diagram of forming an interlayer insulating layer on the basis of Fig. 12;
  • Fig. 14 is a schematic diagram of forming overlapping holes on the basis of Fig. 13;
  • FIG. 15 is a schematic diagram of forming the first source-drain layer, the second source-drain layer and the third capacitor electrode on the basis of FIG. 14 .
  • the first base 1012. The first buffer layer;
  • the second buffer layer 2. Electrostatic shielding layer;
  • Shading unit 10. The first capacitor medium;
  • the second capacitor electrode 12. The second active layer;
  • the second capacitor medium 16. Interlayer insulating layer;
  • the third capacitor electrode 18. The first source and drain layer;
  • the second source and drain layer 20. Passivation layer;
  • this embodiment provides a display panel 100 .
  • the display panel 100 includes a substrate 101 and a plurality of pixel units 102 disposed on the substrate 101 .
  • the pixel units 102 are arranged in an array.
  • each pixel unit 102 includes: a driving area 1021 and a switching area 1022 .
  • the substrate 101 is located in a driving area 1021 and a switching area 1022 .
  • the substrate 101 includes: a first base 1011 , a first buffer layer 1012 and a second base 1013 .
  • the material of the first substrate 1011 includes polyimide, polycarbonate, polyethylene terephthalate, polyethylene naphthalate and the like.
  • the first buffer layer 1012 is disposed on the first substrate 1011 .
  • the material of the first buffer layer 1012 may be SiOx or SiNx.
  • the first buffer layer 1012 may also be a multilayer thin film formed of SiOx and SiNx. In this way, the impact resistance of the substrate 101 is improved, thereby effectively protecting the display panel 100 .
  • the second base 1013 is disposed on the surface of the first buffer layer 1012 away from the first base 1011 .
  • the material of the second substrate 1013 includes polyimide, polycarbonate, polyethylene terephthalate, polyethylene naphthalate and the like.
  • each pixel unit 102 includes: a second buffer layer 1, an electrostatic shielding layer 2, a third buffer layer 3, a barrier layer 4, a first active layer 5, a Vss wiring 6, a first Insulating layer 7, first capacitive electrode 8, shading unit 9, first capacitive medium 10, second capacitive electrode 11, second active layer 12, second insulating layer 13, second gate 14, second capacitive medium 15 , an interlayer insulating layer 16 , a third capacitor electrode 17 , a first source-drain layer 18 , a second source-drain layer 19 , and a passivation layer 20 .
  • the second buffer layer 1 is disposed on the surface of the second substrate 1013 away from the first substrate 1011 , and is located in the driving area 1021 and the switching area 1022 .
  • the material of the second buffer layer 1 can be SiOx or SiNx.
  • the second buffer layer 1 may also be a multi-layer thin film formed of SiOx and SiNx.
  • the electrostatic shielding layer 2 is disposed on the surface of the second buffer layer 1 away from the substrate 101 and located in the driving area 1021 .
  • the material of the electrostatic shielding layer 2 may be a-Si. This prevents static electricity from damaging the driving thin film transistor.
  • the third buffer layer 3 is disposed on the surface of the electrostatic shielding layer 2 away from the substrate 101 , and extends to cover the second buffer layer 1 of the driving region 1021 and the switching region 1022 .
  • the material of the third buffer layer 3 may be SiOx or SiNx.
  • the third buffer layer 3 may also be a multilayer thin film formed of SiOx and SiNx.
  • the barrier layer 4 is disposed on the surface of the third buffer layer 3 away from the substrate 101 , and is located in the driving area 1021 and the switching area 1022 .
  • the barrier layer 4 is mainly used to prevent water vapor from intruding, thereby preventing water vapor from damaging the driving thin film transistor.
  • the material of the barrier layer 4 can be SiOx or SiNx.
  • the barrier layer 4 can also be a multilayer film formed of SiOx and SiNx.
  • the first active layer 5 is disposed on the surface of the barrier layer 4 away from the substrate 101 and located in the driving region 1021 .
  • the first active layer 5 includes a first channel portion 51 and two first connection portions 52 located at two ends of the first channel portion 51 .
  • the first channel portion 51 of the first active layer 5 is disposed corresponding to the electrostatic shielding layer 2 .
  • the Vss wiring 6 is set on the same layer as the first active layer 5 and is located in the driving region 1021 .
  • the material of the Vss wiring 6 is the same as that of the first active layer 5 , so it can be prepared and formed simultaneously with the first active layer 5 , saving production steps and improving production efficiency.
  • the Vss line 6 is mainly used to discharge the static electricity of the switching thin film transistor.
  • the first insulating layer 7 is disposed on the surface of the first active layer 5 and the Vss wiring 6 away from the substrate 101 , and extends to cover the barrier layer 4 .
  • the material of the first insulating layer 7 may be SiOx or SiNx.
  • the first insulating layer 7 may also be a multi-layer film formed of SiOx and SiNx. The thickness of the first insulating layer 7 ranges from 1000 angstroms to 3000 angstroms.
  • the first capacitive electrode 8 is disposed on the surface of the first insulating layer 7 away from the substrate 101 , and is disposed corresponding to the first channel portion 51 of the first active layer 5 .
  • the material of the first capacitor electrode 8 may be Mo, Al, Cu, Ti, etc., or an alloy.
  • the thickness of the first capacitive electrode 8 ranges from 2000 angstroms to 8000 angstroms.
  • the light-shielding unit 9 is disposed on the same layer as the first capacitive electrode 8 and is located in the switch area 1022 .
  • the material of the shading unit 9 is the same as that of the first capacitive electrode 8 , so it can be prepared and formed simultaneously with the first capacitive electrode 8 , which saves the production process and improves the production efficiency.
  • the first capacitive medium 10 is disposed on the surface of the first capacitive electrode 8 and the light-shielding unit 9 away from the substrate 101 , and extends to cover the first insulating layer 7 .
  • the material of the first capacitive medium 10 may be SiOx or SiNx.
  • the first capacitive medium 10 may also be a multilayer thin film formed of SiOx and SiNx. The thickness of the first capacitive medium 10 ranges from 1000 angstroms to 3000 angstroms.
  • the second capacitive electrode 11 is disposed on the surface of the first capacitive medium 10 away from the substrate 101 , and is disposed corresponding to the first capacitive electrode 8 .
  • the second capacitive electrode 11 is a metal oxide semiconductor, and its material can be IGZO, IZTO, IGZTO and the like.
  • the thickness of the second capacitive electrode 11 ranges from 100 angstroms to 1000 angstroms.
  • the second active layer 12 is disposed on the same layer as the second capacitive electrode 11 and is disposed corresponding to the light shielding unit 9 .
  • the material of the second active layer 12 is the same as that of the second capacitive electrode 11 , so it can be prepared and formed simultaneously with the second capacitive electrode 11 , which saves the production process and improves the production efficiency.
  • the second active layer 12 includes a second channel part 121 and two second connection parts 122 .
  • the second insulating layer 13 is disposed on the surface of the second active layer 12 away from the substrate 101 , and is disposed corresponding to the second channel portion 121 of the second active layer 12 .
  • the material of the second insulating layer 13 may be SiOx or SiNx.
  • the second insulating layer 13 may also be a multi-layer thin film formed of SiOx and SiNx. The thickness of the second insulating layer 13 ranges from 1000 angstroms to 3000 angstroms.
  • the second gate 14 is disposed on the surface of the second insulating layer 13 away from the substrate 101 , and is disposed corresponding to the second channel portion 121 of the second active layer 12 .
  • the material of the second grid 14 may be Mo, Al, Cu, Ti, etc., or an alloy.
  • the thickness of the second gate 14 ranges from 2000 angstroms to 8000 angstroms.
  • the second capacitive medium 15 is disposed on the surface of the second capacitive electrode 11 away from the substrate 101 , and extends to cover the first capacitive medium 10 .
  • the second capacitive medium 15 is partially covered on the two second connecting portions 122 of the second active layer 12; both sides of the second insulating layer 13 and the second capacitive medium 15 have gap.
  • the material of the second capacitor medium 15 is Al 2 O 3 . Since the dielectric constant of Al 2 O 3 is relatively high, the capacitance value of the storage capacitor can be increased, thereby satisfying the requirements of the display panel 100 for charging, discharging and maintaining charge capability.
  • the thickness of the second capacitor medium 15 ranges from 50 angstroms to 100 angstroms. In this embodiment, the thickness of the second capacitive medium 15 is 75 angstroms, and in other embodiments, the thickness of the second capacitive medium 15 may be 60 angstroms, 80 angstroms, or 90 angstroms. In this embodiment, the thickness of the second capacitive dielectric 15 formed with Al 2 O 3 is thinner than that of the insulating layer (1000 angstroms-3000 angstroms) formed by SiOx and SiNx in the prior art, which can improve The capacitance value of the storage capacitor further satisfies the requirements of the display panel 100 for charging, discharging and charge retention. At the same time, the overall thickness of the display panel 100 is reduced, thereby meeting the development requirements of ultra-thin display technology.
  • the interlayer insulating layer 16 is disposed on the surface of the second capacitive medium 15 away from the substrate 101 .
  • the material of the interlayer insulating layer 16 can be SiOx or SiNx, and can also be an organic material.
  • the thickness of the interlayer insulating layer 16 ranges from 2000 angstroms to 10000 angstroms.
  • the third capacitive electrode 17 is disposed on the surface of the interlayer insulating layer 16 away from the substrate 101 , and is disposed corresponding to the second capacitive electrode 11 .
  • the material of the third capacitive electrode 17 may be Mo, Al, Cu, Ti, etc., or an alloy.
  • the thickness of the third capacitive electrode 17 ranges from 2000 angstroms to 8000 angstroms.
  • the first source-drain layer 18 is provided on the same layer as the third capacitance electrode 17 , and is electrically connected to the two first connection portions 52 of the first active layer 5 .
  • the material of the first source-drain layer 18 is the same as that of the third capacitor electrode 17 , so it can be prepared and formed simultaneously with the third capacitor electrode 17 , which saves the production process and improves the production efficiency.
  • the second source-drain layer 19 is provided on the same layer as the third capacitor electrode 17 , electrically connected to the two second connection portions 122 of the second active layer 12 , and electrically connected to the Vss wiring 6 .
  • the material of the second source-drain layer 19 is the same as that of the third capacitor electrode 17 , so it can be prepared and formed simultaneously with the third capacitor electrode 17 , which saves the production process and improves the production efficiency.
  • the passivation layer 20 is disposed on the surface of the first source-drain layer 18 , the second source-drain layer 19 and the third capacitive electrode 17 away from the substrate 101 , and extends to cover the interlayer insulating layer 16 superior.
  • the electrode layer 18 together constitutes a driving thin film transistor.
  • the second active layer 12 , the second insulating layer 13 , the second gate 14 , the interlayer insulating layer 16 , and the second source-drain layer 19 together form a switch thin film transistor.
  • the first capacitor electrode 8 , the first capacitor medium 10 , the second capacitor electrode 11 , the second capacitor medium 15 , the interlayer insulating layer 16 , and the third capacitor electrode 17 together form a three-layer sandwich storage capacitor.
  • the storage capacitor in this embodiment has a larger capacitance.
  • the dielectric constant of the second capacitive medium in this embodiment is large and the thickness is thin, and the capacitance value of the storage capacitor can also be increased, thereby meeting the requirements of the display panel for charging and discharging and maintaining charge capabilities, and at the same time meeting the needs of ultra-high capacity.
  • the development needs of thin display technology are examples of thin display technology.
  • this embodiment also provides a method for manufacturing a display panel of this embodiment, which includes: providing a substrate 101, and preparing a plurality of pixel units 102 on the substrate 101, each of the Each pixel unit 102 includes: a driving area 1021 and a switching area 1022 .
  • each pixel unit 102 includes: S1, preparing the second buffer layer 1 on the substrate 101 of the driving area 1021 and the switching area 1022; S2, preparing the second buffer layer 1 on the second An electrostatic shielding layer 2 is prepared on the buffer layer 1; S3, a third buffer layer 3 is prepared on the electrostatic shielding layer 2 and the second buffer layer 1; S4, a barrier layer 4 is prepared on the third buffer layer 3.
  • the preparation step of each pixel unit 102 further includes: S5 , preparing the first active layer semi-finished product 23 and the Vss wiring semi-finished product 24 on the barrier layer 4 .
  • S5 specifically includes: depositing a layer of low-temperature polysilicon (LTPS) on the barrier layer 4 , and patterning it to form the first active layer semi-finished product 23 and the Vss wiring semi-finished product 24 .
  • the first active layer semi-finished product 23 and the Vss wiring semi-finished product 24 are prepared and formed at the same time, so that the production process can be saved and the production efficiency can be improved.
  • LTPS low-temperature polysilicon
  • the preparation step of each pixel unit 102 further includes: S6 , preparing the first insulating layer 7 on the first active layer semi-finished product 23 , the Vss wiring semi-finished product 24 and the barrier layer 4 . S7 , preparing the first capacitive electrode 8 and the light shielding unit 9 on the first insulating layer 7 .
  • S7 specifically includes: preparing the first metal film 25 on the entire surface of the first insulating layer 7, and then patterning the first metal film 25 to form the first capacitive electrode 8 and the light-shielding unit 9. Divide the first active layer semi-finished product 23 corresponding to the first capacitive electrode 8 into the first channel portion 51, and divide the first active layer semi-finished product 23 not corresponding to the first capacitive electrode 8 into the first channel portion 51. Connecting semi-finished products. Doping the semi-finished product of the first connection portion forms the first connection portion 52 , and doping the semi-finished product 24 of the Vss line to form the Vss line 6 .
  • the preparation step of each pixel unit 102 further includes: S8 , preparing the first capacitor medium 10 on the first capacitor electrode 8 , the light shielding unit 9 and the first insulating layer 7 .
  • the preparation step of each pixel unit 102 further includes: S9 , forming a second capacitive electrode semi-finished product 26 and a second active layer semi-finished product 27 on the first capacitive medium 10 .
  • the second capacitive electrode semi-finished product 26 and the second active layer semi-finished product 27 are prepared at the same time, thereby saving production steps and improving production efficiency.
  • the material of the second capacitive electrode semi-finished product 26 and the second active layer semi-finished product 27 can be IGZO, IZTO, IGZTO and the like.
  • each pixel unit 102 further includes: S10, forming a second insulating layer semi-finished product 28 on the second capacitor electrode semi-finished product 26, the second active layer semi-finished product 27 and the first capacitor medium 10 .
  • the preparation step of each pixel unit 102 further includes: S11 , preparing the second gate 14 on the second insulating layer semi-finished product 28 .
  • S11 specifically includes: preparing a second metal film 29 on the second insulating layer semi-finished product 28, then coating a layer of photoresist on the entire surface of the second metal film 29, and then patterning the entire surface of the photoresist to retain part of the light. Form the photoresist pattern 21, then etch the second metal film 29 not covered by the photoresist pattern 21 to form the second gate 14, and etch the second insulating layer semi-finished product 28 not covered by the photoresist pattern 21 The second insulating layer 13 is formed.
  • the preparation step of each pixel unit 102 further includes: S12, retain the photoresist pattern 21, and prepare on the second capacitive electrode semi-finished product 26, part of the second active layer semi-finished product 27, and the photoresist pattern 21
  • Aluminum layer 22 partially covers the second active layer semi-finished product 27 and has gaps with the second insulating layer 13 and the second gate 14 .
  • the main purpose is to disconnect the aluminum layer on the photoresist pattern 21 from the aluminum layer 22 on the second active layer semi-finished product 27 , so as to ensure that the aluminum layer on the photoresist pattern 21 can be removed by stripping the photoresist pattern 21 later. It can also be used to prevent the short circuit between the aluminum layer 22 and the second gate 14 .
  • each pixel unit 102 further include: S13, stripping and removing the photoresist pattern 21, annealing the aluminum layer 22, and the aluminum layer 22 and the second capacitive electrode semi-finished product 26 covered thereunder.
  • the O in the material is combined to form Al 2 O 3 , that is, the second capacitor medium 15, and at the same time, the second capacitor electrode semi-finished product is conductorized to become the second capacitor electrode 11; the aluminum layer 22 and the part of the second active layer semi-finished product 27 covered thereunder
  • the O in the material is combined to form Al 2 O 3 , that is, the second capacitor medium 15, and at the same time, the part of the second active layer semi-finished product 27 covered by the aluminum layer 22 is conductorized to become the second connection part 122;
  • the second active layer semi-finished product 27 maintains semiconductor properties to form the second channel portion 121 .
  • each pixel unit 102 further includes: S14, at the gap between the second capacitor medium 15 , the second gate 14 and the second capacitor medium 15 and the second insulating layer 13 An interlayer insulating layer 16 is prepared.
  • the preparation step of each pixel unit 102 further includes: S15, engraving the interlayer insulating layer 16, the second capacitor medium 15, the first capacitor medium 10, and the first insulating layer 7 A plurality of overlapping holes 30 are formed by etching.
  • the preparation step of each pixel unit 102 further includes: S16, preparing the third capacitance electrode 17, the first source and drain layer 18 and the first Two source and drain layers 19 .
  • the first source-drain layer 18 , the second source-drain layer 19 and the third capacitive electrode 17 are formed at the same time, thereby saving production steps and improving production efficiency.
  • each pixel unit 102 further includes: S17, on the third capacitor electrode 17 , the first source-drain layer 18 , the second source-drain layer 19 and the interlayer insulating layer 16 A passivation layer 20 is prepared.

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Abstract

一种显示面板（100）及其制备方法，显示面板（100）包括存储电容；存储电容包括：第一电容电极（8）、第一电容介质（10）、第二电容电极（11）、第二电容介质（15）、层间绝缘层（16）以及第三电容电极（17）。由于第二电容介质（15）的厚度较薄，且第二电容介质（15）的介电常数较高，因此可以提升整个存储电容的电容值，满足显示面板（100）的充放电及保持电荷能力的需求。

Description

一种显示面板及其制备方法 技术领域
本申请涉及显示技术领域，具体涉及一种显示面板及其制备方法。
 背景技术
OLED (英文全称：Organic Light-Emitting Diode，中文：有机发光显示装置)又称为有机电激光显示装置、有机发光半导体器件。OLED凭借电压需求低、省电效率高、重量轻、厚度薄、构造简单、成本低、广视角、几乎无穷高的对比度、较低耗电、极高反应速度等诸多优势，已经成为当今最重要的显示技术之一。目前的OLED一般采用LTPO（英文全称：Low Temperature Polycrystalline Oxide，中文：低温多晶氧化物）基板。LTPO基板包含IGZO（英文全称：Indium Gallium Zinc Oxide，中文：铟镓锌氧化物）TFT（英文全称：Thin Film Transistor，中文：薄膜晶体管）和LTPS（Low Temperature Poly-Silicon，低温多晶硅）TFT两种TFT结构。
 技术问题
目前，一般采用LTPS TFT的栅极作为存储电容的第一电容电极，然后在第一电容电极上设置电容介质，然后在电容介质上设置第二栅极作为存储电容的第二电容电极。目前的电容介质的厚度范围为1000埃-3000埃，电容介质的厚度较大；目前的电容介质的材质一般为SiOx或SiNx，其介电常数较小，由此形成的存储电容的电容值较小，无法满足显示面板的充放电及保持电荷能力的需求。
目前，一般在定义存储电容的第二电容电极（第二栅极）的同时，还定义出IGZO TFT的遮光单元，然后在第二电容电极上设置绝缘层，然后在绝缘层上定义出IGZO TFT。因此，目前的LTPO基板需要三张栅极掩膜板（LTPS TFT的栅极、存储电容的第二电容电极以及IGZO TFT的栅极），制备工艺繁琐。目前第二电容电极上的绝缘层的厚度范围为2000埃-10000埃，其厚度较厚，导致LTPO基板的膜厚较厚，无法满足超薄显示技术的开发需求。
 技术解决方案
本发明的目的是提供一种显示面板及其制备方法，其能够解决现有显示面板中存在的存储电容的电容值较小无法满足显示面板的充放电及保持电荷能力的需求、膜厚较厚无法满足超薄显示技术的开发需求等问题。
为了解决上述问题，本发明提供了一种显示面板，其包括基板及设置于所述基板上的多个像素单元；每一所述像素单元均包括：驱动区和开关区；每一所述像素单元均包括：存储电容，位于所述驱动区，其包括：第一电容电极，设置于所述驱动区的所述基板上；第一电容介质，设置于所述第一电容电极远离所述基板的一侧的表面上，且延伸覆盖于所述基板上；第二电容电极，设置于所述第一电容介质远离所述基板的一侧的表面上，且与所述第一电容电极对应设置；第二电容介质，设置于所述第二电容电极远离所述基板的一侧的表面上，且延伸覆盖于所述第一电容介质上；层间绝缘层，设置于所述第二电容介质远离所述基板的一侧的表面上；以及第三电容电极，设置于所述层间绝缘层远离所述基板的一侧的表面上，且与所述第二电容电极对应设置。
进一步的，每一所述像素单元均包括：驱动薄膜晶体管，位于所述驱动区，其包括：第一有源层，设置于所述基板与所述第一电容电极之间；第一绝缘层，设置于所述第一有源层与所述第一电容电极之间，且延伸覆盖于所述基板上；第一栅极，与所述第一电容电极为同一膜层；以及第一源漏极层，设置于所述层间绝缘层远离所述基板的一侧的表面上，且与所述第三电容电极同层设置。
进一步的，每一所述像素单元均包括：开关薄膜晶体管，位于所述开关区，其包括：第二有源层，设置于所述第一电容介质与所述层间绝缘层之间，且与所述第二电容电极同层设置；第二绝缘层，设置于所述第二有源层与所述层间绝缘层之间；第二栅极，设置于所述第二绝缘层与所述层间绝缘层之间；第二源漏极层，设置于所述层间绝缘层远离所述基板的一侧的表面上，且与所述第三电容电极同层设置。
进一步的，每一所述像素单元还包括：遮光单元，设置于所述第一绝缘层与所述第一电容介质之间，且与所述第二有源层对应设置，且与所述第一电容电极同层设置。
进一步的，所述第二电容介质部分覆盖于所述第二有源层上；所述第二绝缘层的两侧与所述第二电容介质之间均具有间隙。
进一步的，所述第二电容介质的材质为Al 2O 3。
进一步的，所述第二电容介质的厚度范围为50埃-100埃。
为了解决上述问题，本发明还提供了一种显示面板的制备方法，其包括以下步骤：提供一基板，在所述基板上制备多个像素单元，每一所述像素单元均包括：驱动区和开关区；每一所述像素单元的制备步骤包括：在所述驱动区制备存储电容，其包括：在所述驱动区的所述基板上制备第一电容电极；在所述第一电容电极远离所述基板的一侧的表面上制备第一电容介质，所述第一电容介质延伸覆盖于所述基板上；在所述第一电容介质远离所述基板的一侧的表面上制备第二电容电极，所述第二电容电极与所述第一电容电极对应设置；在所述第二电容电极远离所述基板的一侧的表面上制备第二电容介质，所述第二电容介质延伸覆盖于所述第一电容介质上；在所述第二电容介质远离所述基板的一侧的表面上制备层间绝缘层；以及在所述层间绝缘层远离所述基板的一侧的表面上制备第三电容电极，所述第三电容电极与所述第二电容电极对应设置。
进一步的，在在所述第一电容电极远离所述基板的一侧的表面上制备第一电容介质的步骤之前还包括以下步骤：在所述开关区的所述基板上制备遮光单元；所述遮光单元与所述第一电容电极同时制备形成。
进一步的，在在所述第二电容电极远离所述基板的一侧的表面上制备第二电容介质的步骤之前还包括以下步骤：在所述第一电容介质远离所述基板的一侧的表面上制备第二有源层；所述第二有源层与所述第二电容电极同时制备形成；在所述第二有源层远离所述基板的一侧的表面上制备第二绝缘层；以及在所述第二绝缘层远离所述基板的一侧的表面上制备第二栅极。
 有益效果
相较于现有技术，本申请制备驱动薄膜晶体管的第一栅极的同时形成遮光单元，在形成开关薄膜晶体管的第二有源层的同时，形成存储电容的第二电容电极，在形成驱动薄膜晶体管的第一源漏极层的同时形成存储电容的第三电容电极，由此可以节省一张栅极掩膜板，提高生产效率，节约生产成本。本发明采用第一电容电极、第一电容介质、第二电容电极、第二电容介质以及第三电容电极形成夹心电容，由于第二电容介质的厚度较薄，且第二电容介质的介电常数较高，因此可以提升整个存储电容的电容值，进而满足显示面板的充放电及保持电荷能力的需求。同时，第二电容介质的厚度较薄，可以降低显示面板的厚度，进而满足超薄显示技术的开发需求。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明的显示面板的平面示意图；
图2是本发明的显示面板的结构示意图；
图3是在基板上形成第二缓冲层、静电屏蔽层、第三缓冲层以及阻隔层的示意图；
图4是在阻隔层上形成第一有源层半成品以及Vss走线半成品的示意图；
图5是在第一绝缘层上制备第一金属薄膜的示意图；
图6是对第一金属薄膜图形化处理形成第一电容电极和遮光单元的示意图；
图7是在第一电容电极、遮光单元以及第一绝缘层上形成第一电容介质的示意图；
图8是在第一电容介质上形成第二电容电极半成品和第二有源层半成品的示意图；
图9是在第二电容电极半成品、第二有源层半成品以及第一电容介质上制备第二绝缘层半成品，在第二绝缘层半成品上制备第二金属薄膜的示意图；
图10是利用光阻图案对第二绝缘层半成品和第二金属薄膜进行刻蚀后的示意图；
图11是在图10的基础上沉积铝层的示意图；
图12是剥离去除光阻，对铝层进行退火处理后的示意图；
图13是在图12的基础上形成层间绝缘层的示意图；
图14是在图13的基础上形成搭接孔的示意图；
图15是在图14的基础上形成第一源漏极层、第二源漏极层以及第三电容电极的示意图。
附图标记说明：
100、显示面板；                     101、基板；
102、像素单元；
1011、第一基底；                    1012、第一缓冲层；
1013、第二基底；
1021、驱动区；                      1022、开关区；
1、第二缓冲层；                     2、静电屏蔽层；
3、第三缓冲层；                     4、阻隔层；
5、第一有源层；                     6、Vss走线；
7、第一绝缘层；                     8、第一电容电极；
9、遮光单元；                       10、第一电容介质；
11、第二电容电极；                  12、第二有源层；
13、第二绝缘层；                    14、第二栅极；
15、第二电容介质；                  16、层间绝缘层；
17、第三电容电极；                  18、第一源漏极层；
19、第二源漏极层；                  20、钝化层；
21、光阻图案；                      22、铝层；
23、第一有源层半成品；              24、Vss走线半成品；
25、第一金属薄膜；                  26、第二电容电极半成品；
27、第二有源层半成品；              28、第二绝缘层半成品；
29、第二金属薄膜；                  30、搭接孔；
51、第一沟道部；                    52、第一连接部；
121、第二沟道部；                   122、第二连接部。
 本发明的实施方式
以下结合说明书附图详细说明本发明的优选实施例，以向本领域中的技术人员完整介绍本发明的技术内容，以举例证明本发明可以实施，使得本发明公开的技术内容更加清楚，使得本领域的技术人员更容易理解如何实施本发明。然而本发明可以通过许多不同形式的实施例来得以体现，本发明的保护范围并非仅限于文中提到的实施例，下文实施例的说明并非用来限制本发明的范围。
本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是附图中的方向，本文所使用的方向用语是用来解释和说明本发明，而不是用来限定本发明的保护范围。
在附图中，结构相同的部件以相同数字标号表示，各处结构或功能相似的组件以相似数字标号表示。此外，为了便于理解和描述，附图所示的每一组件的尺寸和厚度是任意示出的，本发明并没有限定每个组件的尺寸和厚度。
如图1所示，本实施例提供了一种显示面板100。显示面板100包括基板101以及设置于所述基板101上的多个像素单元102。本实施例中，所述像素单元102呈阵列式排布。
如图2所示，每一所述像素单元102均包括：驱动区1021和开关区1022。
如图2所示，基板101位于驱动区1021和开关区1022。基板101包括：第一基底1011、第一缓冲层1012以及第二基底1013。
其中，第一基底1011的材质包括聚酰亚胺、聚碳酸酯、聚对苯二甲酸乙二醇酯以及聚萘二甲酸乙二醇酯等。
其中，第一缓冲层1012设置于所述第一基底1011上。第一缓冲层1012的材质可以是SiOx，也可以是SiNx。第一缓冲层1012也可以是SiOx与SiNx形成的多层结构薄膜。由此提升基板101的抗冲击能力，进而有效保护显示面板100。
其中，第二基底1013设置于第一缓冲层1012远离第一基底1011的一侧的表面上。第二基底1013的材质均包括聚酰亚胺、聚碳酸酯、聚对苯二甲酸乙二醇酯以及聚萘二甲酸乙二醇酯等。
如图2所示，每一所述像素单元102包括：第二缓冲层1、静电屏蔽层2、第三缓冲层3、阻隔层4、第一有源层5、Vss走线6、第一绝缘层7、第一电容电极8、遮光单元9、第一电容介质10、第二电容电极11、第二有源层12、第二绝缘层13、第二栅极14、第二电容介质15、层间绝缘层16、第三电容电极17、第一源漏极层18、第二源漏极层19、钝化层20。
如图2所示，第二缓冲层1设置于第二基底1013远离所述第一基底1011的一侧的表面上，且位于驱动区1021和开关区1022。第二缓冲层1的材质可以是SiOx，也可以是SiNx。第二缓冲层1也可以是SiOx与SiNx形成的多层结构薄膜。
如图2所示，静电屏蔽层2设置于第二缓冲层1远离所述基板101的一侧的表面上，且位于驱动区1021。静电屏蔽层2的材质可以是a-Si。由此防止静电对驱动薄膜晶体管造成损伤。
如图2所示，第三缓冲层3设置于静电屏蔽层2远离所述基板101的一侧的表面上，且延伸覆盖于驱动区1021和开关区1022的第二缓冲层1上。第三缓冲层3的材质可以是SiOx，也可以是SiNx。第三缓冲层3也可以是SiOx与SiNx形成的多层结构薄膜。
如图2所示，阻隔层4设置于第三缓冲层3远离所述基板101的一侧的表面上，且位于驱动区1021和开关区1022。阻隔层4主要用于防止水汽入侵，进而避免水汽对驱动薄膜晶体管造成损伤。阻隔层4的材质可以是SiOx，也可以是SiNx。阻隔层4也可以是SiOx与SiNx形成的多层结构薄膜。
如图2所示，第一有源层5设置于阻隔层4远离所述基板101的一侧的表面上，且位于驱动区1021。所述第一有源层5包括第一沟道部51和位于第一沟道部51两端的两个第一连接部52。
其中，第一有源层5的第一沟道部51与静电屏蔽层2对应设置。
其中，Vss走线6与第一有源层5同层设置，且位于驱动区1021。本实施例中，Vss走线6的材质与第一有源层5的材质相同，由此可以与第一有源层5同时制备形成，节省生产工序，提升生产效率。Vss走线6主要用于释放开关薄膜晶体管的静电。
其中，第一绝缘层7设置于第一有源层5及Vss走线6远离基板101的一侧的表面上，且延伸覆盖于阻隔层4上。第一绝缘层7的材质可以是SiOx，也可以是SiNx。第一绝缘层7也可以是SiOx与SiNx形成的多层结构薄膜。第一绝缘层7的厚度范围为1000埃-3000埃。
其中，第一电容电极8设置于所述第一绝缘层7远离基板101的一侧的表面上，且与第一有源层5的第一沟道部51对应设置。第一电容电极8的材质可以是Mo，Al，Cu，Ti等，也可以是合金。第一电容电极8的厚度范围为2000埃-8000埃。
其中，遮光单元9与第一电容电极8同层设置，且位于开关区1022。本实施例中，遮光单元9的材质与第一电容电极8的材质相同，由此可以与第一电容电极8同时制备形成，节省生产工序，提升生产效率。
其中，第一电容介质10设置于所述第一电容电极8及遮光单元9远离所述基板101的一侧的表面上，且延伸覆盖于所述第一绝缘层7上。第一电容介质10的材质可以是SiOx，也可以是SiNx。第一电容介质10也可以是SiOx与SiNx形成的多层结构薄膜。第一电容介质10的厚度范围为1000埃-3000埃。
其中，第二电容电极11设置于第一电容介质10远离所述基板101的一侧的表面上，且与第一电容电极8对应设置。第二电容电极11为金属氧化物半导体，其材质可以是IGZO、IZTO、IGZTO等。第二电容电极11的厚度范围为100埃-1000埃。
其中，第二有源层12与第二电容电极11同层设置，且与所述遮光单元9对应设置。本实施例中，第二有源层12的材质与第二电容电极11的材质相同，由此可以与第二电容电极11同时制备形成，节省生产工序，提升生产效率。第二有源层12包括第二沟道部121和两个第二连接部122。
其中，第二绝缘层13设置于第二有源层12远离所述基板101的一侧的表面上，且与所述第二有源层12的第二沟道部121对应设置。第二绝缘层13的材质可以是SiOx，也可以是SiNx。第二绝缘层13也可以是SiOx与SiNx形成的多层结构薄膜。第二绝缘层13的厚度范围为1000埃-3000埃。
其中，第二栅极14设置于第二绝缘层13远离所述基板101的一侧的表面上，且与所述第二有源层12的第二沟道部121对应设置。第二栅极14的材质可以是Mo，Al，Cu，Ti等，也可以是合金。第二栅极14的厚度范围为2000埃-8000埃。
其中，第二电容介质15设置于所述第二电容电极11远离所述基板101的一侧的表面上，且延伸覆盖于所述第一电容介质10上。所述第二电容介质15部分覆盖于所述第二有源层12的两个第二连接部122上；所述第二绝缘层13的两侧与所述第二电容介质15之间均具有间隙。
其中，第二电容介质15的材质为Al 2O 3。由于Al 2O 3的介电常数较高，由此可以提升存储电容的电容值，进而满足显示面板100的充放电及保持电荷能力的需求。
其中，第二电容介质15的厚度范围为50埃-100埃。本实施例中，所述第二电容介质15的厚度为75埃，其他实施例中，所述第二电容介质15的厚度可以为60埃、80埃、90埃。本实施例中用Al 2O 3形成的第二电容介质15的厚度相较于现有技术中采用SiOx与SiNx形成的绝缘层（1000埃-3000埃）的厚度减薄了，由此可以提升存储电容的电容值进而满足显示面板100的充放电及保持电荷能力的需求。同时，降低了显示面板100的整体厚度，进而可以满足超薄显示技术的开发需求。
其中，层间绝缘层16设置于第二电容介质15远离所述基板101的一侧的表面上。层间绝缘层16的材质可以是SiOx或SiNx，还可以是有机材料。层间绝缘层16的厚度范围为2000埃-10000埃。
其中，第三电容电极17设置于层间绝缘层16远离所述基板101的一侧的表面上，且与第二电容电极11对应设置。第三电容电极17的材质可以是Mo，Al，Cu，Ti等，也可以是合金。第三电容电极17的厚度范围为2000埃-8000埃。
其中，第一源漏极层18与所述第三电容电极17同层设置，电连接于所述第一有源层5的两个第一连接部52。本实施例中，第一源漏极层18的材质与第三电容电极17的材质相同，由此可以与第三电容电极17同时制备形成，节省生产工序，提升生产效率。
其中，第二源漏极层19与所述第三电容电极17同层设置，电连接于所述第二有源层12的两个第二连接部122，且电连接至Vss走线6。本实施例中，第二源漏极层19的材质与第三电容电极17的材质相同，由此可以与第三电容电极17同时制备形成，节省生产工序，提升生产效率。
其中，钝化层20设置于第一源漏极层18、第二源漏极层19以及第三电容电极17远离所述基板101的一侧的表面上，且延伸覆盖于层间绝缘层16上。
综上，第一有源层5、第一绝缘层7、第一电容电极（第一栅极）8、第一电容介质10、第二电容介质15、层间绝缘层16、第一源漏极层18共同组成驱动薄膜晶体管。
综上，第二有源层12、第二绝缘层13、第二栅极14、层间绝缘层16、第二源漏极层19共同组成开关薄膜晶体管。
综上，第一电容电极8、第一电容介质10、第二电容电极11、第二电容介质15、层间绝缘层16、第三电容电极17共同形成三层夹心的存储电容。相较于现有技术中的两极板电容，本实施例的存储电容的电容值大。而且，本实施例中的第二电容介质的介电常数大，厚度薄，也可以增大存储电容的电容值，由此可以满足显示面板的充放电及保持电荷能力的需求，同时可以满足超薄显示技术的开发需求。
如图3-图15所示，本实施例还提供了本实施例的显示面板的制备方法，其包括：提供一基板101，在所述基板101上制备多个像素单元102，每一所述像素单元102均包括：驱动区1021和开关区1022。
如图3所示，每一所述像素单元102的制备步骤包括：S1，在所述驱动区1021和开关区1022的基板101上制备第二缓冲层1；S2，在驱动区1021的第二缓冲层1上制备静电屏蔽层2；S3，在静电屏蔽层2以及第二缓冲层1上制备第三缓冲层3；S4，在第三缓冲层3上制备阻隔层4。
如图4所示，每一所述像素单元102的制备步骤还包括：S5，在阻隔层4上制备第一有源层半成品23以及Vss走线半成品24。S5具体包括：在阻隔层4上沉积一层低温多晶硅（LTPS），并对其进行图形化处理，形成第一有源层半成品23以及Vss走线半成品24。所述第一有源层半成品23以及Vss走线半成品24同时制备形成，由此可以节省生产工序，提升生产效率。
如图5、图6所示，每一所述像素单元102的制备步骤还包括：S6，在第一有源层半成品23、Vss走线半成品24以及阻隔层4上制备第一绝缘层7。S7，在第一绝缘层7上制备第一电容电极8以及遮光单元9。
如图5、图6所示，S7具体包括：在第一绝缘层7上整面制备第一金属薄膜25，然后对第一金属薄膜25进行图形化处理，形成第一电容电极8和遮光单元9。将与所述第一电容电极8对应的第一有源层半成品23分为第一沟道部51，将没有与所述第一电容电极8对应的第一有源层半成品23分为第一连接部半成品。对第一连接部半成品进行掺杂形成第一连接部52，对Vss走线半成品24进行掺杂形成Vss走线6。
如图7所示，每一所述像素单元102的制备步骤还包括：S8，在第一电容电极8、遮光单元9以及第一绝缘层7上制备第一电容介质10。
如图8所示，每一所述像素单元102的制备步骤还包括：S9，在第一电容介质10上形成第二电容电极半成品26和第二有源层半成品27。所述第二电容电极半成品26和第二有源层半成品27同时制备形成，由此可以节省生产工序，提升生产效率。第二电容电极半成品26和第二有源层半成品27的材质可以是IGZO、IZTO、IGZTO等。
如图9所示，每一所述像素单元102的制备步骤还包括：S10，在第二电容电极半成品26、第二有源层半成品27以及第一电容介质10上形成第二绝缘层半成品28。
如图9、图10所示，每一所述像素单元102的制备步骤还包括：S11，在第二绝缘层半成品28上制备第二栅极14。S11具体包括：在第二绝缘层半成品28上制备第二金属薄膜29，然后在第二金属薄膜29上整面涂布一层光阻，然后对整面光阻进行图案化处理，保留部分光阻形成光阻图案21，然后对未被光阻图案21覆盖的第二金属薄膜29进行刻蚀形成第二栅极14，对未被光阻图案21覆盖的第二绝缘层半成品28进行刻蚀形成第二绝缘层13。
如图11所示，每一所述像素单元102的制备步骤还包括：S12，保留光阻图案21，在第二电容电极半成品26、部分第二有源层半成品27、光阻图案21上制备铝层22。铝层22部分覆盖第二有源层半成品27，且与第二绝缘层13和第二栅极14之间具有间隙。主要是为了使得光阻图案21上的铝层与第二有源层半成品27上的铝层22断开，进而保证后期剥离光阻图案21可以将光阻图案21上面的铝层去除。还可以用于防止铝层22和第二栅极14之间接触发生短路现象。
如图12所示，每一所述像素单元102的制备步骤还包括：S13，剥离去除光阻图案21，对铝层22进行退火处理，铝层22与其下覆盖的第二电容电极半成品26的材料中的O结合形成Al 2O 3，即第二电容介质15，同时将第二电容电极半成品导体化变成第二电容电极11；铝层22与其下覆盖的部分第二有源层半成品27的材料中的O结合形成Al 2O 3，即第二电容介质15，同时将铝层22覆盖的部分第二有源层半成品27导体化变成第二连接部122；其余没有被导体化的第二有源层半成品27保持半导体特性形成第二沟道部121。
如图13所示，每一所述像素单元102的制备步骤还包括：S14，在第二电容介质15、第二栅极14以及第二电容介质15与第二绝缘层13之间的间隙处制备层间绝缘层16。
如图14所示，每一所述像素单元102的制备步骤还包括：S15，对所述层间绝缘层16、第二电容介质15、第一电容介质10、以及第一绝缘层7进行刻蚀形成多个搭接孔30。
如图15所示，每一所述像素单元102的制备步骤还包括：S16，在层间绝缘层16上以及搭接孔30内制备第三电容电极17、第一源漏极层18以及第二源漏极层19。所述第一源漏极层18、第二源漏极层19以及第三电容电极17同时制备形成，由此可以节省生产工序，提升生产效率。
如图1所示，每一所述像素单元102的制备步骤还包括：S17，在第三电容电极17、第一源漏极层18、第二源漏极层19以及层间绝缘层16上制备钝化层20。
以上对本申请所提供的一种显示面板及其制备方法进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (10)

  1. 一种显示面板，包括基板及设置于所述基板上的多个像素单元；每一所述像素单元均包括：驱动区和开关区；
    每一所述像素单元均包括：
    存储电容，位于所述驱动区，其包括：
    第一电容电极，设置于所述驱动区的所述基板上；
    第一电容介质，设置于所述第一电容电极远离所述基板的一侧的表面上，且延伸覆盖于所述基板上；
    第二电容电极，设置于所述第一电容介质远离所述基板的一侧的表面上，且与所述第一电容电极对应设置；
    第二电容介质，设置于所述第二电容电极远离所述基板的一侧的表面上，且延伸覆盖于所述第一电容介质上；
    层间绝缘层，设置于所述第二电容介质远离所述基板的一侧的表面上；以及
    第三电容电极，设置于所述层间绝缘层远离所述基板的一侧的表面上，且与所述第二电容电极对应设置。
  2. 根据权利要求1所述的显示面板，每一所述像素单元均包括：
    驱动薄膜晶体管，位于所述驱动区，其包括：
    第一有源层，设置于所述基板与所述第一电容电极之间；
    第一绝缘层，设置于所述第一有源层与所述第一电容电极之间，且延伸覆盖于所述基板上；
    第一栅极，与所述第一电容电极为同一膜层；以及
    第一源漏极层，设置于所述层间绝缘层远离所述基板的一侧的表面上，且与所述第三电容电极同层设置。
  3. 根据权利要求2所述的显示面板，每一所述像素单元均包括：
    开关薄膜晶体管，位于所述开关区，其包括：
    第二有源层，设置于所述第一电容介质与所述层间绝缘层之间，且与所述第二电容电极同层设置；
    第二绝缘层，设置于所述第二有源层与所述层间绝缘层之间；
    第二栅极，设置于所述第二绝缘层与所述层间绝缘层之间；
    第二源漏极层，设置于所述层间绝缘层远离所述基板的一侧的表面上，且与所述第三电容电极同层设置。
  4. 根据权利要求3所述的显示面板，每一所述像素单元还包括：
    遮光单元，设置于所述第一绝缘层与所述第一电容介质之间，且与所述第二有源层对应设置，且与所述第一电容电极同层设置。
  5. 根据权利要求3所述的显示面板，所述第二电容介质部分覆盖于所述第二有源层上；
    所述第二绝缘层的两侧与所述第二电容介质之间均具有间隙。
  6. 根据权利要求1所述的显示面板，所述第二电容介质的材质为Al 2O 3。
  7. 根据权利要求1所述的显示面板，所述第二电容介质的厚度范围为50埃-100埃。
  8. 一种显示面板的制备方法，包括以下步骤：
    提供一基板，在所述基板上制备多个像素单元，每一所述像素单元均包括：驱动区和开关区；
    每一所述像素单元的制备步骤包括：
    在所述驱动区制备存储电容，其包括：
    在所述驱动区的所述基板上制备第一电容电极；
    在所述第一电容电极远离所述基板的一侧的表面上制备第一电容介质，所述第一电容介质延伸覆盖于所述基板上；
    在所述第一电容介质远离所述基板的一侧的表面上制备第二电容电极，所述第二电容电极与所述第一电容电极对应设置；
    在所述第二电容电极远离所述基板的一侧的表面上制备第二电容介质，所述第二电容介质延伸覆盖于所述第一电容介质上；
    在所述第二电容介质远离所述基板的一侧的表面上制备层间绝缘层；以及
    在所述层间绝缘层远离所述基板的一侧的表面上制备第三电容电极，所述第三电容电极与所述第二电容电极对应设置。
  9. 根据权利要求8所述的显示面板的制备方法，在在所述第一电容电极远离所述基板的一侧的表面上制备第一电容介质的步骤之前还包括以下步骤：
    在所述开关区的所述基板上制备遮光单元；
    所述遮光单元与所述第一电容电极同时制备形成。
  10. 根据权利要求8所述的显示面板的制备方法，在在所述第二电容电极远离所述基板的一侧的表面上制备第二电容介质的步骤之前还包括以下步骤：
    在所述第一电容介质远离所述基板的一侧的表面上制备第二有源层；所述第二有源层与所述第二电容电极同时制备形成；
    在所述第二有源层远离所述基板的一侧的表面上制备第二绝缘层；以及
    在所述第二绝缘层远离所述基板的一侧的表面上制备第二栅极。
PCT/CN2021/139032 2021-12-10 2021-12-17 一种显示面板及其制备方法 WO2023103031A1 (zh)

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