WO2023097973A1 - 硅片及其制备方法和太阳能电池 - Google Patents

硅片及其制备方法和太阳能电池 Download PDF

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WO2023097973A1
WO2023097973A1 PCT/CN2022/092275 CN2022092275W WO2023097973A1 WO 2023097973 A1 WO2023097973 A1 WO 2023097973A1 CN 2022092275 W CN2022092275 W CN 2022092275W WO 2023097973 A1 WO2023097973 A1 WO 2023097973A1
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silicon wafer
line
uneven
uneven structure
parameters
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English (en)
French (fr)
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赵赞良
谢君霞
刘世科
王肖肖
李卫东
任金龙
孙惠
周硕
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宁夏隆基乐叶科技有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0236—Special surface textures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

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  • the invention belongs to the technical field of solar cells, and in particular relates to a silicon wafer, a preparation method thereof and a solar cell.
  • the current technology is to first cut the silicon wafer into a flat surface, and then use the low-concentration lye to polish the silicon wafer in a low-alkali concentration (NaOH or KOH and H 2 O) high-temperature tank through the texturing process.
  • a low-alkali concentration NaOH or KOH and H 2 O
  • the height of the pyramid is increased , It is difficult to etch and polish the backside, and the pyramid is not clean, which affects the passivation effect, resulting in serious recombination, and the etching needs to increase longitudinal corrosion, and the amount of HF increases more.
  • the present invention aims to solve one of the technical problems in the related art at least to a certain extent.
  • the object of the present invention is to propose a kind of silicon chip and its preparation method and solar cell.
  • the invention provides a silicon wafer.
  • the surface of the silicon chip has an uneven structure, and the surface of the uneven structure is provided with a suede.
  • the specific surface area of the silicon chip surface is increased by setting the uneven line mark surface on the silicon chip surface, and then a suede surface is set on the undulating line mark surface, thereby making the silicon chip pyramid
  • the number increases, and the specific surface of the silicon chip with textured surface increases by 21%-66% (compared with the flat silicon chip surface).
  • the silicon chip with textured surface Based on the silicon chip substrate per unit area, the silicon chip with textured surface The number of pyramids on the surface increases to 931,800-1,195,600/mm 2 (while the number of pyramids per unit area on a flat silicon wafer surface in the prior art is only 800,000/mm 2 ), thereby improving the solar cell
  • the short-circuit current increases the light conversion efficiency of the solar cells.
  • the present invention solves the current problem that enlarging the specific surface area on the surface of a flat silicon wafer makes the etching process unclean, thereby greatly reducing the risk of poor appearance and EL degradation caused by poor back polishing, and also solves the problem of back polishing
  • the problem of poor passivation effect caused by poor passivation is easy to do back throwing, and is also conducive to the passivation of the back surface, which further increases the open circuit voltage of the solar cell and further improves the light conversion efficiency of the cell.
  • silicon chip according to the above-mentioned embodiments of the present invention may also have the following additional technical features:
  • the distance between the highest point and the lowest point of the uneven structure is 2-55 ⁇ m, preferably 15-30 ⁇ m.
  • the uneven structure is wavy, rectangular, V-shaped, semicircular or trapezoidal.
  • the uneven structure is wavy, and the included angle between the wavy slope and the horizontal plane where the silicon wafer is located is not more than 30 degrees, preferably 15-20 degrees.
  • the ratio of the surface area of the textured surface to the base area of the silicon wafer is 1.45-2.
  • the number of quasi-pyramids on the textured surface is 931,800-1,195,600/mm 2 .
  • the present invention proposes a method for preparing the silicon wafer described in the above embodiments. According to an embodiment of the present invention, the method includes:
  • an uneven line trace surface is formed on the surface of the silicon wafer, so that the specific surface area of the silicon wafer surface is increased, and then a pyramid-like structure is formed on the undulating line trace surface, so that
  • the number of silicon wafer pyramids increases, and the specific surface of the silicon wafer after the suede surface is set increases by 21%-66% (compared with the flat silicon wafer surface), based on the silicon wafer base per unit area, the suede surface
  • the number of pyramid-like pyramids increased to 931,800-1,195,600/mm 2 (while the number of pyramid-like pyramids per unit area of the flat silicon chip surface in the prior art is only 800,000/mm 2 ), thereby improving the short circuit of solar cells
  • the current increases the conversion efficiency of solar cells.
  • the present invention can achieve the purpose of having a larger specific surface area of the pyramid-like microstructure without adding chemicals, greatly saving the amount of chemicals and additives, and at the same time achieving the effect of improving the electrical performance parameters of the solar cells.
  • the present invention solves the current problem that large specific surface area on the surface of a flat silicon wafer is not clean in the etching process, and greatly reduces the amount of etching chemicals, thereby greatly reducing the appearance and EL caused by poor back polishing. risk of undesirable degradation while also addressing the issue of poor passivation due to poor backside polishing.
  • the textured structure that is, the silicon wafer microstructure
  • the parameters of the cutting line for forming the wavy uneven structure are: the length of the line is 4600-5000m, the tension is 2-3N, the circumference of the line is The number is 0.2-0.3, the return rate is 65%-70%, and the wire diameter is 0.035 ⁇ m;
  • the parameters of the cutting line to form the rectangular uneven structure are: the length of the incoming line is 3800-4000m, the tension is 4-10N, the number of cycles of the incoming line is 0.3-0.5, and the return rate is 55%-70 %, wire diameter is 0.035 ⁇ m;
  • the parameters of the cutting line for forming the V-shaped uneven structure are: the length of the line is 2400-3200m, the tension is 2-4N, the number of cycles of the line is 0.4-2, and the return rate is 85% -95%, wire diameter is 0.042 ⁇ m;
  • the cutting line parameters of the uneven structure forming a semicircular arc are: the length of the line is 400-800m, the tension is 3-7N, the number of cycles of the line is 3-5, and the return rate is 65%-75 %, wire diameter is 0.038 ⁇ m;
  • the cutting line parameters of the uneven structure forming a trapezoidal shape are: the length of the line is 1000-1500m, the tension is 2-4N, the number of cycles of the line is 0.4-2, and the return rate is 55%-70 %, the wire diameter is 0.047 ⁇ m.
  • step (3) includes: placing the polished surface of the uneven silicon wafer in an alkali solution with a concentration of 1-10wt% to react, the reaction temperature is 70-90 degrees Celsius, and the reaction The time is 20-800s, so that a suede surface is formed on the uneven surface of the silicon wafer.
  • the invention proposes a solar cell.
  • the solar cell has the silicon wafer prepared by the method described in the above embodiment or the silicon wafer described in the above embodiment.
  • the short-circuit current of the solar cell is increased, so that the conversion efficiency is improved.
  • Fig. 1 is the structural representation of the silicon wafer of the corrugated surface of an embodiment of the present invention
  • Fig. 2 is the structural representation after making texture on the silicon chip of wave-shaped surface shown in Fig. 1;
  • Fig. 3 is the schematic structural view of the silicon wafer of the corrugated surface of another embodiment of the present invention.
  • Fig. 4 is the structural representation after making texture on the silicon chip of wave-shaped surface shown in Fig. 3;
  • FIG. 5 is a schematic structural view of a silicon wafer with a rectangular surface according to an embodiment of the present invention.
  • Fig. 6 is the structural representation after making texture on the silicon chip of rectangular shape surface shown in Fig. 5;
  • FIG. 7 is a schematic structural view of a silicon wafer with a V-shaped surface according to an embodiment of the present invention.
  • Fig. 8 is the structural representation after making texture on the silicon chip of V-shaped surface shown in Fig. 7;
  • Fig. 9 is a schematic structural view of a silicon wafer with a trapezoidal surface according to an embodiment of the present invention.
  • Fig. 10 is the structural representation after making texture on the silicon chip of trapezoidal surface shown in Fig. 9;
  • FIG. 11 is a schematic structural view of a silicon wafer with a trapezoidal surface according to another embodiment of the present invention.
  • Fig. 12 is the structural representation after making texture on the silicon chip of trapezoidal surface shown in Fig. 11;
  • Fig. 13 is a schematic structural view of a silicon wafer with a semi-arc surface according to an embodiment of the present invention.
  • Fig. 14 is the structure schematic diagram after making texture on the silicon chip of semicircular arc-shaped surface shown in Fig. 13;
  • FIG. 15 is a schematic structural view of a silicon wafer with a semi-arc surface in another embodiment of the present invention.
  • Fig. 16 is a structural schematic diagram after textured on the silicon chip of the semicircular arc-shaped surface shown in Fig. 15;
  • FIG. 17 is a flow chart of preparing a silicon wafer with an uneven structure according to an embodiment of the present invention.
  • FIG. 18 is a schematic diagram of printing grid lines on an uneven slope surface according to an embodiment of the present invention.
  • Fig. 19 is a schematic diagram of printing grid lines on uneven slopes according to another embodiment of the present invention.
  • FIG. 21 is a schematic diagram of the structure after texturing on the silicon wafer with a flat surface shown in FIG. 20 .
  • the invention provides a silicon wafer.
  • the surface of the silicon chip has an uneven structure, and the surface of the uneven structure is provided with a suede.
  • the specific surface area of the silicon wafer surface is increased by arranging the uneven line trace surface on the silicon wafer surface, and then a suede surface is set on the undulating line trace surface, thereby increasing the number of silicon wafer pyramids.
  • the specific surface of the textured silicon chip has increased by 21%-66% (compared with the flat silicon chip surface), based on the silicon chip substrate per unit area, the number of pyramids on the silicon chip with the textured surface has increased to 931,800-1,195,600/mm 2 (while the number of pyramids per unit area on the flat silicon wafer surface in the prior art is only 800,000/mm 2 ), thereby increasing the short-circuit current of the solar cell, making the solar cell The light conversion efficiency of the sheet is improved.
  • the present invention solves the current problem that enlarging the specific surface area on the surface of a flat silicon wafer makes the etching process unclean, thereby greatly reducing the risk of poor appearance and EL degradation caused by poor back polishing, and also solves the problem of back polishing
  • the problem of poor passivation effect caused by poor passivation is easy to do back throwing, and is also conducive to the passivation of the back surface, which further increases the open circuit voltage of the solar cell and further improves the light conversion efficiency of the cell.
  • the specific surface of the textured silicon wafer refers to the ratio of the total surface area of the pyramid-like texture to the base area of the silicon wafer
  • the base area of the silicon wafer refers to the ratio of the base area of the silicon wafer.
  • the distance between the highest point and the lowest point of the uneven structure is 2-55 ⁇ m, preferably 15-30 ⁇ m, thereby further increasing the number of silicon chip pyramids, so that there are The specific surface of the textured silicon wafer increases, thereby further improving the short-circuit current of the solar cell, and further improving the light conversion efficiency of the solar cell.
  • the specific structure of the unevenness is not particularly limited, and those skilled in the art can set it arbitrarily according to the actual situation.
  • the uneven structure is wavy (refer to accompanying drawing 1 and 3), rectangular shape (referring to accompanying drawing 5), V-shaped (referring to accompanying drawing 7), semicircular arc shape (referring to accompanying drawing 13 and 15) or trapezoidal (referring to accompanying drawing 9 and 11).
  • the uneven structure is wavy, and the included angle between the wavy slope and the horizontal plane where the silicon wafer is located is not more than 30 degrees, preferably 15-20 degrees, thus, Further increasing the number of pyramids of silicon wafers increases the specific surface of the textured silicon wafers, thereby further increasing the short-circuit current of the solar cells and further improving the light conversion efficiency of the solar cells.
  • the ratio of the surface area of the textured silicon wafer to the base area of the silicon wafer is 1.45-2, thereby further improving the short-circuit current of the solar cell, so that the solar energy The light conversion efficiency of the battery sheet is further improved.
  • the number of quasi-pyramids on the textured silicon wafer is 931,800-1,195,600/mm 2 , which further improves the short-circuit current of the solar cell , so that the light conversion efficiency of the solar cell is further improved.
  • the present invention proposes a method for preparing the silicon wafer described in the above embodiments. According to an embodiment of the present invention, with reference to accompanying drawing 17, described method comprises:
  • an uneven structure is formed on the surface of the silicon wafer by adjusting the parameters of the cutting line, so that the specific surface area of the silicon wafer surface is increased.
  • the parameters of the cutting line for forming the wavy uneven structure are: the length of the line is 4600-5000 m, the tension is 2-3 N, the number of cycles of the line is 0.2-0.3, The return rate is 65%-70%, and the wire diameter is 0.035 ⁇ m.
  • the number of incoming wire cycles refers to how many rounds per minute the diamond wire cuts on the surface of the silicon wafer.
  • the return rate refers to the proportion of the diamond line in the process of entering the line. For example, if the line enters 100 meters, then returns for 90 meters, then enters for 100 meters, and then returns for 90 meters, then the return rate is 90. %.
  • the parameters of the cutting line for forming the rectangular uneven structure are: the length of the incoming line is 3800-4000 m, the tension is 4-10 N, the number of cycles of the incoming line is 0.3-0.5, The return rate is 55%-70%, and the wire diameter is 0.035 ⁇ m.
  • the cutting line parameters for forming the V-shaped uneven structure are as follows: the length of the incoming line is 2400-3200 m, the tension is 2-4 N, and the number of cycles of the incoming line is 0.4- 2. The return rate is 85%-95%, and the wire diameter is 0.042 ⁇ m.
  • the parameters of the cutting line for forming the semicircular arc-shaped uneven structure are: the length of the incoming line is 400-800 m, the tension is 3-7 N, the number of cycles of the incoming line is 3-5, The return rate is 65%-75%, and the wire diameter is 0.038 ⁇ m.
  • the parameters of the cutting line for forming the trapezoidal uneven structure are: the length of the incoming line is 1000-1500 m, the tension is 2-4 N, the number of cycles of the incoming line is 0.4-2, The return rate is 55%-70%, and the wire diameter is 0.047 ⁇ m.
  • the uneven surface of the silicon wafer is polished with an alkaline solution (NaOH or KOH) with a lower concentration (1-10wt%), so that the slope surface of the line marks becomes smooth, and the peak value of the line marks is reduced at the same time. , become more uniform.
  • an alkaline solution NaOH or KOH
  • the thickness of the uneven silicon wafer is reduced by 3-5 ⁇ m.
  • suede grows on the polished surface of the uneven silicon wafer to form pyramids, thereby increasing the number of pyramid-like microstructures and specific surface area, and improving efficiency.
  • Fig. 2 is the structural representation after making texture on the silicon chip of wave-shaped surface shown in Fig. 1;
  • Fig. 4 is the structural representation after making texture on the silicon chip of wave-like surface shown in Fig. 3;
  • Fig. 5 is a schematic diagram of the structure after texturing on the silicon chip with a rectangular surface shown in Fig. 5;
  • Fig. 8 is a structural schematic diagram after texturing on a silicon chip with a V-shaped surface shown in Fig. 7;
  • Fig. 10 is a schematic diagram of the structure shown in Fig.
  • Figure 12 is a schematic structural view of the silicon wafer with the trapezoidal surface shown in Figure 11 after texturing;
  • Figure 14 is a semi-arc surface shown in Figure 13
  • Figure 16 is a schematic structural view of the semi-arc surface of the silicon wafer shown in Figure 15 after texturing.
  • step S300 includes:
  • the reaction time is 20-800s
  • the reaction temperature is 70-90 degrees Celsius (the temperature range is the optimum temperature range between alkali and silicon).
  • the reaction temperature can effectively remove the organic matter on the surface of the silicon wafer to form a smooth undulating surface), so as to form a suede on the surface of the uneven silicon wafer.
  • the uneven line trace surface is formed on the surface of the silicon wafer, so that the specific surface area of the silicon wafer surface is increased, and then a pyramid structure is formed on the undulating line trace surface, thereby making the silicon wafer
  • the number of sheet pyramids increases, and the specific surface of the textured silicon wafer increases by 21%-66% (compared with the flat silicon wafer surface).
  • the textured silicon wafer Based on the silicon wafer base per unit area, the textured silicon wafer The number of pyramids on the chip increases to 931,800-1,195,600/mm 2 (while the number of pyramids per unit area on the surface of a flat silicon wafer in the prior art is only 800,000/mm 2 ), thereby improving the solar cell
  • the short-circuit current increases the conversion efficiency of solar cells.
  • the present invention can achieve the purpose of having a larger specific surface area of the pyramid-like microstructure without adding chemicals, greatly saving the amount of chemicals and additives, and at the same time achieving the effect of improving the electrical performance parameters of the solar cells.
  • the present invention solves the current problem that large specific surface area on the surface of a flat silicon wafer is not clean in the etching process, and greatly reduces the amount of etching chemicals, thereby greatly reducing the appearance and EL caused by poor back polishing. risk of undesirable degradation while also addressing the issue of poor passivation due to poor backside polishing.
  • the textured structure that is, the silicon wafer microstructure
  • the silicon wafer microstructure is easy to do back throwing, and is also conducive to the passivation of the back surface, which further improves the open circuit voltage of the solar cell and further improves the conversion efficiency of the cell.
  • the invention proposes a solar cell.
  • the solar cell has the silicon wafer prepared by the method described in the above embodiment or the silicon wafer described in the above embodiment.
  • the short-circuit current of the solar cell is increased, so that the conversion efficiency is improved.
  • This embodiment provides a solar cell, the preparation method of which is as follows:
  • the P-type monocrystalline silicon rod is cut under the action of the diamond wire, and a wave-like structure is formed on the surface of the silicon wafer by adjusting the parameters of the cutting line.
  • the parameters of the cutting line are shown in Table 1.
  • Texturing Using 4.5wt% NaOH solution and controlling the temperature of 88 degrees Celsius to corrode silicon wafers, forming a pyramid-like structure with complete individuality, uniform size and smooth surface on the surface of any shape of the line marks, achieving the effect of increasing the specific surface area of silicon wafers. To achieve the purpose of improving electrical performance.
  • a rectangular structure is formed on the surface of the silicon wafer by adjusting the cutting line parameters, and the cutting line parameters are shown in Table 1. Other content is all identical with embodiment 1.
  • a semi-arc structure is formed on the surface of the silicon wafer by adjusting the parameters of the cutting line, and the parameters of the cutting line are shown in Table 1. Other content is all identical with embodiment 1.
  • a V-shaped structure is formed on the surface of the silicon wafer by adjusting the parameters of the cutting line, and the parameters of the cutting line are shown in Table 1. Other content is all identical with embodiment 1.
  • a trapezoidal structure is formed on the surface of the silicon wafer by adjusting the parameters of the cutting line, and the parameters of the cutting line are shown in Table 1. Other content is all identical with embodiment 1.
  • FIG. 20 is the silicon wafer of the flat surface of comparative example 1 Schematic diagram of the structure
  • FIG. 21 is a schematic diagram of the structure after texturing on the silicon wafer with a flat surface shown in FIG. 20 .

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Abstract

本发明公开了硅片及其制备方法和太阳能电池，所述硅片的表面为凸凹不平的结构，所述凸凹不平的结构表面设有绒面。通过在硅片表面设置凸凹不平的线痕面，使硅片表面的比表面积增大，再在起伏的线痕面上设置绒面，从而使硅片表面的类金字塔数量大幅增多，从而增大了太阳能电池片的短路电流，提升了太阳能电池片的光转换效率。

Description

硅片及其制备方法和太阳能电池
相关申请的交叉引用
本公开要求在2021年12月3日提交中国专利局、申请号为202111474392.1、名称为“硅片及其制备方法和太阳能电池”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本发明属于太阳能电池技术领域，具体涉及一种硅片及其制备方法和太阳能电池。
背景技术
目前技术是先将硅片切割成平整的表面，再通过制绒工序利用低浓度的碱液，先将硅片在低碱浓度(NaOH或KOH和H 2O)高温度的槽里进行抛光，达到去除表面的机械损伤及形成平整的表面，再通过一定浓度的臭氧对硅片表面的有机物进行清洗，再将清洗后的硅片利用低碱浓度(NaOH或KOH和H 2O和添加剂)高温度的槽里进行反应，形成绒面，再通过溶液中的添加剂对绒面结构进行修复，形成个体完整、大小均匀、表面平滑的金字塔结构，达到了光束的多次折射，促进了投射光的二次吸收，从而提升Isc，再利用一定浓度的臭氧清洗掉硅片表面添加剂中残留的有机物，同时再一定浓度的混酸(HCL\HF\H 2O)槽里进行硅片清洗，从而降低了表面复合，提升电性能Uoc。
为提高电池绒面比表面积，提升Isc，提升效率，目前常采用高的碱浓度和添加剂浓度进行反应，增大金字塔高度从而使比表面积增大，但是这种方式存在以下缺点：1.化学品和添加剂用量相对较多，导致成本较高；2.碱浓度较高，化学反应比较剧烈，会导致花篮齿部位反应不均匀，容易出现花篮印，降级或返工数量较多；3.金字塔高度增高，刻蚀背面抛光困难，金字塔抛不干净，影响钝化效果，导致复合严重，且刻蚀需要增加纵向腐蚀，HF用量增加较多。
发明内容
本发明旨在至少在一定程度上解决相关技术中的技术问题之一。为此，本发明的目的在于提出一种硅片及其制备方法和太阳能电池。通过在硅片表面设置凸凹不平的线痕面，使硅片表面的比表面积增大，再在起伏的线痕面上设置绒面，从而使硅片表面的类金字塔数量大幅增多，从而增大了太阳能电池片的短路电流，提升了太阳能电池片的光转换效率。
在本发明的一个方面，本发明提出了一种硅片。根据本发明的实施例，所述硅片的表面为凸凹不平的结构，所述凸凹不平的结构表面设有绒面。
根据本发明实施例的硅片，通过在硅片表面设置凸凹不平的线痕面，使硅片表面的比表面积增大，再在起伏的线痕面上设置绒面，从而使硅片类金字塔数量增多，所述设有绒面硅片的比表面增大了21％-66％(与平整的硅片表面相比)，基于单位面积的硅片基底，所述设有绒面的硅片上的类金字塔数量增加至93.18-119.56万个/mm 2(而现有技术中平整的硅片表面的单位面积的类金字塔数量仅为80万个/mm 2)，从而提升了太阳能电池片的短路电流，使得太阳能电池片的光转换效率提高。本发明解决了目前在平整硅片的表面做大比表面积对刻蚀工序背抛抛不干净的难题，从而大大降低了背面抛光不良造成的外观及EL不良降级的风险，同时还解决了背面抛光差导致的钝化效果差的问题。另外，小的绒面结构(即硅片微结构)容易做背抛，也有利于背表面的钝化，进一步提升了太阳能电池片的开路电压，进一步提高了电池的光转换效率。
另外，根据本发明上述实施例的硅片还可以具有如下附加的技术特征：
在本发明的一些实施例中，所述凸凹不平的结构的最高点与最低点之间的距离为2-55μm，优选15-30μm。
在本发明的一些实施例中，所述凸凹不平的结构为波浪状、矩形状、V状、半圆弧状或者梯形状。
在本发明的一些实施例中，所述凸凹不平的结构为波浪状，所述波浪状的坡度与所述硅片所在水平面的夹角不大于30度，优选15-20度。
在本发明的一些实施例中，所述绒面的表面积与所述硅片的基底面积的比值为1.45-2。
在本发明的一些实施例中，基于单位面积的硅片基底，所述绒面上的类 金字塔数量为93.18-119.56万个/mm 2。
在本发明的再一个方面，本发明提出了一种制备以上实施例所述的硅片。根据本发明的实施例，所述方法包括：
(1)通过调整切割线参数在硅片表面形成凸凹不平的结构；
(2)对凸凹不平的硅片表面进行抛光；
(3)在抛光后的所述凸凹不平的硅片表面形成绒面。
根据本发明实施例的方法，通过调整切割线参数在硅片表面形成凸凹不平的线痕面，使硅片表面的比表面积增大，再在起伏的线痕面上长类金字塔结构，从而使硅片类金字塔数量增多，所述硅片设置绒面后的比表面增大了21％-66％(与平整的硅片表面相比)，基于单位面积的硅片基底，所述绒面上的类金字塔数量增加至93.18-119.56万个/mm 2(而现有技术中平整的硅片表面的单位面积的类金字塔数量仅为80万个/mm 2)，从而提升了太阳能电池片的短路电流，使得太阳能电池片的转换效率提高。且本发明不添加化学品就可以达到具有更大的类金字塔微结构比表面积的目的，大幅度节省了化学品和添加剂的用量，同时还达到了提升太阳能电池片的电性能参数的效果。本发明解决了目前在平整硅片的表面做大比表面积对刻蚀工序背抛抛不干净的难题，且大幅度降低了刻蚀化学品用量，从而大大降低了背面抛光不良造成的外观及EL不良降级的风险，同时还解决了背面抛光差导致的钝化效果差的问题。另外，绒面结构(即硅片微结构)容易做背抛，也有利于背表面的钝化，进一步提升了太阳能电池片的开路电压，进一步提高了电池转换效率。
另外，根据本发明上述实施例的方法还可以具有如下技术方案：
在本发明的一些实施例中，在步骤(1)中，形成波浪状的所述凸凹不平的结构的切割线参数为：进线长度为4600-5000m，张力为2-3牛，进线周数为0.2-0.3，回线率为65％-70％，线径为0.035μm；
或，形成矩形状的所述凸凹不平的结构的切割线参数为：进线长度为3800-4000m，张力为4-10牛，进线周数为0.3-0.5，回线率为55％-70％，线径为0.035μm；
或，形成所述V状的所述凸凹不平的结构的切割线参数为：进线长度为2400-3200m，张力为2-4牛，进线周数为0.4-2，回线率为85％-95％，线径为0.042μm；
或，形成半圆弧状的所述凸凹不平的结构的切割线参数为：进线长度为400-800m，张力为3-7牛，进线周数为3-5，回线率为65％-75％，线径为0.038μm；
或，形成梯形状的所述凸凹不平的结构的切割线参数为：进线长度为1000-1500m，张力为2-4牛，进线周数为0.4-2，回线率为55％-70％，线径为0.047μm。
在本发明的一些实施例中，步骤(3)包括：将抛光后的所述凸凹不平的硅片表面置于浓度为1-10wt％的碱液中反应，反应温度为70-90摄氏度，反应时间为20-800s，以便在所述凸凹不平的硅片表面形成绒面。
在本发明的第三个方面，本发明提出一种太阳能电池。根据本发明的实施例，所述太阳能电池具有以上实施例所述的方法制得的硅片或以上实施例所述的硅片。由此，提升了太阳能电池的短路电流，使得转换效率提高。
本发明的附加方面和优点将在下面的描述中部分给出，部分将从下面的描述中变得明显，或通过本发明的实践了解到。
上述说明仅是本公开技术方案的概述，为了能够更清楚了解本公开的技术手段，而可依照说明书的内容予以实施，并且为了让本公开的上述和其它目的、特征和优点能够更明显易懂，以下特举本公开的具体实施方式。
附图说明
为了更清楚地说明本公开实施例或相关技术中的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
本发明的上述和/或附加的方面和优点从结合下面附图对实施例的描述中将变得明显和容易理解，其中：
图1为本发明一个实施例的波浪状表面的硅片的结构示意图；
图2为在图1所示的波浪状表面的硅片上制绒后的结构示意图；
图3为本发明再一个实施例的波浪状表面的硅片的结构示意图；
图4为在图3所示的波浪状表面的硅片上制绒后的结构示意图；
图5为本发明实施例的矩形状表面的硅片的结构示意图；
图6为在图5所示的矩形状表面的硅片上制绒后的结构示意图；
图7为本发明实施例的V状表面的硅片的结构示意图；
图8为在图7所示的V状表面的硅片上制绒后的结构示意图；
图9为本发明一个实施例的梯形状表面的硅片的结构示意图；
图10为在图9所示的梯形状表面的硅片上制绒后的结构示意图；
图11为本发明再一个实施例的梯形状表面的硅片的结构示意图；
图12为在图11所示的梯形状表面的硅片上制绒后的结构示意图；
图13为本发明一个实施例的半圆弧状表面的硅片的结构示意图；
图14为在图13所示的半圆弧状表面的硅片上制绒后的结构示意图；
图15为本发明再一个实施例的半圆弧状表面的硅片的结构示意图；
图16为在图15所示的半圆弧状表面的硅片上制绒后的结构示意图；
图17为本发明实施例的制备具有凸凹不平的结构的硅片的流程图；
图18为本发明一个实施例的将栅线印刷在凸凹不平的斜坡面上的示意图；
图19为本发明再一个实施例的将栅线印刷在凸凹不平的斜坡面上的示意图；
图20为对比例1的平整表面的硅片的结构示意图；
图21为在图20所示的平整表面的硅片上制绒后的结构示意图。
具体实施例
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
下面详细描述本发明的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，旨在用于解释本发明，而不能理解为对本发明的限制。
在本发明的一个方面，本发明提出了一种硅片。根据本发明的实施例，所述硅片的表面为凸凹不平的结构，所述凸凹不平的结构表面设有绒面。由 此，通过在硅片表面设置凸凹不平的线痕面，使硅片表面的比表面积增大，再在起伏的线痕面上设置绒面，从而使硅片类金字塔数量增多，所述设有绒面硅片的比表面增大了21％-66％(与平整的硅片表面相比)，基于单位面积的硅片基底，所述设有绒面的硅片上的类金字塔数量增加至93.18-119.56万个/mm 2(而现有技术中平整的硅片表面的单位面积的类金字塔数量仅为80万个/mm 2)，从而提升了太阳能电池片的短路电流，使得太阳能电池片的光转换效率提高。本发明解决了目前在平整硅片的表面做大比表面积对刻蚀工序背抛抛不干净的难题，从而大大降低了背面抛光不良造成的外观及EL不良降级的风险，同时还解决了背面抛光差导致的钝化效果差的问题。另外，绒面结构(即硅片微结构)容易做背抛，也有利于背表面的钝化，进一步提升了太阳能电池片的开路电压，进一步提高了电池的光转换效率。需要说明的是，所述设有绒面硅片的比表面指的是所述类金字塔绒面的总表面积与所述硅片的基底面积的比值，所述硅片的基底面积指的是所述硅片表面在所述硅片基底的正投影面积。
根据本发明的一个具体实施例，所述凸凹不平的结构的最高点与最低点之间的距离为2-55μm，优选15-30μm，由此，进一步使硅片类金字塔数量增多，使设有绒面硅片的比表面增大，从而进一步提升了太阳能电池片的短路电流，使得太阳能电池片的光转换效率进一步提高。
在本发明的实施例中，所述凸凹不平的具体结构并不受特别限制，本领域人员可根据实际情况随意设置，作为一个具体示例，所述凸凹不平的结构为波浪状(参考附图1和3)、矩形状(参考附图5)、V状(参考附图7)、半圆弧状(参考附图13和15)或者梯形状(参考附图9和11)。
根据本发明的再一个具体实施例，所述凸凹不平的结构为波浪状，所述波浪状的坡度与所述硅片所在水平面的夹角不大于30度，优选15-20度，由此，进一步使硅片类金字塔数量增多，使设有绒面硅片的比表面增大，从而进一步提升了太阳能电池片的短路电流，使得太阳能电池片的光转换效率进一步提高。
根据本发明的又一个具体实施例，所述设有绒面硅片的表面积与所述硅片的基底面积的比值为1.45-2，由此，进一步提升了太阳能电池片的短路电流，使得太阳能电池片的光转换效率进一步提高。
根据本发明的又一个具体实施例，基于单位面积的硅片基底，所述设有绒面硅片上的类金字塔数量为93.18-119.56万个/mm 2，进一步提升了太阳能电池片的短路电流，使得太阳能电池片的光转换效率进一步提高。
在本发明的再一个方面，本发明提出了一种制备以上实施例所述硅片的方法。根据本发明的实施例，参考附图17，所述方法包括：
S100：通过调整切割线参数在硅片表面形成凸凹不平的结构
在该步骤中，通过调整切割线参数在硅片表面形成凸凹不平的结构，使硅片表面的比表面积增大。
根据本发明的又一个具体实施例，形成波浪状的所述凸凹不平的结构的切割线参数为：进线长度为4600-5000m，张力为2-3牛，进线周数为0.2-0.3，回线率为65％-70％，线径为0.035μm。
需要说明的是，进线周数是指金刚石线在硅片表面每分钟切割多少回合。回线率是指金刚石线在进线过程中回线的比例，举例来说，进线100米，再回过来90米，再接着进100米，再接着回90米，那么回线率就是90％。
根据本发明的又一个具体实施例，形成矩形状的所述凸凹不平的结构的切割线参数为：进线长度为3800-4000m，张力为4-10牛，进线周数为0.3-0.5，回线率为55％-70％，线径为0.035μm。
根据本发明的又一个具体实施例，形成所述V状的所述凸凹不平的结构的切割线参数为：进线长度为2400-3200m，张力为2-4牛，进线周数为0.4-2，回线率为85％-95％，线径为0.042μm。
根据本发明的又一个具体实施例，形成半圆弧状的所述凸凹不平的结构的切割线参数为：进线长度为400-800m，张力为3-7牛，进线周数为3-5，回线率为65％-75％，线径为0.038μm。
根据本发明的又一个具体实施例，形成梯形状的所述凸凹不平的结构的切割线参数为：进线长度为1000-1500m，张力为2-4牛，进线周数为0.4-2，回线率为55％-70％，线径为0.047μm。
S200：对凸凹不平的硅片表面进行抛光
在该步骤中，采用较低浓度(1-10wt％)的碱溶液(NaOH或KOH)对凸凹不平的硅片表面进行抛光，使线痕斜坡面变得平滑，同时线痕峰值极差减小，变得更均匀。
根据本发明的又一些具体实施例，将所述凸凹不平的硅片厚度减薄3-5μm。
S300：在抛光后的所述凸凹不平的硅片表面形成绒面
在该步骤中，在抛光后的所述凸凹不平的硅片表面长出绒面，形成金字塔，从而增加类金字塔微结构数量和比表面积，提升效率。
图2为在图1所示的波浪状表面的硅片上制绒后的结构示意图；图4为在图3所示的波浪状表面的硅片上制绒后的结构示意图；图6为在图5所示的矩形状表面的硅片上制绒后的结构示意图；图8为在图7所示的V状表面的硅片上制绒后的结构示意图；图10为在图9所示的梯形状表面的硅片上制绒后的结构示意图；图12为在图11所示的梯形状表面的硅片上制绒后的结构示意图；图14为在图13所示的半圆弧状表面的硅片上制绒后的结构示意图；图16为在图15所示的半圆弧状表面的硅片上制绒后的结构示意图。
根据本发明的又一些具体实施例，步骤S300包括：
将抛光后的所述凸凹不平的硅片表面在浓度为1-10wt％的碱液中反应,反应时间为20-800s，反应温度为70-90摄氏度(该温度范围为碱与硅的最佳反应温度，能有效去除硅片表面的有机物，形成光滑的起伏面)，以便在所述凸凹不平的硅片表面形成绒面。
根据本发明实施例的方法，通过调整切割线参数在硅片表面形成凸凹不平的线痕面，使硅片表面的比表面积增大，再在起伏的线痕面上长金字塔结构，从而使硅片金字塔数量增多，所述设有绒面硅片的比表面增大了21％-66％(与平整的硅片表面相比)，基于单位面积的硅片基底，所述设有绒面硅片上的类金字塔数量增加至93.18-119.56万个/mm 2(而现有技术中平整的硅片表面的单位面积的类金字塔数量仅为80万个/mm 2)，从而提升了太阳能电池片的短路电流，使得太阳能电池片的转换效率提高。且本发明不添加化学品就可以达到具有更大的类金字塔微结构比表面积的目的，大幅度节省了化学品和添加剂的用量，同时还达到了提升太阳能电池片的电性能参数的效果。本发明解决了目前在平整硅片的表面做大比表面积对刻蚀工序背抛抛不干净的难题，且大幅度降低了刻蚀化学品用量，从而大大降低了背面抛光不良造成的外观及EL不良降级的风险，同时还解决了背面抛光差导致的钝化效果差的问题。另外，绒面结构(即硅片微结构)容易做背抛，也有利于背表面的钝化，进一步提升了太阳能电池片的开路电压，进一步提高了电池转换效率。
在后续的印刷过程中，参考附图18和19，通过对线痕斜坡面和丝网印刷网版膜的张力角度、线高的调整，将栅线细栅印刷在线痕的脊梁、线痕的沟凹、线痕的斜坡面上，实现后续的印刷技术。
在本发明的第三个方面，本发明提出一种太阳能电池。根据本发明的实施例，所述太阳能电池具有以上实施例所述的方法制得的硅片或以上实施例所述的硅片。由此，提升了太阳能电池的短路电流，使得转换效率提高。
下面详细描述本发明的实施例，需要说明的是下面描述的实施例是示例性的，仅用于解释本发明，而不能理解为对本发明的限制。另外，如果没有明确说明，在下面的实施例中所采用的所有试剂均为市场上可以购得的，或者可以按照本文或已知的方法合成的，对于没有列出的反应条件，也均为本领域技术人员容易获得的。
实施例1
本实施例提供一种太阳能电池，其制备方法如下：
切割：P型单晶硅棒在金刚石线的作用下进行切割，通过调整切割线参数在硅片表面形成波浪状结构，切割线参数如表1所示。
制绒：利用4.5wt％的NaOH溶液，88摄氏度的温控对硅片进行腐蚀，在线痕任意形状面形成个体完整、大小均匀、表面平滑的类金字塔结构，达到硅片比表面增加的效果，实现提高电性能目的。
然后按照PERC工艺进行扩散、制结、钝化、镀减反膜、丝网印刷由此形成电池片。
对制绒步骤后得到的硅片的类金字塔数量、比表面积以及对光的反射率进行测试，测试结果如表2所示。对电池片的Isc以及EFF进行测试，测试结果如表2所示。
实施例2
本实施例中，通过调整切割线参数在硅片表面形成矩形状结构，切割线参数如表1所示。其他内容均与实施例1相同。
对制绒步骤后得到的硅片的类金字塔数量、比表面积以及对光的反射率进行测试，测试结果如表2所示。对电池片的Isc以及EFF进行测试，测试结果如表2所示。
实施例3
本实施例中，通过调整切割线参数在硅片表面形成半圆弧状结构，切割线参数如表1所示。其他内容均与实施例1相同。
对制绒步骤后得到的硅片的类金字塔数量、比表面积以及对光的反射率进行测试，测试结果如表2所示。对电池片的Isc以及EFF进行测试，测试结果如表2所示。
实施例4
本实施例中，通过调整切割线参数在硅片表面形成V字状结构，切割线参数如表1所示。其他内容均与实施例1相同。
对制绒步骤后得到的硅片的类金字塔数量、比表面积以及对光的反射率进行测试，测试结果如表2所示。对电池片的Isc以及EFF进行测试，测试结果如表2所示。
实施例5
本实施例中，通过调整切割线参数在硅片表面形成梯形状结构，切割线参数如表1所示。其他内容均与实施例1相同。
对制绒步骤后得到的硅片的类金字塔数量、比表面积以及对光的反射率进行测试，测试结果如表2所示。对电池片的Isc以及EFF进行测试，测试结果如表2所示。
对比例1
该对比例1中，先将硅片切割成平整的表面，然后再在平整的表面上进行制绒工序，参考附图20和21，其中，图20为对比例1的平整表面的硅片的结构示意图；图21为在图20所示的平整表面的硅片上制绒后的结构示意图。
其他内容均与实施例1相同。
对制绒步骤后得到的硅片的类金字塔数量、比表面积以及对光的反射率进行测试，测试结果如表2所示。对电池片的Isc以及EFF进行测试，测试结果如表2所示。
表1
Figure PCTCN2022092275-appb-000001
表2
Figure PCTCN2022092275-appb-000002
从表2中可以看出，与对比例1相比，实施例1-5的比表面积和单位面积的类金字塔数量均大幅增加，对光的反射率均降低，Isc和EFF均有所提升。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本发明的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且， 描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
尽管上面已经示出和描述了本发明的实施例，可以理解的是，上述实施例是示例性的，不能理解为对本发明的限制，本领域的普通技术人员在本发明的范围内可以对上述实施例进行变化、修改、替换和变型。

Claims (10)

  1. 一种硅片，其特征在于，所述硅片的表面为凸凹不平的结构，所述凸凹不平的结构表面设有绒面。
  2. 根据权利要求1所述的硅片，其特征在于，所述凸凹不平的结构的最高点与最低点之间的距离为2-55μm，优选15-30μm。
  3. 根据权利要求1所述的硅片，其特征在于，所述凸凹不平的结构为波浪状、矩形状、V状、半圆弧状或者梯形状。
  4. 根据权利要求1所述的硅片，其特征在于，所述凸凹不平的结构为波浪状，所述波浪状的坡度与所述硅片所在水平面的夹角不大于30度，优选15-20度。
  5. 根据权利要求1-4任一项所述的硅片，其特征在于，所述绒面的表面积与所述硅片的基底面积的比值为1.45-2。
  6. 根据权利要求1-4任一项所述的硅片，其特征在于，基于单位面积的硅片基底，所述类金字塔绒面上的类金字塔数量为93.18-119.56万个/mm 2。
  7. 一种制备权利要求1-6任一项所述的硅片的方法，其特征在于，包括：
    (1)通过调整切割线参数在硅片表面形成凸凹不平的结构；
    (2)对凸凹不平的硅片表面进行抛光；
    (3)在抛光后的所述凸凹不平的硅片表面形成绒面。
  8. 根据权利要求7所述的方法，其特征在于，在步骤(1)中，形成波浪状的所述凸凹不平的结构的切割线参数为：进线长度为4600-5000m，张力为2-3牛，进线周数为0.2-0.3，回线率为65％-70％，线径为0.035μm；
    或，形成矩形状的所述凸凹不平的结构的切割线参数为：进线长度为3800-4000m，张力为4-10牛，进线周数为0.3-0.5，回线率为55％-70％，线径为0.035μm；
    或，形成所述V状的所述凸凹不平的结构的切割线参数为：进线长度为2400-3200m，张力为2-4牛，进线周数为0.4-2，回线率为85％-95％，线径为0.042μm；
    或，形成半圆弧状的所述凸凹不平的结构的切割线参数为：进线长度为400-800m，张力为3-7牛，进线周数为3-5，回线率为65％-75％，线径为0.038μm；
    或，形成梯形状的所述凸凹不平的结构的切割线参数为：进线长度为1000-1500m，张力为2-4牛，进线周数为0.4-2，回线率为55％-70％，线径为0.047μm。
  9. 根据权利要求7或8所述的方法，其特征在于，步骤(3)包括：
    将抛光后的所述凸凹不平的硅片表面置于浓度为1-10wt％的碱液中反应，反应温度为70-90摄氏度，反应时间为20-800s，以便在所述凸凹不平的硅片表面形成绒面。
  10. 一种太阳能电池，其特征在于，所述太阳能电池具有权利要求1-6任一项所述的硅片或权利要求7-9任一项所述方法制备的硅片。
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