WO2023097779A1 - 显示面板和显示装置 - Google Patents

显示面板和显示装置 Download PDF

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Publication number
WO2023097779A1
WO2023097779A1 PCT/CN2021/137995 CN2021137995W WO2023097779A1 WO 2023097779 A1 WO2023097779 A1 WO 2023097779A1 CN 2021137995 W CN2021137995 W CN 2021137995W WO 2023097779 A1 WO2023097779 A1 WO 2023097779A1
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Prior art keywords
terminal
opening
display
binding
substrate
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PCT/CN2021/137995
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English (en)
French (fr)
Inventor
江应传
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US17/622,336 priority Critical patent/US20240038773A1/en
Publication of WO2023097779A1 publication Critical patent/WO2023097779A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/411—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by materials, geometry or structure of the substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/127—Active-matrix OLED [AMOLED] displays comprising two substrates, e.g. display comprising OLED array and TFT driving circuitry on different substrates
    • H10K59/1275—Electrical connections of the two substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations

Definitions

  • the present application relates to the field of display technology, in particular to a display panel and a display device.
  • Ultra-large display screens can meet people's needs for long-distance viewing and large-scale information display. Due to cost considerations, current super-sized display screens are usually implemented using a splicing technology, that is, multiple sub-display screens are spliced together to form a super-sized display screen. However, when multiple display screens are spliced together, there will be a large black splicing gap at the splicing place, which seriously affects the display quality of the super-sized display screen. In order to solve the black splicing gap at the splicing place, a borderless splicing display technology has emerged.
  • the present application provides a display panel and a display device to alleviate the technical problem of poor lapping between the display screen and the motherboard existing in the existing borderless splicing display technology.
  • An embodiment of the present application provides a display panel, including a driving backplane and a display substrate electrically connected to the driving backplane, and the display substrate includes:
  • a plurality of first binding terminals are arranged on the side of the first substrate away from the driving backplane, and the display substrate is bound to the driving backplane through the first binding terminals to realize electrical connection ;
  • At least one first opening is provided on the first substrate and the first bonding terminal, and the first opening runs through the The first substrate and the first binding terminal; a bridging terminal is provided in the first opening, the first binding terminal is electrically connected to the driving backplane through the bridging terminal, and the The bridging terminal is electrically connected to the side surface of the first binding terminal.
  • the display substrate further includes an auxiliary conductive layer disposed in the first opening, and the first binding terminal is electrically connected to the bridging terminal through the auxiliary conductive layer. connect.
  • the auxiliary conductive layer covers the surface of the first substrate in the first opening and the first binding terminal in the first opening superior.
  • the number of the first openings is multiple.
  • the plurality of first openings are uniformly arranged in the binding area.
  • the display substrate further includes:
  • a driving circuit layer disposed on the first barrier layer, including a plurality of thin film transistors and a plurality of signal lines, and the signal lines are electrically connected to the corresponding first binding terminals;
  • a pixel electrode disposed on the driving circuit layer and electrically connected to the corresponding thin film transistor
  • the pixel definition layer covers the pixel electrode and the driving circuit layer, the pixel definition layer has a second opening, and the second opening exposes a part of the pixel electrode.
  • the first opening also penetrates part of the first barrier layer.
  • the pixel definition layer further has a third opening, and the third opening penetrates the pixel definition layer and the driving circuit layer.
  • the side of the driving backplane facing the display substrate is provided with a second binding terminal, and the second binding terminal is electrically connected to the first binding terminal.
  • the display panel provided in the embodiment of the present application, there are multiple display substrates, and the plurality of display substrates are arranged in an array on the driving backplane.
  • An embodiment of the present application further provides a display device, which includes a casing and the display panel of one of the foregoing embodiments, the casing is formed with an accommodating cavity, and the display panel is disposed in the accommodating cavity.
  • a plurality of display substrates are arrayed on the driving backplane, and each display substrate includes a first substrate and a plurality of first bindings arranged on the first substrate.
  • fixed terminal the display substrate is bound to the driving backplane through the first binding terminal to realize electrical connection, and in the binding area between the display substrate and the driving backplane, the first substrate and the driving backplane
  • the first binding terminal is provided with at least one first opening, and the first opening passes through the first substrate and the first binding terminal;
  • a bridging terminal is provided in the first opening , the first binding terminal is electrically connected to the drive backplane through the bridge terminal, and the bridge terminal is electrically connected to the side surface of the first binding terminal, so as to reduce the distance between the first binding terminal and the bridge terminal. contact resistance, thereby improving the reliability of the conduction between the display substrate and the driving backplane, and solving the problem of poor lap between the display screen and the motherboard existing in the existing borderless splicing display technology.
  • FIG. 1 is a schematic top view structural diagram of a display panel provided by an embodiment of the present application.
  • FIG. 2 is a partial cross-sectional structural schematic diagram of a display panel provided by an embodiment of the present application.
  • FIG. 3 is a schematic diagram of a first partial cross-sectional structure of a display substrate provided by an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a second partial cross-sectional structure of a display substrate provided by an embodiment of the present application.
  • FIG. 5 is a schematic diagram of a third partial cross-sectional structure of a display substrate provided by an embodiment of the present application.
  • FIG. 6 is a schematic diagram of a fourth partial cross-sectional structure of a display substrate provided by an embodiment of the present application.
  • FIG. 7 is a schematic diagram of a fifth partial cross-sectional structure of a display substrate provided by an embodiment of the present application.
  • FIG. 8 is a schematic diagram of a sixth partial cross-sectional structure of a display substrate provided by an embodiment of the present application.
  • FIG. 9 is a schematic cross-sectional structure diagram of a display device provided by an embodiment of the present application.
  • FIG. 1 is a schematic top view of the display panel provided by the embodiment of the present application.
  • FIG. 4 is a schematic diagram of the second partial cross-sectional structure of the display substrate provided in the embodiment of the present application.
  • the display panel 100 includes a driving backplane 1 and a plurality of display substrates 2 arrayed on the driving backplane 1 .
  • Each of the display substrates 2 includes a first substrate 12 disposed on a side facing the driving backplane 1 , a plurality of first binding terminals 11 , and a first barrier layer 13 .
  • a plurality of first binding terminals 11 are disposed on a side of the first substrate 12 away from the drive backplane 1, and the first barrier layer 13 covers the first binding terminals 11 and the first on the substrate 12.
  • the display substrate 2 is bound to the driving backplane 1 through the first binding terminal 11 to realize electrical connection.
  • the drive backplane 1 is provided with a second binding terminal 50 corresponding to the first binding terminal 11 of each of the display substrates 2, and the second binding terminal 50 is connected to the first binding terminal 50.
  • the binding terminals 11 are electrically connected, so that the display substrate 2 is electrically connected with the driving backplane 1 .
  • the first substrate 12 under the first binding terminal 11 may be peeled off by laser drilling, The first binding terminal 11 is exposed to facilitate electrical connection between the first binding terminal 11 and the second binding terminal 50 .
  • the fluctuation of the laser energy itself and the surface flatness caused by the difference in the thickness of the material of the first binding terminal 11 make it difficult to control only the removal of the first lining by adjusting the laser process parameters during laser drilling. bottom 12 without damaging the first binding terminal 11. If part of the first binding terminal 11 is pierced, the conduction performance between the first binding terminal 11 and the second binding terminal 50 will be affected.
  • the display panel 100 of the present application can solve the above-mentioned problems caused by damage to the first binding terminal 11 .
  • At least one first opening 121 is provided on the first substrate 12 and the first bonding terminal 11, the The first opening 121 penetrates through the first substrate 12 and the first binding terminal 11 to expose part of the first barrier layer 13 .
  • a bridging terminal 10 is provided in the first opening 121, the first binding terminal 11 is electrically connected to the driving backplane 1 through the bridging terminal 10, and the bridging terminal 10 is connected to the first The sides of the binding terminal 11 are electrically connected so that the driving backplane 1 and the display substrate 2 are electrically connected, so as to avoid poor lapping between the display screen and the motherboard caused by laser drilling in the existing borderless splicing display technology question.
  • the side of the first binding terminal 11 refers to the cross section of the first binding terminal 11 exposed by the first opening 121, and the bridge terminal 10 and the first binding terminal 11
  • the side electrical connection refers to the conductive function realized by the bridging terminal 10 directly or indirectly contacting the side of the first binding terminal 11 .
  • the bridging terminal 10 and the first binding terminal When the sides of the bridge terminal 11 are electrically connected, the side surfaces of the bridging terminal 10 and the first binding terminal 11 need to meet a certain contact area, that is, the side surfaces of the bridging terminal 10 and the first binding terminal 11 need to be effective touch.
  • the effective contact between the bridging terminal 10 and the side of the first binding terminal 11 means that the area of the bridging terminal 10 directly or indirectly in contact with the side of the first binding terminal 11 is at least not less than A minimum area that satisfies the impedance requirement of the electrical connection between the bridging terminal 10 and the first binding terminal 11 .
  • the orthographic projection of the first opening 121 on the first binding terminal 11 falls within the range of the first binding terminal 11, so that the size of the first opening 121 is smaller than the first binding terminal 11.
  • the size of the first binding terminal 11 is described above.
  • the cross-sectional shape of the first binding terminal 11 includes circle, square, etc. When the cross-sectional shape of the first binding terminal 11 is circular, the size of the first binding terminal 11 refers to the The diameter of the first binding terminal 11 ; when the cross-sectional shape of the first binding terminal 11 is square, the size of the first binding terminal 11 refers to the side length of the first binding terminal 11 .
  • the definition of the size of the first opening 121 is the same as that of the first binding terminal 11, depending on the cross-sectional shape of the first opening 121, and the cross-sectional shape of the first opening 121 is the same as that of the first binding terminal 11.
  • the cross-sectional shape of the first binding terminal 11 is related.
  • the cross-sectional shape of the first opening 121 also includes circle, square, etc.
  • the size of the first opening 121 refers to the The diameter of the first opening 121; when the cross-sectional shape of the first opening 121 is a square, the size of the first opening 121 refers to the side length of the first opening 121. It can be understood that when the cross-sectional shape of the first opening 121 is circular, the inner surface of the first opening 121 is more rounded, so that the conductive material is filled in the first opening 121 to form the When the bridging terminal 10 is described above, it is more conducive to the preparation of the bridging terminal 10 .
  • first binding terminal 11 is electrically connected to the second binding terminal 50 through the bridging terminal 10, and of course optionally, the connection between the bridging terminal 10 and the second binding terminal 50
  • An auxiliary bridging layer 112 can also be provided to make good contact between the bridging terminal 10 and the second binding terminal 50 .
  • the first binding terminal 11 and the second binding terminal 50 can be made of metals or alloys with strong oxidation resistance and low resistivity, such as MO, Al alloy, etc., to ensure that the first binding Stability of Terminal 11.
  • the bridging terminal 10 can be formed by filling the first opening 121 with conductive silver paste, and the auxiliary bridging layer 112 can be made of conductive adhesive or metal to ensure that the first binding terminal 11 is in contact with the first opening 121. The reliability of the connection of the second binding terminal 50 is described.
  • an auxiliary conductive layer 111 may be provided in the first opening 121, and the material of the auxiliary conductive layer 111 may be The material is the same as that of the first binding terminal 11 .
  • the manner of disposing the auxiliary conductive layer 111 includes using an evaporation process and the like.
  • the auxiliary conductive layer 111 covers at least the first binding terminal 11 in the first opening 121 and the exposed first barrier layer 13 in the first opening 121, or the auxiliary conductive The layer 111 can also at least cover the first binding terminal 11 in the first opening 121 and the first substrate 12 in the first opening 121, of course, the auxiliary conductive layer 111 The first binding terminal 11 , the first substrate 12 and the exposed first barrier layer 13 in the first opening 121 may also be covered.
  • the bridging terminal 10 is filled in the first opening 121 and is in contact with the auxiliary conductive layer 111, and the auxiliary conductive layer 111 is vapor-deposited in the first opening 121, which is equivalent to the contact with the first opening 121.
  • a binding terminal 11 is provided integrally, so that the side of the bridging terminal 10 and the first binding terminal 11 are electrically connected through indirect contact, and the bridging terminal 10 and the side of the first binding terminal 11 The effective contact area on the side is greatly improved. Wherein the effective contact area between the bridging terminal 10 and the side surface of the first binding terminal 11 refers to the contact area between the bridging terminal 10 and the auxiliary conductive layer 111 .
  • the impedance between the bridging terminal 10 and the first binding terminal 11 can be reduced, and the first binding terminal 11 can be improved.
  • the electrical conductivity of the binding terminal 11 and the second binding terminal 50 further improves the binding stability of the display substrate 2 and the driving backplane 1 .
  • the driving backplane 1 is bound to the display substrate 2 for providing various driving signals to the display substrate 2 .
  • a driving chip (not shown) etc. is also arranged on the driving backplane 1, and the second binding terminal 50 is electrically connected to the driving chip so as to pass the driving signal of the driving chip through the
  • the first binding terminal 11 is transmitted to the corresponding display substrate 2 .
  • peripheral circuits such as driving chips on the driving backplane 1, and setting first binding terminals 11 on each of the display substrates 2, each of the signal lines in the display substrate 2 It is electrically connected to the first binding terminal 11 and connected to the driving chip through the corresponding second binding terminal 50 to realize signal transmission. Therefore, there is no need to reserve a frame area for each display substrate 2 to set driver chips and various binding wirings, so that after splicing a plurality of display substrates 2, there will be no gaps between adjacent display substrates 2. Large stitching gaps.
  • the film layer structure of the display substrate 2 will be described in detail below:
  • the display substrate 2 further includes a second substrate 14, a second barrier layer 15, a buffer layer 16, a driving circuit layer 20, a pixel electrode 31, and a pixel electrode 31 stacked in sequence on the first barrier layer 13.
  • the first barrier layer 13, the second barrier layer 15, and the buffer layer 16 can be formed of inorganic materials such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), etc., to prevent undesired Desired impurities or contaminants (eg, moisture, oxygen, etc.) diffuse from the first substrate 12, the second substrate 14 into devices that may be damaged by these impurities or contaminants.
  • the materials of the first substrate 12 and the second substrate 14 include polyimide (Polyimide, PI) and other flexible film materials.
  • the buffer layer 16 can also provide a flat top surface to facilitate the preparation of other film structures on the buffer layer 16 .
  • the display substrate 2 of the present application is not limited thereto, and the display substrate 2 of the present application may include more or less substrate film layers and barrier film layers.
  • the driving circuit layer 20 is disposed on the first barrier layer 13 , more specifically, the driving circuit layer 20 is disposed on the buffer layer 16 .
  • the driving circuit layer 20 includes a plurality of thin film transistors and a plurality of signal lines, and the signal lines are electrically connected to the corresponding first binding terminals 11 .
  • the driving circuit layer 20 includes a semiconductor layer 21, a gate insulating layer 22, a gate layer 23, an interlayer insulating layer 24, and a source-drain layer 25, and the semiconductor layer 21 is disposed on the buffer layer 16
  • the semiconductor layer 21 includes a channel region 211 and a source region 212 and a drain region 213 located on opposite sides of the channel region 211 .
  • the gate insulating layer 22 covers the semiconductor layer 21 and the buffer layer 16 .
  • the gate layer 23 is disposed on the gate insulating layer 22, and the gate layer 23 is patterned to form gates 231 and other signal lines such as gate scanning lines 232.
  • the gates 231 and the semiconductor layer The channel region 211 of 21 is provided correspondingly, and the gate scanning line 232 is electrically connected to the corresponding first binding terminal 11 .
  • the interlayer insulating layer 24 covers the gate layer 23 and the gate insulating layer 22 .
  • the source-drain layer 25 is disposed on the interlayer insulating layer 24, and the source-drain layer 25 is patterned to form other signal lines such as a source electrode 251, a drain electrode 252, and a data line 253.
  • the drain electrode 252 is electrically connected to the corresponding source region 212 and the drain region 213 of the semiconductor layer 21
  • the data line 253 is electrically connected to the corresponding first binding terminal 11 .
  • the multiple signal lines of the driving circuit layer 20 include the gate scanning lines 232 and the data lines 253 , and different signal lines are electrically connected to different first binding terminals 11 .
  • the thin film transistor includes the semiconductor layer 21 , the gate 231 , the source 251 and the drain 252 .
  • the interlayer insulating layer 24 is patterned to form a first via hole 241, and the first via hole 241 penetrates through the interlayer insulating layer 24, the gate insulating layer 22, the buffer layer 16,
  • the second barrier layer 15 , the second substrate 14 , the first barrier layer 13 and the first binding terminal 11 are used to expose part of the first binding terminal 11 .
  • the data line 253 is electrically connected to the first binding terminal 11 through the first via hole 241, and at the same time, the data line 253 is also electrically connected to the source 251 or the drain 252.
  • the data line 253 is electrically connected to the source electrode 251 as an example for illustration.
  • the interlayer insulating layer 24 is patterned to form a second via hole 242 and a third via hole 243, and the second via hole 242 has the same structure as the first via hole 241. , that is, the second via hole 242 also penetrates through the interlayer insulating layer 24, the gate insulating layer 22, the buffer layer 16, the second barrier layer 15, the second substrate 14, the The first barrier layer 13 reaches the first binding terminal 11, so as to expose part of the first binding terminal 11.
  • the third via hole 243 penetrates through the interlayer insulating layer 24 to the gate scan line 232 to expose a part of the gate scan line 232 .
  • the source-drain layer 25 also includes a signal transfer line 254 arranged on the same layer as the data line 253, and the signal transfer line 254 passes through the second via hole 242 and the third via hole 243 to communicate with the data line 253 respectively.
  • the first binding terminal 11 is electrically connected to the gate scanning line 232 , so that the gate scanning line 232 is electrically connected to the first binding terminal 11 . It can be understood that, the gate scanning line 232 and the data line 253 are respectively connected to different first binding terminals 11 .
  • the interlayer insulating layer 24 is patterned to form a plurality of fifth via holes 244, and the plurality of fifth via holes 244 all penetrate the interlayer insulating layer 24 and the gate insulating layer 22, to expose the source region 212 and the drain region 213 respectively.
  • the source 251 is electrically connected to the source region 212 through one of the fifth via holes 244
  • the drain 252 is electrically connected to the drain region 213 through the other fifth via hole 244 .
  • the "same layer setting" in this application means that in the preparation process, the film layer formed by the same material is patterned to obtain at least two different features, and the at least two different features are the same layer settings.
  • the signal transfer line 254 and the data line 253 in this embodiment are obtained by patterning the same conductive film layer, then the signal transfer line 254 and the data line 253 are arranged on the same layer.
  • the plurality of signal lines of the driving circuit layer 20 in the present application are not limited to the data lines 253 and the gate scanning lines 232, and the plurality of signal lines may also include VSS, VDD power lines and other Various signal lines are used for display or non-display, and different signal lines are electrically connected to different first binding terminals 11 to obtain different signals.
  • the data line 253 is electrically connected to the corresponding first binding terminal 11 to obtain a source driving signal and provide it to the source 251;
  • the gate scan line 232 is connected to the corresponding first binding terminal 11.
  • the binding terminal 11 is electrically connected to obtain a gate scan signal and provide it to the gate 231 .
  • the driving circuit layer 20 further includes a planarization layer 26 covering the source-drain layer 25 and the interlayer insulating layer 24 .
  • the structure of the driving circuit layer 20 in the present application is not limited to that shown in this embodiment, the driving circuit layer 20 of the present application may also include more or fewer film layers, and the positional relationship of each film layer is not limited to this embodiment.
  • the gate layer 23 of the present application can also adopt a double gate structure, and the gate layer 23 can also be located under the semiconductor layer 21 to form a bottom gate structure.
  • the display substrate 2 in order to realize the display function of the display substrate 2 , the display substrate 2 further includes a light emitting function layer 30 disposed on the driving circuit layer 20 , and the driving circuit layer 20 It is used to provide a driving voltage to the light-emitting functional layer 30 to make the light-emitting functional layer 30 emit light.
  • the display substrate 2 further includes an encapsulation layer 40 .
  • the light emitting functional layer 30 includes a pixel electrode 31 , a pixel definition layer 32 , a light emitting unit 33 and a cathode 34 .
  • the pixel electrodes 31 are disposed on the driving circuit layer 20 and electrically connected to the corresponding thin film transistors.
  • the pixel definition layer 32 covers the pixel electrode 31 and the driving circuit layer 20, the pixel definition layer 32 has a second opening 321, and the second opening 321 exposes part of the pixel electrode 31 .
  • the pixel electrode 31 is disposed on the planarization layer 26, and is electrically connected to the source electrode 251 or the drain electrode 252 through the via hole of the planarization layer 26.
  • the embodiment is described by taking the electrical connection between the data line 253 and the source electrode 251 as an example, and correspondingly, this embodiment is described by taking the electrical connection between the pixel electrode 31 and the drain electrode 252 as an example.
  • the pixel definition layer 32 is disposed on the pixel electrode 31 and the planarization layer 26, and the pixel definition layer 32 is patterned to form the second opening 321, and the second opening 321 exposes a part
  • the pixel electrode 31 is used to define a disposition area of the light emitting unit 33 .
  • the light-emitting units 33 are formed by printing or vapor-depositing light-emitting materials in the second openings 321 of the pixel definition layer 32 , and light-emitting materials of different colors form light-emitting units 33 of different colors.
  • the light-emitting unit 33 may include a red light-emitting unit formed by a red light-emitting material, a green light-emitting unit formed by a green light-emitting material, and a blue light-emitting unit formed by a blue light-emitting material.
  • the red light-emitting unit emits red light
  • the green light-emitting unit emits green light.
  • light the blue light-emitting unit emits blue light.
  • the cathode 34 covers the light emitting unit 33 and the pixel definition layer 32 .
  • the light-emitting unit 33 emits light under the joint action of the pixel electrode 31 and the cathode 34 , and the light-emitting units 33 of different colors emit light of different colors, thereby realizing the pixel display of the display substrate 2 .
  • the pixel electrode 31 may be a transparent electrode or a reflective electrode. If the pixel electrode 31 is a transparent electrode, the pixel electrode 31 may be made of, for example, indium tin oxide (ITO), indium zinc oxide (IZO), Formation of ZnO or In2O3. If the pixel electrode 31 is a reflective electrode, the pixel electrode 31 may include, for example, a reflective layer formed of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr or a combination thereof and a reflective layer made of ITO , IZO, ZnO or In2O3 layer. However, the pixel electrode 31 is not limited thereto, and the pixel electrode 31 may be formed of various materials, and may also be formed in a single-layer or multi-layer structure.
  • the pixel electrode 31 is a transparent electrode or a reflective electrode depends on the light emitting direction of the display panel 100.
  • the pixel electrode 31 can be a transparent electrode or a reflective electrode.
  • the electrodes of course, when reflective electrodes are used, the utilization rate of light emitted by the light emitting unit 33 can be improved; when the display panel 100 adopts bottom emission, the pixel electrodes 31 use transparent electrodes to increase the transmittance of light.
  • the display panel 100 adopts top emission as an example for illustration.
  • the cathode 34 needs to be formed of a transparent conductive material.
  • the cathode 34 may be formed of transparent conductive oxide (Transparent Conductive Oxide, TCO) such as ITO, IZO, ZnO or In2O3.
  • TCO Transparent Conductive Oxide
  • the light emitting functional layer 30 may also include a hole injection layer (HIL) and a hole transport layer (HTL) disposed between the light emitting unit 33 and the pixel electrode 31; An electron injection layer (EIL) and an electron transport layer (ETL) between the light emitting unit 33 and the cathode 34 .
  • HIL hole injection layer
  • HTL hole transport layer
  • EIL electron injection layer
  • ETL electron transport layer
  • the hole injection layer receives the holes transmitted by the pixel electrode 31, the holes are transmitted to the light emitting unit 33 through the hole transport layer, the electron injection layer receives the electrons transmitted by the cathode 34, and the electrons are transmitted to the light emitting unit 33 through the electron transport layer, and the holes and The electrons combine at the position of the light emitting unit 33 to generate excitons, and the excitons transition from the excited state to the ground state to release energy and emit light.
  • the encapsulation layer 40 covers the light-emitting functional layer 30 and is used to protect the light-emitting unit 33 of the light-emitting functional layer 30 and prevent the light-emitting unit 33 from failing due to intrusion of water and oxygen.
  • the encapsulation layer 40 can be encapsulated with a thin film, for example, the encapsulation layer 40 can be a laminated structure formed by sequentially laminating three layers of thin films of a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer or more Multilayer laminated structure.
  • the display panel 100 includes a driving backplane 1 and a plurality of display substrates 2 arranged in an array on the driving backplane 1, that is, a plurality of the display substrates 2 are spliced and bound to each other. on the drive backplane 1.
  • Multiple signal lines of each of the display substrates 2 are electrically connected to the driving backplane 1 through different first binding terminals 11, specifically, the driving backplane 1 corresponds to each of the display
  • the first binding terminal 11 of the substrate 2 is provided with a second binding terminal 50, and the second binding terminal 50 is electrically connected to the first binding terminal 11, so that the display substrate 2 and the The drive backplane 1 is electrically connected.
  • the first opening 121 is provided in the binding area between the first binding terminal 11 and the second binding terminal 50
  • the auxiliary conductive layer 111 is provided in the first opening 121
  • the bridging terminal 10 is filled in the first opening 121 and is in contact with the auxiliary conductive layer 111, so that the effective contact area between the bridging terminal 10 and the first binding terminal 11 is greatly increased, thereby enabling reducing the impedance between the bridging terminal 10 and the first binding terminal 11, improving the conductivity between the first binding terminal 11 and the second binding terminal 50, and further improving the connection between the display substrate 2 and the second binding terminal 50.
  • the binding stability of the driving backplane 1 solves the problem of poor lapping between the display screen and the motherboard existing in the existing borderless splicing display technology.
  • FIG. 5 is a schematic diagram of a third partial cross-sectional structure of a display substrate provided by an embodiment of the present application.
  • the number of the first openings 121 is multiple, and each of the first openings 121 is provided with a bridging terminal 10, so the number of the bridging terminals 10 is also multiple.
  • the dimensions of the plurality of first openings 121 are the same and the plurality of first openings 121 are uniformly arranged in the binding area.
  • the contact area between the bridging terminal 10 and the first binding terminal 11 cannot meet the requirements of the bridging terminal 10 and the first binding terminal.
  • a plurality of first openings 121 can be provided in the binding area, and there is no need to vapor-deposit the auxiliary conductive layer 111 in the first openings 121, so that the bridging terminal 10 can also be satisfied.
  • the area in effective contact with the side surface of the first binding terminal 11 further meets the impedance requirement of the electrical connection between the bridging terminal 10 and the first binding terminal 11 .
  • the effective contact area between the bridging terminal 10 and the side of the first binding terminal 11 refers to the area within each of the first openings 121 where the bridging terminal 10 and the first binding terminal 11 are in contact. The sum of the areas where the sides of the binding terminal 11 are in direct contact.
  • the effective contact area between the bridging terminal 10 and the side surface of the first binding terminal 11 can be increased, thereby enabling reducing the impedance between the bridging terminal 10 and the first binding terminal 11, improving the electrical conductivity between the first binding terminal 11 and the second binding terminal 50, and further improving the connection between the display substrate 2 and the The driving backplane 1 is bound for stability.
  • the auxiliary conductive layer 111 can also be vapor-deposited in each of the first openings 121, so that the connection between the bridging terminal 10 and the first bond can be further increased.
  • the effective contact area of the side of the fixed terminal 11 better meets the impedance requirement of the electrical connection between the bridging terminal 10 and the first binding terminal 11 .
  • FIG. 6 is a schematic diagram of a fourth partial cross-sectional structure of a display substrate provided by an embodiment of the present application.
  • the first opening 121 also penetrates a part of the first barrier layer 13 to ensure that the bridging terminal 10 is fully in contact with the first binding terminal 11 .
  • the above-mentioned embodiments please refer to the above-mentioned embodiments, which will not be repeated here.
  • FIG. 7 is a schematic diagram of a fifth partial cross-sectional structure of a display substrate provided by an embodiment of the present application.
  • the thickness of the first binding terminal 11 is relatively thick.
  • the first opening 121 can be directly filled with a low-resistivity conductive material to form the bridging terminal 10, and so on Effective contact between the bridging terminal 10 and the side of the first binding terminal 11 can be achieved.
  • the area where the bridging terminal 10 is in effective contact with the side of the first binding terminal 11 is the area where the bridging terminal 10 is in direct contact with the side of the first binding terminal 11 .
  • the bridging terminal is formed by using a conductive material with low resistivity to meet the effective contact between the bridging terminal 10 and the side of the first binding terminal 11, the connection between the bridging terminal 10 and the first binding terminal 11 can be further reduced.
  • the impedance between the binding terminals 11 improves the electrical conductivity between the first binding terminal 11 and the second binding terminal 50, thereby improving the binding stability of the display substrate 2 and the driving backplane 1 .
  • FIG. 8 is a schematic diagram of a sixth partial cross-sectional structure of a display substrate provided by an embodiment of the present application.
  • the pixel definition layer 32 also has a third opening 322, the third opening 322 runs through the pixel definition layer 32, the driving circuit layer 20, and the encapsulation layer 40 fills The third opening 322 is used to increase the transmittance of this area to realize transparent display.
  • the third opening 322 penetrates through the pixel definition layer 32 and the planarization layer 26, the interlayer insulating layer 24, the gate insulating layer 22 and other film layers on the driving circuit layer 20.
  • the The third opening 322 can also penetrate through the buffer layer 16 , the second barrier layer 15 and other inorganic film layers, so as to further improve the transmittance of the display panel 100 in this area.
  • the first inorganic encapsulation layer 41 in the encapsulation layer 40 covers the wall of the third opening 322, the organic encapsulation layer 42 fills the third opening 322, and the second inorganic encapsulation layer 43 covers the wall of the third opening 322. on the organic encapsulation layer 42 .
  • the pixel definition layer 32 is also provided with a retaining wall 35, and the retaining wall 35 is used to block overflow.
  • the hole transport layer 36 will also be vapor-deposited in the third opening 322.
  • the first inorganic encapsulation layer 41 covers the hole transport layer 36 .
  • the light-emitting functional layer 30 may also include a light extraction layer 37, the light extraction layer 37 is arranged between the light-emitting unit 33 and the cathode 34, and is used to improve the light extraction of the light-emitting unit 33. efficiency.
  • the light extraction layer 37 is also disposed in the third opening 322, so that in the third opening 322, the light extraction layer 37 covers the hole transport layer 36, so The first inorganic encapsulation layer 41 covers the light extraction layer 37 .
  • the display substrate 2 further includes a color filter 60 disposed on the encapsulation layer 40 , which is used to replace a conventional polarizer to reduce the thickness of the display substrate 2 .
  • the color filter 60 includes a plurality of color filters 61 and a light-shielding layer 62 between each color filter 61.
  • the color filter 61 includes a red color filter, a green color filter, and a blue color filter, wherein the red color filter is combined with the red color filter.
  • the light-emitting unit corresponds
  • the green color film corresponds to the green light-emitting unit
  • the blue color film corresponds to the blue light-emitting unit.
  • the light shielding layer 62 is provided with a fourth opening 621 at a position corresponding to the third opening 322 .
  • the light shielding layer 62 is provided with a fourth opening 621 at a position corresponding to the third opening 322 .
  • FIG. 9 is a schematic cross-sectional structure diagram of a display device provided by an embodiment of the present application.
  • the display device 1000 includes a casing 200 and a display panel 100 according to one of the above-mentioned embodiments, the casing 200 is formed with an accommodating cavity 201 , and the display panel 100 is disposed in the accommodating cavity 201 .
  • the present application provides a display panel and a display device.
  • the display panel includes a driving backplane and a plurality of display substrates arranged in an array on the driving backplane.
  • Each of the display substrates includes a first substrate and a substrate arranged on the first substrate.
  • a plurality of first binding terminals on the display substrate are bound to the driving backplane through the first binding terminals to realize electrical connection.
  • the At least one first opening is provided on the first substrate and the first binding terminal, and the first opening penetrates through the first substrate and the first binding terminal;
  • a bridging terminal is provided in the opening, the first binding terminal is electrically connected to the drive backplane through the bridging terminal, and the bridging terminal is electrically connected to the side of the first binding terminal, so as to reduce the
  • the contact impedance between the binding terminal and the bridge terminal improves the reliability of the conduction between the display substrate and the drive backplane, and solves the problem of poor lap between the display and the motherboard existing in the existing borderless splicing display technology .

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Abstract

一种显示面板（100）和显示装置（1000）；显示面板（100）包括驱动背板（1）以及多个显示基板（2），显示基板（2）的第一衬底（12）和第一绑定端子（11）上设置有至少一个第一开孔（121），第一开孔（121）贯穿第一衬底（12）和第一绑定端子（11）；在第一开孔（121）内设置有桥接端子（10），桥接端子（10）与第一绑定端子（11）的侧面电连接，以缓解现有无边框拼接显示技术存在的显示屏与母板之间搭接不良问题。

Description

显示面板和显示装置 技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板和显示装置。
 背景技术
随着显示技术的不断发展，超大尺寸显示屏的应用越来越广泛，超大尺寸显示屏能够满足人们远距离观看、较大信息量显示等需求。出于成本的考虑，目前的超大尺寸显示屏通常采用拼接技术实现，即把多个子显示屏相互拼接形成超大尺寸显示屏。然而当多个显示屏拼接起来时，会在拼接处出现较大的黑色拼接缝隙，严重影响超大尺寸显示屏的显示品味。为了解决拼接处的黑色拼接缝隙，出现了无边框拼接显示技术，把多个显示屏相互拼接并绑定到母板上，该技术需在每个显示屏上设置绑定端子与母板绑定，而为了实现显示屏与母板之间的良好接触，可借助激光打孔把绑定端子下面的膜层去除以完全裸露出绑定端子，但长时间的激光打孔会损伤绑定端子，导致显示屏与母板之间出现搭接不良。
因此，现有无边框拼接显示技术存在的显示屏与母板之间搭接不良的问题需要解决。
 技术问题
本申请提供一种显示面板和显示装置，以缓解现有无边框拼接显示技术存在的显示屏与母板之间搭接不良的技术问题。
 技术解决方案
为解决上述问题，本申请提供的技术方案如下：
本申请实施例提供一种显示面板，包括驱动背板以及与所述驱动背板电连接的显示基板，所述显示基板包括：
第一衬底，面向所述驱动背板设置；以及
多个第一绑定端子，设置于所述第一衬底远离所述驱动背板的一侧，所述显示基板通过所述第一绑定端子与所述驱动背板绑定以实现电连接；
其中，在所述显示基板和所述驱动背板的绑定区，所述第一衬底和所述第一绑定端子上设置有至少一个第一开孔，所述第一开孔贯穿所述第一衬底和所述第一绑定端子；在所述第一开孔内设置有桥接端子，所述第一绑定端子通过所述桥接端子与所述驱动背板电连接，且所述桥接端子与所述第一绑定端子的侧面电连接。
在本申请实施例提供的显示面板中，所述显示基板还包括设置在所述第一开孔内的辅助导电层，所述第一绑定端子通过所述辅助导电层与所述桥接端子电连接。
在本申请实施例提供的显示面板中，所述辅助导电层覆盖在所述第一开孔内的所述第一衬底和所述第一开孔内的所述第一绑定端子的表面上。
在本申请实施例提供的显示面板中，所述第一开孔的数量为多个。
在本申请实施例提供的显示面板中，多个所述第一开孔均匀排布在所述绑定区。
在本申请实施例提供的显示面板中，所述显示基板还包括：
第一阻隔层，覆于所述第一绑定端子和所述第一衬底上；
驱动电路层，设置于所述第一阻隔层上，包括多个薄膜晶体管和多条信号线，所述信号线与对应的所述第一绑定端子电连接；
像素电极，设置于所述驱动电路层上，并与对应的所述薄膜晶体管电连接；
像素定义层，覆于所述像素电极以及所述驱动电路层上，所述像素定义层具有第二开孔，所述第二开孔裸露出部分所述像素电极。
在本申请实施例提供的显示面板中，所述第一开孔还贯穿部分所述第一阻隔层。
在本申请实施例提供的显示面板中，所述像素定义层还具有第三开孔，所述第三开孔贯穿所述像素定义层、所述驱动电路层。
在本申请实施例提供的显示面板中，所述驱动背板面向所述显示基板的一侧设置有第二绑定端子，所述第二绑定端子与所述第一绑定端子电连接。
在本申请实施例提供的显示面板中，所述显示基板的数量为多个，多个所述显示基板阵列排布在所述驱动背板上。
本申请实施例还提供一种显示装置，其包括壳体和前述实施例其中之一的显示面板，所述壳体形成有容纳腔，所述显示面板设置在所述容纳腔内。
 有益效果
本申请提供的显示面板和显示装置中多个显示基板阵列排布在所述驱动背板上，每个所述显示基板包括第一衬底和设置在第一衬底上的多个第一绑定端子，显示基板通过所述第一绑定端子与所述驱动背板绑定以实现电连接，在所述显示基板和所述驱动背板的绑定区，所述第一衬底和所述第一绑定端子上设置有至少一个第一开孔，所述第一开孔贯穿所述第一衬底和所述第一绑定端子；在所述第一开孔内设置有桥接端子，所述第一绑定端子通过所述桥接端子与所述驱动背板电连接，且所述桥接端子与所述第一绑定端子的侧面电连接，以降低第一绑定端子与桥接端子的接触阻抗，进而提高了显示基板和驱动背板之间导通的可靠性，解决了现有无边框拼接显示技术存在的显示屏与母板之间搭接不良问题。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的显示面板的一种俯视结构示意图。
图2为本申请实施例提供的显示面板的部分剖面结构示意图。
图3为本申请实施例提供的显示基板的第一种部分剖面结构示意图。
图4为本申请实施例提供的显示基板的第二种部分剖面结构示意图。
图5为本申请实施例提供的显示基板的第三种部分剖面结构示意图。
图6为本申请实施例提供的显示基板的第四种部分剖面结构示意图。
图7为本申请实施例提供的显示基板的第五种部分剖面结构示意图。
图8为本申请实施例提供的显示基板的第六种部分剖面结构示意图。
图9为本申请实施例提供的显示装置的剖面结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。在附图中，为了清晰理解和便于描述，夸大了一些层和区域的厚度。即附图中示出的每个组件的尺寸和厚度是任意示出的，但是本申请不限于此。
请结合参照图1至图4，图1为本申请实施例提供的显示面板的一种俯视结构示意图，图2为本申请实施例提供的显示面板的部分剖面结构示意图，图3为本申请实施例提供的显示基板的第一种部分剖面结构示意图，图4为本申请实施例提供的显示基板的第二种部分剖面结构示意图。所述显示面板100包括驱动背板1以及阵列排布在所述驱动背板1上的多个显示基板2。每个所述显示基板2包括面向所述驱动背板1的一侧设置的第一衬底12、多个第一绑定端子11、第一阻隔层13。多个第一绑定端子11设置于所述第一衬底12远离所述驱动背板1的一侧，所述第一阻隔层13覆于所述第一绑定端子11和所述第一衬底12上。所述显示基板2通过所述第一绑定端子11与所述驱动背板1绑定以实现电连接。具体地，所述驱动背板1在对应每个所述显示基板2的所述第一绑定端子11处设置有第二绑定端子50，所述第二绑定端子50和所述第一绑定端子11电连接，进而使得所述显示基板2与所述驱动背板1电连接。
为了实现所述第一绑定端子11和所述第二绑定端子50的电连接，可采用激光打孔的方式剥离掉所述第一绑定端子11下面的所述第一衬底12，使所述第一绑定端子11裸露出来，以便于所述第一绑定端子11和所述第二绑定端子50电连接。但是在激光打孔时激光能量本身波动、第一绑定端子11的材料本身厚度差异导致的表面平整度问题，使得激光打孔时仅仅靠调整激光工艺参数很难控制只去除所述第一衬底12而不伤及所述第一绑定端子11。如若部分所述第一绑定端子11被打穿，会影响所述第一绑定端子11和所述第二绑定端子50之间的导通性能。而本申请的所述显示面板100能够解决所述第一绑定端子11受损后导致的上述问题。
具体地，在所述显示基板2和所述驱动背板1的绑定区，所述第一衬底12和所述第一绑定端子11上设置有至少一个第一开孔121，所述第一开孔121贯穿所述第一衬底12和所述第一绑定端子11以裸露出部分所述第一阻隔层13。在所述第一开孔121内设置有桥接端子10，所述第一绑定端子11通过所述桥接端子10与所述驱动背板1电连接，且所述桥接端子10与所述第一绑定端子11的侧面电连接，以使所述驱动背板1和所述显示基板2电连接，避免现有无边框拼接显示技术因激光打孔导致的显示屏与母板之间搭接不良问题。其中所述第一绑定端子11的侧面是指所述第一开孔121裸露出来的所述第一绑定端子11的截面，而所述桥接端子10与所述第一绑定端子11的侧面电连接是指所述桥接端子10直接或间接与所述第一绑定端子11的侧面接触实现的导电功能。
进一步地，为了降低第一绑定端子11与桥接端子10的接触阻抗，进而提高显示基板2和驱动背板1之间导通的可靠性，所述桥接端子10与所述第一绑定端子11的侧面电连接时，所述桥接端子10与所述第一绑定端子11的侧面需满足一定的接触面积，即需满足所述桥接端子10与所述第一绑定端子11的侧面有效接触。具体而言所述桥接端子10与所述第一绑定端子11的侧面有效接触是指所述桥接端子10直接或间接与所述第一绑定端子11的侧面接触的面积，至少不小于能够满足所述桥接端子10与所述第一绑定端子11之间电连接的阻抗需求的最小面积。
下面将具体阐述如何使所述桥接端子10与所述第一绑定端子11的侧面有效接触：
可选地，所述第一开孔121在所述第一绑定端子11上的正投影落在所述第一绑定端子11的范围内，使得所述第一开孔121的尺寸小于所述第一绑定端子11的尺寸。所述第一绑定端子11的截面形状包括圆形、方形等，当所述第一绑定端子11的截面形状为圆形时，所述第一绑定端子11的尺寸即是指所述第一绑定端子11的直径；当所述第一绑定端子11的截面形状为方形时，所述第一绑定端子11的尺寸即是指所述第一绑定端子11的边长。而所述第一开孔121尺寸的定义和所述第一绑定端子11相同，具体取决于所述第一开孔121的截面形状，而所述第一开孔121的截面形状与所述第一绑定端子11的截面形状相关。
具体地，所述第一开孔121的截面形状也包括圆形、方形等，当所述第一开孔121的截面形状为圆形时，所述第一开孔121的尺寸即是指所述第一开孔121的直径；当所述第一开孔121的截面形状为方形时，所述第一开孔121的尺寸即是指所述第一开孔121的边长。可以理解的是，当所述第一开孔121的截面形状为圆形时，所述第一开孔121的内表面更圆滑，如此把导电材料填充在所述第一开孔121内形成所述桥接端子10时，则更利于所述桥接端子10的制备。
进一步地，所述第一绑定端子11通过所述桥接端子10与所述第二绑定端子50电连接，当然可选地，所述桥接端子10与所述第二绑定端子50之间还可设置辅助桥接层112，以使所述桥接端子10与所述第二绑定端子50接触良好。其中，所述第一绑定端子11、所述第二绑定端子50可使用抗氧化性强且电阻率低的金属或合金制备，如MO、Al合金等，以保证所述第一绑定端子11的稳定性。而所述桥接端子10可由导电银浆填充在所述第一开孔121内形成，所述辅助桥接层112可由导电胶材或者金属等材料制备，以保证所述第一绑定端子11与所述第二绑定端子50连接的可靠性。
可选地，为了使所述桥接端子10与所述第一绑定端子11的侧面有效接触，可在所述第一开孔121内设置辅助导电层111，所述辅助导电层111的材料可与所述第一绑定端子11的材料相同。设置所述辅助导电层111的方式包括采用蒸镀工艺等。所述辅助导电层111至少覆盖所述第一开孔121内的所述第一绑定端子11和所述第一开孔121内裸露出的所述第一阻隔层13，或者所述辅助导电层111也可至少覆盖所述第一开孔121内的所述第一绑定端子11和所述第一开孔121内的所述第一衬底12，当然地，所述辅助导电层111还可覆盖所述第一开孔121内的所述第一绑定端子11、所述第一衬底12以及裸露的所述第一阻隔层13。
所述桥接端子10填充在所述第一开孔121内，与所述辅助导电层111接触，而所述辅助导电层111蒸镀在所述第一开孔121内，相当于与所述第一绑定端子11一体式设置，如此使得所述桥接端子10与所述第一绑定端子11的侧面通过间接接触实现电连接，且所述桥接端子10与所述第一绑定端子11的侧面有效接触的面积大大提升。其中所述桥接端子10与所述第一绑定端子11的侧面有效接触的面积即指所述桥接端子10与所述辅助导电层111的接触面积。
通过提升所述桥接端子10与所述第一绑定端子11的侧面有效接触的面积，进而能够降低所述桥接端子10与所述第一绑定端子11之间的阻抗，提高所述第一绑定端子11与所述第二绑定端子50的导电性能，进而提高所述显示基板2与所述驱动背板1绑定的稳定性。
所述驱动背板1与所述显示基板2绑定，用于给所述显示基板2提供各种驱动信号。具体地，所述驱动背板1上还设置有驱动芯片（图未示）等，所述第二绑定端子50与所述驱动芯片电连接，以把所述驱动芯片的驱动信号通过所述第一绑定端子11传输给对应的所述显示基板2。如此，通过把驱动芯片等外围电路设置在所述驱动背板1上，并在每个所述显示基板2上设置第一绑定端子11，使得所述显示基板2内的各所述信号线与所述第一绑定端子11电连接，并通过对应的所述第二绑定端子50连接到所述驱动芯片，实现信号的传递。从而每个所述显示基板2无需预留边框区域来设置驱动芯片以及各种绑定走线，使得多个所述显示基板2拼接后，相邻的所述显示基板2之间不会存在较大的拼接缝隙。
下面将具体阐述所述显示基板2的膜层结构：
可选地，所述显示基板2还包括依次层叠设置在所述第一阻隔层13上的第二衬底14、第二阻隔层15、缓冲层16、驱动电路层20、像素电极31以及像素定义层32。所述第一阻隔层13、所述第二阻隔层15以及所述缓冲层16均可由氧化硅（SiOx）、氮化硅（SiNx）、氮氧化硅（SiON）等无机材料形成，以防止不期望的杂质或污染物（例如湿气、氧气等）从所述第一衬底12、所述第二衬底14扩散至可能因这些杂质或污染物而受损的器件中。而所述第一衬底12和所述第二衬底14的材料包括聚酰亚胺（Polyimide，PI）等柔性薄膜材料。同时所述缓冲层16还可以提供平坦的顶表面，以利于在所述缓冲层16上制备其他膜层结构。当然地，本申请的显示基板2不限于此，本申请的显示基板2可包括更多或更少的衬底膜层以及阻隔膜层。
所述驱动电路层20设置于所述第一阻隔层13上，更具体地，所述驱动电路层20设置于所述缓冲层16上。所述驱动电路层20包括多个薄膜晶体管和多条信号线，所述信号线与对应的所述第一绑定端子11电连接。
可选地，所述驱动电路层20包括半导体层21、栅极绝缘层22、栅极层23、层间绝缘层24以及源漏极层25，所述半导体层21设置于所述缓冲层16上，所述半导体层21包括沟道区211以及位于所述沟道区211相对两侧的源极区212和漏极区213。所述栅极绝缘层22覆于所述半导体层21及所述缓冲层16上。所述栅极层23设置于所述栅极绝缘层22上，图案化所述栅极层23形成栅极231以及栅极扫描线232等其他信号线，所述栅极231与所述半导体层21的沟道区211对应设置，所述栅极扫描线232与对应的所述第一绑定端子11电连接。所述层间绝缘层24覆于所述栅极层23及所述栅极绝缘层22上。所述源漏极层25设置于所述层间绝缘层24上，图案化所述源漏极层25形成有源极251、漏极252以及数据线253等其他信号线，所述源极251和所述漏极252分别与对应的所述半导体层21的源极区212和漏极区213电连接，所述数据线253与对应的所述第一绑定端子11电连接。其中，所述驱动电路层20的多个所述信号线包括所述栅极扫描线232和所述数据线253，不同的所述信号线与不同的所述第一绑定端子11电连接。其中所述薄膜晶体管包括所述半导体层21、所述栅极231、所述源极251和所述漏极252。
具体地，所述层间绝缘层24图案化形成有第一过孔241，所述第一过孔241贯穿所述层间绝缘层24、所述栅极绝缘层22、所述缓冲层16、所述第二阻隔层15、所述第二衬底14、第一阻隔层13直至所述第一绑定端子11，以裸露出部分所述第一绑定端子11。所述数据线253通过所述第一过孔241与所述第一绑定端子11电连接，同时所述数据线253还与所述源极251或所述漏极252电连接，本申请以所述数据线253与所述源极251电连接为例说明。
进一步地，如图3所示，所述层间绝缘层24图案化还形成有第二过孔242和第三过孔243，所述第二过孔242和所述第一过孔241结构相同，即所述第二过孔242也贯穿所述层间绝缘层24、所述栅极绝缘层22、所述缓冲层16、所述第二阻隔层15、所述第二衬底14、所述第一阻隔层13直至所述第一绑定端子11，以裸露出部分所述第一绑定端子11。所述第三过孔243贯穿所述层间绝缘层24至所述栅极扫描线232，以裸露出部分所述栅极扫描线232。所述源漏极层25还包括与所述数据线253同层设置的信号转接线254，所述信号转接线254分别通过所述第二过孔242和所述第三过孔243与所述第一绑定端子11和所述栅极扫描线232电连接，以使所述栅极扫描线232与所述第一绑定端子11电连接。可以理解的是，所述栅极扫描线232和所述数据线253分别连接不同的所述第一绑定端子11。
进一步地，所述层间绝缘层24图案化还形成有多个第五过孔244，多个所述第五过孔244均贯穿所述层间绝缘层24以及所述栅极绝缘层22，以分别裸露出所述源极区212和所述漏极区213。所述源极251通过其中一个所述第五过孔244与所述源极区212电连接，所述漏极252通过另一个所述第五过孔244与所述漏极区213电连接。
需要说明的是，本申请中的“同层设置”是指在制备工艺中，将相同材料形成的膜层进行图案化处理得到至少两个不同的特征，则所述至少两个不同的特征同层设置。比如，本实施例的所述信号转接线254与所述数据线253由同一导电膜层进行图案化处理后得到，则所述信号转接线254与所述数据线253同层设置。
另外，本申请中所述驱动电路层20的多个所述信号线不限于所述数据线253和所述栅极扫描线232，多个所述信号线还可包括VSS、VDD电源线以及其他用于显示或非显示的各种信号线，且不同的所述信号线与不同的所述第一绑定端子11电连接，以获取不同的信号。比如，所述数据线253与对应的所述第一绑定端子11电连接，以获取源极驱动信号并提供给所述源极251；所述栅极扫描线232与对应的所述第一绑定端子11电连接，以获取栅极扫描信号并提供给所述栅极231。
同时为了给所述驱动电路层20提供平坦的表面，所述驱动电路层20还包括覆于所述源漏极层25以及所述层间绝缘层24上的平坦化层26。当然地，本申请中驱动电路层20的结构不限于本实施例示意的，本申请的驱动电路层20还可包括更多或更少的膜层，且各膜层的位置关系也不限于本实施例示意的，比如本申请的所述栅极层23还可采用双栅结构，且所述栅极层23还可位于所述半导体层21的下方，形成底栅结构。
可以理解的是，如图4所示，为了实现所述显示基板2的显示功能，所述显示基板2还包括设置在所述驱动电路层20上的发光功能层30，所述驱动电路层20用于给所述发光功能层30提供驱动电压，以使所述发光功能层30发光。而为了保护所述发光功能层30的可靠性，避免水氧入侵导致发光功能层30失效，所述显示基板2还包括封装层40。
具体地，所述发光功能层30包括像素电极31、像素定义层32、发光单元33以及阴极34。所述像素电极31设置于所述驱动电路层20上，并与对应的所述薄膜晶体管电连接。所述像素定义层32覆于所述像素电极31以及所述驱动电路层20上，所述像素定义层32具有第二开孔321，所述第二开孔321裸露出部分所述像素电极31。
更具体地，所述像素电极31设置在所述平坦化层26上，并通过所述平坦化层26的过孔与所述源极251或所述漏极252电连接，当然地，由于本实施例以所述数据线253与所述源极251电连接为例说明，则相对应地，本实施例以所述像素电极31与所述漏极252电连接为例说明。所述像素定义层32设置于所述像素电极31以及所述平坦化层26上，且所述像素定义层32图案化形成所述第二开孔321，所述第二开孔321裸露出部分所述像素电极31，以定义出发光单元33的设置区域。
所述发光单元33是由打印或蒸镀在所述像素定义层32的第二开孔321内的发光材料形成，不同颜色的发光材料形成不同颜色的发光单元33。比如发光单元33可以包括由红色发光材料形成的红色发光单元，由绿色发光材料形成的绿色发光单元，由蓝色发光材料形成的蓝色发光单元，红色发光单元发出红光，绿色发光单元发出绿光，蓝色发光单元发出蓝光。
所述阴极34覆盖所述发光单元33以及所述像素定义层32。所述发光单元33在所述像素电极31和所述阴极34的共同作用下发光，不同颜色的发光单元33发射不同颜色的光，进而实现所述显示基板2的像素显示。
可选地，所述像素电极31可以是透明电极或反射电极，如果所述像素电极31是透明电极，则所述像素电极31可以由例如氧化铟锡(ITO)、氧化铟锌(IZO)、ZnO或In2O3形成。如果所述像素电极31是反射电极，则所述像素电极31例如可以包括由Ag、Mg、Al、Pt、Pd、Au、Ni、Nd、Ir、Cr或它们的组合形成的反射层以及由ITO、IZO、ZnO或In2O3形成的层。然而，像素电极31不限于此，像素电极31可以由各种材料形成，并且也可以形成为单层或多层结构。
需要说明的是，所述像素电极31具体是采用透明电极还是反射电极需取决于所述显示面板100的出光方向，当显示面板100采用顶发光时，所述像素电极31可以是透明电极或反射电极，当然地，采用反射电极时能够提高发光单元33发出光线的利用率；当显示面板100采用底发光时，所述像素电极31采用透明电极，以提高光线的透过率。本实施例以所述显示面板100采用顶发光为例说明，如此，为了提高光线的透过率，所述阴极34需采用透明导电材料形成。例如所述阴极34可由ITO、IZO、ZnO或In2O3等透明导电氧化物（Transparent Conductive Oxide，TCO）形成。
可选地，所述发光功能层30还可包括设置于所述发光单元33与所述像素电极31之间的空穴注入层(HIL)、空穴传输层(HTL)；以及设置于所述发光单元33与所述阴极34之间的电子注入层(EIL)、电子传输层(ETL)。空穴注入层接收像素电极31传输的空穴，空穴经由空穴传输层传输至发光单元33，电子注入层接收阴极34传输的电子，电子经由电子传输层传输至发光单元33，空穴和电子在发光单元33位置结合后产生激子，激子由激发态跃迁至基态释放能量并发光。
所述封装层40覆盖所述发光功能层30，用于保护所述发光功能层30的发光单元33，避免水氧入侵导致发光单元33失效。可选地，所述封装层40可采用薄膜封装，比如所述封装层40可以为由第一无机封装层、有机封装层、第二无机封装层三层薄膜依次层叠形成的叠层结构或更多层的叠层结构。
在本实施例，所述显示面板100包括驱动背板1以及阵列排布在所述驱动背板1上的多个显示基板2，也即多个所述显示基板2相互拼接并绑定在所述驱动背板1上。每个所述显示基板2的多个信号线分别通过不同的所述第一绑定端子11与所述驱动背板1电连接，具体地，所述驱动背板1在对应每个所述显示基板2的所述第一绑定端子11处设置有第二绑定端子50，所述第二绑定端子50和所述第一绑定端子11电连接，进而使得所述显示基板2与所述驱动背板1电连接。
同时，在所述第一绑定端子11和所述第二绑定端子50的绑定区设置所述第一开孔121，并在所述第一开孔121内设置所述辅助导电层111，所述桥接端子10填充在所述第一开孔121内并与所述辅助导电层111接触，使得所述桥接端子10与所述第一绑定端子11的有效接触面积大大提升，进而能够降低所述桥接端子10与所述第一绑定端子11之间的阻抗，提高所述第一绑定端子11与所述第二绑定端子50的导电性能，进而提高所述显示基板2与所述驱动背板1绑定的稳定性，从而解决了现有无边框拼接显示技术存在的显示屏与母板之间搭接不良问题。
在一种实施例中，请结合参照图1至图5，图5为本申请实施例提供的显示基板的第三种部分剖面结构示意图。与上述实施例不同的是，所述第一开孔121的数量为多个，每个所述第一开孔121内均设置有桥接端子10，则所述桥接端子10的数量也为多个。可选地，多个所述第一开孔121的尺寸相同且多个所述第一开孔121均匀排布在所述绑定区。
具体地，当所述第一绑定端子11的厚度较薄时，所述桥接端子10与所述第一绑定端子11的接触面积不能满足所述桥接端子10与所述第一绑定端子11之间电性连接的阻抗需求。此时可通过在所述绑定区设置多个所述第一开孔121，且无需再在所述第一开孔121内蒸镀所述辅助导电层111，同样能够满足所述桥接端子10与所述第一绑定端子11的侧面有效接触的面积，进而满足所述桥接端子10与所述第一绑定端子11之间的电连接的阻抗需求。其中于本实施例而言，所述桥接端子10与所述第一绑定端子11的侧面有效接触的面积是指各个所述第一开孔121内，所述桥接端子10与所述第一绑定端子11的侧面直接接触的面积之和。
下面以所述第一绑定端子11的厚度为h，所述绑定区为边长为100微米的方形区域为例说明设置多个所述第一开孔121能够满足所述桥接端子10与所述第一绑定端子11之间电连接的阻抗需求的原理。当在边长为100微米（um）的方形绑定区域设置一个开孔时，桥接端子与第一绑定端子的接触面积S1=100*h*4=400hum 2；当在边长为100微米的方形绑定区域设置多个所述第一开孔121，比如可以设置25个边长为10um的方形的所述第一开孔121，多个所述第一开孔121之间的孔间距为10um，所述桥接端子10与所述第一绑定端子的有效接触面积S2=10*h*4*25=1000hum 2。由此可见，在相同面积的绑定区，通过设置多个所述第一开孔121，能够增大所述桥接端子10与所述第一绑定端子11的侧面有效接触的面积，进而能够降低所述桥接端子10与所述第一绑定端子11之间的阻抗，提高所述第一绑定端子11与所述第二绑定端子50的导电性能，进而提高所述显示基板2与所述驱动背板1绑定的稳定性。
另外，需要说明的是，在本实施例中，每个所述第一开孔121内还可以蒸镀所述辅助导电层111，如此可进一步增大所述桥接端子10与所述第一绑定端子11的侧面有效接触的面积，更好地满足所述桥接端子10与所述第一绑定端子11之间电连接的阻抗需求。其他说明请参照上述实施例，在此不再赘述。
在一种实施例中，请参照图6，图6为本申请实施例提供的显示基板的第四种部分剖面结构示意图。与上述实施例不同的是，所述第一开孔121还贯穿部分所述第一阻隔层13，以保证所述桥接端子10与所述第一绑定端子11充分接触。其他说明请参照上述实施例，在此不再赘述。
在一种实施例中，请参照图7，图7为本申请实施例提供的显示基板的第五种部分剖面结构示意图。与上述实施例不同的是，所述第一绑定端子11的厚度较厚，此时可在所述第一开孔121内直接填充低电阻率的导电材料形成所述桥接端子10，如此同样能够实现所述桥接端子10与所述第一绑定端子11的侧面有效接触。这样所述桥接端子10与所述第一绑定端子11的侧面有效接触的面积即为所述桥接端子10与所述第一绑定端子11的侧面直接接触的面积。如此通过使用低电阻率的导电材料形成所述桥接端子在满足所述桥接端子10与所述第一绑定端子11的侧面有效接触时，还可进一步降低所述桥接端子10与所述第一绑定端子11之间的阻抗，提高所述第一绑定端子11与所述第二绑定端子50的导电性能，进而提高所述显示基板2与所述驱动背板1绑定的稳定性。其他说明请参照上述实施例，在此不再赘述。
在一种实施例中，请参照图8，图8为本申请实施例提供的显示基板的第六种部分剖面结构示意图。与上述实施例不同的是，所述像素定义层32还具有第三开孔322，所述第三开孔322贯穿所述像素定义层32、所述驱动电路层20，所述封装层40填充所述第三开孔322，以提高该区域的透过率，实现透明显示。
具体地，所述第三开孔322贯穿所述像素定义层32以及所述驱动电路层20上的平坦化层26、层间绝缘层24、栅极绝缘层22等膜层，当然地，所述第三开孔322还可贯穿缓冲层16、第二阻隔层15等无机膜层，以进一步提高显示面板100在该区域的透过率。所述封装层40中的第一无机封装层41覆盖所述第三开孔322的孔壁，所述有机封装层42填充所述第三开孔322，所述第二无机封装层43覆盖在所述有机封装层42上。另外，所述像素定义层32上还设置有挡墙35，所述挡墙35用于阻挡溢流。
可选地，当所述发光功能层30还包括空穴传输层36时，所述空穴传输层36也会蒸镀在所述第三开孔322内，此时在所述第三开孔322内，所述第一无机封装层41覆盖在所述空穴传输层36上。
可选地，所述发光功能层30还可包括光取出层37，所述光取出层37设置在所述发光单元33与所述阴极34之间，用于提高所述发光单元33的光提出效率。此时所述光取出层37也会设置在所述第三开孔322内，如此在所述第三开孔322内，所述光取出层37覆盖在所述空穴传输层36上，所述第一无机封装层41覆盖在所述光取出层37上。
进一步地，所述显示基板2还包括设置于所述封装层40上的彩色滤光片60，用于替代常规的偏光片，以减薄所述显示基板2的厚度。所述彩色滤光片60包括多个彩膜61以及位于各彩膜61之间的遮光层62，所述彩膜61包括红色彩膜、绿色彩膜、蓝色彩膜，其中红色彩膜与红色发光单元相对应，绿光彩膜与绿色发光单元相对应，蓝色彩膜与蓝色发光单元相对应。而为了提高所述第三开孔322区域的透过率，所述遮光层62在对应所述第三开孔322的位置设置第四开孔621。其他说明请参照上述实施例，在此不再赘述。
在一种实施例中，请参照图9，图9为本申请实施例提供的显示装置的剖面结构示意图。所述显示装置1000包括壳体200和上述实施例其中之一的显示面板100，所述壳体200形成有容纳腔201，所述显示面板100设置在所述容纳腔201内。
根据上述实施例可知：
本申请提供一种显示面板和显示装置，显示面板包括驱动背板以及阵列排布在驱动背板上的多个显示基板，每个所述显示基板包括第一衬底和设置在第一衬底上的多个第一绑定端子，显示基板通过所述第一绑定端子与所述驱动背板绑定以实现电连接，在所述显示基板和所述驱动背板的绑定区，所述第一衬底和所述第一绑定端子上设置有至少一个第一开孔，所述第一开孔贯穿所述第一衬底和所述第一绑定端子；在所述第一开孔内设置有桥接端子，所述第一绑定端子通过所述桥接端子与所述驱动背板电连接，且所述桥接端子与所述第一绑定端子的侧面电连接，以降低第一绑定端子与桥接端子的接触阻抗，进而提高了显示基板和驱动背板之间导通的可靠性，解决了现有无边框拼接显示技术存在的显示屏与母板之间搭接不良问题。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种显示面板，其包括驱动背板以及与所述驱动背板电连接的显示基板，所述显示基板包括：
    第一衬底，面向所述驱动背板设置；以及
    多个第一绑定端子，设置于所述第一衬底远离所述驱动背板的一侧，所述显示基板通过所述第一绑定端子与所述驱动背板绑定以实现电连接；
    其中，在所述显示基板和所述驱动背板的绑定区，所述第一衬底和所述第一绑定端子上设置有至少一个第一开孔，所述第一开孔贯穿所述第一衬底和所述第一绑定端子；在所述第一开孔内设置有桥接端子，所述第一绑定端子通过所述桥接端子与所述驱动背板电连接，且所述桥接端子与所述第一绑定端子的侧面电连接。
  2. 根据权利要求1所述的显示面板，其中，所述显示基板还包括设置在所述第一开孔内的辅助导电层，所述第一绑定端子通过所述辅助导电层与所述桥接端子电连接。
  3. 根据权利要求2所述的显示面板，其中，所述辅助导电层覆盖在所述第一开孔内的所述第一衬底和所述第一开孔内的所述第一绑定端子的表面上。
  4. 根据权利要求1所述的显示面板，其中，所述第一开孔的数量为多个。
  5. 根据权利要求4所述的显示面板，其中，多个所述第一开孔均匀排布在所述绑定区。
  6. 根据权利要求5所述的显示面板，其中，所述显示基板还包括：
    第一阻隔层，覆于所述第一绑定端子和所述第一衬底上；
    驱动电路层，设置于所述第一阻隔层上，包括多个薄膜晶体管和多条信号线，所述信号线与对应的所述第一绑定端子电连接；
    像素电极，设置于所述驱动电路层上，并与对应的所述薄膜晶体管电连接；
    像素定义层，覆于所述像素电极以及所述驱动电路层上，所述像素定义层具有第二开孔，所述第二开孔裸露出部分所述像素电极。
  7. 根据权利要求6所述的显示面板，其中，所述第一开孔还贯穿部分所述第一阻隔层。
  8. 根据权利要求6所述的显示面板，其中，所述像素定义层还具有第三开孔，所述第三开孔贯穿所述像素定义层、所述驱动电路层。
  9. 根据权利要求1所述的显示面板，其中，所述驱动背板面向所述显示基板的一侧设置有第二绑定端子，所述第二绑定端子与所述第一绑定端子电连接。
  10. 根据权利要求9所述的显示面板，其中，所述显示基板的数量为多个，多个所述显示基板阵列排布在所述驱动背板上。
  11. 一种显示装置，其包括壳体和显示面板，所述壳体形成有容纳腔；所述显示面板设置在所述容纳腔内，其中所述显示面板包括驱动背板以及与所述驱动背板电连接的显示基板，所述显示基板包括：
    第一衬底，面向所述驱动背板设置；以及
    多个第一绑定端子，设置于所述第一衬底远离所述驱动背板的一侧，所述显示基板通过所述第一绑定端子与所述驱动背板绑定以实现电连接；
    其中，在所述显示基板和所述驱动背板的绑定区，所述第一衬底和所述第一绑定端子上设置有至少一个第一开孔，所述第一开孔贯穿所述第一衬底和所述第一绑定端子；在所述第一开孔内设置有桥接端子，所述第一绑定端子通过所述桥接端子与所述驱动背板电连接，且所述桥接端子与所述第一绑定端子的侧面电连接。
  12. 根据权利要求11所述的显示装置，其中，所述显示基板还包括设置在所述第一开孔内的辅助导电层，所述第一绑定端子通过所述辅助导电层与所述桥接端子电连接。
  13. 根据权利要求12所述的显示装置，其中，所述辅助导电层覆盖在所述第一开孔内的所述第一衬底和所述第一开孔内的所述第一绑定端子的表面上。
  14. 根据权利要求11所述的显示装置，其中，所述第一开孔的数量为多个。
  15. 根据权利要求14所述的显示装置，其中，多个所述第一开孔均匀排布在所述绑定区。
  16. 根据权利要求15所述的显示装置，其中，所述显示基板还包括：
    第一阻隔层，覆于所述第一绑定端子和所述第一衬底上；
    驱动电路层，设置于所述第一阻隔层上，包括多个薄膜晶体管和多条信号线，所述信号线与对应的所述第一绑定端子电连接；
    像素电极，设置于所述驱动电路层上，并与对应的所述薄膜晶体管电连接；
    像素定义层，覆于所述像素电极以及所述驱动电路层上，所述像素定义层具有第二开孔，所述第二开孔裸露出部分所述像素电极。
  17. 根据权利要求16所述的显示装置，其中，所述第一开孔还贯穿部分所述第一阻隔层。
  18. 根据权利要求16所述的显示装置，其中，所述像素定义层还具有第三开孔，所述第三开孔贯穿所述像素定义层、所述驱动电路层。
  19. 根据权利要求11所述的显示装置，其中，所述驱动背板面向所述显示基板的一侧设置有第二绑定端子，所述第二绑定端子与所述第一绑定端子电连接。
  20. 根据权利要求19所述的显示装置，其中，所述显示基板的数量为多个，多个所述显示基板阵列排布在所述驱动背板上。
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