WO2023093740A1 - 器件芯片及其制造方法、散热基板及其制造方法、封装结构及其制造方法 - Google Patents

器件芯片及其制造方法、散热基板及其制造方法、封装结构及其制造方法 Download PDF

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Publication number
WO2023093740A1
WO2023093740A1 PCT/CN2022/133602 CN2022133602W WO2023093740A1 WO 2023093740 A1 WO2023093740 A1 WO 2023093740A1 CN 2022133602 W CN2022133602 W CN 2022133602W WO 2023093740 A1 WO2023093740 A1 WO 2023093740A1
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WIPO (PCT)
Prior art keywords
substrate
heat conduction
layer
device chip
area
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PCT/CN2022/133602
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English (en)
French (fr)
Inventor
魏涛
赖志国
杨清华
钱盈
王友良
于保宁
Original Assignee
苏州汉天下电子有限公司
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Priority claimed from CN202111396304.0A external-priority patent/CN114121828A/zh
Priority claimed from CN202111590863.5A external-priority patent/CN114388458A/zh
Application filed by 苏州汉天下电子有限公司 filed Critical 苏州汉天下电子有限公司
Publication of WO2023093740A1 publication Critical patent/WO2023093740A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon

Definitions

  • the invention relates to the technical field of semiconductors, in particular to a device chip and a manufacturing method thereof, a heat dissipation substrate and a manufacturing method thereof, a packaging structure and a manufacturing method thereof.
  • the flip package structure includes an FBAR device chip, a cap, a sealing ring 30 , a package substrate and a plastic package 50 .
  • the FBAR device chip includes a substrate 10, a resonant device on the substrate 10, and a cavity 11 between the substrate 10 and the resonant device, wherein the resonant device includes a lower electrode 12, a piezoelectric layer 13 and Upper electrode 14.
  • the cap includes a body 20 , a via structure 21 formed in the body 20 , and a solder ball 22 formed on the back of the body 20 .
  • the sealing ring 30 is formed between the FBAR device chip and the cap, and forms a sealed structure with the FBAR device chip and the cap, and the resonant device on the FBAR device chip is located in the cavity 31 of the sealed structure.
  • the package substrate includes a body 40 , a front pad 41 , a back pad 42 , and a via structure 43 electrically connecting the front pad 41 and the back pad 42 .
  • the solder balls 22 on the back of the cap are soldered to the front pads 41 of the package substrate, so as to realize the connection between the sealing structure and the package substrate.
  • the plastic package 50 is formed on the outer surface of the sealing structure to wrap the sealing structure.
  • the resonant device in the FBAR device chip generates heat during operation, and is a heat generating component of the above-mentioned flip-package structure.
  • the heat generated by the resonant device is mainly transferred to the outside of the packaging structure through the substrate.
  • Existing substrates are mainly realized by insulating materials or semiconductor materials (such as Si, SiO2, SiN, AlN, SiC, etc.). Due to the poor thermal conductivity of these materials, it is easy to cause the above-mentioned existing flip-package structure to fail to achieve efficient heat dissipation.
  • the resonant device in the FBAR device chip will pass through the plastic package in addition to the substrate.
  • the existing plastic package it is mainly made of insulating organic materials (such as epoxy resin, silicone resin, phenolic resin, polyurethane and other organic resin materials). Since the thermal conductivity of these insulating organic materials is often poor, the above-mentioned existing flip-package structure cannot achieve efficient heat dissipation. However, the inability of the flip-pack structure to efficiently dissipate heat will lead to high temperature of the heat-generating components in the flip-pack structure, which will reduce the life of the flip-pack structure, affect the reliability of the flip-pack structure, and reduce the power carrying capacity of the flip-pack structure. The rupture of the physical structure of the inverted package structure or even the failure of burning out.
  • insulating organic materials such as epoxy resin, silicone resin, phenolic resin, polyurethane and other organic resin materials. Since the thermal conductivity of these insulating organic materials is often poor, the above-mentioned existing flip-package structure cannot achieve efficient heat dissipation. However, the inability of the flip-pack structure to efficiently diss
  • the invention provides a device chip, which includes:
  • thermal conduction hole structure is formed at the bottom of the substrate structure, each of the thermal conduction hole structures includes a first blind hole formed at the bottom of the substrate structure and a first blind hole filled in the first blind hole a first thermally conductive material;
  • At least one device unit is formed on the substrate structure.
  • each of the device units is a lower electrode, a piezoelectric layer, and an upper electrode in sequence from bottom to top, and each of the device units and the substrate structure is formed Acoustic reflection structure.
  • the substrate structure sequentially includes a first substrate layer and a second substrate layer from bottom to top; the first substrate layer is formed with at least one through hole in the thickness direction, The at least one through hole and the bottom surface of the second substrate form the first blind hole; the at least one through hole is filled with the first heat conducting material.
  • the substrate structure further includes a third substrate layer formed between the first substrate layer and the second substrate layer, and the material of the third substrate layer is the second thermally conductive material.
  • the thermal conductivity of the second substrate layer material is greater than or equal to the thermal conductivity of the first substrate layer material; the first thermally conductive material and the second thermally conductive material The thermal conductivity of the material is greater than the thermal conductivity of the material of the first substrate layer.
  • the ratio of the sum of the projected areas of the thermal conduction hole structure in the horizontal direction to the projected area of the device chip in the horizontal direction ranges from 30% to 90%.
  • the first substrate layer includes core regions corresponding to the device units one by one, and each core region is located below the corresponding device unit;
  • the area of the first substrate layer other than the core area is a non-core area; wherein, the distribution density of the heat conduction hole structure in the core area is greater than the distribution density of the heat conduction hole structure in the non-core area .
  • the projected edge of each device unit in the horizontal direction and the projected edge of the core region below it in the horizontal direction form a ring shape, and the ring shape
  • the width is 100 ⁇ m or less.
  • a first interconnection structure is formed on the first substrate layer, and the first interconnection structure is formed on the In the grooves on the upper surface of the first substrate layer and interconnect the first heat-conducting material in the heat-conducting hole structure.
  • the third substrate layer includes a thermal conduction area corresponding to the device units one-to-one, and a second interconnection structure , wherein each of the heat conduction regions is located below the corresponding device unit, and the second interconnection structure forms interconnections between the heat conduction regions.
  • the ratio of the projected area of the third substrate layer in the horizontal direction to the projected area of the device chip in the horizontal direction ranges from 30% to 90%; and each There is an overlapping area between the projection of the heat conduction area in the horizontal direction and the projection of the corresponding device unit in the horizontal direction, and the projected area of the overlapping area is the same as that of the corresponding device unit in the horizontal direction.
  • the proportion of the projected area is greater than 50%.
  • the present invention also provides a manufacturing method of a device chip, the manufacturing method comprising:
  • each of the thermal conduction hole structures includes a first blind hole formed at the bottom of the substrate structure and a first blind hole filled in the first blind hole a first thermally conductive material;
  • At least one device unit is formed on the substrate structure.
  • each of the device units is a lower electrode, a piezoelectric layer, and an upper electrode in sequence from bottom to top, and each device unit and the substrate structure are formed Acoustic reflection structure.
  • the step of forming the substrate structure includes: providing a first substrate layer and forming at least one second blind hole on the upper surface of the first substrate layer; filling the blind hole with a first thermally conductive material; depositing a second substrate layer on the first substrate layer, and performing a planarization operation on the lower surface of the first substrate layer to expose the first thermally conductive material to form The substrate structure, wherein the sidewall of the second blind hole and the bottom surface of the second substrate layer form the first blind hole.
  • the step of forming the substrate structure further includes: forming a third substrate layer between the first substrate layer and the second substrate layer, the third substrate layer
  • the material is a second thermally conductive material.
  • the thermal conductivity of the second substrate layer material is greater than or equal to the thermal conductivity of the first substrate layer material; the first thermally conductive material and the second thermally conductive material The thermal conductivity of the material is greater than the thermal conductivity of the material of the first substrate layer.
  • the ratio of the sum of the projected areas of the heat conduction hole structure in the horizontal direction to the projected area of the device chip in the horizontal direction ranges from 30% to 90%.
  • the first substrate layer includes core regions corresponding to the device units one by one, and each core region is located below the corresponding device unit; A region of a substrate layer other than the core region is a non-core region; wherein, the distribution density of the heat conduction hole structures in the core region is greater than the distribution density of the heat conduction hole structures in the non-core region.
  • the projected edge of each device unit in the horizontal direction and the projected edge of the core region below it in the horizontal direction form a ring shape, and the ring shape
  • the width is 100 ⁇ m or less.
  • the step of forming the substrate structure further includes: forming a first interconnection structure on the first substrate layer, The first interconnection structure is formed in the groove on the upper surface of the first substrate layer and interconnects the first heat conduction material in the heat conduction hole structure.
  • the third substrate layer includes a heat conduction area corresponding to the device units one-to-one, and a second interconnection structure , wherein each of the heat conduction regions is located below the corresponding device unit, and the second interconnection structure forms interconnections between the heat conduction regions.
  • the ratio of the projected area of the third substrate layer in the horizontal direction to the projected area of the device chip in the horizontal direction ranges from 30% to 90%; and There is an overlapping area between the projection of the heat conduction area in the horizontal direction and the projection of the corresponding device unit in the horizontal direction, and the projected area of the overlapping area is the same as that of the corresponding device unit in the horizontal direction.
  • the proportion of the projected area is greater than 50%.
  • the present invention also provides a packaging structure, which includes:
  • a cap the front of the cap is opposite to the device chip, and the back is provided with a connecting portion;
  • a sealing ring is arranged between the device chip and the cap, and forms a sealing structure with the device chip and the cap, and the at least one device unit is located in a cavity of the sealing structure;
  • the sealing structure is connected to the packaging substrate through the connecting portion;
  • a plastic package which wraps the sealing structure.
  • the present invention also provides a manufacturing method of the packaging structure, the manufacturing method comprising:
  • the front of the cap is opposite to the device chip
  • a sealing ring is formed between the device chip and the cap, the sealing ring forms a sealing structure with the device chip and the cap, and the at least one device unit is located in a cavity of the sealing structure;
  • a plastic package wrapping the sealing structure is formed.
  • the present invention provides a heat dissipation substrate, which is used for heat dissipation of device chips, and the heat dissipation substrate includes:
  • At least one first heat conduction hole structure wherein each of the first heat conduction hole structures includes a first through hole penetrating through the substrate body in the thickness direction, and a first heat conduction material filled in the first through hole ;
  • a first connection part, the first connection part is formed on the front side of the substrate body, and the heat dissipation substrate is connected to the back side of the device chip through the first connection part.
  • the heat dissipation substrate further includes: a top heat conduction layer formed on the front surface of the substrate body; a bottom heat conduction layer formed on the back surface of the substrate body.
  • the thermal conductivity of the material of the top heat conduction layer, the material of the bottom heat conduction layer, and the first heat conduction material is higher than that of the plastic package used for device chip packaging.
  • the thermal conductivity of the body; the thermal conductivity of the material of the substrate body is higher than or equal to the thermal conductivity of the plastic package used for device chip packaging.
  • the thicknesses of the top heat conduction layer and the bottom heat conduction layer are both less than or equal to 50 ⁇ m; the thickness of the substrate body is less than or equal to 100 ⁇ m.
  • the ratio of the horizontal projected area of the top heat conducting layer to the horizontal projected area of the device chip ranges from 30% to 130%; and/or the ratio of the bottom heat conducting layer
  • the ratio of the horizontal projected area to the horizontal projected area of the device chip ranges from 30% to 130%.
  • the number of device units in the device chip is greater than or equal to 2;
  • the top heat conduction layer includes a first a heat conduction area, and a first interconnection structure for interconnecting the first heat conduction area; and/or the bottom heat conduction layer includes a second heat conduction area corresponding to each device unit in the device chip in position, And a second interconnection structure for interconnecting the second heat conduction area.
  • the heat dissipation substrate there is a first overlapping area between the horizontal projection of each of the first heat conduction regions and the corresponding horizontal projection of the device unit, and the projection of the first overlapping area
  • the ratio of the area to the horizontal projected area of the corresponding device unit is greater than 50%; and/or there is a second overlap between the horizontal projection of each of the second heat transfer regions and the corresponding horizontal projection of the device unit area, the ratio of the projected area of the second overlapping area to the horizontal projected area of the corresponding device unit is greater than 50%.
  • the ratio of the sum of the horizontal projected areas of the first thermal conduction hole structure to the horizontal projected area of the device chip ranges from 30% to 130%.
  • the heat dissipation substrate in the heat dissipation substrate, includes a first core region corresponding to each device unit in the device chip in position; the heat dissipation substrate except the first core region
  • the outer area is the first non-core area; wherein, the distribution density of the first heat conduction hole structure in the first core area is greater than or equal to the distribution density of the first heat conduction hole structure in the first non-core area.
  • the horizontal projection edge of each first core region and the corresponding horizontal projection edge of the device unit form a ring shape, and the width of the ring shape is less than or equal to 100 ⁇ m.
  • the present invention also provides a method for manufacturing a heat dissipation substrate, the heat dissipation substrate is used for heat dissipation of device chips, and the method includes:
  • At least one first heat conduction hole structure is formed on the substrate body, wherein each of the first heat conduction hole structures includes a first through hole penetrating through the substrate body in the thickness direction, and filling the first through hole a first thermally conductive material within the hole;
  • a first connection part is formed on the front surface of the substrate body, and the heat dissipation substrate is connected to the back surface of the device chip through the first connection part.
  • the manufacturing method after forming at least one first heat conduction hole structure on the substrate body, the manufacturing method further includes: forming a top heat conduction layer on the front surface of the substrate body, and The bottom heat conduction layer is formed on the back side of the substrate body.
  • the thermal conductivity of the material of the top heat conduction layer, the material of the bottom heat conduction layer, and the first heat conduction material are all higher than those of the plastic package used for device chip packaging.
  • the thermal conductivity of the body; the thermal conductivity of the material of the substrate body is higher than or equal to the thermal conductivity of the plastic package used for device chip packaging.
  • the thicknesses of the top heat conduction layer and the bottom heat conduction layer are both less than or equal to 50 ⁇ m; the thickness of the substrate body is less than or equal to 100 ⁇ m.
  • the ratio of the horizontal projected area of the top heat conducting layer to the horizontal projected area of the device chip ranges from 30% to 130%; and/or the ratio of the bottom heat conducting layer
  • the ratio of the horizontal projected area to the horizontal projected area of the device chip ranges from 30% to 130%.
  • the number of device units in the device chip is greater than or equal to 2;
  • the top heat conduction layer includes a first a heat conduction area, and a first interconnection structure for interconnecting the first heat conduction area; and/or the bottom heat conduction layer includes a second heat conduction area corresponding to each device unit in the device chip in position, And a second interconnection structure for interconnecting the second heat conduction area.
  • the manufacturing method there is a first overlapping area between the horizontal projection of each of the first heat conduction regions and the corresponding horizontal projection of the device unit, and the projection of the first overlapping area
  • the ratio of the area to the horizontal projected area of the corresponding device unit is greater than 50%; and/or there is a second overlap between the horizontal projection of each of the second heat transfer regions and the corresponding horizontal projection of the device unit area, the ratio of the projected area of the second overlapping area to the horizontal projected area of the corresponding device unit is greater than 50%.
  • the ratio of the sum of the horizontal projected areas of the first heat conduction hole structure to the horizontal projected area of the device chip ranges from 30% to 130%.
  • the heat dissipation substrate in the manufacturing method, includes a first core region corresponding to each device unit in the device chip, and each core region is located on the corresponding device unit Below; the area of the heat dissipation substrate other than the first core area is a first non-core area; wherein, the distribution density of the first heat conduction hole structure in the first core area is greater than or equal to the first non-core area The distribution density of the first heat conduction hole structure in the core area.
  • the horizontal projection edge of each first core region and the corresponding horizontal projection edge of the device unit form a ring shape, and the width of the ring shape is less than or equal to 100 ⁇ m.
  • the present invention also provides a method for manufacturing a heat dissipation substrate, the heat dissipation substrate is used for heat dissipation of device chips, and the method includes:
  • a multi-layer structure sequentially includes a top heat conduction layer, a substrate body and a bottom heat conduction layer from top to bottom;
  • At least one first heat conduction hole structure is formed on the multilayer structure, wherein each of the first heat conduction hole structures includes a first through hole penetrating through the multilayer structure in the thickness direction, and a first through hole filled in the first heat conduction hole structure. a first thermally conductive material in a through hole;
  • a first connection part is formed on the front side of the multilayer structure, and the heat dissipation substrate is connected to the back side of the device chip through the first connection part.
  • the present invention also provides a packaging structure, which includes:
  • a sealing structure includes a device chip and a cap disposed opposite to each other, and a sealing ring arranged between the device chip and the cap;
  • a first packaging substrate, the first packaging substrate is connected to the back surface of the device chip, and the first packaging substrate is realized by the aforementioned heat dissipation substrate or formed by the aforementioned manufacturing method;
  • the second packaging substrate is connected to the back of the cap
  • a plastic package the plastic package is located between the first package substrate and the second package substrate and forms a package for the sealing structure.
  • the device chip in the packaging structure, includes a substrate structure and at least one device unit; at least one second heat conduction hole structure is formed at the bottom of the substrate structure, and each of the second heat conduction holes
  • the hole structures each include a blind hole formed at the bottom of the substrate structure and a second heat-conducting material filled in the blind hole; the at least one device unit is formed on the substrate structure.
  • the substrate structure sequentially includes a first substrate layer and a second substrate layer from bottom to top; the first substrate layer is formed with at least one second via in the thickness direction.
  • the at least one second through hole and the bottom surface of the second substrate form the blind hole; the at least one second through hole is filled with the second heat-conducting material.
  • the substrate structure further includes a third substrate layer formed between the first substrate layer and the second substrate layer, and the material of the third substrate layer is the third thermally conductive material.
  • the present invention also provides a manufacturing method of the packaging structure, the manufacturing method comprising:
  • the device chip and the front of the cap are arranged oppositely, and the two are sealed by a sealing ring to form a sealing structure;
  • a plastic package enclosing the sealing structure is formed between the first package substrate and the second package substrate.
  • the bottom of the substrate structure of the device chip provided by the present invention is formed with a heat conduction hole structure made of high thermal conductivity material.
  • the heat dissipation effect of the present invention is significantly improved.
  • Implementing the manufacturing method provided by the invention can obtain device chips with high heat dissipation efficiency.
  • the packaging structure formed based on the device chip provided by the present invention and the manufacturing method thereof can effectively improve the heat dissipation efficiency of the packaging structure.
  • the heat dissipation substrate provided by the present invention includes a substrate body, at least one first heat conduction hole structure, and a first connection portion, wherein each first heat conduction hole structure includes a first through hole penetrating through the substrate body in the thickness direction, and a filling
  • the first heat conducting material in the first through hole and the first connecting portion are formed on the front surface of the substrate body.
  • the heat conduction hole structure efficiently transfers to the outside, thereby helping to improve the heat dissipation efficiency of the packaging structure.
  • the existing package structure that is, the back of the device chip is a plastic package with poor heat dissipation
  • the implementation of the present invention obviously has a better heat dissipation effect.
  • the heat dissipation substrate obtained based on the manufacturing method provided by the present invention, as well as the packaging structure formed based on the heat dissipation substrate provided by the present invention and the manufacturing method thereof have excellent heat dissipation efficiency.
  • FIG. 1 is a schematic cross-sectional view of a common inverted packaging structure in the prior art
  • Fig. 2 is a flow chart of a manufacturing method of a device chip according to a specific embodiment of the present invention
  • 3 to 9 are schematic cross-sectional views of various stages of manufacturing a device chip according to a preferred embodiment of the present invention.
  • Figure 10(a) and Figure 10(b-1) are schematic top views of the first substrate layer according to two specific embodiments of the present invention.
  • Fig. 10 (b-2) and Fig. 10 (b-3) are respectively the cross-sectional schematic diagrams of the structure shown in Fig. (b-1) along the line AA' line and BB' line;
  • FIG. 11 and FIG. 12 are schematic cross-sectional views of device chips according to two preferred embodiments of the present invention.
  • Figure 13(a) and Figure 13(b) are schematic top views of the third substrate layer according to two specific embodiments of the present invention.
  • FIG. 14 is a flow chart of a manufacturing method of a package structure according to a specific embodiment of the present invention.
  • 15 to 19 are schematic cross-sectional views of various stages of forming the packaging structure according to the method flow shown in FIG. 14;
  • Fig. 20 is a flowchart of a manufacturing method of a heat dissipation substrate according to a specific embodiment of the present invention.
  • 21(a) to 21(d) are schematic cross-sectional views of various stages of forming a heat dissipation substrate according to the method flow shown in FIG. 20;
  • Fig. 22 is a flowchart of a manufacturing method of a heat dissipation substrate according to another specific embodiment of the present invention.
  • 23(a) to 23(d) are schematic cross-sectional views of various stages of forming a heat dissipation substrate according to the method flow shown in FIG. 22;
  • FIG. 24 is a flow chart of a manufacturing method of a packaging structure according to a specific embodiment of the present invention.
  • 25(a) to 25(c) are schematic cross-sectional views of various stages of forming a packaging structure according to the method flow shown in FIG. 24;
  • Figure 26(a) and Figure 26(b) are schematic cross-sectional views of device chips according to two preferred embodiments of the present invention.
  • Fig. 27 is a schematic cross-sectional view of a package structure according to a preferred embodiment of the present invention, wherein the device chip in the package structure is realized by the structure shown in Fig. 26(b).
  • the invention provides a device chip, which includes:
  • thermal conduction hole structure is formed at the bottom of the substrate structure, each of the thermal conduction hole structures includes a first blind hole formed at the bottom of the substrate structure and a first blind hole filled in the first blind hole a first thermally conductive material;
  • At least one device unit is formed on the substrate structure.
  • the device chip provided by the present invention includes a substrate structure, and at least one thermal hole structure is formed at the bottom of the substrate structure.
  • each thermal via structure includes a blind hole (hereinafter referred to as the first blind hole) formed at the bottom of the substrate structure and a thermally conductive material (hereinafter referred to as the first thermally conductive material) filled in the first blind hole. express).
  • the first blind hole a blind hole formed at the bottom of the substrate structure
  • a thermally conductive material hereinafter referred to as the first thermally conductive material filled in the first blind hole. express.
  • the lower surface of the first heat-conducting material is flush with the lower surface of the substrate structure (the term "flush" in the present invention means that the height difference between the two is within the allowable range of process error).
  • the depth of the first blind hole is smaller than the thickness of the substrate structure, and accordingly the height of the thermal hole structure is smaller than the thickness of the substrate structure.
  • the present invention does not make any limitation on the thickness of the substrate structure and the height of the heat conduction hole structure, which can be formulated according to actual design requirements.
  • the thickness of the substrate structure is not more than 100 ⁇ m, and the height of the heat conduction hole structure is greater than 30 ⁇ m.
  • the main part of the substrate structure (that is, the part of the substrate structure other than the thermal hole structure) can be realized by using existing conventional substrate materials.
  • the existing conventional substrate materials are not listed one by one.
  • the thermal conductivity of the first thermal conductive material is higher than the thermal conductivity of the material of the main part of the substrate structure.
  • the first thermally conductive material is realized by using a metal material with high thermal conductivity, such as one of Cu, Au, Ag, Al, Ni, Fe, Mo, W or any combination thereof.
  • the first thermally conductive material should not be limited to metal materials only, and in other embodiments, non-metallic materials with higher thermal conductivity than the main part of the substrate structure are also suitable for the first thermally conductive material, for the sake of simplicity For the sake of simplicity, all possibilities of the first heat-conducting material are not listed here.
  • the first heat-conducting material it may be a single crystal material, a polycrystalline material, or a combination of a single crystal material and a polycrystalline material, which is not limited in the present invention.
  • the device chip provided by the present invention further includes at least one device unit, and the at least one device unit is formed on the substrate structure.
  • the device unit is a resonant unit, and the resonant unit is a lower electrode, a piezoelectric layer, and an upper electrode in order from bottom to top, and an acoustic reflection for acoustic wave reflection is formed between each resonant unit and the substrate structure.
  • the acoustic reflection structure may be a cavity, a Bragg reflection layer, or the like.
  • each resonance unit, the acoustic reflection structure and the substrate located below it form a bulk acoustic wave resonator.
  • the device chip may be a bulk acoustic wave filter chip, a duplexer chip, or a multiplexer chip.
  • the device units and device chips should not be limited to the above-mentioned schematic examples, and all device units that can be formed on the substrate structure fall within the protection scope of the present invention. All possible device units are listed one by one. In addition, it should be noted that the specific number of device units is determined by the actual design requirements of the device chip, which is not limited in the present invention.
  • the bottom of the substrate structure of the device chip provided by the present invention is formed with a heat conduction hole structure made of high thermal conductivity material.
  • the device chip provided by the present invention will be described in a preferred embodiment below with reference to FIG. 9 .
  • the substrate structure of the device chip provided by the present invention includes a first substrate layer 100 and a second substrate layer 105 sequentially from bottom to top.
  • the material of the first substrate layer 100 is an insulating material or a semiconductor material, such as one or any combination of Si, SiO2, SiN, AlN, SiC, and sapphire.
  • a semiconductor material such as one or any combination of Si, SiO2, SiN, AlN, SiC, and sapphire.
  • the above-mentioned Si, SiO2, SiN, AlN, SiC, and sapphire are only illustrative examples, and all existing and future materials suitable for substrates are applicable to the first substrate of the present invention.
  • the substrate layer for the sake of brevity, all possible materials of the first substrate layer are not listed here.
  • the material of the first substrate layer 100 is a semiconductor material
  • the resistivity of the semiconductor material is greater than
  • the thickness range of the first substrate layer 100 is preferably 30 ⁇ m to 100 ⁇ m.
  • the material of the second substrate layer 105 is an insulating material or a semiconductor material with high thermal conductivity, and its thermal conductivity is greater than that of the first substrate layer 100 .
  • the material of the second substrate layer 105 is a semiconductor material, preferably the resistivity of the semiconductor material is greater than
  • the thickness range of the second substrate layer 105 is preferably 3 ⁇ m to 10 ⁇ m.
  • the thermal hole structure is formed in the first substrate layer 100 .
  • the first substrate layer 100 is formed with at least one through hole penetrating through the first substrate layer 100 in the thickness direction, and the at least one through hole is filled with the first thermally conductive material 103 .
  • the upper surface and the lower surface of the first heat conducting material 103 are respectively flush with the upper surface and the lower surface of the first substrate layer 100 .
  • it forms a first blind hole together with the bottom surface of the second substrate layer 105 located at its upper opening, and further forms a heat conducting hole structure with the first heat conducting material 103 filled in the through hole . Since the thickness of the heat conduction hole structure is the same as that of the first substrate layer 100 , the height of the heat conduction hole structure is also preferably in the range of 30 ⁇ m to 100 ⁇ m.
  • the thermal conductivity of the first thermal conductive material 103 is higher than the thermal conductivity of the material of the first substrate layer 100 .
  • the first thermally conductive material 103 is preferably realized by a metal material with high thermal conductivity, such as one of Cu, Au, Ag, Al, Ni, Fe, Mo, W or any combination thereof.
  • the first heat-conducting material can also be realized by using a non-metallic material whose thermal conductivity is higher than that of the first substrate layer 100 .
  • an adhesive layer 102 is further formed between the first substrate layer 100 and the first heat-conducting material 103 .
  • the adhesion layer 102 is made of a metal material with good adhesion, preferably one of Ti, TiW, Cr or any combination thereof.
  • the thickness of the adhesive layer 102 is preferably in the range of 0.1 ⁇ m to 0.5 ⁇ m.
  • the role of the adhesion layer 102 is to improve the adhesion between the first thermally conductive material 103 and the first substrate layer 100 on the one hand, and to prevent atoms of the first thermally conductive material 103 from diffusing into the first substrate layer 100 on the other hand.
  • a seed layer (not shown) is further formed between the adhesive layer 102 and the first thermally conductive material 103 .
  • the material of the seed layer is the same as that of the first heat conducting material 103 .
  • the substrate structure of the device chip provided by the present invention further includes at least one device unit formed on the substrate structure.
  • all device units are resonant units, and each resonant unit includes a lower electrode 107a, a piezoelectric layer 108, and an upper electrode 109 from bottom to top, each resonant unit and the substrate structure A cavity 106 is formed therebetween.
  • the cavity 106 is formed in the second substrate layer 105, so its depth is less than or equal to the thickness of the second substrate layer 105;
  • the actual device chip often includes a plurality of device units, here for For the sake of simplicity, only one device unit is drawn in FIG. 9 for illustration, while other device units and connection relationships between the device units are omitted.
  • the device chip will often form a connection part (the part circled by the dotted circle) connected to the lower electrode, which is used to lead out the signal of the device unit during subsequent packaging, or for the device unit electrical connection between.
  • the portion with reference numeral 107b in FIG. 9 is formed on the edge of the substrate structure (ie, located outside the device unit), and the subsequent sealing ring is formed on this portion.
  • the heat generated by the device unit in the device chip is transferred to the outside through the heat dissipation channel on the side of the substrate structure.
  • its substrate structure is the second substrate layer 105 and the first substrate layer 100 in order from top to bottom, and the first substrate layer 100 is formed with a Thermal hole structure.
  • the thermal conductivity of the material of the second substrate layer 105 is greater than the thermal conductivity of the material of the first substrate layer 100 , which is beneficial to efficiently transfer the heat generated by the device unit to the first substrate layer 100 .
  • the thermal conductivity of the thermal hole structure in the first substrate layer 100 is greater than the thermal conductivity of the material of the first substrate layer 100 , which is conducive to efficient transfer of heat transferred to the first substrate layer 100 to the outside of the packaging structure through the thermal hole structure. In this way, a heat dissipation channel with low thermal resistance and high thermal conductivity is provided on the side of the substrate structure for the device units in the package structure.
  • the substrate structure is arranged along the heat dissipation
  • the channel direction is set as a two-layer structure of the second substrate layer 105 and the first substrate layer 100, and the thermal conductivity of the second substrate layer 105 is greater than that of the first substrate layer 100, which can further improve the heat dissipation efficiency of the package structure .
  • the thermal conductivity of the second substrate layer 105 may also be equal to the thermal conductivity of the first substrate layer 100 .
  • FIG. 10( a ) is a schematic top view of the first substrate layer according to a specific embodiment of the present invention, where the drawing of the adhesion layer and the seed layer is ignored.
  • the cross-section of the heat conduction hole structure in the horizontal direction is rectangular.
  • the projection of all heat conduction hole structures in the device chip in the horizontal direction is defined as the first projection, and the area of the first projection is called the first projected area (that is, the sum of the projected areas of all heat conduction hole structures in the horizontal direction ); and define the projection of the device chip in the horizontal direction as the second projection, and the area of the second projection is called the second projection area.
  • an area for forming a ring-shaped bonding part will be reserved on the device chip, and the ring-shaped bonding part is used for subsequent bonding with the bonding part of the cap to form a sealing ring, so that the device on the device chip The unit is sealed in the sealed space formed by the device chip, the cap and the sealing ring.
  • the outer edge of the ring-shaped bond area on the device chip is defined as the boundary of the device chip, and the projection of the outer edge of the ring-shaped bond area on the device chip in the horizontal direction is the second projection of the device chip in the horizontal direction .
  • the ratio of the first projected area of the heat conduction hole structure to the second projected area of the device chip ranges from 30% to 90%.
  • the first substrate layer 100 may be divided into core regions corresponding to device units one by one, and each core region is located below the corresponding device unit. Other regions of the first substrate layer 100 except the core region are called non-core regions.
  • the distribution density of the heat conduction hole structure in the core area is greater than the distribution density of the heat conduction hole structure in the non-core area.
  • the projection of the former in the horizontal direction is defined as the third projection
  • the projection of the latter in the horizontal direction is defined as the fourth projection.
  • the edge of the third projection and the edge of the fourth projection form a ring shape (it can be that the third projection falls within the scope of the fourth projection, or the fourth projection falls within the scope of the third projection ), the width of the annular shape is less than or equal to 100 ⁇ m.
  • the third projection of the device unit mainly refers to the projection of the lower electrode in the horizontal direction.
  • the thermal conduction hole structures can also be evenly distributed in the first substrate layer 100 as shown in FIG. 10( a ).
  • an interconnection structure (hereinafter referred to as the first interconnection structure) is also formed on the first substrate layer in the device chip substrate structure provided by the present invention, wherein the first A groove communicating with the heat conduction hole structure is formed on the upper surface of the substrate layer, and the first interconnection structure is formed in the groove so that the first heat conduction material in the heat conduction hole structure communicates with each other.
  • the first interconnection structure is also formed on the first substrate layer in the device chip substrate structure provided by the present invention, wherein the first A groove communicating with the heat conduction hole structure is formed on the upper surface of the substrate layer, and the first interconnection structure is formed in the groove so that the first heat conduction material in the heat conduction hole structure communicates with each other.
  • FIG. 10(b-3) are schematic cross-sectional views of the structure shown in FIG. (b-1) along the lines AA' and BB', respectively.
  • the first interconnection structure 103' is embedded in the groove on the upper surface of the first substrate layer 100, and the first heat conduction material 103 in each heat conduction hole structure is interconnected through the first interconnection structure 103'.
  • the first interconnection structure should not be limited to the structure shown in FIG.
  • all possibilities of the first interconnection structure are not listed here.
  • the existence of the first interconnection structure can make the heat generated by the device unit quickly transfer through all the heat conduction hole structures, thereby further improving the heat dissipation efficiency.
  • the substrate structure further includes a third substrate layer formed between the first substrate layer and the second substrate layer, and the third substrate layer is connected to the thermal hole structure in the first substrate layer.
  • the material of the third substrate layer is a thermally conductive material (hereinafter referred to as the second thermally conductive material), wherein the thermal conductivity of the second thermally conductive material is greater than that of the first substrate layer material. It is preferably realized by using a metal material with high thermal conductivity, such as one of Cu, Au, Ag, Al, Ni, Fe, Mo, W or any combination thereof.
  • the second thermally conductive material can also be realized by using non-metallic materials with higher thermal conductivity than the first substrate layer.
  • the second heat-conducting material it may be a single crystal material, a polycrystalline material, or a combination of a single crystal material and a polycrystalline material, which is not limited in the present invention.
  • the existence of the third substrate layer facilitates the transfer of heat from the second substrate layer to the first substrate layer, thereby further improving the heat dissipation efficiency.
  • the thickness range of the third substrate layer is preferably less than or equal to 50 ⁇ m.
  • the material of the third substrate layer may be different from the first thermally conductive material. As shown in FIG. 11 , the third substrate layer 104 and the first thermally conductive material 103 in the thermally conductive hole structure are two independent parts. The material of the third substrate layer may also be the same as that of the first thermally conductive material. As shown in FIG. 12 , the third substrate layer 104 and the first thermally conductive material 103 in the thermally conductive hole structure present an integrated structure.
  • the difference between the first substrate layer and the second substrate layer may be different or the same.
  • the third substrate layer 104 is a whole layer.
  • the third substrate layer includes heat conduction regions corresponding to device units one by one, and each heat conduction region is located below its corresponding device unit.
  • the third substrate layer further includes an interconnection structure (hereinafter referred to as a second interconnection structure), and the second interconnection structure interconnects the heat conduction regions. Please refer to Figure 13(a) and Figure 13(b). In FIG.
  • the third substrate layer 104 only includes the heat conduction area below the device unit, where only two device units and the heat conduction area below them are schematically drawn in the figure and other components of the device chip are ignored. part, and the device unit is a resonant unit represented by the lower electrode 107 in the figure.
  • the third substrate layer includes a heat conduction region 104a under the device unit and a second interconnection structure 104b for interconnecting the heat conduction region 104a, wherein only two device units are schematically drawn in the figure, and the The thermal conduction area under the two device units and the second interconnection structure ignore other components of the device chip, and the device unit is a resonant unit represented by the lower electrode 107 in the figure.
  • the heat conduction area under the device unit is in the form of a sheet rather than a ring.
  • the heat conduction area is in the shape of a regular pentagon Shaped area rather than ring-shaped area.
  • the heat conduction area and the second interconnection structure should not be limited to the structure shown in FIG. Shapes, etc., even irregular shapes, for the sake of brevity, all possible heat conduction regions and the second interconnection structure are not listed here.
  • the existence of the second interconnection structure can make the heat generated by the device units quickly transfer to the first substrate layer through the third substrate layer, thereby further improving the heat dissipation efficiency.
  • the projection of the third substrate layer in the horizontal direction is defined as the fifth projection, and accordingly the area of the fifth projection is called the fifth projected area; and each heat conduction area in the third substrate layer is defined as The projection in the horizontal direction is the sixth projection, and accordingly the area of the fifth projection is called the fifth projection area.
  • the ratio range of the fifth projected area of the third substrate layer to the second projected area of the device chip is 30% to 90%; and each heat conduction area
  • FIG. 2 is a flowchart of a method for manufacturing a device chip according to a specific embodiment of the present invention. As shown, the manufacturing method includes:
  • step S101 a substrate structure is formed, at least one thermal conduction hole structure is formed at the bottom of the substrate structure, each of the thermal conduction hole structures includes a first blind hole formed at the bottom of the substrate structure and a first blind hole filled in the first blind hole. a first thermally conductive material in a blind hole;
  • step S102 at least one device unit is formed on the substrate structure.
  • step S101 to step S102 will be described in detail.
  • each thermal via structure includes a blind hole (hereinafter referred to as the first blind hole) formed at the bottom of the substrate structure and a thermally conductive material (hereinafter referred to as the first thermally conductive material) filled in the first blind hole. express).
  • the first blind hole a blind hole formed at the bottom of the substrate structure
  • a thermally conductive material hereinafter referred to as the first thermally conductive material
  • the substrate may be provided first, then the lower surface of the substrate is etched to form at least one first blind hole, and finally the first blind hole is filled with a first heat-conducting material to form a heat-conducting hole structure, so far the substrate structure is formed .
  • the above examples are for illustrative purposes only, and any method that can form the above-mentioned substrate structure with a thermal hole structure at the bottom falls within the protection scope of the present invention. All implementations of step S101 are described one by one.
  • the depth of the first blind hole is smaller than the thickness of the substrate structure, and accordingly the height of the thermal hole structure is smaller than the thickness of the substrate structure.
  • the present invention does not make any limitation on the thickness of the substrate structure and the height of the heat conduction hole structure, which can be formulated according to actual design requirements.
  • the thickness of the substrate structure is not more than 100 ⁇ m, and the height of the heat conduction hole structure is greater than 30 ⁇ m.
  • the main part of the substrate structure (that is, the part of the substrate structure other than the thermal hole structure) can be realized by using existing conventional substrate materials.
  • the existing conventional substrate materials are not listed one by one.
  • the thermal conductivity of the first thermal conductive material is higher than the thermal conductivity of the material of the main part of the substrate structure.
  • the first thermally conductive material is realized by using a metal material with high thermal conductivity, such as one of Cu, Au, Ag, Al, Ni, Fe, Mo, W or any combination thereof.
  • the first thermally conductive material should not be limited to metal materials only, and in other embodiments, non-metallic materials with higher thermal conductivity than the main part of the substrate structure are also suitable for the first thermally conductive material, for the sake of simplicity For the sake of simplicity, all possibilities of the first heat-conducting material are not listed here.
  • the first heat-conducting material it may be a single crystal material, a polycrystalline material, or a combination of a single crystal material and a polycrystalline material, which is not limited in the present invention.
  • the device unit is a resonant unit
  • the resonant unit is a lower electrode, a piezoelectric layer, and an upper electrode in order from bottom to top, and an acoustic reflection for acoustic wave reflection is formed between each resonant unit and the substrate structure.
  • the acoustic reflection structure may be a cavity, a Bragg reflection layer, or the like.
  • each resonance unit, the acoustic reflection structure and the substrate located below it form a bulk acoustic wave resonator.
  • the device chip may be a bulk acoustic wave filter chip, a duplexer chip, or a multiplexer chip.
  • the device units and device chips should not be limited to the above-mentioned schematic examples, and all device units that can be formed on the substrate structure fall within the protection scope of the present invention. All possible device units are listed one by one.
  • the specific number of device units is determined by the actual design requirements of the device chip, and the present invention does not make any restrictions on this; 2) the present invention is mainly aimed at improving the substrate structure in the device chip, so There is no limitation on how to form the device unit on the substrate structure, and those skilled in the art can form the device unit on the substrate structure by using existing and possible future manufacturing methods according to the specific type of the device chip. Considering that there are many possibilities of device units and manufacturing methods, all possible forming processes of the device units will not be described here one by one.
  • a thermal conduction hole structure made of high thermal conductivity material can be formed at the bottom of the substrate structure.
  • the heat generated by the operation of the device unit in the device chip is transferred through the heat dissipation channel on the side of the substrate structure, it can be efficiently transmitted to the outside through the heat conduction hole structure in the substrate structure. Heat is transferred, thereby effectively improving the heat dissipation efficiency of the package structure.
  • the improvement of the heat dissipation efficiency of the package structure is beneficial to reduce the temperature of the device unit, thereby improving the service life, reliability and power carrying capacity of the package structure. It is especially suitable for the case where there is a cavity under the device unit.
  • a first substrate layer 100 is provided.
  • the material of the first substrate layer 100 is an insulating material or a semiconductor material, such as one or any combination of Si, SiO2, SiN, AlN, SiC, and sapphire.
  • the above-mentioned Si, SiO2, SiN, AlN, SiC, and sapphire are only illustrative examples, and all existing and future materials suitable for substrates are applicable to the first substrate of the present invention.
  • the substrate layer for the sake of brevity, all possible materials of the first substrate layer are not listed here.
  • the material of the first substrate layer 100 is a semiconductor material, preferably the resistivity of the semiconductor material is greater than
  • the upper surface of the first substrate layer 100 is etched to form at least one blind hole 101 (hereinafter referred to as a second blind hole) on the first substrate layer 100, wherein the second blind hole
  • the depth of the holes is smaller than the thickness of the first substrate layer 100 .
  • an adhesive layer 102 is deposited on the first substrate layer 100 to form an adhesive layer 102 on the upper surface of the first substrate layer 100 and the second blind hole.
  • the surface of 101 ie, the sidewall and bottom surface of the second blind hole 101 ) forms a covering.
  • the adhesion layer 102 is made of a metal material with good adhesion, preferably one of Ti, TiW, Cr or any combination thereof.
  • the thickness of the adhesive layer 102 is preferably in the range of 0.1 ⁇ m to 0.5 ⁇ m.
  • the function of the adhesive layer 102 is to improve the adhesion between the first heat-conducting material filled in the second blind hole 101 and the surface of the second blind hole 101 in subsequent steps, and on the other hand, it can also block the adhesion of the first heat-conducting material.
  • the atoms diffuse into the first substrate layer 100 . The following steps will be described based on the structure shown in FIG. 5 .
  • the second blind hole 101 is filled with a first thermally conductive material 103 , and the upper surface of the first thermally conductive material 103 is flush with the upper surface of the first substrate layer 100 .
  • the thermal conductivity of the first thermal conductive material 103 is higher than the thermal conductivity of the material of the first substrate layer 100 .
  • the first thermally conductive material 103 is preferably realized by a metal material with high thermal conductivity, such as one of Cu, Au, Ag, Al, Ni, Fe, Mo, W or any combination thereof.
  • the first heat-conducting material can also be realized by using a non-metallic material whose thermal conductivity is higher than that of the first substrate layer 100 .
  • the first heat conducting material 103 is a metal material as an example for description.
  • a metal layer is formed on the surface of the adhesion layer 102 by electroplating, and the metal layer fills the second blind hole 101; then, the metal layer on the upper surface of the first substrate layer 100 and the adhesion layer 102 are planarized until they are exposed. On the upper surface of the first substrate layer 100, only the metal layer part in the second blind hole 101 remains.
  • a seed layer (not shown) is deposited on the adhesive layer 102 , wherein the material of the seed layer is the same as that of the first thermally conductive material 103 .
  • a second substrate layer 105 is deposited on the first substrate layer 100 to cover the upper surface of the structure shown in FIG. 6 .
  • the material of the second substrate layer 105 is an insulating material or a semiconductor material with high thermal conductivity, and its thermal conductivity is greater than that of the first substrate layer 100 .
  • the material of the second substrate layer 105 is an insulating material or a semiconductor material with high thermal conductivity, and its thermal conductivity is greater than that of the first substrate layer 100 .
  • the material of the second substrate layer 105 is an insulating material or a semiconductor material with high thermal conductivity, and its thermal conductivity is greater than that of the first substrate layer 100 .
  • the material of the second substrate layer 105 is an insulating material or a semiconductor material with high thermal conductivity, and its thermal conductivity is greater than that of the first substrate layer 100 .
  • the material of the second substrate layer 105 is an insulating material or a semiconductor material with high thermal conductivity, and its thermal conductivity is greater than that of the first substrate layer 100
  • a planarization operation is performed on the lower surface of the first substrate layer 100 to expose the first heat-conducting material 103 and make the thickness of the first substrate layer 100 meet the design requirements, so far the substrate structure is formed.
  • the sidewall of the second blind hole and the bottom surface of the second substrate layer 105 constitute a first blind hole opened at the bottom of the substrate structure, and the first blind hole and the first heat conducting material 103 filled therein constitute a heat conducting hole structure.
  • the thickness of the first substrate layer 100 after the planarization operation is preferably in the range of 30 ⁇ m to 100 ⁇ m. Since the heat conduction hole structure in the substrate structure penetrates the first substrate layer 100 in the thickness direction, the height of the heat conduction hole structure is the same as the thickness of the first substrate layer 100 .
  • the second substrate layer 105 is formed first and then the lower surface of the first substrate layer 100 is planarized.
  • the first substrate layer 100 can also be planarized The lower surface of 100 is planarized and then the second substrate layer 105 is formed. Even after the acoustic reflection structure and device units are formed on the second substrate layer 105 and packaged with matching caps, the first substrate layer 100 The lower surface is planarized.
  • each device unit is formed on the substrate structure to obtain a device chip.
  • all device units are resonant units, and each resonant unit includes a lower electrode 107a, a piezoelectric layer 108, and an upper electrode 109 from bottom to top, and a cavity is formed between each resonant unit and the substrate structure 106.
  • the specific implementation process is as follows: first, the upper surface of the substrate structure (that is, the upper surface of the second substrate layer 105) is etched to form a groove, then the groove is filled with a sacrificial material, and then sequentially formed on the sacrificial material.
  • Cavity 106 It should be noted that (1) the cavity 106 is formed in the second substrate layer 105, so its depth is less than or equal to the thickness of the second substrate layer 105; (2) the actual device chip often includes a plurality of device units, Here, for the sake of simplicity, only one device unit is drawn in FIG. 9 for illustration, while other device units and the connection relationship between device units are omitted.
  • the heat generated by the device unit in the device chip is transferred to the outside through the heat dissipation channel on the side of the substrate structure.
  • its substrate structure is the second substrate layer 105 and the first substrate layer 100 in order from top to bottom, and the first substrate layer 100 is formed with a Thermal hole structure.
  • the thermal conductivity of the material of the second substrate layer 105 is greater than the thermal conductivity of the material of the first substrate layer 100 , which is beneficial to efficiently transfer the heat generated by the device unit to the first substrate layer 100 .
  • the thermal conductivity of the thermal hole structure in the first substrate layer 100 is greater than the thermal conductivity of the material of the first substrate layer 100 , which is conducive to efficient transfer of heat transferred to the first substrate layer 100 to the outside of the packaging structure through the thermal hole structure. In this way, a heat dissipation channel with low thermal resistance and high thermal conductivity is provided on the side of the substrate structure for the device units in the package structure.
  • the substrate structure is arranged along the heat dissipation
  • the channel direction is set as a two-layer structure of the second substrate layer 105 and the first substrate layer 100, and the thermal conductivity of the second substrate layer 105 is greater than that of the first substrate layer 100, which can further improve the heat dissipation efficiency of the package structure .
  • the thermal conductivity of the second substrate layer 105 may also be equal to the thermal conductivity of the first substrate layer 100 .
  • FIG. 10( a ) is a schematic top view of the first substrate layer according to a specific embodiment of the present invention, where the drawing of the adhesion layer and the seed layer is ignored.
  • the cross-section of the heat conduction hole structure in the horizontal direction is rectangular.
  • the projection of all heat conduction hole structures in the device chip in the horizontal direction is defined as the first projection, and the area of the first projection is called the first projected area (that is, the sum of the projected areas of all heat conduction hole structures in the horizontal direction ); and define the projection of the device chip in the horizontal direction as the second projection, and the area of the second projection is called the second projection area.
  • an area for forming a ring-shaped bonding part will be reserved on the device chip, and the ring-shaped bonding part is used for subsequent bonding with the bonding part of the cap to form a sealing ring, so that the device on the device chip The unit is sealed in the sealed space formed by the device chip, the cap and the sealing ring.
  • the outer edge of the ring-shaped bond area on the device chip is defined as the boundary of the device chip, and the projection of the outer edge of the ring-shaped bond area on the device chip in the horizontal direction is the second projection of the device chip in the horizontal direction .
  • the ratio of the first projected area of the heat conduction hole structure to the second projected area of the device chip ranges from 30% to 90%.
  • the first substrate layer 100 may be divided into core regions corresponding to device units one by one, and each core region is located below the corresponding device unit. Other regions of the first substrate layer 100 except the core region are called non-core regions.
  • the distribution density of the heat conduction hole structure in the core area is greater than the distribution density of the heat conduction hole structure in the non-core area.
  • the projection of the former in the horizontal direction is defined as the third projection
  • the projection of the latter in the horizontal direction is defined as the fourth projection.
  • the edge of the third projection and the edge of the fourth projection form a ring shape (it can be that the third projection falls within the scope of the fourth projection, or the fourth projection falls within the scope of the third projection ), the width of the annular shape is less than or equal to 100 ⁇ m.
  • the third projection of the device unit mainly refers to the projection of the lower electrode in the horizontal direction.
  • the thermal conduction hole structures can also be evenly distributed in the first substrate layer 100 as shown in FIG. 10( a ).
  • the step of forming the substrate structure further includes: forming an interconnection structure (hereinafter referred to as the first interconnection structure) on the first substrate layer ), the first interconnection structure is formed in the groove on the upper surface of the first substrate layer and makes the first heat conduction material in the heat conduction hole structure communicate with each other.
  • the upper surface of the first substrate layer can be etched to form a groove for communicating with the second blind hole, and the groove is filled with a thermally conductive material (it can be the first thermally conductive material, or it can be is other thermally conductive material) to form the second interconnection structure.
  • the first interconnection structure 103' is embedded in the groove on the upper surface of the first substrate layer 100, and the first heat conduction material 103 in each heat conduction hole structure is interconnected through the first interconnection structure 103'.
  • the first interconnection structure should not be limited to the structure shown in FIG.
  • all possibilities of the first interconnection structure are not listed here.
  • the existence of the first interconnection structure can make the heat generated by the device unit quickly transfer through all the heat conduction hole structures, thereby further improving the heat dissipation efficiency.
  • the step of forming the substrate structure further includes: forming a third substrate layer between the first substrate layer and the second substrate layer, and the third substrate layer is thermally conductive with the first substrate layer.
  • the material of the third substrate layer is a thermally conductive material (hereinafter referred to as the second thermally conductive material), wherein the thermal conductivity of the second thermally conductive material is greater than that of the first substrate layer material. It is preferably realized by using a metal material with high thermal conductivity, such as one of Cu, Au, Ag, Al, Ni, Fe, Mo, W or any combination thereof.
  • the second thermally conductive material can also be realized by using non-metallic materials with higher thermal conductivity than the first substrate layer.
  • the second heat-conducting material it may be a single crystal material, a polycrystalline material, or a combination of a single crystal material and a polycrystalline material, which is not limited in the present invention.
  • the existence of the third substrate layer facilitates the transfer of heat from the second substrate layer to the first substrate layer, thereby further improving the heat dissipation efficiency.
  • the thickness range of the third substrate layer is preferably less than or equal to 50 ⁇ m.
  • the third substrate layer is formed on the first substrate layer.
  • the third substrate layer 104 is formed between the first substrate layer 100 and the second substrate layer 105 .
  • the third substrate layer may also be formed while filling the second blind hole with the first heat-conducting material.
  • a metal layer is formed on the surface of the adhesion layer (or seed layer) by electroplating. By controlling the thickness of the metal layer, on the one hand, the metal layer fills the second blind hole, and on the other hand, the metal layer is formed on the first substrate layer.
  • the thickness of the part on the surface is greater than the thickness of the third substrate layer; then the metal layer is planarized until the thickness of the part of the metal layer on the surface of the first substrate layer is equal to the thickness of the third substrate layer.
  • the third substrate layer is also formed while the second blind hole is being filled.
  • the material of the third substrate layer is the first thermally conductive material, and the third substrate layer and the filling material in the second blind hole have an integrated structure.
  • the third substrate layer 104 is formed between the first substrate layer 100 and the second substrate layer 105 , and presents an integrated structure with the filling material in the second blind hole.
  • the difference between the first substrate layer and the second substrate layer may be different or the same.
  • the third substrate layer 104 is a whole layer.
  • the third substrate layer includes heat conduction regions corresponding to device units one by one, and each heat conduction region is located below its corresponding device unit.
  • the third substrate layer further includes an interconnection structure (hereinafter referred to as a second interconnection structure), and the second interconnection structure interconnects the heat conduction regions.
  • the formation process of the third substrate layer is as follows: firstly, the material of the third substrate layer is deposited on the first substrate layer, and then the material of the third substrate layer is etched to form a thermal conduction layer corresponding to the device units one by one. regions, and a second interconnection structure, wherein each heat conduction region is located below its corresponding device unit, and the second interconnection structure forms interconnection between the heat conduction regions.
  • the thickness of the first heat-conducting material located above the first substrate layer and the second blind hole is greater than the thickness of the to-be-formed blind hole through process control.
  • the thickness of the third substrate layer then planarize the first thermally conductive material above the first substrate layer and the second blind hole until the thickness is equal to the thickness of the third substrate layer to be formed, and finally place the first substrate layer and the second blind hole on the thickness of the third substrate layer.
  • the first thermally conductive material over the second blind hole is patterned to form a third substrate layer. This method realizes the deposition of the third substrate layer material while filling the second blind hole, which is beneficial to the simplification of the process. Please refer to Figure 13(a) and Figure 13(b). In FIG.
  • the third substrate layer 104 only includes the heat conduction area below the device unit, where only two device units and the heat conduction area below them are schematically drawn in the figure and other components of the device chip are ignored. part, and the device unit is a resonant unit represented by the lower electrode 107 in the figure.
  • the third substrate layer includes a heat conduction region 104a under the device unit and a second interconnection structure 104b for interconnecting the heat conduction region 104a, wherein only two device units are schematically drawn in the figure, and the The thermal conduction area under the two device units and the second interconnection structure ignore other components of the device chip, and the device unit is a resonant unit represented by the lower electrode 107 in the figure.
  • the heat conduction area under the device unit is in the form of a sheet rather than a ring.
  • the heat conduction area is in the shape of a regular pentagon Shaped area rather than ring-shaped area.
  • the heat conduction area and the second interconnection structure should not be limited to the structure shown in FIG. Shapes, etc., even irregular shapes, for the sake of brevity, all possible heat conduction regions and the second interconnection structure are not listed here.
  • the existence of the second interconnection structure can make the heat generated by the device units quickly transfer to the first substrate layer through the third substrate layer, thereby further improving the heat dissipation efficiency.
  • the projection of the third substrate layer in the horizontal direction is defined as the fifth projection, and accordingly the area of the fifth projection is called the fifth projected area; and each heat conduction area in the third substrate layer is defined as The projection in the horizontal direction is the sixth projection, and accordingly the area of the fifth projection is called the fifth projection area.
  • the ratio range of the fifth projected area of the third substrate layer to the second projected area of the device chip is 30% to 90%; and each heat conduction area
  • the present invention also provides a packaging structure, which includes:
  • a cap the front of the cap is opposite to the device chip, and the back is provided with a connecting portion;
  • a sealing ring is arranged between the device chip and the cap, and forms a sealing structure with the device chip and the cap, and the at least one device unit is located in a cavity of the sealing structure;
  • the sealing structure is connected to the packaging substrate through the connecting portion;
  • a plastic package which wraps the sealing structure.
  • the packaging structure provided by the present invention includes a device chip, and the device chip is realized by using the aforementioned device chip of the present invention.
  • the specific structure of the device chip will not be described here, and the specific structure can refer to the relevant parts above.
  • the packaging structure formed based on the device chip shown in FIG. 11 will be described below as an example.
  • the packaging structure provided by the present invention further includes a cap, and the front side of the cap is opposite to the device chip.
  • the cap includes a body 200 , a first via (TSV) structure and a connecting portion 205 .
  • the first via hole structure is formed in the body 200 , wherein the first via hole structure includes a through hole penetrating through the body 200 in the thickness direction, and a metal material 201 (such as Cu, etc.) filled in the through hole.
  • a metal material 201 such as Cu, etc.
  • an adhesion layer 202 may also be formed between the metal material 201 and the sidewall of the through hole.
  • the connection part 205 is formed on the back of the cap body 200 .
  • the connecting portion 205 is a solder ball formed on the back of the cap body 200 and is connected to the first via structure. It should be noted that, in other embodiments, grooves may also be formed on the front of the cap body 200 at positions corresponding to the device units, for keeping a sufficient distance between the device units on the device chip and the cap after packaging, so as to Make sure that the performance of the device unit is not affected.
  • the packaging structure provided by the present invention also includes a sealing ring 300a, which is arranged between the device chip and the cap, and forms a sealed structure with the device chip and the cap, and the device unit in the device chip is located Inside the cavity 301 of the sealing structure.
  • the material of the sealing ring 300a is a bonding material such as Au.
  • the sealing structure also includes a connection structure 300b located in the cavity 301, one end of the connection structure 300b is connected to the connection part of the lower electrode 107 of the device unit in the device chip, and the other end is connected to the bottom electrode 107 of the device chip.
  • the first via hole on the cap is connected for signal extraction of the device unit.
  • an adhesive layer 204 is formed between the sealing ring 300a, the connecting structure 300b and the cap, and an adhesive layer 120 is formed between the sealing ring 300a, the connecting structure 300b and the device chip.
  • the package structure provided by the present invention further includes a package substrate.
  • the packaging substrate includes a substrate body 400, a front pad 401 formed on the front side of the substrate body 400 (the surface facing the sealing structure), a back pad 402 formed on the back side of the substrate body 400, and a pad 402 formed in the substrate body 400.
  • the second via hole structure 403 is used to realize the electrical connection between the front pad 401 and the back pad 402 .
  • the front soldering pad 401 is formed on the front of the substrate body 400 at the position corresponding to the solder ball 205 on the back of the cap (that is, the connecting portion 205), and the solder ball 205 on the back of the cap is welded to the soldering ball 401 on the front of the package substrate to achieve sealing. connection of the structure to the package substrate.
  • the packaging structure provided by the present invention further includes a plastic package 500 , and the plastic package 500 forms a package for the sealing structure.
  • the material of the plastic package 500 can be realized by conventional technical means, and for the sake of brevity, details are not repeated here.
  • the corresponding packaging structure is a flip-packaging structure.
  • the packaging structure provided by the present invention is realized by using the aforementioned device chips.
  • the packaging structure provided by the present invention works, the heat generated by the device units in the device chip can efficiently transfer heat to the outside through the heat conduction hole structure in the substrate structure. Therefore, compared with the existing packaging structure, the packaging structure provided by the present invention has better heat dissipation efficiency.
  • the excellent heat dissipation efficiency makes the packaging structure provided by the present invention have a longer service life, higher reliability and stronger power carrying capacity.
  • FIG. 14 is a flowchart of a manufacturing method of a packaging structure according to a specific embodiment of the present invention. As shown, the manufacturing method includes:
  • step S201 the aforementioned device chip is provided, or the aforementioned manufacturing method is used to form the device chip;
  • step S202 a cap is provided, and the front side of the cap is opposite to the device chip;
  • a sealing ring is formed between the device chip and the cap, the sealing ring forms a sealing structure with the device chip and the cap, and the at least one device unit is located in a cavity of the sealing structure;
  • step S204 forming a connection part on the back of the cap and connecting the sealing structure to the packaging substrate through the connection part;
  • step S205 a plastic package wrapping the sealing structure is formed.
  • step S201 to step S205 will be described in detail below with reference to FIG. 15 to FIG. 19 .
  • step S201 a device chip is provided or formed, wherein the device chip is implemented by using the aforementioned device chip of the present invention or by using the aforementioned manufacturing method of the present invention.
  • the formation process of the device chip will not be described here, and the formation process can refer to the content of the relevant part above.
  • the subsequent steps will be described below by taking the device chip shown in FIG. 11 as an example.
  • the first bonding structure includes a first bonding portion 121a and a second bonding portion 121b.
  • the first bonding portion 121a is formed on the edge area of the device chip, and is used to form a sealing ring in the subsequent stage;
  • the second bonding portion 121b is formed in the inner area of the device chip, and is connected to the lower electrode 107a through a connection portion, and is used for subsequent devices
  • the signal of the unit is drawn out.
  • the first bonding portion 121a and the second bonding portion 121b are made of existing conventional bonding materials (such as Au, etc.).
  • the adhesion layer 120 is formed in the first bonding region before forming the first bonding structure.
  • a cap for cooperating with the device chip is provided, and the front side of the cap is opposite to the device chip.
  • the cap includes a body 200 and a first via (TSV) structure.
  • the first via hole structure is formed in the body 200 , wherein the first via hole structure includes a through hole penetrating through the body 200 in the thickness direction, and a metal material 201 (such as Cu, etc.) filled in the through hole.
  • a metal material 201 such as Cu, etc.
  • an adhesion layer 202 may also be formed between the metal material 201 and the sidewall of the through hole.
  • a second bonding structure is also formed on the cap.
  • the second bonding structure is formed on the front surface of the body 200 and forms a connection with the first via hole structure, wherein the second bonding structure includes a first bonding portion with the device chip.
  • the third bonding portion 203a and the fourth bonding portion 203b are made of existing conventional bonding materials (such as Au, etc.).
  • an adhesive layer 204 is formed between the second bonding structure and the cap body 200 .
  • grooves may also be formed on the front of the cap body 200 at positions corresponding to the device units, for keeping a sufficient distance between the device units on the device chip and the cap after packaging, so as to Make sure that the performance of the device unit is not affected.
  • step S203 the third bonding portion 203a of the cap is aligned with the first bonding portion 121a of the device chip, and the fourth bonding portion 203b of the cap is aligned with the second bonding portion 203b of the device chip.
  • the bonding portion 121b is aligned, and then the cap and the device chip are bonded and fixed.
  • the third bonding portion 203a of the cap is bonded to the first bonding portion 121a of the device chip to form a sealing ring 300a
  • the sealing ring 300a forms a sealed structure with the cap and the device chip
  • the device unit in the device chip is located Inside the cavity 301 of the sealing structure.
  • the fourth bonding portion 203b of the cap is bonded to the second bonding portion 121b of the device chip to form a connection structure 300b for signal extraction, and the connection structure 300b is also located in the cavity 301 of the sealing structure.
  • a connection portion 205 is formed on the back of the cap and the sealing structure is connected to the package substrate through the connection portion 205 .
  • the connecting portion 205 is a solder ball, which is formed on the back of the cap body 200 and connected to the first via hole structure.
  • the package substrate includes a substrate body 400, a front pad 401 formed on the front side of the substrate body 400 (the surface facing the sealing structure), a back pad 402 formed on the back side of the base 400, and a front pad formed in the substrate body 400 for realizing the front pad. 401 and the second via hole structure 403 electrically connected to the back pad 402 .
  • the front pad 401 is formed on the front of the substrate body 400 at the position corresponding to the solder ball 205 on the back of the cap, and the solder ball 205 on the back of the cap is soldered to the front pad 401 of the package substrate to realize the connection between the sealing structure and the package substrate .
  • step S205 as shown in FIG. 19 , the sealing structure is plastic-encapsulated to form a plastic-encapsulation body 500 wrapping the sealing structure.
  • the implementation process of the plastic package and the material of the plastic package 500 can be realized by conventional technical means, and for the sake of brevity, details are not repeated here.
  • a step of planarizing the lower surface of the first substrate layer 100 to expose the first thermally conductive material 103 is included. In some application scenarios, this step can also be performed after the cap and the device chip are bonded to form a sealing structure.
  • the encapsulation structure formed by implementing the manufacturing method provided by the present invention has good heat dissipation efficiency.
  • the heat dissipation substrate provided by the present invention is used for packaging device chips. Specifically, when the device chip is packaged, the heat dissipation substrate is installed on the back of the device chip to improve the heat dissipation effect of the heat dissipation channel on the substrate side of the package structure.
  • the present invention does not impose any limitation on the specific type of the device chip, and any device chip that has at least one device unit that generates heat during operation and needs to be packaged is applicable to the present invention.
  • the device unit can be a resonant unit, and the resonant unit is a lower electrode, a piezoelectric layer, and an upper electrode from bottom to top, and an acoustic reflection structure (for example, a hollow space) for acoustic wave reflection is formed between each resonant unit and the substrate. cavities, Bragg reflectors, etc.).
  • each resonance unit, the acoustic reflection structure and the substrate located below it form a bulk acoustic wave resonator.
  • the device chip may be a filter chip, a duplexer chip, a multiplexer chip, a sensor chip, and the like.
  • the device units and device chips should not be limited to the above schematic examples, and for the sake of brevity, all possible device units and device chips are not listed here.
  • the heat dissipation substrate provided by the present invention will be described below by taking the device unit as a resonance unit and the device chip as a filter as an example.
  • the invention provides a heat dissipation substrate, which includes:
  • At least one first heat conduction hole structure wherein each of the first heat conduction hole structures includes a first through hole penetrating through the substrate body in the thickness direction, and a first heat conduction material filled in the first through hole ;
  • the first connection part is formed on the front surface of the substrate body, and the heat dissipation substrate is connected to the back surface of the device chip through the first connection part.
  • the heat dissipation substrate provided by the present invention includes a substrate body 500 .
  • the substrate body 500 is realized by using insulating material or semiconductor material.
  • the specific type of the substrate body 500 is related to its realization material.
  • the substrate body can be a hard substrate body realized by materials such as BT (bismaleimide triazine resin), ABF, MIS, etc., and can be a single crystal body such as AlN, SiC, GaN, Si, Al2O3, etc.
  • the ceramic substrate body realized by polycrystalline material can also be a flexible substrate body realized by materials such as PI (polyimide resin), PE (polyester resin), PPO (diphenylene ether resin), PCH resin and the like.
  • PI polyimide resin
  • PE polyyester resin
  • PPO diphenylene ether resin
  • PCH resin PCH resin
  • PI polyimide resin
  • PE polyyester resin
  • PPO diphenylene ether resin
  • PCH resin PCH resin
  • the thickness of the substrate body 500 is preferably less than or equal to 100 ⁇ m.
  • the thermal conductivity of the material of the substrate body 500 needs to be higher than or equal to the thermal conductivity of the plastic package material.
  • the heat dissipation substrate provided by the present invention further includes at least one heat conduction hole structure (hereinafter referred to as a first heat conduction hole structure).
  • each first heat conduction hole structure includes a through hole (hereinafter referred to as a first through hole) penetrating through the substrate body 500 in the thickness direction, and a heat conduction material 502 filled in the first through hole ( Hereinafter, it is represented by the first thermally conductive material 502).
  • the upper surface and the lower surface of the first heat conduction material 502 are respectively flush with the two surfaces of the substrate body 500 , that is, the height of the first heat conduction hole structure is the same as the thickness of the substrate body 500 .
  • the first thermally conductive material 502 is preferably realized by metal materials with high thermal conductivity and combinations thereof, such as one of Cu, Au, Ag, Al, Ni, Ti, Cr, TiW, Fe, Mo, W or any combination thereof.
  • the first heat-conducting material 502 can also be realized by using alloy materials and combinations thereof, or non-metallic materials with higher thermal conductivity than the substrate body 500 .
  • the heat dissipation substrate provided by the present invention further includes a connection portion (hereinafter referred to as a first connection portion) formed on the front surface of the substrate body 500 .
  • a connection portion hereinafter referred to as a first connection portion
  • the surface used to connect with the device chip when the heat dissipation substrate is mounted is defined as the front side of the substrate body, and the other surface corresponding to the front side of the substrate body is defined as the back side of the substrate body.
  • the first connection portion includes a plurality of first connection units, and each connection unit further includes bumps 503 and solder balls 504 .
  • the bump 503 is formed on the front surface of the heat dissipation substrate, and is preferably connected to the first heat conduction hole structure; the solder ball 504 is formed on the bump 503 .
  • the heat dissipation substrate is welded to the back surface of the device chip through the first connecting portion.
  • both the bumps 503 and the solder balls 504 are made of materials with high thermal conductivity.
  • the material of the bump 503 can be, for example, Au, Cu, etc.
  • the material of the solder ball 504 can be, for example, SnAg, SnPb, SnCu, Au—Sn solder, Au—Ge solder, Au—Si solder, etc.
  • the height range of the solder balls 504 is preferably not more than 100 ⁇ m. It should be noted that (1) the first connection unit may also only include solder balls 504; (2) the first connection unit should not be limited to the above-mentioned bumps 503 and solder balls 504, any one that can be used to connect the substrate body 500 to A device chip and a structure with good thermal conductivity are applicable to the first connection part of the present invention, and for the sake of brevity, all possible structures of the first connection part are not listed here.
  • the heat dissipation substrate is connected to the back side of the device chip (i.e., the bottom surface of the substrate) through the first connection part on the front side, wherein the first heat conduction hole structure penetrating the substrate body forms an efficient heat dissipation on the substrate side.
  • the heat generated by the device chip can efficiently transfer heat to the outside through the first thermal hole structure on the substrate side, thereby effectively improving the heat dissipation efficiency of the packaging structure.
  • the heat dissipation effect of the heat dissipation substrate provided by the present invention is obviously better.
  • an adhesive layer (not shown) is formed on both surfaces of the substrate body, and the adhesive layer covers the surface of the substrate body and the first thermal hole structure.
  • the adhesion layer is made of a metal material with good adhesion, such as one of Ti, TiW, Cr or any combination thereof.
  • the thickness of the adhesive layer is preferably in the range of 0.1 ⁇ m to 0.5 ⁇ m.
  • the heat dissipation substrate provided by the present invention further includes a top heat conduction layer 505 and a bottom heat conduction layer 506, wherein the top heat conduction layer 505 is formed on the front of the substrate body 500, and the bottom heat conduction layer 506 is formed on the back of the substrate body 500 . More preferably, the top heat conduction layer 505 and the bottom heat conduction layer 506 are respectively connected to the first heat conduction hole structure in the substrate body 500 .
  • top heat conduction layer 505 is conducive to the rapid transfer of heat to the substrate body 500 and the first heat conduction hole structure, and the formation of the bottom heat conduction layer 506 is useful for quickly transferring the heat in the substrate body 500 and the first heat conduction hole structure to the external space .
  • the top heat conduction layer or only the bottom heat conduction layer may be included.
  • the materials of the top thermal conduction layer 505 and the bottom thermal conduction layer 506 are both made of materials with a thermal conductivity higher than that of the plastic package material used for device chip packaging, preferably metal materials with high thermal conductivity and combinations thereof, such as Cu, Au , Ag, Al, Ni, Ti, Cr, TiW, Fe, Mo, W or any combination thereof.
  • the materials of the top heat conduction layer 505 and the bottom heat conduction layer 506 can also be realized by alloy materials and combinations thereof, or non-metal materials with higher thermal conductivity than the substrate body 500 .
  • the material of the top heat conduction layer 505 , the first heat conduction material 502 , and the material of the bottom heat conduction layer 506 can be the same or different.
  • the thickness ranges of the top heat conduction layer 505 and the bottom heat conduction layer 506 are preferably less than or equal to 50 ⁇ m. It should be noted here that, for the case where the heat dissipation substrate includes a top heat conduction layer and a bottom heat conduction layer, the adhesive layer is formed on the top heat conduction layer and the bottom heat conduction layer.
  • the top thermally conductive layer 505 is a monolithic layer.
  • the top heat conducting layer 505 may also be mainly formed on the position corresponding to the device unit.
  • the top heat conduction layer 505 includes a heat conduction region (hereinafter referred to as a first heat conduction region) corresponding to each device unit in the device chip in position.
  • the positional correspondence between the first heat conduction area and its corresponding device unit means that after the heat dissipation substrate is installed on the device chip, the first heat conduction area in the top heat conduction layer 505 is located above its corresponding device unit (flip package structure heat dissipation The substrate sits above the device die). Since the main heat-generating component of the device chip is the device unit, setting the first heat conduction area at a position corresponding to the device unit facilitates rapid transfer of heat generated by the device unit.
  • the first heat conduction area is only formed on the position corresponding to the device unit, although the heat dissipation effect may be weakened to a certain extent, but it can effectively reduce the heat dissipation of the top heat conduction layer 505.
  • Materials are used so as to reduce the manufacturing cost of the heat dissipation substrate. Those skilled in the art can balance the heat dissipation effect and manufacturing cost according to actual requirements, which is not limited in the present invention.
  • the number of device units in the device chip is greater than 1
  • the number of first heat conduction regions in the top heat conduction layer 505 is also greater than 1.
  • An interconnected interconnection structure hereinafter referred to as a first interconnection structure).
  • the arrangement of the first interconnection structure can enable the heat generated by the device units to be quickly transferred between the first heat conduction regions, which is beneficial to the improvement of heat dissipation efficiency.
  • the first overlapping area there is an overlapping area (hereinafter referred to as the first overlapping area) between the horizontal projection of each first heat conduction area and the horizontal projection of the corresponding device unit.
  • the projected area of the first overlapping area and The proportion of the horizontal projected area of the corresponding device units is preferably greater than 50%.
  • the horizontal projection of the device unit mainly refers to the horizontal projection of the lower electrode.
  • the bottom heat conduction layer 506 may be a whole layer, or may include a heat conduction area corresponding to each device unit in the device chip (hereinafter referred to as the second heat conduction area).
  • the second heat conduction area corresponds to the position of the corresponding device unit means that when the heat dissipation substrate is mounted on the device After being placed on the chip, the second heat conduction area in the bottom heat conduction layer 506 is located above its corresponding device unit (the heat dissipation substrate of the flip-package structure is located above the device chip).
  • the main heat-generating component of the device chip is the device unit
  • setting the second heat conduction area at a position corresponding to the device unit is beneficial to quickly transfer the heat generated by the device unit to the external space.
  • the second heat conduction area is only formed on the position corresponding to the device unit, although the heat dissipation effect may be weakened to a certain extent, but it can effectively reduce the heat dissipation of the bottom heat conduction layer 506.
  • Materials are used so as to reduce the manufacturing cost of the heat dissipation substrate. Those skilled in the art can balance the heat dissipation effect and manufacturing cost according to actual requirements, which is not limited in the present invention.
  • the bottom heat conduction layer 506 also includes an An interconnected interconnection structure (hereinafter referred to as a second interconnection structure).
  • the arrangement of the second interconnection structure can make the heat in the substrate body and the first heat conduction hole structure transfer quickly between the second heat conduction area, which is beneficial to the improvement of heat dissipation efficiency.
  • there is an overlapping area hereinafter referred to as the second overlapping area
  • the projected area of the second overlapping area is the same as The proportion of the horizontal projected area of the corresponding device units is preferably greater than 50%.
  • the ratio of the horizontal projected area of the top heat conduction layer 505 to the horizontal projected area of the device chip is 30 % to 130%.
  • the ratio of the horizontal projected area of the bottom heat conduction layer 506 to the horizontal projected area of the device chip is 30% to 130%.
  • the edge of the device chip will reserve an area for forming a ring-shaped bonding part, and the ring-shaped bonding part is used for subsequent bonding with the bonding part of the cap to form a sealing ring,
  • the device unit on the device chip is sealed in the sealed space formed by the device unit, the cap and the sealing ring, wherein the outer edge of the annular bonding portion on the device chip is defined as the boundary of the device chip, and correspondingly the boundary of the boundary Horizontal projection is defined as the horizontal projection of the device chip.
  • the ratio of the horizontal projected area of the top heat conduction layer and the bottom heat conduction layer to the horizontal projected area of the device chip may be greater than 100%.
  • the ratio of the sum of the horizontal projected areas of all the first heat conduction hole structures to the horizontal projected area of the device chip ranges from 30% to 130%, which is beneficial for the first heat conduction hole structure to achieve efficient heat transfer.
  • the ratio of the sum of the horizontal projected areas of the first thermal hole structure to the horizontal projected area of the device chip may be greater than 100%.
  • the heat dissipation substrate can be divided into a non-core area (hereinafter referred to as the first non-core area) and a core area (hereinafter referred to as the first core area) corresponding to the device units in the device chip in one-to-one position.
  • the corresponding position of the first core region and its corresponding device unit means that after the heat dissipation substrate is installed on the device chip, the first core region in the heat dissipation substrate is located above its corresponding device unit (the heat dissipation substrate of the flip-down package structure is located above the device chip).
  • the distribution density of the first heat conduction hole structures in the first core region is greater than or equal to the distribution density of the first heat conduction hole structures in the first non-core region.
  • the horizontal projection edge of the first core region and the horizontal projection edge of the corresponding device unit form a ring shape (that is, the horizontal projection of the former falls into the horizontal projection of the latter, or the horizontal projection of the latter falls into In the horizontal projection of the former), the width of the annular shape is less than or equal to 100 ⁇ m.
  • the horizontal projections of the first core region and its corresponding device units can also coincide exactly.
  • the first heat conduction hole structures may also be evenly distributed in the heat dissipation substrate.
  • the invention also provides a manufacturing method of the heat dissipation substrate, wherein the heat dissipation substrate is used for heat dissipation of device chips.
  • FIG. 20 is a flowchart of a manufacturing method of a heat dissipation substrate according to a specific embodiment of the present invention. As shown, the manufacturing method includes:
  • step S301 a substrate body is provided
  • step S302 at least one first heat conduction hole structure is formed on the substrate body, wherein each of the first heat conduction hole structures includes a first through hole penetrating through the substrate body in the thickness direction, and a filling a first thermally conductive material within the first through hole;
  • step S303 a first connection portion is formed on the front surface of the substrate body, and the heat dissipation substrate is connected to the back surface of the device chip through the first connection portion.
  • step S301 to step S303 will be described in detail below with reference to FIG. 21( a ) to FIG. 21( d ).
  • the following only describes the manufacturing method of each component in the heat dissipation substrate, and the specific material, shape, size, etc. of each component can refer to the relevant content in the previous description of the structure of the heat dissipation substrate. For the sake of brevity, the description will not be repeated here.
  • step S301 a substrate body 500 is provided as shown in FIG. 21(a).
  • step S302 first, as shown in FIG. 21( b ), at least one first through hole 501 penetrating through the substrate body 500 is formed on the substrate body 500 .
  • the present invention does not make any limitation on the implementation of the first through hole 501, for example, it can be formed by laser drilling (CO2 laser drilling, excimer laser drilling, solid-state laser drilling, etc.), and mechanical drilling can also be used. way to form.
  • the surface of the first through hole 501 is ground and polished after laser drilling or mechanical drilling.
  • a first heat conduction material 502 is filled in the first through hole 501 to form a first heat conduction hole structure.
  • the steps of filling the first through-hole 501 with the first heat-conducting material 502 are as follows: First, a very thin layer of the first heat-conducting material is chemically plated on the surface of the first through-hole 501, and its thickness ranges from 0.1 ⁇ m to 0.3 ⁇ m; then continue to electroplate the first heat-conducting material on the surface of the electroless plating layer until the first heat-conducting material completely fills the first through hole 501; finally, polish the first heat-conducting material and clean the surface of the substrate body. So far the first thermal hole structure is formed.
  • a first connection portion for connecting with the device chip during packaging is formed on the front surface of the substrate body 500 .
  • the first connection portion includes a plurality of first connection units, and each connection unit further includes a bump 503 formed on the front surface of the substrate body 500 and a solder ball 504 formed on the bump 503 .
  • the bumps 503 can be formed by electroplating, and the solder balls 504 can be formed by solder printing or glue dispensing.
  • the heat dissipation substrate formed based on the manufacturing method provided by the present invention can realize efficient heat dissipation due to the first heat conducting hole structure penetrating through the substrate body.
  • the manufacturing method provided by the present invention further includes: forming a top heat conduction layer on the front surface of the substrate body, and forming a bottom heat conduction layer on the back surface of the substrate body.
  • the formation of the top heat conduction layer facilitates the rapid transfer of heat to the substrate body and the first heat conduction hole structure
  • the formation of the bottom heat conduction layer facilitates the rapid transfer of heat from the substrate body and the first heat conduction hole structure to the external space.
  • the top heat conduction layer can be formed only on the front of the substrate body, or the bottom heat conduction layer can be formed only on the back of the substrate body.
  • the manufacturing method provided by the present invention further includes forming an adhesive layer.
  • the adhesive layer is formed on the surface of the top heat conduction layer and/or the bottom heat conduction layer.
  • the adhesive layer may be directly formed on the surface of the substrate body.
  • the top heat conduction layer may be a whole layer, or may include a first heat conduction region corresponding to each device unit in the device chip in position.
  • the top heat conduction layer including the first heat conduction area corresponding to each device unit in the device chip since the main heat generating component of the device chip is the device unit, the first heat conduction area is set to correspond to the device unit The location is conducive to the rapid transfer of heat generated by the device unit.
  • the top heat conduction layer also includes interconnecting parts or all of the first heat conduction regions.
  • the first interconnection structure (hereinafter referred to as the first interconnection structure).
  • the arrangement of the first interconnection structure can enable the heat generated by the device units to be quickly transferred between the first heat conduction regions, which is beneficial to the improvement of heat dissipation efficiency. It should be noted that there is a first overlapping area between the horizontal projection of each first heat conduction region and the horizontal projection of its corresponding device unit. In order to ensure the heat dissipation effect, the projected area of the first overlapping area is the same as the horizontal The proportion of projected area is preferably greater than 50%. It should be noted here that the first heat conduction region and the first interconnection structure can be obtained by forming a layer of top heat conduction layer material on the surface of the substrate body and then patterning it.
  • the bottom heat conduction layer may be a whole layer, or may include a second heat conduction region corresponding to each device unit in the device chip in position.
  • the bottom heat conduction layer including the second heat conduction area corresponding to each device unit in the device chip since the main heat generating component of the device chip is the device unit, the second heat conduction area is set to correspond to the device unit In terms of location, it is beneficial to quickly transfer the heat generated by the device unit to the external space.
  • the number of device units in the device chip is greater than 1
  • the number of the second heat conduction regions in the bottom heat conduction layer is also greater than 1.
  • the bottom heat conduction layer also includes a part or all of the second heat conduction regions. Second interconnection structure.
  • the arrangement of the second interconnection structure can make the heat in the substrate body and the first heat conduction hole structure transfer quickly between the second heat conduction area, which is beneficial to the improvement of heat dissipation efficiency. It should be noted that there is a second overlapping area between the horizontal projection of each second heat conduction area and the horizontal projection of its corresponding device unit. The proportion of projected area is preferably greater than 50%. It should be noted here that the second heat conduction region and the second interconnection structure can be obtained by forming a layer of bottom heat conduction layer material on the surface of the substrate body and then patterning it.
  • the ratio of the horizontal projected area of the top heat conduction layer to the horizontal projected area of the device chip is 30% to 130%.
  • the ratio of the horizontal projected area of the bottom heat conduction layer to the horizontal projected area of the device chip is 30%. to 130%.
  • the ratio of the sum of the horizontal projected areas of all the first heat conduction hole structures to the horizontal projected area of the device chip ranges from 30% to 130%, which is beneficial for the first heat conduction hole structure to achieve efficient heat transfer.
  • the main heat-generating component of the device chip is the device unit
  • the heat dissipation substrate can be divided into a first non-core area and a first core area corresponding to the device units in the device chip in one-to-one position.
  • the distribution density of the first heat conduction hole structures in the first core region is greater than or equal to the distribution density of the first heat conduction hole structures in the first non-core region.
  • the horizontal projection edge of the first core region and the horizontal projection edge of the corresponding device unit form a ring shape (that is, the horizontal projection of the former falls into the horizontal projection of the latter, or the horizontal projection of the latter falls into In the horizontal projection of the former), the width of the annular shape is less than or equal to 100 ⁇ m.
  • the horizontal projections of the first core region and its corresponding device units can also coincide exactly.
  • the first heat conduction hole structures may also be uniformly distributed in the heat dissipation substrate.
  • the manufacturing method of the heat dissipation substrate provided by the present invention further includes: forming a solder resist layer on the substrate body, and the solder resist layer is used to prevent soldering short circuit from occurring.
  • the heat dissipation substrate includes a top heat conduction layer and a bottom heat conduction layer as an example for illustration.
  • top heat conduction layer and the bottom heat conduction layer After forming the top heat conduction layer and the bottom heat conduction layer, first form a dry film (for example, composed of a polyethylene film layer, a photoresist layer and a polyester film layer) on the surface of the top heat conduction layer and the bottom heat conduction layer; then pattern the dry film Then use the dry film as a mask to remove part of the top heat conduction layer and the bottom heat conduction layer to expose the area on the substrate body where the solder resist layer needs to be formed, wherein the formation area of the solder resist layer on the substrate body needs to be determined accordingly according to the actual design requirements; Then remove the dry film; finally form a solder resist layer (commonly known as green oil in the prior art) on the exposed area of the substrate body.
  • a dry film for example, composed of a polyethylene film layer, a photoresist layer and a polyester film layer
  • the invention also provides a manufacturing method of the heat dissipation substrate, wherein the heat dissipation substrate is used for heat dissipation of device chips.
  • FIG. 22 is a flowchart of a manufacturing method of a heat dissipation substrate according to another specific embodiment of the present invention.
  • the manufacturing method includes:
  • step S401 a multi-layer structure is provided, the multi-layer structure sequentially includes a top heat conduction layer, a substrate body and a bottom heat conduction layer from top to bottom;
  • step S402 at least one first heat conduction hole structure is formed on the multilayer structure, wherein each of the first heat conduction hole structures includes a first through hole penetrating the multilayer structure in the thickness direction, and a first heat-conducting material filled in the first through hole;
  • step S403 a first connection part is formed on the front side of the multilayer structure, and the heat dissipation substrate is connected to the back side of the device chip through the first connection part.
  • step S401 to step S403 will be described in detail below with reference to FIG. 23( a ) to FIG. 23( d ).
  • the following only describes the manufacturing method of each component in the heat dissipation substrate, and the specific material, shape, size, etc. of each component can refer to the relevant content in the previous description of the structure of the heat dissipation substrate. For the sake of brevity, the description will not be repeated here.
  • a multilayer structure is provided, and the multilayer structure includes a top heat conduction layer 505 , a substrate body 500 and a bottom heat conduction layer 506 sequentially from top to bottom.
  • the multilayer structure can be realized directly by using existing organic substrates, such as copper clad substrates (copper foil, resin, glass fiber cloth, and copper foil from top to bottom), etc.
  • existing substrates such as copper clad substrates (copper foil, resin, glass fiber cloth, and copper foil from top to bottom), etc.
  • All existing substrates suitable for the manufacturing method of the present invention will not be listed here. Directly using the existing substrate to manufacture the heat dissipation substrate provided by the present invention is beneficial to simplify the manufacturing process of the heat dissipation substrate.
  • step S402 first, as shown in FIG. 23(b), at least one first through hole 501 penetrating through the multilayer structure is formed on the multilayer structure.
  • a first heat conduction material 502 is filled in the first through hole 501 to form a first heat conduction hole structure.
  • step S403 as shown in FIG. 23( d ), a first connection portion for connecting to the device chip during packaging is formed on the front side of the multilayer structure.
  • the present invention also provides a packaging structure, which includes:
  • a sealing structure includes a device chip and a cap disposed opposite to each other, and a sealing ring arranged between the device chip and the cap;
  • a first packaging substrate, the first packaging substrate is connected to the back surface of the device chip, and the first packaging substrate is realized by the aforementioned heat dissipation substrate or formed by the aforementioned manufacturing method;
  • the second packaging substrate is connected to the back of the cap
  • a plastic package the plastic package is located between the first package substrate and the second package substrate and forms a package for the sealing structure.
  • the packaging structure provided by the present invention includes a sealing structure, wherein the sealing structure includes a device chip, a cap and a sealing ring.
  • the device chip includes a substrate 100 and device units formed on the substrate 100 .
  • the device unit includes a lower electrode 101 , a piezoelectric layer 102 and an upper electrode 103 sequentially formed on the substrate 100 , and a cavity 104 is formed between the device unit and the substrate 100 .
  • a device chip usually includes a plurality of device units, and here only one device unit is schematically drawn for the sake of simplicity.
  • the cap includes a cap body 200 , a first via structure 201 and a second connection portion 202 .
  • the sealing ring 300 is formed between the device chip and the cap to form a sealed structure with the device chip and the cap, and the device units in the device chip are located in the cavity of the sealed structure.
  • the packaging structure provided by the present invention further includes a first packaging substrate.
  • the first packaging substrate is realized by using the heat dissipation substrate provided by the present invention, or is formed by using the manufacturing method of the heat dissipation substrate provided by the present invention.
  • the heat dissipation substrate is connected to the back side of the device chip through the first connecting portion on the front side.
  • relevant content For the sake of brevity, the structure of the heat dissipation substrate and its manufacturing method will not be repeated here.
  • the packaging structure provided by the present invention further includes a second packaging substrate, and the second packaging substrate is connected to the cap through the second connection portion on the back of the cap.
  • the second packaging substrate includes a substrate body 400, a front pad 401 formed on the front side of the substrate body 400, a back pad 402 formed on the back side of the substrate body 400, and a front side pad 402 formed inside the substrate body 400 for realizing the front side.
  • the pad 401 and the back pad 402 are electrically connected to a second via hole structure 403 .
  • FIG. 25(c) is only a schematic example. According to actual design requirements, electronic components such as spiral inductors connected to the device chip are usually formed in the substrate body 400. Devices, etc., these are existing conventional technical means, for the sake of brevity, no more details are given here.
  • the packaging structure provided by the present invention further includes a plastic package 600, which is located between the first packaging substrate and the second packaging substrate to form a package for the sealing structure.
  • the plastic package 600 is mainly made of insulating organic materials, such as epoxy resin, silicone resin, phenolic resin, polyurethane and other organic resin materials.
  • the packaging structure provided by the present invention is connected with a heat dissipation substrate on the back of the device chip, and the heat generated during the operation of the packaging structure can be efficiently transferred to the packaged device through the heat dissipation substrate on the substrate side. outside space. That is to say, compared with the existing packaging structure, the packaging structure provided by the present invention has better heat dissipation efficiency.
  • the device chip in the package structure includes a substrate structure and at least one device unit formed on the substrate structure, wherein at least one thermal hole structure is formed on the bottom of the substrate structure (hereinafter referred to as the first two heat conduction hole structures), each second heat conduction hole structure includes a blind hole formed at the bottom of the substrate structure and a heat conduction material (hereinafter referred to as the second heat conduction material) filled in the blind hole.
  • the depth of the blind hole is smaller than the thickness of the substrate structure, and accordingly the height of the second thermal hole structure is smaller than the thickness of the substrate structure.
  • the thickness of the substrate structure is not more than 100 ⁇ m, and the height of the thermal hole structure is greater than 30 ⁇ m.
  • the main part of the substrate structure (that is, the part of the substrate structure except the second thermal hole structure) can be realized by using existing conventional substrate materials.
  • the thermal conductivity of the second thermally conductive material is higher than the thermal conductivity of the material of the main part of the substrate structure.
  • the second heat conduction material is realized by using a metal material with high heat conductivity, such as one of Cu, Au, Ag, Al, Ni, Fe, Mo, W or any combination thereof.
  • the second thermally conductive material should not be limited to metallic materials only. In other embodiments, alloy materials and combinations with higher thermal conductivity than the main part of the substrate structure, as well as non-metallic materials are also suitable for the second thermally conductive material. 2.
  • Thermally conductive materials In addition, it should be noted that, for the second heat-conducting material, it may be a single crystal material, a polycrystalline material, or a combination of a single crystal material and a polycrystalline material, which is not limited in the present invention.
  • the device chips in this embodiment Compared with the existing device chips whose substrates are made of conventional materials, the device chips in this embodiment have a second thermal hole structure made of high thermal conductivity material formed at the bottom of the substrate structure, so the substrate structure is effectively improved.
  • the heat dissipation efficiency of the bottom structure Used together with the heat dissipation substrate provided by the present invention, a more efficient heat dissipation channel can be formed on the substrate side of the package structure, further improving the heat dissipation efficiency of the package structure.
  • the substrate structure includes a first substrate layer 100a and a second substrate layer 100c from bottom to top.
  • the material of the first substrate layer 100a is an insulating material or a semiconductor material, such as one or any combination of Si, SiO2, SiN, AlN, SiC, and sapphire.
  • the resistivity of the semiconductor material is greater than
  • the thickness of the first substrate layer 100a is preferably in the range of 30 ⁇ m to 100 ⁇ m.
  • the material of the second substrate layer 100c is an insulating material or a semiconductor material with high thermal conductivity, and its thermal conductivity is greater than or equal to the thermal conductivity of the first substrate layer 100a.
  • the material of the second substrate layer 100c is a semiconductor material, preferably the resistivity of the semiconductor material is greater than
  • the thickness of the second substrate layer 100c is preferably in the range of 3 ⁇ m to 10 ⁇ m.
  • the second thermal hole structure is formed in the first substrate layer 100a.
  • the first substrate layer 100a is formed with at least one second through hole penetrating through the first substrate layer 100a in the thickness direction, and the at least one second through hole is filled with the second thermally conductive material 100b.
  • the second through hole it forms a blind hole together with the bottom surface of the second substrate layer 100c at its upper opening, and further forms a blind hole with the second heat conducting material 100b filled in the second through hole.
  • the second thermal hole structure is the same as that of the first substrate layer 100a.
  • the thermal conductivity of the second thermal conductive material 100b is higher than the thermal conductivity of the material of the first substrate layer 100a.
  • the second thermally conductive material 100b is preferably realized by a metal material with high thermal conductivity, such as one of Cu, Au, Ag, Al, Ni, Fe, Mo, W or any combination thereof.
  • the second thermally conductive material 100b can also be realized by using alloy materials and combinations thereof, or non-metallic materials with higher thermal conductivity than the first substrate layer 100a.
  • each resonant unit includes a lower electrode 101, a piezoelectric layer 102, and an upper electrode 103 from bottom to top, and the connection between each resonant unit and the substrate structure A cavity 104 is formed between them.
  • the cavity 104 is formed in the second substrate layer 100c; (2) the actual device chip often includes a plurality of device units, here for the sake of simplicity, only one device unit is drawn in the figure For illustrative purposes, other device units and connection relationships between device units are omitted.
  • the thermal conductivity of the material of the second substrate layer 100c is greater than or equal to the thermal conductivity of the material of the first substrate layer 100a, which is beneficial to efficiently transfer the heat generated by the device unit to the first substrate layer 100a.
  • the thermal conductivity of the second thermal hole structure in the first substrate layer 100a is greater than the thermal conductivity of the material of the first substrate layer 100a, which is conducive to efficiently transferring the heat transferred to the first substrate layer 100a to the heat dissipation substrate through the second thermal hole structure .
  • the ratio of the sum of the horizontal projected areas of the second heat conduction hole structure to the horizontal projected area of the device chip ranges from 30% to 90%.
  • the main heat-generating component of the device chip is the device unit
  • the first substrate layer 100a may be divided into second core regions corresponding to device units one by one, and each second core region is located below the corresponding device unit. Other regions of the first substrate layer 100a except the second core region are referred to as second non-core regions.
  • the distribution density of the second heat conduction hole structures in the second core region is greater than the distribution density of the heat conduction hole structures in the second non-core region.
  • the horizontal projection edge of the second core region and the horizontal projection edge of the corresponding device unit form a ring shape (that is, the horizontal projection of the former falls into the horizontal projection of the latter, or the horizontal projection of the latter falls into In the horizontal projection of the former), the width of the annular shape is less than or equal to 100 ⁇ m.
  • the horizontal projections of the second core region and its corresponding device units can also coincide exactly.
  • the second thermal hole structures may also be uniformly distributed in the first substrate layer 100a.
  • a third interconnection structure is further formed on the first substrate layer 100a in the substrate structure.
  • grooves communicating with the second heat conduction hole structures are formed on the upper surface of the first substrate layer 100a, and the third interconnection structure is formed in the grooves to form communication between the second heat conduction hole structures.
  • the existence of the third interconnection structure enables the heat generated by the device units to be quickly transferred through all the second heat conduction hole structures, thereby further improving the heat dissipation efficiency of the substrate structure.
  • the substrate structure further includes a third substrate formed between the first substrate layer 100a and the second substrate layer 100c.
  • the bottom layer 100d, the material of the third substrate layer 100d is a third thermal conductive material.
  • the third substrate layer 100d is connected to the second thermal hole structure in the first substrate layer 100a.
  • the thermal conductivity of the third thermal conductive material is greater than the thermal conductivity of the material of the first substrate layer 100a. It is preferably realized by using a metal material with high thermal conductivity, such as one of Cu, Au, Ag, Al, Ni, Fe, Mo, W or any combination thereof.
  • the third heat conducting material may also be realized by using alloy materials and combinations thereof, or non-metal materials with higher thermal conductivity than the first substrate layer 100a.
  • the third heat-conducting material it may be a single crystal material, a polycrystalline material, or a combination of a single crystal material and a polycrystalline material, which is not limited in the present invention.
  • the existence of the third substrate layer 100d facilitates the transfer of heat from the second substrate layer 100c to the first substrate layer 100a, thereby further improving the heat dissipation efficiency.
  • the thickness range of the third substrate layer 100d is preferably less than or equal to 50 ⁇ m.
  • the material of the third substrate layer 100d may be different from the second thermally conductive material, or may be the same as the second thermally conductive material. What needs to be explained here is that for the case where the third substrate layer is provided in the substrate structure to realize efficient transfer of heat from the second substrate layer to the first substrate layer, the difference between the first substrate layer and the second substrate layer The materials may be different or the same.
  • the third substrate layer 100d may be a whole layer. In other embodiments, considering that the main heat-generating component of the device chip is the device unit, the third substrate layer 100d may also be formed only under the device unit. Specifically, the third substrate layer 100d includes third heat conduction regions corresponding to the device units one by one, and each third heat conduction region is located below the corresponding device unit. For the case where the number of device units is greater than or equal to 2, more preferably, the third substrate layer 100d further includes a fourth interconnection structure, and the fourth interconnection structure enables interconnection between the third heat conduction regions.
  • the existence of the fourth interconnection structure can make the heat generated by the device units transfer quickly between the third heat conduction regions, which is beneficial to the improvement of heat dissipation efficiency. It should be noted that there is a third overlapping area between the horizontal projection of each third heat conduction area and the horizontal projection of the corresponding device unit. In order to ensure the heat dissipation effect, the projected area of the third overlapping area and the horizontal projection of the corresponding device unit The proportion of projected area is preferably greater than 50%.
  • the ratio of the horizontal projected area of the third substrate layer 100d to the horizontal projected area of the device chip is 30% to 90%.
  • FIG. 24 is a flowchart of a manufacturing method of a packaging structure according to a specific embodiment of the present invention. As shown, the manufacturing method includes:
  • step S501 the front side of the device chip and the cap are arranged oppositely, and the two are sealed by a sealing ring to form a sealing structure;
  • step S502 a first packaging substrate is mounted on the back of the device chip, and a second packaging substrate is mounted on the back of the cap, wherein the first packaging substrate is realized by using the aforementioned heat dissipation substrate, or using the aforementioned manufacturing method form;
  • step S503 a plastic package enclosing the sealing structure is formed between the first packaging substrate and the second packaging substrate.
  • step S501 to step S503 will be described in detail with reference to FIG. 25(a) to FIG. 25(c).
  • step S501 first provide the device chip to be packaged and the cap corresponding to the device chip; then form the first bonding portion on the front side of the device chip (that is, the surface where the device unit is located), and form the first bonding portion on the front side of the cap (that is, the surface facing the device chip during packaging) to form a second bonding portion corresponding to the first bonding portion; then, the device chip is arranged opposite to the front of the cap and the first bonding portion and the second bonding portion are bonded together. Internal alignment; finally, bonding and fixing the cap and the device chip. After the first bonding part and the second bonding part are bonded, a sealing ring is formed between the device chip and the cap.
  • the device chip, the cap and the sealing ring form a sealing structure (please refer to the structure shown in FIG. 25( a )).
  • a sealing structure please refer to the structure shown in FIG. 25( a )
  • the structure of the device chip, the cap, and the sealing ring in the sealing structure reference may be made to the relevant content in the packaging structure above, and for the sake of brevity, the description will not be repeated here.
  • a second connection part 202 is first formed on the back of the cap and the sealing structure is connected (flip-chip) to the second package through the second connection part 202.
  • a substrate then mounting the first packaging substrate to the back surface of the device chip through the first connection portion on the first packaging substrate.
  • the first packaging substrate and the device chip can also be connected first, and then the sealing structure can be flip-chipped onto the second packaging substrate.
  • step S503 as shown in FIG. 25(c), the structure shown in FIG. 25(b) is plastic-encapsulated to form a plastic package 600 enclosing the sealing structure between the first packaging substrate and the second packaging substrate.
  • the encapsulation structure formed by implementing the manufacturing method provided by the present invention has excellent heat dissipation efficiency.

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Abstract

本发明提供了一种器件芯片，该器件芯片包括：衬底结构，该衬底结构的底部形成有至少一个导热孔结构，每一所述导热孔结构均包括形成在所述衬底结构底部的第一盲孔以及填充在该第一盲孔内的第一导热材料；至少一个器件单元，该至少一个器件单元形成在所述衬底结构上。相应地，本发明还提供了一种器件芯片的制造方法、散热基板及其制造方法、以及封装结构及其制造方法。本发明有利于提高封装结构的散热性能。

Description

器件芯片及其制造方法、散热基板及其制造方法、封装结构及其制造方法 技术领域
本发明涉及半导体技术领域，尤其涉及一种器件芯片及其制造方法、散热基板及其制造方法、封装结构及其制造方法。
背景技术
请参考图1，图1是现有技术中常见倒封装结构的剖面示意图。如图所示，该倒封装结构包括FBAR器件芯片、盖帽、密封环30、封装基板以及塑封体50。其中，FBAR器件芯片包括衬底10、位于衬底10上的谐振器件、以及位于该衬底10和谐振器件之间的空腔11，其中，谐振器件依次包括下电极12、压电层13以及上电极14。盖帽包括本体20、形成在本体20内的导通孔结构21、以及形成在本体20背面的焊球22。密封环30形成在FBAR器件芯片和盖帽之间，并与该FBAR器件芯片和盖帽形成密封结构，FBAR器件芯片上的谐振器件位于该密封结构的空腔31中。封装基板包括本体40、正面焊盘41、背面焊盘42、以及电连接该正面焊盘41和背面焊盘42的导通孔结构43。盖帽背面的焊球22与封装基板的正面焊盘41焊接，从而实现密封结构与封装基板的连接。塑封体50则形成在密封结构的外表面对密封结构形成包裹。
FBAR器件芯片中的谐振器件工作时会产生热量，是上述倒封装结构的发热部件。其中，谐振器件所产生的热量主要通过衬底向封装结构的外部传递。现有衬底主要采用绝缘材料或半导体材料(例如Si、SiO2、SiN、AlN、SiC等)实现，由于这些材料的导热性不佳，所以容易导致上述现有倒封装结构无法实现高效散热。FBAR器件芯片中的谐振器件除了通过衬底之外还会通过塑封体向外传递。针对于现有塑封体来说，其主要采用绝缘有机材料(例如环氧树脂、硅树脂、酚醛树脂、聚氨酯等有机树脂材料)制成。由于这些绝缘有机材料的导热性往往不佳，所以导致上述现有倒封装结构无法实现高效散热。而倒封装结构无法高效散热会导致倒封装结构中发热部件出现高温的情况，进而降低倒封装结构的寿命、影响倒封装结 构的可靠性、以及降低倒封装结构的功率承载能力，严重时会导致倒封装结构物理结构的破裂甚至是烧坏失效。
发明内容
为了克服现有技术中的上述缺陷，本发明提供了一种器件芯片，该器件芯片包括：
衬底结构，该衬底结构的底部形成有至少一个导热孔结构，每一所述导热孔结构均包括形成在所述衬底结构底部的第一盲孔以及填充在该第一盲孔内的第一导热材料；
至少一个器件单元，该至少一个器件单元形成在所述衬底结构上。
根据本发明的一个方面，该器件芯片中，每一所述器件单元从下至上依次是下电极、压电层以及上电极，且每一所述器件单元与所述衬底结构之间均形成有声反射结构。
根据本发明的另一个方面，该器件芯片中，所述衬底结构从下至上依次包括第一衬底层和第二衬底层；所述第一衬底层在厚度方向上形成有至少一个通孔，该至少一个通孔与所述第二衬底的底面构成所述第一盲孔；所述至少一个通孔内填充有所述第一导热材料。
根据本发明的又一个方面，该器件芯片中，所述衬底结构还包括形成在所述第一衬底层和所述第二衬底层之间的第三衬底层，该第三衬底层的材料是第二导热材料。
根据本发明的又一个方面，该器件芯片中，所述第二衬底层材料的热导率大于等于所述第一衬底层材料的热导率；所述第一导热材料以及所述第二导热材料的热导率大于所述第一衬底层材料的热导率。
根据本发明的又一个方面，该器件芯片中，所述导热孔结构在水平方向上的投影面积之和与所述器件芯片在水平方向上的投影面积的比例范围是30％至90％。
根据本发明的又一个方面，该器件芯片中，所述第一衬底层包括与所述器件单元一一对应的核心区域，每一所述核心区域位于与其相对应的所述器件单元的下方；所述第一衬底层除了所述核心区域之外的区域为非 核心区域；其中，所述核心区域中所述导热孔结构的分布密度大于所述非核心区域中所述导热孔结构的分布密度。
根据本发明的又一个方面，该器件芯片中，每一所述器件单元在水平方向上的投影边缘与位于其下方的所述核心区域在水平方向上的投影边缘构成环形形状，该环形形状的宽度小于等于100μm。
根据本发明的又一个方面，该器件芯片中，当所述导热孔结构的数量大于等于2个时，所述第一衬底层上还形成有第一互联结构，该第一互联结构形成在所述第一衬底层上表面的凹槽内并使所述导热孔结构内的所述第一导热材料之间形成互联。
根据本发明的又一个方面，该器件芯片中，当所述器件单元的数量大于等于2个时，所述第三衬底层包括与所述器件单元一一对应的导热区域、以及第二互联结构，其中，每一所述导热区域位于与其相对应的所述器件单元的下方，所述第二互联结构使所述导热区域之间形成互联。
根据本发明的又一个方面，该器件芯片中，所述第三衬底层在水平方向上的投影面积与所述器件芯片在水平方向上的投影面积的比例范围是30％至90％；以及每一所述导热区域在水平方向上的投影与相对应的所述器件单元在水平方向上的投影之间存在重叠区域，该重叠区域的投影面积与相对应的所述器件单元在水平方向上的投影面积的比例大于50％。
本发明还提供了一种器件芯片的制造方法，该制造方法包括：
形成衬底结构，该衬底结构底部形成有至少一个导热孔结构，每一所述导热孔结构均包括形成在所述衬底结构底部的第一盲孔以及填充在该第一盲孔内的第一导热材料；
在所述衬底结构上形成至少一个器件单元。
根据本发明的一个方面，该制造方法中，每一所述器件单元从下至上依次是下电极、压电层以及上电极，且每一所述器件单元与所述衬底结构之间均形成有声反射结构。
根据本发明的另一个方面，该制造方法中，形成衬底结构的步骤包括：提供第一衬底层并在该第一衬底层的上表面形成至少一个第二盲孔；在所述至少一个第二盲孔内填充第一导热材料；在所述第一衬底层上沉积 第二衬底层、以及对所述第一衬底层的下表面进行平坦化操作使所述第一导热材料暴露，以形成所述衬底结构，其中，所述第二盲孔的侧壁与所述第二衬底层的底面构成所述第一盲孔。
根据本发明的又一个方面，该制造方法中，形成衬底结构的步骤还包括：在所述第一衬底层和所述第二衬底层之间形成第三衬底层，该第三衬底层的材料是第二导热材料。
根据本发明的又一个方面，该制造方法中，所述第二衬底层材料的热导率大于等于所述第一衬底层材料的热导率；所述第一导热材料以及所述第二导热材料的热导率大于所述第一衬底层材料的热导率。
根据本发明的又一个方面，该制造方法中，所述导热孔结构在水平方向上的投影面积之和与所述器件芯片在水平方向上的投影面积的比例范围是30％至90％。
根据本发明的又一个方面，该制造方法中，所述第一衬底层包括与所述器件单元一一对应的核心区域，每一所述核心区域位于相应所述器件单元的下方；所述第一衬底层除了所述核心区域之外的区域为非核心区域；其中，所述核心区域中所述导热孔结构的分布密度大于所述非核心区域中所述导热孔结构的分布密度。
根据本发明的又一个方面，该制造方法中，每一所述器件单元在水平方向上的投影边缘与位于其下方的所述核心区域在水平方向上的投影边缘构成环形形状，该环形形状的宽度小于等于100μm。
根据本发明的又一个方面，该制造方法中，当所述导热孔结构的数量大于等于2个时，形成衬底结构的步骤还包括：在所述第一衬底层上形成第一互联结构，该第一互联结构形成在所述第一衬底层上表面的凹槽内并使所述导热孔结构内的所述第一导热材料之间形成互联。
根据本发明的又一个方面，该制造方法中，当所述器件单元的数量大于等于2个时，所述第三衬底层包括与所述器件单元一一对应的导热区域、以及第二互联结构，其中，每一所述导热区域位于与其相对应的所述器件单元的下方，所述第二互联结构使所述导热区域之间形成互联。
根据本发明的又一个方面，该制造方法中，所述第三衬底层在水平 方向上的投影面积与所述器件芯片在水平方向上的投影面积的比例范围是30％至90％；以及每一所述导热区域在水平方向上的投影与相对应的所述器件单元在水平方向上的投影之间存在重叠区域，该重叠区域的投影面积与相对应的所述器件单元在水平方向上的投影面积的比例大于50％。
本发明还提供了一种封装结构，该封装结构包括：
前述器件芯片；
盖帽，该盖帽的正面与所述器件芯片相对设置、背面设置有连接部；
密封环，该密封环设置在所述器件芯片和所述盖帽之间，与所述器件芯片和所述盖帽形成密封结构，所述至少一个器件单元位于该密封结构的腔体内；
封装基板，所述密封结构通过所述连接部与所述封装基板形成连接；
塑封体，该塑封体对所述密封结构形成包裹。
本发明还提供了一种封装结构的制造方法，该制造方法包括：
提供前述器件芯片或采用前述制造方法形成器件芯片；
提供盖帽，该盖帽的正面与所述器件芯片相对设置；
在所述器件芯片和所述盖帽之间形成密封环，该密封环与所述器件芯片和所述盖帽形成密封结构，所述至少一个器件单元位于该密封结构的腔体内；
在所述盖帽背面形成连接部并通过该连接部将所述密封结构连接至封装基板；
形成对所述密封结构包裹的塑封体。
本发明提供了一种散热基板，用于器件芯片的散热，该散热基板包括：
基板本体；
至少一个第一导热孔结构，其中，每一所述第一导热孔结构均包括在厚度方向上贯穿所述基板本体的第一通孔、以及填充在该第一通孔内的第一导热材料；
第一连接部，该第一连接部形成在所述基板本体的正面，所述散热 基板通过所述第一连接部连接至器件芯片的背面。
根据本发明的一个方面，该散热基板还包括：顶导热层，该顶导热层形成在所述基板本体正面；底导热层，该底导热层形成在所述基板本体的背面。
根据本发明的另一个方面，该散热基板中，所述顶导热层的材料、所述底导热层的材料以及所述第一导热材料的热导率均高于器件芯片封装时所采用的塑封体的热导率；所述基板本体其材料的热导率高于或等于器件芯片封装时所采用的塑封体的热导率。
根据本发明的又一个方面，该散热基板中，所述顶导热层和所述底导热层的厚度均小于等于50μm；所述基板本体的厚度小于等于100μm。
根据本发明的又一个方面，该散热基板中，所述顶导热层的水平投影面积与所述器件芯片的水平投影面积的比例范围是30％至130％；和/或所述底导热层的水平投影面积与所述器件芯片的水平投影面积的比例范围是30％至130％。
根据本发明的又一个方面，该散热基板中，所述器件芯片中器件单元的数量大于等于2个；所述顶导热层包括位置上与所述器件芯片中各器件单元一一对应的第一导热区域、以及用于对所述第一导热区域进行互联的第一互联结构；和/或所述底导热层包括位置上与所述器件芯片中各器件单元一一对应的第二导热区域、以及用于对所述第二导热区域进行互联的第二互联结构。
根据本发明的又一个方面，该散热基板中，每一所述第一导热区域的水平投影与相对应的所述器件单元的水平投影之间存在第一重叠区域，该第一重叠区域的投影面积与相对应的所述器件单元的水平投影面积的比例大于50％；和/或每一所述第二导热区域的水平投影与相对应的所述器件单元的水平投影之间存在第二重叠区域，该第二重叠区域的投影面积与相对应的所述器件单元的水平投影面积的比例大于50％。
根据本发明的又一个方面，该散热基板中，所述第一导热孔结构的水平投影面积之和与所述器件芯片的水平投影面积的比例范围是30％至130％。
根据本发明的又一个方面，该散热基板中，所述散热基板包括位置上与所述器件芯片中各器件单元一一对应的第一核心区域；所述散热基板除了所述第一核心区域之外的区域为第一非核心区域；其中，所述第一核心区域内所述第一导热孔结构的分布密度大于等于所述第一非核心区域内所述第一导热孔结构的分布密度。
根据本发明的又一个方面，该散热基板中，每一所述第一核心区域的水平投影边缘与相对应的所述器件单元的水平投影边缘构成环形形状，该环形形状的宽度小于等于100μm。
本发明还提供了一种散热基板的制造方法，该散热基板用于器件芯片的散热，该制造方法包括：
提供基板本体；
在所述基板本体上形成至少一个第一导热孔结构，其中，每一所述第一导热孔结构均包括在厚度方向上贯穿所述基板本体的第一通孔、以及填充在该第一通孔内的第一导热材料；
在所述基板本体的正面形成第一连接部，所述散热基板通过所述第一连接部连接至器件芯片的背面。
根据本发明的一个方面，该制造方法中，在所述基板本体上形成至少一个第一导热孔结构之后，该制造方法还包括：在所述基板本体的正面形成顶导热层、以及在所述基板本体的背面形成底导热层。
根据本发明的另一个方面，该制造方法中，所述顶导热层的材料、所述底导热层的材料以及所述第一导热材料的热导率均高于器件芯片封装时所采用的塑封体的热导率；所述基板本体其材料的热导率高于或等于器件芯片封装时所采用的塑封体的热导率。
根据本发明的又一个方面，该制造方法中，所述顶导热层和所述底导热层的厚度均小于等于50μm；所述基板本体的厚度小于等于100μm。
根据本发明的又一个方面，该制造方法中，所述顶导热层的水平投影面积与所述器件芯片的水平投影面积的比例范围是30％至130％；和/或所述底导热层的水平投影面积与所述器件芯片的水平投影面积的比例范围是30％至130％。
根据本发明的又一个方面，该制造方法中，所述器件芯片中器件单元的数量大于等于2个；所述顶导热层包括位置上与所述器件芯片中各器件单元一一对应的第一导热区域、以及用于对所述第一导热区域进行互联的第一互联结构；和/或所述底导热层包括位置上与所述器件芯片中各器件单元一一对应的第二导热区域、以及用于对所述第二导热区域进行互联的第二互联结构。
根据本发明的又一个方面，该制造方法中，每一所述第一导热区域的水平投影与相对应的所述器件单元的水平投影之间存在第一重叠区域，该第一重叠区域的投影面积与相对应的所述器件单元的水平投影面积的比例大于50％；和/或每一所述第二导热区域的水平投影与相对应的所述器件单元的水平投影之间存在第二重叠区域，该第二重叠区域的投影面积与相对应的所述器件单元的水平投影面积的比例大于50％。
根据本发明的又一个方面，该制造方法中，所述第一导热孔结构的水平投影面积之和与所述器件芯片的水平投影面积的比例范围是30％至130％。
根据本发明的又一个方面，该制造方法中，所述散热基板包括与所述器件芯片中各器件单元一一对应的第一核心区域，每一所述核心区域位于与其相对应的器件单元的下方；所述散热基板除了所述第一核心区域之外的区域为第一非核心区域；其中，所述第一核心区域内所述第一导热孔结构的分布密度大于等于所述第一非核心区域内所述第一导热孔结构的分布密度。
根据本发明的又一个方面，该制造方法中，每一所述第一核心区域的水平投影边缘与相对应的所述器件单元的水平投影边缘构成环形形状，该环形形状的宽度小于等于100μm。
本发明还提供了一种散热基板的制造方法，该散热基板用于器件芯片的散热，该制造方法包括：
提供多层结构，该多层结构从上至下依次包括顶导热层、基板本体以及底导热层；
在所述多层结构上形成至少一个第一导热孔结构，其中，每一所述 第一导热孔结构均包括在厚度方向上贯穿所述多层结构的第一通孔、以及填充在该第一通孔内的第一导热材料；
在所述多层结构的正面形成第一连接部，所述散热基板通过所述第一连接部连接至器件芯片的背面。
本发明还提供了一种封装结构，该封装结构包括：
密封结构，该密封结构包括正面相对设置的器件芯片和盖帽、以及设置在该器件芯片和盖帽之间的密封环；
第一封装基板，该第一封装基板与所述器件芯片的背面连接，该第一封装基板采用前述散热基板实现、或采用前述制造方法形成；
第二封装基板，该第二封装基板与所述盖帽的背面连接；
塑封体，该塑封体位于所述第一封装基板和所述第二封装基板之间、并对所述密封结构形成包裹。
根据本发明的一个方面，该封装结构中，所述器件芯片包括衬底结构以及至少一个器件单元；所述衬底结构的底部形成有至少一个第二导热孔结构，每一所述第二导热孔结构均包括形成在所述衬底结构底部的盲孔以及填充在该盲孔内的第二导热材料；所述至少一个器件单元形成在所述衬底结构上。
根据本发明的另一个方面，该封装结构中，所述衬底结构从下至上依次包括第一衬底层和第二衬底层；所述第一衬底层在厚度方向上形成有至少一个第二通孔，该至少一个第二通孔与所述第二衬底的底面构成所述盲孔；所述至少一个第二通孔内填充有所述第二导热材料。
根据本发明的又一个方面，该封装结构中，所述衬底结构还包括形成在所述第一衬底层和所述第二衬底层之间的第三衬底层，该第三衬底层的材料是第三导热材料。
本发明还提供了一种封装结构的制造方法，该制造方法包括：
将器件芯片与盖帽正面相对设置，并通过密封环将其二者进行密封以形成密封结构；
将所述第一封装基板连接至所述器件芯片的背面、以及将所述第二封装基板连接至在所述盖帽的背面，其中，所述第一封装基板采用前述散 热基板实现、或利用前述制造方法形成；
在所述第一封装基板和所述第二封装基板之间形成对所述密封结构包裹的塑封体。
本发明所提供的器件芯片其衬底结构的底部形成有高热导率材料构成的导热孔结构。如此一来，对器件芯片进行封装形成封装结构后，器件芯片中器件单元工作所产生的热量在通过衬底结构一侧的散热通道进行传递时，可以通过衬底结构中的导热孔结构向外部高效传递热量，从而有效地提高了封装结构的散热效率。封装结构散热效率的提高有利于降低器件单元的温度，从而使封装结构的寿命、可靠性以及功率承载能力得到提高。特别是针对于器件单元下方存在空腔的情况，实施本发明散热效果提升尤为明显。实施本发明所提供的制造方法可以得到高散热效率的器件芯片。相应地，基于本发明所提供的器件芯片所形成的封装结构及其制造方法可以有效提高封装结构的散热效率。
本发明所提供的散热基板包括基板本体、至少一个第一导热孔结构以及第一连接部，其中，每一第一导热孔结构均包括在厚度方向上贯穿基板本体的第一通孔、以及填充在该第一通孔内的第一导热材料，第一连接部形成在基板本体的正面。在对器件芯片进行封装时，将本发明所提供的散热芯片通过第一连接部连接至器件芯片的背面，如此一来，器件芯片从衬底侧传递出的热量可以通过散热基板中的第一导热孔结构向外部高效传递，从而有利于提高封装结构的散热效率。与现有封装结构(即器件芯片背面是散热性较差的塑封体)相比，实施本发明很明显散热效果更佳。相应地，基于本发明所提供的制造方法得到的散热基板、以及基于本发明所提供的散热基板所形成的封装结构及其制造方法具有优异的散热效率。
附图说明
通过阅读参照以下附图所作的对非限制性实施例所作的详细描述，本发明的其它特征、目的和优点将会变得更明显：
图1是现有技术中常见倒封装结构的剖面示意图；
图2是根据本发明一个具体实施例的器件芯片的制造方法流程图；
图3至图9是根据本发明的一个优选实施例的制造器件芯片的各个阶段的剖面示意图；
图10(a)和图10(b-1)是根据本发明的两个具体实施例的第一衬底层的俯视示意图；
图10(b-2)和图10(b-3)分别是图(b-1)所示结构沿线AA’线和BB’线的剖面示意图；
图11和图12是根据本发明的两个优选实施例的器件芯片的剖面示意图；
图13(a)和图13(b)是根据本发明的两个具体实施例的第三衬底层的俯视示意图；
图14是根据本发明一个具体实施例的封装结构的制造方法流程图；
图15至图19是按照图14所示方法流程形成封装结构的各个阶段的剖面示意图；
图20是根据本发明的一个具体实施例的散热基板的制造方法流程图；
图21(a)至图21(d)是根据图20所示方法流程形成散热基板的各个阶段的剖面示意图；
图22是根据本发明的另一个具体实施例的散热基板的制造方法流程图；
图23(a)至图23(d)是根据图22所示方法流程形成散热基板的各个阶段的剖面示意图；
图24是根据本发明的一个具体实施例的封装结构的制造方法流程图；
图25(a)至图25(c)是根据图24所示方法流程形成封装结构的各个阶段的剖面示意图；
图26(a)和图26(b)是根据本发明的两个优选实施例的器件芯片的剖面示意图；
图27是根据本发明的一个优选实施例的封装结构的剖面示意图，其中，该封装结构中的器件芯片采用图26(b)所示结构实现。
附图中相同或相似的附图标记代表相同或相似的部件。
具体实施方式
为了更好地理解和阐释本发明，下面将结合附图对本发明作进一步的详细描述。
本发明提供了一种器件芯片，该器件芯片包括：
衬底结构，该衬底结构的底部形成有至少一个导热孔结构，每一所述导热孔结构均包括形成在所述衬底结构底部的第一盲孔以及填充在该第一盲孔内的第一导热材料；
至少一个器件单元，该至少一个器件单元形成在所述衬底结构上。
下面将结合附图对上述器件芯片的各个构成部分进行详细说明。
具体地，本发明所提供的器件芯片包括衬底结构，该衬底结构的底部形成有至少一个导热孔结构。在本实施例中，每一导热孔结构均包括形成在衬底结构底部的盲孔(下文以第一盲孔表示)以及填充在该第一盲孔内的导热材料(下文以第一导热材料表示)。其中，第一导热材料的下表面与衬底结构的下表面齐平(本发明中术语“齐平”意是指两者之间的高度差在工艺误差允许的范围内)。
在本实施例中，第一盲孔的深度小于衬底结构的厚度，相应地导热孔结构的高度小于衬底结构的厚度。本发明对衬底结构的厚度以及导热孔结构的高度不做任何限定，可以根据实际设计需求相应制定。为了提升衬底结构的散热性能，优选地，衬底结构的厚度不超过100μm，导热孔结构的高度大于30μm。
在本实施例中，衬底结构的主体部分(即衬底结构中除了导热孔结构之外的部分)可以采用现有常规的衬底材料实现。此处为了简明起见，不再对现有常规的衬底材料进行一一列举。此外，在本实施例中，第一导热材料的热导率高于衬底结构主体部分材料的热导率。优选地，第一导热材料采用高热导率的金属材料实现，例如Cu、Au、Ag、Al、Ni、Fe、Mo、W中的一种或其任意组合。本领域技术人员可以理解的是，第一导热材料不应仅仅限于金属材料，在其他实施例中，热导率高于衬底结构主体部分 的非金属材料也适用于第一导热材料，为了简明起见，在此不再对第一导热材料的所有可能进行一一列举。此外需要说明的是，对于第一导热材料来说，其可以是单晶材料、也可以是多晶材料，或者是单晶材料和多晶材料的组合，本发明对此不做任何限定。
本发明所提供的器件芯片还包括至少一个器件单元，该至少一个器件单元形成在衬底结构上。在一个具体实施例中，器件单元是谐振单元，该谐振单元从下至上依次是下电极、压电层以及上电极，且每一谐振单元与衬底结构之间形成有用于声波反射的声反射结构。例如该声反射结构可以是空腔、布拉格反射层等。其中，每一谐振单元与位于其下方的声反射结构以及衬底构成体声波谐振器。相应地，器件芯片可以是体声波滤波器芯片、双工器芯片、或多工器芯片。本领域技术人员可以理解，器件单元以及器件芯片不应仅限于上述示意性举例，凡是可以形成在衬底结构上的器件单元均落入本发明的保护范围，为了简明起见，在此不再对器件单元所有可能进行一一列举。此外需要说明的是，器件单元的具体数量由器件芯片的实际设计需求决定，本发明对此不做任何限制。
本发明所提供的器件芯片其衬底结构的底部形成有高热导率材料构成的导热孔结构。如此一来，对器件芯片进行封装形成封装结构后，器件芯片中器件单元工作所产生的热量在通过衬底结构一侧的散热通道进行传递时，可以通过衬底结构中的导热孔结构向外部高效传递热量，从而有效地提高了封装结构的散热效率。封装结构散热效率的提高有利于降低器件单元的温度，从而使封装结构的寿命、可靠性以及功率承载能力得到提高。特别是针对于器件单元下方存在空腔的情况，尤为适用。
下面将结合图9以一个优选实施例对本发明所提供的器件芯片进行说明。
如图9所示，本发明所提供的器件芯片其衬底结构从下至上依次包括第一衬底层100和第二衬底层105。
在本实施例中，第一衬底层100的材料是绝缘材料或半导体材料，例如Si、SiO2、SiN、AlN、SiC、蓝宝石中的一种或任意组合。本领域技术人员可以理解的是，上述Si、SiO2、SiN、AlN、SiC、蓝宝石仅为示意性举 例，凡是现有以及未来可能出现的适用于衬底的材料均适用于本发明中的第一衬底层，为了简明起见，在此不再对第一衬底层所有可能的材料进行一一列举。针对于第一衬底层100的材料是半导体材料的情况，优选该半导体材料的电阻率大于
Figure PCTCN2022133602-appb-000001
此外，第一衬底层100的厚度范围优选是30μm至100μm。
在本实施例中，第二衬底层105的材料是高热导率的绝缘材料或半导体材料，其热导率大于第一衬底层100的热导率。例如Si、AlN、SiC、金刚石、石墨、GaN、石英中的一种或其任意组合。本领域技术人员可以理解的是，上述Si、AlN、SiC、金刚石、石墨、GaN、石英仅为示意性举例，第二衬底层105材料的实际选择和第一衬底层100的材料有关。其中，针对于第二衬底层105的材料是半导体材料的情况，优选该半导体材料的电阻率大于
Figure PCTCN2022133602-appb-000002
此外，第二衬底层105的厚度范围优选是3μm至10μm。
在本实施例中，导热孔结构形成在第一衬底层100中。具体地，第一衬底层100在厚度方向上形成有贯穿该第一衬底层100的至少一个通孔，该至少一个通孔内填充有第一导热材料103。其中，第一导热材料103的上表面和下表面分别与第一衬底层100的上表面和下表面齐平。针对于任一通孔来说，其与位于其上端开口处的第二衬底层105的底面共同构成一个第一盲孔，并与填充在该通孔内的第一导热材料103进一步构成导热孔结构。由于导热孔结构的和第一衬底层100的厚度相同，所以导热孔结构的高度范围优选也是30μm至100μm。
在本实施例中，第一导热材料103的热导率高于第一衬底层100材料的热导率。在本实施例中，第一导热材料103优选采用高热导率的金属材料实现，例如Cu、Au、Ag、Al、Ni、Fe、Mo、W中的一种或其任意组合。当然第一导热材料也可以采用热导率高于第一衬底层100的非金属材料实现。
优选地，如图9所示，在第一衬底层100与第一导热材料103之间还形成有粘附层102。粘附层102采用粘附性好的金属材料制成，优选是Ti、TiW、Cr中的一种或其任意组合。粘附层102的厚度范围优选是0.1μm至 0.5μm。粘附层102的作用一方面在于提高第一导热材料103与第一衬底层100之间的附着力，另一方面还可以阻挡第一导热材料103的原子扩散至第一衬底层100中。
优选地，在粘附层102和第一导热材料103之间还形成有种子层(未示出)。在本实施例中，种子层的材料与第一导热材料103相同。
本发明所提供的器件芯片其衬底结构还包括形成在衬底结构上的至少一个器件单元。如图9所示，在本实施例中，所有器件单元均为谐振单元，每一谐振单元从下至上依次包括下电极107a、压电层108以及上电极109，每一谐振单元与衬底结构之间形成有空腔106。需要说明的是，(1)空腔106形成在第二衬底层105内，因此其深度小于等于第二衬底层105的厚度；(2)实际的器件芯片往往包括多个器件单元，此处为了简明起见，仅在图9中绘制了一个器件单元用以示意，而省略了其他器件单元以及器件单元之间的连接关系。(3)典型地，器件芯片除了下电极107a之外往往还会形成与下电极连接的连接部(虚线圈起的部分)，用于后续封装时将器件单元的信号引出、或者用于器件单元之间的电连接。(4)图9中附图标记107b的部分形成在衬底结构的边缘(即位于所述器件单元的外侧)，后续密封环形成在该部分之上。
器件芯片封装形成封装结构后，器件芯片中器件单元所产生的热量在衬底结构一侧通过散热通道向外部传递。基于本实施例所提供的器件芯片，其衬底结构从上至下依次是第二衬底层105以及第一衬底层100，第一衬底层100中形成有厚度方向上贯穿第一衬底层100的导热孔结构。其中，第二衬底层105材料的热导率大于第一衬底层100材料的热导率，有利于使器件单元所产生的热量高效传递至第一衬底层100。第一衬底层100中导热孔结构的热导率大于第一衬底层100材料的热导率，有利于使传递至第一衬底层100的热量通过导热孔结构向封装结构外部高效传递。如此一来，为封装结构中的器件单元在衬底结构一侧提供了低热阻高热导率的散热通道。相较于衬底结构为单层结构的情况(即衬底结构中除了导热孔结构之外的其他部分采用同一种衬底材料制成的情况)，本实施例中，将衬底结构沿散热通道方向设置为第二衬底层105和第一衬底层100两层结构、且令第二 衬底层105的热导率大于第一衬底层100的热导率，可以更进一步提高封装结构的散热效率。当然本领域技术人员可以理解的是，在其他实施例中，第二衬底层105的热导率还可以等于第一衬底层100的热导率。
本发明对于导热孔结构的具体形状不做任何限定，例如其水平方向的截面可以是多边形、圆形等任意规则形状，也可以是任意不规则形状。请参考图10(a)，图10(a)是根据本发明一个具体实施例的第一衬底层的俯视示意图，其中忽略了粘附层以及种子层的绘制。如图10(a)所示，在本实施例中，导热孔结构在水平方向上的截面呈矩形形状。
本发明中，定义器件芯片中所有导热孔结构在水平方向上的投影为第一投影，该第一投影的面积称为第一投影面积(即所有导热孔结构在水平方向上的投影面积之和)；以及定义器件芯片在水平方向上的投影为第二投影，该第二投影的面积称为第二投影面积。此处需要说明的是，器件芯片上会留出形成环形键合部的区域，该环形键合部用于后续与盖帽的键合部进行键合以形成密封环，从而将器件芯片上的器件单元密封在器件芯片、盖帽以及密封环所形成的密封空间内。将器件芯片上环形键合部区域的外侧边缘定义为器件芯片的边界，相应地器件芯片上环形键合部区域的外侧边缘在水平方向上的投影即为器件芯片在水平方向上的第二投影。为了使导热孔结构可以实现有效的热量传递，优选地，导热孔结构的第一投影面积与器件芯片的第二投影面积的比例范围是30％至90％。
考虑到器件芯片的主要发热部是器件单元，所以优选地使器件单元下方区域内导热孔结构分布的更为密集些。具体地，第一衬底层100可以被划分成与器件单元一一对应的核心区域，每一核心区域位于相对应的器件单元的下方。第一衬底层100除了核心区域之外的其他区域称为非核心区域。其中，核心区域中导热孔结构的分布密度大于非核心区域中导热孔结构的分布密度。本发明中，针对于每一器件单元和与其相对应的核心区域来说，定义前者在水平方向上的投影是第三投影、以及定义后者在水平方向上的投影是第四投影。在一个具体实施例中，第三投影的边缘和第四投影的边缘构成环形形状(可以是第三投影落入第四投影的范围内、也可以是第四投影落入第三投影的范围内)，该环形形状的宽度小于等于100μm。 此处需要说明的是，针对于器件单元是谐振单元的情况，器件单元的第三投影主要指的是下电极在水平方向上的投影。此外，本领域技术人员可以理解的是，在其他实施例中，导热孔结构也可以如图10(a)所示均匀分布在第一衬底层100中。
针对于导热孔结构的数量大于等于2个的情况，本发明所提供的器件芯片衬底结构中的第一衬底层上还形成有互联结构(下文以第一互联结构表示)，其中，第一衬底层上表面形成有连通导热孔结构的凹槽，该第一互联结构形成在该凹槽内以使导热孔结构内的第一导热材料之间形成连通。请参考图10(b-1)、图10(b-2)以及10(b-3)，图10(b-1)是根据本发明一个具体实施例的第一衬底层的俯视示意图，图10(b-2)和图10(b-3)分别是图(b-1)所示结构沿线AA’线和BB’线的剖面示意图。如图所示，第一互联接结构103’嵌入在第一衬底层100上表面的凹槽内，各导热孔结构中的第一导热材料103通过第一互联结构103’形成互联。本领域技术人员可以理解的是，第一互联结构不应仅仅限制为图10(b-1)中所示结构，凡是可以使热量在部分或全部导热孔结构之间传递的结构均适用于本发明中的第一互联结构，为了简明起见，在此不再对第一互联结构的所有可能进行一一列举。第一互联结构的存在可以使器件单元所产生的热量快速地通过所有导热孔结构进行传递，从而更进一步地提高散热效率。
在本发明所提供的器件芯片中，衬底结构进一步还包括形成在第一衬底层和第二衬底层之间的第三衬底层，该第三衬底层与第一衬底层中导热孔结构中的第一导热材料连接。第三衬底层的材料是导热材料(下文以第二导热材料表示)，其中，第二导热材料的热导率大于第一衬底层材料的热导率。优选采用高热导率的金属材料实现，例如Cu、Au、Ag、Al、Ni、Fe、Mo、W中的一种或其任意组合。当然第二导热材料也可以采用热导率高于第一衬底层的非金属材料实现。此外需要说明的是，对于第二导热材料来说，其可以是单晶材料、也可以是多晶材料，或者是单晶材料和多晶材料的组合，本发明对此不做任何限定。第三衬底层的存在有利于热量从第二衬底层向第一衬底层的传递，从而进一步提高散热效率。此外，第三衬底层的厚度范围优选小于等于50μm。
第三衬底层的材料可以不同于第一导热材料，如图11所示，第三衬底层104和导热孔结构中的第一导热材料103是独立的两个部分。第三衬底层材料也可以与第一导热材料相同，如图12所示，第三衬底层104和导热孔结构中的第一导热材料103呈现为一体化结构。
此处需要说明的是，针对于衬底结构中通过设置第三衬底层以实现热量由第二衬底层向第一衬底层高效传递的情况，第一衬底层和第二衬底层其二者的材料可以不同，也可以相同。
图11所示结构中第三衬底层104是一整层，在其他实施例中，考虑到器件芯片的主要发热部是器件单元，还可以优选使第三衬底层仅形成在器件单元下方。所以在一个优选实施例中，第三衬底层包括与器件单元一一对应的导热区域，每一导热区域位于与其相对应的器件单元的下方。针对于器件单元的数量大于等于2个的情况，更为优选地，第三衬底层还包括互联结构(下文以第二互联结构表示)，该第二互联结构使导热区域之间形成互联。请参考图13(a)和图13(b)。图13(a)中第三衬底层104仅包括位于器件单元下方的导热区域，其中，图中仅示意性地绘制了两个器件单元以及位于其下方的导热区域而忽略了器件芯片的其他组成部分，且器件单元为谐振单元在图中以下电极107代表。图13(b)中第三衬底层包括位于器件单元下方的导热区域104a以及用于导热区域104a互联的第二互联结构104b，其中，图中仅示意性地绘制了两个器件单元、位于该两个器件单元下方的导热区域以及第二互联结构而忽略了器件芯片的其他组成部分，且器件单元为谐振单元在图中以下电极107代表。本领域技术人员应该可以理解的是，位于器件单元下方的导热区域呈现为片状而并非环状，针对于图13(a)和图13(b)来说，导热区域是形状为正五边形的区域而并非是环状区域。此外，本领域技术人员可以理解的是，导热区域以及第二互联结构不应仅仅限制为图13(b)中所示结构，例如导热区域可以是正五边形以外的其他多边形、还可以是圆形等，甚至是不规则形状，为了简明起见，在此不再对导热区域以及第二互联结构的所有可能进行一一列举。第二互联结构的存在可以使器件单元所产生的热量快速地通过第三衬底层向第一衬底层传递，从而更进一步地提高散热效率。
进一步地，本发明中，定义第三衬底层在水平方向上的投影为第五投影，相应地该第五投影的面积称为第五投影面积；以及定义第三衬底层中每一导热区域在水平方向上的投影为第六投影，相应地该第五投影的面积称为第五投影面积。为了确保第三衬底层的热量传递效果，在一个优选实施例中，第三衬底层的第五投影面积与器件芯片的第二投影面积的比例范围是30％至90％；以及每一导热区域的第六投影与相对应的器件单元的第三投影之间存在重叠区域，该重叠区域在水平方向上的投影面积与该器件单元的第三投影面积的比例大于50％。
本发明还提供了一种器件芯片的制造方法。请参考图2，图2是根据本发明一个具体实施例的器件芯片的制造方法流程图。如图所示，该制造方法包括：
在步骤S101中，形成衬底结构，该衬底结构底部形成有至少一个导热孔结构，每一所述导热孔结构均包括形成在所述衬底结构底部的第一盲孔以及填充在该第一盲孔内的第一导热材料；
在步骤S102中，在所述衬底结构上形成至少一个器件单元。
下面，对上述步骤S101至步骤S102进行详细说明。
具体地，在步骤S101中，形成衬底结构，该衬底结构的底部形成有至少一个导热孔结构。在本实施例中，每一导热孔结构均包括形成在衬底结构底部的盲孔(下文以第一盲孔表示)以及填充在该第一盲孔内的导热材料(下文以第一导热材料表示)。其中，第一导热材料的下表面与衬底结构的下表面齐平。
上述衬底结构存在多种实现方式。举例说明，可以首先提供衬底，接着刻蚀衬底的下表面以形成至少一个第一盲孔，最后利用第一导热材料对第一盲孔进行填充以形成导热孔结构，至此衬底结构形成。本领域技术人员可以理解的是，上述举例仅为示意性说明，凡是可以形成上述底部具有导热孔结构的衬底结构的方法均落入本发明的保护范围内，为了简明起见，在此不再对步骤S101的所有实现方式一一进行描述。
在本实施例中，第一盲孔的深度小于衬底结构的厚度，相应地导热孔结构的高度小于衬底结构的厚度。本发明对衬底结构的厚度以及导热 孔结构的高度不做任何限定，可以根据实际设计需求相应制定。为了提升衬底结构的散热性能，优选地，衬底结构的厚度不超过100μm，导热孔结构的高度大于30μm。
在本实施例中，衬底结构的主体部分(即衬底结构中除了导热孔结构之外的部分)可以采用现有常规的衬底材料实现。此处为了简明起见，不再对现有常规的衬底材料进行一一列举。此外，在本实施例中，第一导热材料的热导率高于衬底结构主体部分材料的热导率。优选地，第一导热材料采用高热导率的金属材料实现，例如Cu、Au、Ag、Al、Ni、Fe、Mo、W中的一种或其任意组合。本领域技术人员可以理解的是，第一导热材料不应仅仅限于金属材料，在其他实施例中，热导率高于衬底结构主体部分的非金属材料也适用于第一导热材料，为了简明起见，在此不再对第一导热材料的所有可能进行一一列举。此外需要说明的是，对于第一导热材料来说，其可以是单晶材料、也可以是多晶材料，或者是单晶材料和多晶材料的组合，本发明对此不做任何限定。
在步骤S102中，在衬底结构上形成至少一个器件单元。在一个具体实施例中，器件单元是谐振单元，该谐振单元从下至上依次是下电极、压电层以及上电极，且每一谐振单元与衬底结构之间形成有用于声波反射的声反射结构。例如，该声反射结构可以是空腔、布拉格反射层等。其中，每一谐振单元与位于其下方的声反射结构以及衬底构成体声波谐振器。相应地，器件芯片可以是体声波滤波器芯片、双工器芯片、或多工器芯片。本领域技术人员可以理解，器件单元以及器件芯片不应仅限于上述示意性举例，凡是可以形成在衬底结构上的器件单元均落入本发明的保护范围，为了简明起见，在此不再对器件单元所有可能进行一一列举。此外需要说明的是，(1)器件单元的具体数量由器件芯片的实际设计需求决定，本发明对此不做任何限制；2)本发明主要是针对于器件芯片中衬底结构进行改进，所以对如何在衬底结构上形成器件单元不做任何限定，本领域技术人员可以根据器件芯片的具体类型采用现有以及未来可能出现的制造方法在衬底结构上形成器件单元。考虑到器件单元以及制造方法存在众多可能性，所以在此不再对器件单元所有可能的形成过程一一进行说明。
实施本发明所提供的器件芯片的制造方法，可以在衬底结构的底部形成有高热导率材料构成的导热孔结构。如此一来，对器件芯片进行封装形成封装结构后，器件芯片中器件单元工作所产生的热量在衬底结构一侧的散热通道进行传递时，可以通过衬底结构中的导热孔结构向外部高效传递热量，从而有效地提高了封装结构的散热效率。封装结构散热效率的提高有利于降低器件单元的温度，从而使封装结构的寿命、可靠性以及功率承载能力得到提高。特别是针对于器件单元下方存在空腔的情况，尤为适用。
下面将结合附图以一个优选实施例对本发明所提供的器件芯片的制造方法进行说明。
如图3所示，提供第一衬底层100。在本实施例中，第一衬底层100的材料是绝缘材料或半导体材料，例如Si、SiO2、SiN、AlN、SiC、蓝宝石中的一种或任意组合。本领域技术人员可以理解的是，上述Si、SiO2、SiN、AlN、SiC、蓝宝石仅为示意性举例，凡是现有以及未来可能出现的适用于衬底的材料均适用于本发明中的第一衬底层，为了简明起见，在此不再对第一衬底层所有可能的材料进行一一列举。针对于第一衬底层100的材料是半导体材料的情况，优选该半导体材料的电阻率大于
Figure PCTCN2022133602-appb-000003
接着，如图4所示，对第一衬底层100的上表面进行刻蚀，以在第一衬底层100上形成至少一个盲孔101(下文以第二盲孔表示)，其中，第二盲孔的深度小于第一衬底层100的厚度。优选地，如图5所示，在形成第二盲孔101之后，在第一衬底层100上沉积形成粘附层102，该粘附层102对第一衬底层100上表面以及第二盲孔101的表面(即第二盲孔101的侧壁和底面)形成覆盖。粘附层102采用粘附性好的金属材料制成，优选是Ti、TiW、Cr中的一种或其任意组合。粘附层102的厚度范围优选是0.1μm至0.5μm。粘附层102的作用一方面在于提高后续步骤中第二盲孔101内所填充的第一导热材料与第二盲孔101表面之间的附着力，另一方面还可以阻挡第一导热材料的原子扩散至第一衬底层100中。下面将基于图5所示结构对后续步骤进行说明。
接着，如图6所示，在第二盲孔101中填充第一导热材料103，该 第一导热材料103的上表面与第一衬底层100的上表面齐平。其中，第一导热材料103的热导率高于第一衬底层100材料的热导率。在本实施例中，第一导热材料103优选采用高热导率的金属材料实现，例如Cu、Au、Ag、Al、Ni、Fe、Mo、W中的一种或其任意组合。当然第一导热材料也可以采用热导率高于第一衬底层100的非金属材料实现。需要说明的是，在盲孔内填充材料可以采用本领域的常规技术手段实现。下面仅以第一导热材料103是金属材料为例进行说明。首先通过电镀的方式在粘附层102表面形成金属层，该金属层对第二盲孔101形成填充；接着对第一衬底层100上表面的金属层以及粘附层102进行平坦化操作直至暴露第一衬底层100的上表面，仅保留第二盲孔101中的金属层部分。优选地，在第二盲孔101中填充第一导热材料103之前，在粘附层102上沉积形成种子层(未示出)，其中，种子层的材料与第一导热材料103相同。
接着，如图7所示，在第一衬底层100上沉积第二衬底层105，对图6所示结构的上表面形成覆盖。在本实施例中，第二衬底层105的材料是高热导率的绝缘材料或半导体材料，其热导率大于第一衬底层100的热导率。例如Si、AlN、SiC、金刚石、石墨、GaN、石英中的一种或其任意组合。本领域技术人员可以理解的是，上述Si、AlN、SiC、金刚石、石墨、GaN、石英仅为示意性举例，第二衬底层105材料的实际选择和第一衬底层100的材料有关。其中，针对于第二衬底层105的材料是半导体材料的情况，优选该半导体材料的电阻率大于
Figure PCTCN2022133602-appb-000004
此外，第二衬底层105的厚度范围优选是3μm至10μm。
接着，如图8所示，对第一衬底层100的下表面进行平坦化操作使第一导热材料103暴露以及使第一衬底层100的厚度符合设计要求，至此衬底结构形成。其中，第二盲孔的侧壁以及第二衬底层105的底面构成开设在衬底结构底部的第一盲孔，该第一盲孔以及填充在内的第一导热材料103构成导热孔结构。平坦化操作后第一衬底层100的厚度范围优选是30μm至100μm。由于衬底结构中导热孔结构在厚度方向上贯穿第一衬底层100，所以导热孔结构的高度和第一衬底层100的厚度相同。
此处需要说明的是，在本实施例中，先形成第二衬底层105然后 再对第一衬底层100的下表面进行平坦化操作，在其他实施例中，还可以先对第一衬底层100的下表面进行平坦化操作然后再形成第二衬底层105，甚至是在第二衬底层105上形成声反射结构以及器件单元并与相匹配的盖帽进行封装后，再对第一衬底层100的下表面进行平坦化操作。
最后，如图9所示，在衬底结构上形成至少一个器件单元以得到器件芯片。在本实施例中，所有器件单元均为谐振单元，每一谐振单元从下至上依次包括下电极107a、压电层108以及上电极109，每一谐振单元与衬底结构之间形成有空腔106。具体实现过程如下：首先对衬底结构的上表面(即第二衬底层105的上表面进行刻蚀以形成凹槽，接着利用牺牲材料对该凹槽进行填充，接着在该牺牲材料上方依次形成下电极107a、压电层108以及上电极109，其中下电极107a、压电层108以及上电极109在牺牲材料上方存在重叠区域，最后释放牺牲材料以在下电极107a和衬底结构之间形成空腔106。需要说明的是，(1)空腔106形成在第二衬底层105内，因此其深度小于等于第二衬底层105的厚度；(2)实际的器件芯片往往包括多个器件单元，此处为了简明起见，仅在图9中绘制了一个器件单元用以示意，而省略了其他器件单元以及器件单元之间的连接关系。(3)典型地，除了下电极107a之外往往还会形成与下电极连接的连接部(虚线圈起的部分)，用于后续封装时将器件单元的信号引出、或者用于器件单元之间的电连接。(4)图9中附图标记107b的部分形成在衬底结构的边缘(即位于所述器件单元的外侧)，后续密封环形成在该部分之上。其中，该部分往往和下电极107a同时形成。
器件芯片封装形成封装结构后，器件芯片中器件单元所产生的热量在衬底结构一侧通过散热通道向外部传递。基于本实施例所形成的器件芯片，其衬底结构从上至下依次是第二衬底层105以及第一衬底层100，第一衬底层100中形成有厚度方向上贯穿第一衬底层100的导热孔结构。其中，第二衬底层105材料的热导率大于第一衬底层100材料的热导率，有利于使器件单元所产生的热量高效传递至第一衬底层100。第一衬底层100中导热孔结构的热导率大于第一衬底层100材料的热导率，有利于使传递至第一衬底层100的热量通过导热孔结构向封装结构外部高效传递。如此一来，为封 装结构中的器件单元在衬底结构一侧提供了低热阻高热导率的散热通道。相较于衬底结构为单层结构的情况(即衬底结构中除了导热孔结构之外的其他部分采用同一种衬底材料制成的情况)，本实施例中，将衬底结构沿散热通道方向设置为第二衬底层105和第一衬底层100两层结构、且令第二衬底层105的热导率大于第一衬底层100的热导率，可以更进一步提高封装结构的散热效率。当然本领域技术人员可以理解的是，在其他实施例中，第二衬底层105的热导率还可以等于第一衬底层100的热导率。
本发明对于导热孔结构的具体形状不做任何限定，例如其水平方向的截面可以是多边形、圆形等任意规则形状，也可以是任意不规则形状。请参考图10(a)，图10(a)是根据本发明一个具体实施例的第一衬底层的俯视示意图，其中忽略了粘附层以及种子层的绘制。如图10(a)所示，在本实施例中，导热孔结构在水平方向上的截面呈矩形形状。
本发明中，定义器件芯片中所有导热孔结构在水平方向上的投影为第一投影，该第一投影的面积称为第一投影面积(即所有导热孔结构在水平方向上的投影面积之和)；以及定义器件芯片在水平方向上的投影为第二投影，该第二投影的面积称为第二投影面积。此处需要说明的是，器件芯片上会留出形成环形键合部的区域，该环形键合部用于后续与盖帽的键合部进行键合以形成密封环，从而将器件芯片上的器件单元密封在器件芯片、盖帽以及密封环所形成的密封空间内。将器件芯片上环形键合部区域的外侧边缘定义为器件芯片的边界，相应地器件芯片上环形键合部区域的外侧边缘在水平方向上的投影即为器件芯片在水平方向上的第二投影。为了使导热孔结构可以实现有效的热量传递，优选地，导热孔结构的第一投影面积与器件芯片的第二投影面积的比例范围是30％至90％。
考虑到器件芯片的主要发热部是器件单元，所以优选地使器件单元下方区域内导热孔结构分布的更为密集些。具体地，第一衬底层100可以被划分成与器件单元一一对应的核心区域，每一核心区域位于相对应的器件单元的下方。第一衬底层100除了核心区域之外的其他区域称为非核心区域。其中，核心区域中导热孔结构的分布密度大于非核心区域中导热孔结构的分布密度。本发明中，针对于每一器件单元和与其相对应的核心区域 来说，定义前者在水平方向上的投影是第三投影、以及定义后者在水平方向上的投影是第四投影。在一个具体实施例中，第三投影的边缘和第四投影的边缘构成环形形状(可以是第三投影落入第四投影的范围内、也可以是第四投影落入第三投影的范围内)，该环形形状的宽度小于等于100μm。此处需要说明的是，针对于器件单元是谐振单元的情况，器件单元的第三投影主要指的是下电极在水平方向上的投影。此外，本领域技术人员可以理解的是，在其他实施例中，导热孔结构也可以如图10(a)所示均匀分布在第一衬底层100中。
针对于导热孔结构的数量大于等于2个的情况，本发明所提供的制造方法中，形成衬底结构的步骤还进一步包括：在第一衬底层上形成互联结构(下文以第一互联结构表示)，该第一互联结构形成在第一衬底层上表面的凹槽内并使导热孔结构内的第一导热材料之间形成连通。在一个具体实施例中，可以通过刻蚀第一衬底层的上表面以形成用于连通第二盲孔的凹槽，并在该凹槽内填充导热材料(可以是第一导热材料，也可以是其他导热材料)以形成第二互联结构。本文对于第二互联结构形成步骤的执行顺序不作任何限定，例如可以在利用第一导热材料填充第二盲孔之后执行，又或是在形成第二盲孔之后刻蚀第一衬底层上表面形成凹槽、并在对第二盲孔进行填充的同时对该凹槽也进行填充，等等。请参考图10(b-1)、图10(b-2)以及10(b-3)，图10(b-1)是根据本发明一个具体实施例的第一衬底层的俯视示意图，图10(b-2)和图10(b-3)分别是图(b-1)所示结构沿线AA’线和BB’线的剖面示意图。如图所示，第一互联接结构103’嵌入在第一衬底层100上表面的凹槽内，各导热孔结构中的第一导热材料103通过第一互联结构103’形成互联。本领域技术人员可以理解的是，第一互联结构不应仅仅限制为图10(b-1)中所示结构，凡是可以使热量在部分或全部导热孔结构之间传递的结构均适用于本发明中的第一互联结构，为了简明起见，在此不再对第一互联结构的所有可能进行一一列举。第一互联结构的存在可以使器件单元所产生的热量快速地通过所有导热孔结构进行传递，从而更进一步地提高散热效率。
在本发明所提供的制造方法中，形成衬底结构的步骤进一步还包 括：在第一衬底层和第二衬底层之间形成第三衬底层，该第三衬底层与第一衬底层中导热孔结构中的第一导热材料连接。第三衬底层的材料是导热材料(下文以第二导热材料表示)，其中，第二导热材料的热导率大于第一衬底层材料的热导率。优选采用高热导率的金属材料实现，例如Cu、Au、Ag、Al、Ni、Fe、Mo、W中的一种或其任意组合。当然第二导热材料也可以采用热导率高于第一衬底层的非金属材料实现。此外需要说明的是，对于第二导热材料来说，其可以是单晶材料、也可以是多晶材料，或者是单晶材料和多晶材料的组合，本发明对此不做任何限定。第三衬底层的存在有利于热量从第二衬底层向第一衬底层的传递，从而进一步提高散热效率。此外，第三衬底层的厚度范围优选小于等于50μm。
在一个具体实施例中，在对第二盲孔填充第一导热材料之后、以及在第二衬底层形成之前，在第一衬底层上形成第三衬底层。如图11所示，第三衬底层104形成在第一衬底层100和第二衬底层105之间。在另一个具体实施例中，还可以在对第二盲孔填充第一导热材料的同时形成第三衬底层。以在第二盲孔中填充金属材料为例说明。首先通过电镀的方式在粘附层(或种子层)表面形成金属层，通过控制金属层的厚度，一方面使金属层对第二盲孔形成填充，另一方面使金属层在第一衬底层表面上的部分其厚度大于第三衬底层的厚度；接着对金属层进行平坦化操作直至使金属层在第一衬底层表面上的部分其厚度等于第三衬底层的厚度。如此一来，在实现第二盲孔填充的同时还形成了第三衬底层。这种情况下，第三衬底层的材料即为第一导热材料，且第三衬底层和第二盲孔中的填充材料具有一体化结构。如图12所示，第三衬底层104形成在第一衬底层100和第二衬底层105之间、且与第二盲孔中的填充材料呈现为一体化结构。
此处需要说明的是，针对于衬底结构中通过设置第三衬底层以实现热量由第二衬底层向第一衬底层高效传递的情况，第一衬底层和第二衬底层其二者的材料可以不同，也可以相同。
图11所示结构中第三衬底层104是一整层，在其他实施例中，考虑到器件芯片的主要发热部是器件单元，还可以优选使第三衬底层仅形成在器件单元下方。所以在一个优选实施例中，第三衬底层包括与器件单元 一一对应的导热区域，每一导热区域位于与其相对应的器件单元的下方。针对于器件单元的数量大于等于2个的情况，更为优选地，第三衬底层还包括互联结构(下文以第二互联结构表示)，该第二互联结构使导热区域之间形成互联。在一个具体实施例中，第三衬底层的形成过程如下：首先在第一衬底层上沉积第三衬底层材料，接着对第三衬底层材料进行刻蚀以形成与器件单元一一对应的导热区域、以及第二互联结构，其中，每一导热区域位于与其相对应的器件单元的下方，第二互联结构使导热区域之间形成互联。在另一个具体实施例中，还可以是在利用第一导热材料填充第二盲孔时，通过工艺控制使位于第一衬底层以及第二盲孔上方的第一导热材料的厚度大于待形成的第三衬底层的厚度，然后对位于第一衬底层以及第二盲孔上方的第一导热材料进行平坦化操作直至厚度等于待形成的第三衬底层的厚度，最后对位于第一衬底层以及第二盲孔上方的第一导热材料进行图形化以形成第三衬底层。这种方式在填充第二盲孔的同时实现了第三衬底层材料的沉积，有利于工艺的简化。请参考图13(a)和图13(b)。图13(a)中第三衬底层104仅包括位于器件单元下方的导热区域，其中，图中仅示意性地绘制了两个器件单元以及位于其下方的导热区域而忽略了器件芯片的其他组成部分，且器件单元为谐振单元在图中以下电极107代表。图13(b)中第三衬底层包括位于器件单元下方的导热区域104a以及用于导热区域104a互联的第二互联结构104b，其中，图中仅示意性地绘制了两个器件单元、位于该两个器件单元下方的导热区域以及第二互联结构而忽略了器件芯片的其他组成部分，且器件单元为谐振单元在图中以下电极107代表。本领域技术人员应该可以理解的是，位于器件单元下方的导热区域呈现为片状而并非环状，针对于图13(a)和图13(b)来说，导热区域是形状为正五边形的区域而并非是环状区域。此外，本领域技术人员可以理解的是，导热区域以及第二互联结构不应仅仅限制为图13(b)中所示结构，例如导热区域可以是正五边形以外的其他多边形、还可以是圆形等，甚至是不规则形状，为了简明起见，在此不再对导热区域以及第二互联结构的所有可能进行一一列举。第二互联结构的存在可以使器件单元所产生的热量快速地通过第三衬底层向第一衬底层传递，从而更进一步地提高散热效率。
进一步地，本发明中，定义第三衬底层在水平方向上的投影为第五投影，相应地该第五投影的面积称为第五投影面积；以及定义第三衬底层中每一导热区域在水平方向上的投影为第六投影，相应地该第五投影的面积称为第五投影面积。为了确保第三衬底层的热量传递效果，在一个优选实施例中，第三衬底层的第五投影面积与器件芯片的第二投影面积的比例范围是30％至90％；以及每一导热区域的第六投影与相对应的器件单元的第三投影之间存在重叠区域，该重叠区域在水平方向上的投影面积与该器件单元的第三投影面积的比例大于50％。
本发明还提供了一种封装结构，该封装结构包括：
前述器件芯片；
盖帽，该盖帽的正面与所述器件芯片相对设置、背面设置有连接部；
密封环，该密封环设置在所述器件芯片和所述盖帽之间，与所述器件芯片和所述盖帽形成密封结构，所述至少一个器件单元位于该密封结构的腔体内；
封装基板，所述密封结构通过所述连接部与所述封装基板形成连接；
塑封体，该塑封体对所述密封结构形成包裹。
下面对上述封装结构的各个构成部分进行详细说明。
具体地，本发明所提供的封装结构包括器件芯片，该器件芯片采用本发明前述器件芯片实现。为了简明起见，在此不再对器件芯片的具体结构进行说明，该具体结构可以参考前文相关部分的内容。下面将以基于图11所示器件芯片所形成的封装结构为例进行说明。
如图19所示，本发明所提供的封装结构还包括盖帽，该盖帽的正面与器件芯片相对设置。在本实施例中，盖帽包括本体200、第一导通孔(TSV)结构以及连接部205。第一导通孔结构形成在本体200内，其中，第一导通孔结构包括厚度方向上贯穿本体200的通孔、以及填充在该通孔内的金属材料201(例如Cu等)。优选地，金属材料201与通孔侧壁之间还可 以形成有粘附层202。连接部205形成在盖帽本体200的背面。在本实施例中，连接部205是形成在盖帽本体200背面的焊球并与第一导通孔结构形成连接。需要说明的是，在其他实施例中，盖帽本体200正面与器件单元相对应的位置上还可以形成凹槽，用于封装后使器件芯片上的器件单元与盖帽之间保持足够的距离，以确保器件单元的性能不受影响。
如图19所示，本发明所提供的封装结构还包括密封环300a，该密封环300a设置在器件芯片和盖帽之间，与器件芯片和盖帽三者形成密封结构，器件芯片中的器件单元位于该密封结构的腔体301内。在本实施例中，密封环300a的材料是例如Au等键合材料。需要说明的是，如图19所示，该密封结构中还包括位于腔体301内的连接结构300b，该连接结构300b的一端与器件芯片中器件单元下电极107的连接部连接、另一端与盖帽上的第一导通孔连接，以用于器件单元的信号引出。优选地，密封环300a和连接结构300b与盖帽之间形成有粘附层204，以及密封环300a和连接结构300b与器件芯片之间形成有粘附层120。
如图19所示，本发明所提供的封装结构还包括封装基板。在本实施例中，封装基板包括基板本体400、形成在基板本体400正面(朝向密封结构的表面)的正面焊盘401、形成在基本400背面的背面焊盘402、以及形成在基板本体400内用于实现正面焊盘401和背面焊盘402电连接的第二导通孔结构403。其中，正面焊盘401形成在基板本体400正面与盖帽背面焊球205(即连接部205)对应的位置上，通过将盖帽背面焊球205焊接至封装基板的正面焊盘401上，以实现密封结构与封装基板的连接。本领域技术人员可以理解的是，根据实际设计需求，基板本体400内通常还会形成有例如螺旋电感等电子元器件(未示出)，器件芯片上的器件单元可以通过连接结构300b、盖帽中的第一导通孔结构、焊球205、基板本体400的正面焊盘401以及基板本体400内的导通孔结构(未示出)与基板本体400内的电子元器件形成电连接，这些均为现有常规技术手段，为了简明起见，在此不再赘述。
如图19所示，本发明所提供的封装结构还包括塑封体500，该塑封体500对密封结构形成包裹。塑封体500的材料采用常规技术手段实现即 可，为了简明起见，在此不再赘述。
此处需要说明的是，由于器件芯片倒装在封装基板上，所以相应地封装结构为倒封装结构。
本发明所提供的封装结构采用前述器件芯片实现。本发明所提供的封装结构工作时，器件芯片中的器件单元所产生的热量可以通过衬底结构中的导热孔结构向外部高效传递热量。因此，相较于现有封装结构来说，本发明所提供的封装结构具有更优的散热效率。而优异的散热效率使本发明所提供的封装结构其寿命更长、可靠性更高、功率承载能力也更强。
本发明还提供了一种封装结构的制造方法。请参考图14，图14是根据本发明一个具体实施例的封装结构的制造方法流程图。如图所示，该制造方法包括：
在步骤S201中，提供前述器件芯片、或是利用前述制造方法形成器件芯片；
在步骤S202中，提供盖帽，该盖帽的正面与所述器件芯片相对设置；
在步骤S203中，在所述器件芯片和所述盖帽之间形成密封环，该密封环与所述器件芯片和所述盖帽形成密封结构，所述至少一个器件单元位于该密封结构的腔体内；
在步骤S204中，在所述盖帽背面形成连接部并通过该连接部将所述密封结构连接至封装基板；
在步骤S205中，形成对所述密封结构包裹的塑封体。
下面将结合图15至图19对上述步骤S201至步骤S205进行详细说明。
具体地，在步骤S201中，提供器件芯片或是形成器件芯片，其中，器件芯片采用本发明前述器件芯片实现或是利用本发明前述制造方法实现。为了简明起见，在此不再对器件芯片的形成过程进行说明，该形成过程可以参考前文相关部分的内容。下面将以图11所示的器件芯片为例对后续步骤进行说明。
形成器件芯片后还需要在器件芯片的第一键合区域内形成第一 键合结构。典型地，如图15所示，第一键合结构包括第一键合部121a以及第二键合部121b。其中，第一键合部121a形成在器件芯片的边缘区域，后续用于形成密封环；第二键合部121b形成在器件芯片的内部区域，通过连接部与下电极107a连接，用于后续器件单元的信号引出。第一键合部121a和第二键合部121b采用现有常规键合材料(例如Au等)制成。优选地，在形成第一键合结构之前，在第一键合区域内形成粘附层120。
在步骤S202中，提供与器件芯片配合使用的盖帽，该盖帽的正面与器件芯片相对设置。在本实施例中，如图16所示，盖帽包括本体200以及第一导通孔(TSV)结构。第一导通孔结构形成在本体200内，其中，第一导通孔结构包括厚度方向上贯穿本体200的通孔、以及填充在该通孔内的金属材料201(例如Cu等)。优选地，金属材料201与通孔侧壁之间还可以形成有粘附层202。盖帽上还形成有第二键合结构，该第二键合结构形成在本体200的正面并与第一导通孔结构形成连接，其中，第二键合结构包括与器件芯片第一键合部121a对应的第三键合部203a、以及与器件芯片第二键合部121b对应的第四键合部203b。第三键合部203a和第四键合部203b采用现有常规键合材料(例如Au等)制成。优选地，第二键合结构与盖帽本体200之间还形成有粘附层204。
需要说明的是，在其他实施例中，盖帽本体200正面与器件单元相对应的位置上还可以形成凹槽，用于封装后使器件芯片上的器件单元与盖帽之间保持足够的距离，以确保器件单元的性能不受影响。
在步骤S203中，如图17所示，将盖帽的第三键合部203a与器件芯片的第一键合部121a对准、以及将盖帽的第四键合部203b与器件芯片的第二键合部121b对准，然后对盖帽和器件芯片进行键合固定。其中，盖帽的第三键合部203a与器件芯片的第一键合部121a键合连接形成密封环300a，该密封环300a与盖帽以及器件芯片三者形成密封结构，器件芯片中的器件单元位于该密封结构的腔体301内。此外，盖帽的第四键合部203b与器件芯片的第二键合部121b键合后形成用于信号引出的连接结构300b，该连接结构300b也位于密封结构的腔体301内。
在步骤S204中，如图18所示，在盖帽背面形成连接部205并通过 该连接部205将密封结构连接至封装基板。在本实施例中，连接部205是焊球，该焊球形成在盖帽本体200的背面并与第一导通孔结构连接。封装基板包括基板本体400、形成在基板本体400正面(朝向密封结构的表面)的正面焊盘401、形成在基本400背面的背面焊盘402、以及形成在基板本体400内用于实现正面焊盘401和背面焊盘402电连接的第二导通孔结构403。其中，正面焊盘401形成在基板本体400正面与盖帽背面焊球205对应的位置上，通过将盖帽背面焊球205焊接至封装基板的正面焊盘401上，以实现密封结构与封装基板的连接。本领域技术人员可以理解的是，根据实际设计需求，基板本体400内通常还会形成有例如螺旋电感等电子元器件(未示出)，器件芯片上的器件单元可以通过连接结构300b、盖帽中的第一导通孔结构、焊球205、基板本体400的正面焊盘401以及基板本体400内的导通孔结构(未示出)与基板本体400内的电子元器件形成电连接，这些均为现有常规技术手段，为了简明起见，在此不再赘述。
在步骤S205中，如图19所示，对密封结构进行塑封，以形成对密封结构包裹的塑封体500。塑封的实现过程以及塑封体500的材料采用常规技术手段实现即可，为了简明起见，在此不再赘述。
需要说明的是，在形成器件芯片的过程中，包括对第一衬底层100的下表面进行平坦化操作使第一导热材料103暴露的步骤。在一些应用场景中，该步骤也可以在盖帽和器件芯片键合形成密封结构之后执行。
实施本发明所提供的制造方法所形成的封装结构散热效率佳。
在对本发明所提供的散热基板进行说明之前，需要说明的是，本发明所提供的散热基板用于器件芯片的封装。具体地讲，是在对器件芯片进行封装时，将散热基板安装在器件芯片的背面以提升封装结构衬底侧散热通道的散热效果。本发明对于器件芯片的具体类型不做任何限制，凡是衬底上形成有至少一个工作时产生热量的器件单元且需要进行封装的器件芯片均适用于本发明。举例说明，器件单元可以是谐振单元，该谐振单元从下至上依次是下电极、压电层以及上电极，且每一谐振单元与衬底之间形成有用于声波反射的声反射结构(例如空腔、布拉格反射层等)。其中，每一谐振单元与位于其下方的声反射结构以及衬底构成体声波谐振器。相 应地，器件芯片可以是滤波器芯片、双工器芯片、多工器芯片、传感器芯片等。本领域技术人员可以理解，器件单元以及器件芯片不应仅限于上述示意性举例，为了简明起见，在此不再对器件单元以及器件芯片的所有可能进行一一列举。下面将以器件单元是谐振单元、器件芯片是滤波器为例对本发明所提供的散热基板进行说明。
本发明提供了一种散热基板，该散热基板包括：
基板本体；
至少一个第一导热孔结构，其中，每一所述第一导热孔结构均包括在厚度方向上贯穿所述基板本体的第一通孔、以及填充在该第一通孔内的第一导热材料；
第一连接部，该第一连接部形成在所述基板本体的正面，所述散热基板通过所述第一连接部连接至器件芯片的背面。
下面将结合图21(d)对上述散热基板的各个组成部分进行详细说明。
具体地，如图所示，本发明所提供的散热基板包括基板本体500。在本实施例中，基板本体500采用绝缘材料或者半导体材料实现。需要说明的是，基板本体500的具体类型与其实现材料有关。举例说明，基板本体可以是采用诸如BT(双马来酰亚胺三嗪树脂)、ABF、MIS等材料实现的硬质基板本体，可以是采用诸如AlN、SiC、GaN、Si、Al2O3等单晶/多晶材料实现的陶瓷基板本体，还可以是采用诸如PI(聚酰亚胺树脂)、PE(聚酯树脂)、PPO(二亚苯醚树脂)、PCH树脂等材料实现的柔性基板本体。本领域技术人员可以理解的是，凡是现有以及未来可能出现的适用于形成基板的绝缘材料或半导体材料均适用于本发明中的基板本体，为了简明起见，在此不再对基板本体所有可能的材料进行一一列举。基板本体500的厚度优选小于等于100μm。此外，基板本体500材料的热导率需要高于或等于塑封体材料的热导率。
如图所示，本发明所提供的散热基板还包括至少一个导热孔结构(下文以第一导热孔结构表示)。在本实施例中，每一第一导热孔结构均包括在厚度方向上贯穿基板本体500的通孔(下文以第一通孔表示)、以及 填充在该第一通孔内的导热材料502(下文以第一导热材料502表示)。其中，第一导热材料502的上表面和下表面分别与基板本体500的两个表面齐平，即第一导热孔结构的高度与基板本体500的厚度相同。
在本实施例中，第一导热材料502优选采用高热导率的金属材料及其组合实现，例如Cu、Au、Ag、Al、Ni、Ti、Cr、TiW、Fe、Mo、W中的一种或其任意组合。当然第一导热材料502也可以采用热导率高于基板本体500的合金材料及其组合、或非金属材料实现。
如图所示，本发明所提供的散热基板还包括形成在基板本体500正面的连接部(下文以第一连接部表示)。此处需要说明的是，将散热基板安装时用于与器件芯片连接的表面定义为基板本体的正面，相应地将与基板本体正面相对应的另一个表面定义为基板本体的背面。在本实施例中，第一连接部包括多个第一连接单元，每一连接单元进一步包括凸块503以及焊球504。其中，凸块503形成在散热基板的正面，优选与第一导热孔结构形成连接；焊球504形成在凸块503上。封装时，散热基板通过第一连接部焊接至器件芯片的背面。在本实施例中，凸块503和焊球504均材料高导热率的材料实现。其中，凸块503的材料可以是例如Au、Cu等，焊球504的材料可以是例如SnAg、SnPb、SnCu、Au-Sn焊料、Au-Ge焊料、Au-Si焊料等。焊球504的高度范围优选不超过100μm。需要说明的是，(1)第一连接单元也可以仅包括焊球504；(2)第一连接单元不应仅仅限于上述凸块503和焊球504，凡是可以用于将基板本体500连接至器件芯片且具有良好导热性能的结构均适用于本发明的第一连接部，为了简明起见，在此不再对第一连接部的所有可能结构进行一一列举。
在对器件芯片进行封装时，将散热基板通过其正面的第一连接部连接至器件芯片的背面(即衬底底面)，其中，贯穿基板本体的第一导热孔结构在衬底侧构成高效散热通道，如此一来，当封装结构工作时，器件芯片所产生的热量在衬底侧可以通过该第一导热孔结构向外部高效传递热量，从而有效地提高了封装结构的散热效率。相较于现有技术中器件芯片封装后其背面是导热性不佳的塑封体来说，使用本发明所提供的散热基板散热效果明显更佳。
优选地，基板本体的两个表面还形成有粘附层(未示出)，该粘附层对基板本体的表面以及第一导热孔结构形成覆盖。粘附层采用粘附性好的金属材料制成，例如Ti、TiW、Cr中的一种或其任意组合。粘附层的厚度范围优选是0.1μm至0.5μm。
优选地，如图23(d)所示，本发明所提供的散热基板还包括顶导热层505以及底导热层506，其中，顶导热层505形成在基板本体500的正面，底导热层506形成在基板本体500的背面。更优选地，顶导热层505以及底导热层506分别与基板本体500中的第一导热孔结构连接。顶导热层505的形成有利于将热量向基板本体500以及第一导热孔结构快速传递，底导热层506的形成则有利用将基板本体500以及第一导热孔结构中的热量快速传递至外部空间。本领域技术人员可以理解的，在其他实施例中，也可以仅包括顶导热层或仅包括底导热层。顶导热层505和底导热层506的材料均采用热导率高于器件芯片封装时所使用的塑封体材料的热导率，优选采用高热导率的金属材料及其组合实现，例如Cu、Au、Ag、Al、Ni、Ti、Cr、TiW、Fe、Mo、W中的一种或其任意组合。当然顶导热层505和底导热层506的材料也可以采用热导率高于基板本体500的合金材料及其组合、或非金属材料实现。顶导热层505的材料、第一导热材料502、以及底导热层506的材料其三者可以相同也可以不同。此外，顶导热层505和底导热层506的厚度范围均优选小于等于50μm。此处需要说明的是，针对于散热基板包括顶导热层以及底导热层的情况，粘附层形成在该顶导热层以及底导热层上。
下面对顶导热层505的具体结构进行说明。在一个具体实施例中，顶导热层505是一整层。在其他实施例中，考虑到器件芯片的主要发热部件是器件单元，还可以使顶导热层505主要形成在与器件单元对应的位置上。具体地，顶导热层505包括位置上与器件芯片中各器件单元一一对应的导热区域(下文以第一导热区域表示)。第一导热区域与其相对应的器件单元在位置上对应是指，当散热基板安装至器件芯片上以后，顶导热层505中的第一导热区域位于其相对应的器件单元上方(倒封装结构散热基板位于器件芯片上方)。由于器件芯片的主要发热部件是器件单元，所以将第一导热区域设置在与器件单元相对应位置上，有利于对器件单元所产生的热量 快速进行传递。相较于顶导热层505是一整层的方式，仅在与器件单元相对应的位置上形成第一导热区域虽然散热效果可能在一定程度上有所减弱，但是可以有效减少顶导热层505的用料从而降低散热基板的制造成本。本领域技术人员可以根据实际需求平衡散热效果与制造成本，本发明对此不做任何限定。当器件芯片中的器件单元数量大于1时，顶导热层505中第一导热区域的数量也大于1，这种情况下，优选地，顶导热层505还包括对部分或全部第一导热区域进行互联的互联结构(下文以第一互联结构表示)。第一互联结构的设置可以使器件单元所产生的热量在第一导热区域之间快速传递，有利于散热效率的提升。需要说明的是，每一第一导热区域的水平投影与其对应的器件单元的水平投影之间存在重叠区域(下文以第一重叠区域表示)，为了确保散热效果，第一重叠区域的投影面积与相对应的器件单元的水平投影面积的比例优选大于50％。此处需要说明的是，针对于器件单元是谐振单元的情况，器件单元的水平投影主要指的是下电极的水平投影。
与顶导热层505类似，底导热层506可以是一整层，也可以是包括位置上与器件芯片中各器件单元一一对应的导热区域(下文以第二导热区域表示)。针对于底导热层506包括位置上与器件芯片中各器件单元一一对应的第二导热区域来说，第二导热区域与其相对应的器件单元在位置上对应是指，当散热基板安装至器件芯片上以后，底导热层506中的第二导热区域位于其相对应的器件单元上方(倒封装结构散热基板位于器件芯片上方)。由于器件芯片的主要发热部件是器件单元，所以将第二导热区域设置在与器件单元相对应位置上，有利于将器件单元所产生的热量快速向外部空间进行传递。相较于底导热层506是一整层的方式，仅在与器件单元相对应的位置上形成第二导热区域虽然散热效果可能在一定程度上有所减弱，但是可以有效减少底导热层506的用料从而降低散热基板的制造成本。本领域技术人员可以根据实际需求平衡散热效果与制造成本，本发明对此不做任何限定。当器件芯片中的器件单元数量大于1时，底导热层506中第二导热区域的数量也大于1，这种情况下，优选地，底导热层506还包括对部分或全部第二导热区域进行互联的互联结构(下文以第二互联结构表示)。第二 互联结构的设置可以使基板本体和第一导热孔结构内的热量在第二导热区域之间快速传递，有利于散热效率的提升。需要说明的是，每一第二导热区域的水平投影与其对应的器件单元的水平投影之间存在重叠区域(下文以第二重叠区域表示)，为了确保散热效果，第二重叠区域的投影面积与相对应的器件单元的水平投影面积的比例优选大于50％。
此外，无论顶导热层505的具体结构是一整层还是包括多个第一导热区域，为了确保散热效果，优选地，顶导热层505的水平投影面积与器件芯片的水平投影面积的比例是30％至130％。同样地，无论底导热层506的具体结构是一整层还是包括多个第二导热区域，为了确保散热效果，优选地，底导热层506的水平投影面积与器件芯片的水平投影面积的比例是30％至130％。此处需要说明的是，(1)器件芯片的边缘会预留出用于形成环形键合部的区域，该环形键合部用于后续与盖帽的键合部进行键合以形成密封环，从而将器件芯片上的器件单元密封在由器件单元、盖帽以及密封环所形成的密封空间内，其中，将器件芯片上环形键合部的外边缘定义为器件芯片的边界，相应地该边界的水平投影被定义为器件芯片的水平投影。(2)考虑到散热基板的面积通常大于器件芯片的面积，所以顶导热层以及底导热层的水平投影面积与器件芯片的水平投影面积的比例存在大于100％的可能。
优选地，所有第一导热孔结构的水平投影面积之和与器件芯片的水平投影面积的比例范围是30％至130％，有利于第一导热孔结构实现高效的热量传递。考虑到散热基板的面积通常大于器件芯片的面积，所以第一导热孔结构的水平投影面积之和与器件芯片的水平投影面积的比例存在大于100％的可能。
考虑到器件芯片的主要发热部件是器件单元，所以优选使散热基板与器件单元相对应的区域内第一导热孔结构分布的更为密集些。具体地，散热基板可以被划分为非核心区域(下文以第一非核心区域表示)、以及位置上与器件芯片中器件单元一一对应的核心区域(下文以第一核心区域表示)。第一核心区域与其相对应的器件单元在位置上对应是指，当散热基板安装至器件芯片上以后，散热基板中的第一核心区域位于其相对应的 器件单元上方(倒封装结构散热基板位于器件芯片上方)。其中，第一核心区域内第一导热孔结构的分布密度大于等于第一非核心区域内第一导热孔结构的分布密度。在一个具体实施例中，第一核心区域的水平投影边缘与其对应的器件单元的水平投影边缘构成环形形状(即前者的水平投影落入后者的水平投影中、或者后者的水平投影落入前者的水平投影中)，该环形形状的宽度小于等于100μm。当然，第一核心区域与其对应的器件单元二者的水平投影也可以恰好重合。此外，本领域技术人员可以理解的是，在其他实施例中，第一导热孔结构也可以是均匀分布在散热基板中。
本发明还提供了一种散热基板的制造方法，其中散热基板用于器件芯片的散热。请参考图20，图20是根据本发明的一个具体实施例的散热基板的制造方法流程图。如图所示，该制造方法包括：
在步骤S301中，提供基板本体；
在步骤S302中，在所述基板本体上形成至少一个第一导热孔结构，其中，每一所述第一导热孔结构均包括在厚度方向上贯穿所述基板本体的第一通孔、以及填充在该第一通孔内的第一导热材料；
在步骤S303中，在所述基板本体的正面形成第一连接部，所述散热基板通过所述第一连接部连接至器件芯片的背面。
下面将结合图21(a)至图21(d)对上述步骤S301至步骤S303进行详细说明。此处需要说明的是，下面仅针对于散热基板中各个组成部分的制造方法进行说明，而各个组成部分的具体材料、形状、尺寸等可以参考前文对散热基板结构说明中的相关内容，为了简明起见，在此不再重复说明。
具体地，在步骤S301中，如图21(a)所示提供基板本体500。
在步骤S302中，首先如图21(b)所示，在基板本体500上形成贯穿该基板本体500的至少一个第一通孔501。本发明对于第一通孔501的实现方式不做任何限定，例如可以利用激光打孔(CO2激光打孔、准分子激光打孔、固体激光打孔等)的方式形成、还可以利用机械钻孔的方式形成。优选地，在激光打孔或机械钻孔后对第一通孔501的表面进行打磨抛光。
接着如图21(c)所示，在第一通孔501中填充第一导热材料502以形成第一导热孔结构。在本实施例中，在第一通孔501填充第一导热材料502 的步骤如下：首先在第一通孔501的表面化学镀一层非常薄的第一导热材料，其厚度范围是0.1μm至0.3μm；接着在化学镀层的表面继续电镀第一导热材料直至第一导热材料对第一通孔501形成完全填充；最后对第一导热材料进行打磨抛光、以及对基板本体进行表面清洗。至此第一导热孔结构形成。
在步骤S303中，如图21(d)所示，在基板本体500的正面形成封装时用于与器件芯片进行连接的第一连接部。在本实施例中，第一连接部包括多个第一连接单元，每一连接单元进一步包括形成在基板本体500正面的凸块503以及形成在该凸块503上的焊球504。其中凸块503可以通过电镀的方式形成，焊球504可以通过焊料印刷或点胶的方式形成。
基于本发明所提供的制造方法形成的散热基板由于具有贯穿基板本体的第一导热孔结构，因此可以实现高效散热。
优选地，在基板本体上形成至少一个第一导热孔结构之后，本发明所提供的制造方法还包括：在基板本体的正面形成顶导热层、以及在基板本体的背面形成底导热层。其中，顶导热层的形成有利于将热量向基板本体以及第一导热孔结构快速传递，底导热层的形成则有利用将基板本体以及第一导热孔结构中的热量快速传递至外部空间。本领域技术人员可以理解的是，在其他实施例中，还可以仅在基板本体的正面形成顶导热层、或仅在基板本体的背面形成底导热层。
优选地，在形成第一连接部之前，本发明所提供的制造方法还包括形成粘附层。针对于基板本体包括顶导热层和/或底导热层的情况，粘附层形成在顶导热层的表面和/或底导热层的表面。针对于基板本体不包括顶导热层和底导热层的情况，粘附层可以直接形成在基板本体的表面上。
顶导热层可以是一整层，也可以是包括位置上与器件芯片中各器件单元一一对应的第一导热区域。针对于顶导热层包括位置上与器件芯片中各器件单元一一对应的第一导热区域来说，由于器件芯片的主要发热部件是器件单元，所以将第一导热区域设置在与器件单元相对应位置上，有利于对器件单元所产生的热量快速进行传递。当器件芯片中的器件单元数量大于1时，顶导热层中第一导热区域的数量也大于1，这种情况下，优选地，顶导热层还包括对部分或全部第一导热区域进行互联的第一互联结构 (下文以第一互联结构表示)。第一互联结构的设置可以使器件单元所产生的热量在第一导热区域之间快速传递，有利于散热效率的提升。需要说明的是，每一第一导热区域的水平投影与其对应的器件单元的水平投影之间存在第一重叠区域，为了确保散热效果，第一重叠区域的投影面积与相对应的器件单元的水平投影面积的比例优选大于50％。此处需要说明的是，第一导热区域以及第一互联结构可以通过在基板本体表面形成一层顶导热层材料后对其进行图形化得到。
与顶导热层类似，底导热层可以是一整层，也可以是包括位置上与器件芯片中各器件单元一一对应的第二导热区域。针对于底导热层包括位置上与器件芯片中各器件单元一一对应的第二导热区域来说，由于器件芯片的主要发热部件是器件单元，所以将第二导热区域设置在与器件单元相对应位置上，有利于将器件单元所产生的热量快速向外部空间进行传递。当器件芯片中的器件单元数量大于1时，底导热层中第二导热区域的数量也大于1，这种情况下，优选地，底导热层还包括对部分或全部第二导热区域进行互联的第二互联结构。第二互联结构的设置可以使基板本体和第一导热孔结构内的热量在第二导热区域之间快速传递，有利于散热效率的提升。需要说明的是，每一第二导热区域的水平投影与其对应的器件单元的水平投影之间存在第二重叠区域，为了确保散热效果，第二重叠区域的投影面积与相对应的器件单元的水平投影面积的比例优选大于50％。此处需要说明的是，第二导热区域以及第二互联结构可以通过在基板本体表面形成一层底导热层材料后对其进行图形化得到。
此外，无论顶导热层的具体结构是一整层还是包括多个第一导热区域，为了确保散热效果，优选地，顶导热层的水平投影面积与器件芯片的水平投影面积的比例是30％至130％。同样地，无论底导热层的具体结构是一整层还是包括多个第二导热区域，为了确保散热效果，优选地，底导热层的水平投影面积与器件芯片的水平投影面积的比例是30％至130％。
优选地，所有第一导热孔结构的水平投影面积之和与器件芯片的水平投影面积的比例范围是30％至130％，有利于第一导热孔结构实现高效的热量传递。
考虑到器件芯片的主要发热部件是器件单元，所以优选使散热基板与器件单元相对应的区域内第一导热孔结构分布的更为密集些。具体地，散热基板可以被划分为第一非核心区域、以及位置上与器件芯片中器件单元一一对应的第一核心区域。其中，第一核心区域内第一导热孔结构的分布密度大于等于第一非核心区域内第一导热孔结构的分布密度。在一个具体实施例中，第一核心区域的水平投影边缘与其对应的器件单元的水平投影边缘构成环形形状(即前者的水平投影落入后者的水平投影中、或者后者的水平投影落入前者的水平投影中)，该环形形状的宽度小于等于100μm。当然，第一核心区域与其对应的器件单元二者的水平投影也可以恰好重合。本领域技术人员可以理解的是，在其他实施例中，第一导热孔结构也可以是均匀分布在散热基板中。
此外还需要说明的是，在其他实施例中，本发明所提供的散热基板的制造方法还包括：在基板本体上形成阻焊层，该阻焊层用于防止焊接短路情况的出现。以散热基板包括顶导热层以及底导热层为例进行说明。在形成顶导热层以及底导热层之后，首先在顶导热层以及底导热层的表面形成干膜(例如由聚乙烯膜层、光阻层以及聚酯膜层组成)；接着对干膜进行图形化；接着以干膜为掩膜版去除部分顶导热层以及底导热层以暴露基板本体上需要形成阻焊层的区域，其中基板本体上阻焊层的形成区域需要根据实际设计需求相应确定；接着去除干膜；最后在基板本体暴露的区域上形成阻焊层(现有技术中俗称为绿油)。
本发明还提供了一种散热基板的制造方法，其中散热基板用于器件芯片的散热。请参考图22，图22是根据本发明的另一个具体实施例的散热基板的制造方法流程图。该制造方法包括：
在步骤S401中，提供多层结构，该多层结构从上至下依次包括顶导热层、基板本体以及底导热层；
在步骤S402中，在所述多层结构上形成至少一个第一导热孔结构，其中，每一所述第一导热孔结构均包括在厚度方向上贯穿所述多层结构的第一通孔、以及填充在该第一通孔内的第一导热材料；
在步骤S403中，在所述多层结构的正面形成第一连接部，所述散 热基板通过所述第一连接部连接至器件芯片的背面。
下面将结合图23(a)至图23(d)对上述步骤S401至步骤S403进行详细说明。此处需要说明的是，下面仅针对于散热基板中各个组成部分的制造方法进行说明，而各个组成部分的具体材料、形状、尺寸等可以参考前文对散热基板结构说明中的相关内容，为了简明起见，在此不再重复说明。
具体地，在步骤S401中，如图23(a)所示，提供多层结构，该多层结构从上至下依次包括顶导热层505、基板本体500以及底导热层506。在本实施例中，该多层结构可以直接采用现有的有机基板实现，例如覆铜箔基板(从上至下依次是铜箔、树脂及玻璃纤维布以及铜箔)等，为了简明起见，在此不再对所有适用于本发明制造方法的现有基板进行一一列举。直接利用现有基板进行制造本发明所提供的散热基板，有利于简化散热基板的制造工艺。
在步骤S402中，首先，如图23(b)所示，在多层结构上形成贯穿该多层结构的至少一个第一通孔501。接着如图23(c)所示，在第一通孔501中填充第一导热材料502以形成第一导热孔结构。
在步骤S403中，如图23(d)所示，在多层结构的正面形成封装时用于与器件芯片进行连接的第一连接部。
此处需要说明的，针对于直接采用现有有机基板制造散热基板的情况，若顶导热层以及底导热层是非一整层的结构，则还需要对现有有机基板的顶层和底层进行图形化以使其符合设计需求。
本发明还提供了一种封装结构，该封装结构包括：
密封结构，该密封结构包括正面相对设置的器件芯片和盖帽、以及设置在该器件芯片和盖帽之间的密封环；
第一封装基板，该第一封装基板与所述器件芯片的背面连接，该第一封装基板采用前述散热基板实现、或采用前述制造方法形成；
第二封装基板，该第二封装基板与所述盖帽的背面连接；
塑封体，该塑封体位于所述第一封装基板和所述第二封装基板之间、并对所述密封结构形成包裹。
下面将结合图25(c)对上述封装结构的各个构成部分进行说明。
具体地，本发明所提供的封装结构包括密封结构，其中，该密封结构包括器件芯片、盖帽以及密封环。在本实施例中，器件芯片包括衬底100以及形成在该衬底100上的器件单元。其中，器件单元包括依次形成在衬底100上的下电极101、压电层102以及上电极103，器件单元与衬底100之间还形成有空腔104。此处需要说明的是，器件芯片通常包括多个器件单元，此处为了简明起见，只示意性地绘制了一个器件单元。在本实施例中，如图所示，盖帽包括盖帽本体200、第一导通孔结构201以及第二连接部202。在本实施例中，如图所示，密封环300形成在器件芯片和盖帽之间，与器件芯片以及盖帽形成密封结构，器件芯片中的器件单元位于该密封结构的腔体内。需要说明的是，上述器件芯片以及盖帽仅仅是示意性举例，本发明对此不做任何限定，为了简明起见，在此不再对器件芯片以及盖帽的所有可能结构进行一一列举。
如图所示，本发明所提供的封装结构还包括第一封装基板。在本实施例中，第一封装基板采用本发明所提供的散热基板实现、或利用本发明所提供的散热基板的制造方法所形成。其中，该散热基板通过其正面的第一连接部连接至器件芯片的背面。散热基板的结构及其制造方法可以参考前文中的相关内容，为了简明起见，在此不再对散热基板的结构及其制造方法进行重复描述。
如图所示，本发明所提供的封装结构还包括第二封装基板，该第二封装基板通过盖帽背面的第二连接部与盖帽形成连接。在本实施例中，第二封装基板包括基板本体400、形成在基板本体400正面的正面焊盘401、形成在基板本体400背面的背面焊盘402、以及形成在基板本体400内部用于实现正面焊盘401和背面焊盘402电连接的第二导通孔结构403。本领域技术人员可以理解的是，图25(c)中的第二封装基板仅为示意性举例，根据实际设计需求，基板本体400内通常还会形成有与器件芯片连接的螺旋电感等电子元器件等，这些均为现有常规技术手段，为了简明起见，在此不再赘述。
如图所示，本发明所提供的封装结构还包括塑封体600，该塑封体600位于第一封装基板和第二封装基板之间对密封结构形成包裹。塑封体600主要采用绝缘有机材料制成，例如环氧树脂、硅树脂、酚醛树脂、聚氨 酯等有机树脂材料。
相较于现有封装结构来说，本发明所提供的封装结构在器件芯片的背面连接有散热基板，封装结构工作时所产生的热量在衬底侧可以通过散热基板高效地传递至封装器件的外部空间。也就是说，相较于现有封装结构来说，本发明所提供的封装结构具有更优的散热效率。
在一个优选实施例中，封装结构中的器件芯片包括衬底结构、以及形成在该衬底结构上的至少一个器件单元，其中，衬底结构的底部形成有至少一个导热孔结构(下文以第二导热孔结构表示)，每一第二导热孔结构均包括形成在衬底结构底部的盲孔以及填充在该盲孔内的导热材料(下文以第二导热材料表示)。
具体地，在本实施例中，盲孔的深度小于衬底结构的厚度，相应地第二导热孔结构的高度小于衬底结构的厚度。优选地，衬底结构的厚度不超过100μm，导热孔结构的高度大于30μm。
在本实施例中，衬底结构的主体部分(即衬底结构中除了第二导热孔结构之外的部分)可以采用现有常规的衬底材料实现。第二导热材料的热导率高于衬底结构主体部分材料的热导率。优选地，第二导热材料采用高热导率的金属材料实现，例如Cu、Au、Ag、Al、Ni、Fe、Mo、W中的一种或其任意组合。本领域技术人员可以理解的是，第二导热材料不应仅仅限于金属材料，在其他实施例中，热导率高于衬底结构主体部分的合金材料及组合、以及非金属材料也适用于第二导热材料。此外需要说明的是，对于第二导热材料来说，其可以是单晶材料、也可以是多晶材料，或者是单晶材料和多晶材料的组合，本发明对此不做任何限定。
相较于衬底采用常规材料形成的现有器件芯片来说，本实施例中的器件芯片由于衬底结构的底部形成有高热导率材料构成的第二导热孔结构，所以有效地提升了衬底结构的散热效率。与本发明所提供的散热基板配合使用，可以在封装结构的衬底侧形成更为高效的散热通道，进一步提高了封装结构的散热效率。
下面将结合图26(a)以一个优选实施例对上述器件芯片进行说明。
如图26(a)所示，衬底结构从下至上依次包括第一衬底层100a和第 二衬底层100c。在本实施例中，第一衬底层100a的材料是绝缘材料或半导体材料，例如Si、SiO2、SiN、AlN、SiC、蓝宝石中的一种或任意组合。针对于第一衬底层100a的材料是半导体材料的情况，优选该半导体材料的电阻率大于
Figure PCTCN2022133602-appb-000005
此外，第一衬底层100a的厚度范围优选是30μm至100μm。在本实施例中，第二衬底层100c的材料是高热导率的绝缘材料或半导体材料，其热导率大于等于第一衬底层100a的热导率。例如Si、AlN、SiC、金刚石、石墨、GaN、石英中的一种或其任意组合。本领域技术人员可以理解的是，上述Si、AlN、SiC、金刚石、石墨、GaN、石英仅为示意性举例，第二衬底层100c材料的实际选择和第一衬底层100a的材料有关。其中，针对于第二衬底层100c的材料是半导体材料的情况，优选该半导体材料的电阻率大于
Figure PCTCN2022133602-appb-000006
此外，第二衬底层100c的厚度范围优选是3μm至10μm。
在本实施例中，第二导热孔结构形成在第一衬底层100a中。具体地，第一衬底层100a在厚度方向上形成有贯穿该第一衬底层100a的至少一个第二通孔，该至少一个第二通孔内填充有第二导热材料100b。针对于任一第二通孔来说，其与位于其上端开口处的第二衬底层100c的底面共同构成一个盲孔，并与填充在该第二通孔内的第二导热材料100b进一步构成第二导热孔结构。其中，第二导热孔结构的和第一衬底层100a的厚度相同。
在本实施例中，第二导热材料100b的热导率高于第一衬底层100a材料的热导率。在本实施例中，第二导热材料100b优选采用高热导率的金属材料实现，例如Cu、Au、Ag、Al、Ni、Fe、Mo、W中的一种或其任意组合。当然第二导热材料100b也可以采用热导率高于第一衬底层100a的合金材料及组合、或非金属材料实现。
如图所示，在本实施例中，所有器件单元均为谐振单元，每一谐振单元从下至上依次包括下电极101、压电层102以及上电极103，每一谐振单元与衬底结构之间形成有空腔104。需要说明的是，(1)空腔104形成在第二衬底层100c内；(2)实际的器件芯片往往包括多个器件单元，此处为了简明起见，仅在图中绘制了一个器件单元用以示意，而省略了其他器件单元以及器件单元之间的连接关系。
第二衬底层100c材料的热导率大于等于第一衬底层100a材料的热导率，有利于使器件单元所产生的热量高效传递至第一衬底层100a。第一衬底层100a中第二导热孔结构的热导率大于第一衬底层100a材料的热导率，有利于使传递至第一衬底层100a的热量通过第二导热孔结构向散热基板高效传递。
为了使第二导热孔结构可以实现有效的热量传递，优选地，第二导热孔结构的水平投影面积之和与器件芯片的水平投影面积的比例范围是30％至90％。
考虑到器件芯片的主要发热部件是器件单元，所以优选地使器件单元下方区域内第二导热孔结构分布的更为密集些。具体地，第一衬底层100a可以被划分成与器件单元一一对应的第二核心区域，每一第二核心区域位于相对应的器件单元的下方。第一衬底层100a除了第二核心区域之外的其他区域称为第二非核心区域。其中，第二核心区域中第二导热孔结构的分布密度大于第二非核心区域中导热孔结构的分布密度。在一个具体实施例中，第二核心区域的水平投影边缘与其对应的器件单元的水平投影边缘构成环形形状(即前者的水平投影落入后者的水平投影中、或者后者的水平投影落入前者的水平投影中)，该环形形状的宽度小于等于100μm。当然，第二核心区域与其对应的器件单元二者的水平投影也可以恰好重合。此外，本领域技术人员可以理解的是，在其他实施例中，第二导热孔结构也可以均匀分布在第一衬底层100a中。
针对于第二导热孔结构的数量大于等于2个的情况，优选地，衬底结构中的第一衬底层100a上还形成有第三互联结构。在本实施例中，第一衬底层100a上表面形成有连通第二导热孔结构的凹槽，该第三互联结构形成在该凹槽内以使第二导热孔结构之间形成连通。第三互联结构的存在可以使器件单元所产生的热量快速地通过所有第二导热孔结构进行传递，从而更进一步地提高衬底结构的散热效率。
优选地，如图26(b)所示，在图26(a)所示结构的基础上，衬底结构进一步还包括形成在第一衬底层100a和第二衬底层100c之间的第三衬底层100d，该第三衬底层100d的材料是第三导热材料。
具体地，在本实施例中，第三衬底层100d与第一衬底层100a中第二导热孔结构形成连接。第三导热材料的热导率大于第一衬底层100a材料的热导率。优选采用高热导率的金属材料实现，例如Cu、Au、Ag、Al、Ni、Fe、Mo、W中的一种或其任意组合。当然第三导热材料也可以采用热导率高于第一衬底层100a的合金材料及组合、或非金属材料实现。此外需要说明的是，对于第三导热材料来说，其可以是单晶材料、也可以是多晶材料，或者是单晶材料和多晶材料的组合，本发明对此不做任何限定。第三衬底层100d的存在有利于热量从第二衬底层100c向第一衬底层100a的传递，从而进一步提高散热效率。此外，第三衬底层100d的厚度范围优选小于等于50μm。
第三衬底层100d的材料可以不同于第二导热材料，也可以与第二导热材料相同。此处需要说明的是，针对于衬底结构中通过设置第三衬底层以实现热量由第二衬底层向第一衬底层高效传递的情况，第一衬底层和第二衬底层其二者的材料可以不同，也可以相同。
在一个具体实施例中，第三衬底层100d可以是一整层。在其他实施例中，考虑到器件芯片的主要发热部件是器件单元，还可以使第三衬底层100d仅形成在器件单元下方。具体地，第三衬底层100d包括与器件单元一一对应的第三导热区域，每一第三导热区域位于与其相对应的器件单元的下方。针对于器件单元的数量大于等于2个的情况，更为优选地，第三衬底层100d还包括第四互联结构，该第四互联结构使第三导热区域之间形成互联。第四互联结构的存在可以使器件单元所产生的热量在第三导热区域之间快速传递，有利于散热效率的提升。需要说明的是，每一第三导热区域的水平投影与其对应的器件单元的水平投影之间存在第三重叠区域，为了确保散热效果，第三重叠区域的投影面积与相对应的器件单元的水平投影面积的比例优选大于50％。
此外，无论第三衬底层100d的具体结构是一整层还是包括多个第三导热区域，为了确保散热效果，优选地，第三衬底层100d的水平投影面积与器件芯片的水平投影面积的比例是30％至90％。
本发明还提供了一种封装结构的制造方法。请参考图24，图24 是根据本发明的一个具体实施例的封装结构的制造方法流程图。如图所示，该制造方法包括：
在步骤S501中，将器件芯片与盖帽正面相对设置，并通过密封环将其二者进行密封以形成密封结构；
在步骤S502中，在所述器件芯片的背面安装第一封装基板、以及在所述盖帽的背面安装第二封装基板，其中，所述第一封装基板采用前述散热基板实现、或利用前述制造方法形成；
在步骤S503中，在所述第一封装基板和所述第二封装基板之间形成对所述密封结构包裹的塑封体。
下面，将结合图25(a)至图25(c)对上述步骤S501至步骤S503进行详细说明。
具体地，在步骤S501中，首先提供待封装的器件芯片以及与该器件芯片相对应的盖帽；接着在器件芯片的正面(即器件单元所在表面)形成第一键合部，以及在盖帽的正面(即封装时朝向器件芯片的表面)形成位置与该第一键合部相对应的第二键合部；接着，将器件芯片与盖帽正面相对设置并将第一键合部和第二键合部对准；最后对盖帽和器件芯片进行键合固定。第一键合部和第二键合部键合后在器件芯片和盖帽之间形成密封环。器件芯片、盖帽以及密封环形成密封结构(请参考图25(a)所示结构)。密封结构中器件芯片、盖帽以及密封环的结构可以参考前文封装结构中的相关内容，为了简明起见，在此不再重复描述。
在步骤S502中，如图25(b)所示，在本实施例中，首先在盖帽背面形成第二连接部202并通过该第二连接部202将密封结构连接(倒装)至第二封装基板；接着通过第一封装基板上的第一连接部将该第一封装基板安装至器件芯片的背面。本领域技术人员可以理解的是，在其他实施例中，也可以先将第一封装基板与器件芯片进行连接、然后在将密封结构倒装至第二封装基板上。
在步骤S503，如图25(c)所示，对图25(b)所示结构进行塑封，以在第一封装基板和第二封装基板之间形成对密封结构包裹的塑封体600。
实施本发明所提供的制造方法所形成的封装结构散热效率优。
对于本领域技术人员而言，显然本发明不限于上述示范性实施例的细节，而且在不背离本发明的精神或基本特征的情况下，能够以其他的具体形式实现本发明。因此，无论从哪一点来看，均应将实施例看作是示范性的，而且是非限制性的，本发明的范围由所附权利要求而不是上述说明限定，因此旨在将落在权利要求的等同要件的含义和范围内的所有变化涵括在本发明内。不应将权利要求中的任何附图标记视为限制所涉及的权利要求。此外，显然“包括”一词不排除其他部件、单元或步骤，单数不排除复数。系统权利要求中陈述的多个部件、单元或装置也可以由一个部件、单元或装置通过软件或者硬件来实现。
以上所揭露的仅为本发明的一些较佳实施例而已，当然不能以此来限定本发明之权利范围，因此依本发明权利要求所作的等同变化，仍属本发明所涵盖的范围。

Claims (50)

  1. 一种器件芯片，该器件芯片包括：
    衬底结构，该衬底结构的底部形成有至少一个导热孔结构，每一所述导热孔结构均包括形成在所述衬底结构底部的第一盲孔以及填充在该第一盲孔内的第一导热材料；
    至少一个器件单元，该至少一个器件单元形成在所述衬底结构上。
  2. 根据权利要求1所述的器件芯片，其中：
    每一所述器件单元从下至上依次是下电极、压电层以及上电极，且每一所述器件单元与所述衬底结构之间均形成有声反射结构。
  3. 根据权利要求1或2所述的器件芯片，其中：
    所述衬底结构从下至上依次包括第一衬底层和第二衬底层；
    所述第一衬底层在厚度方向上形成有至少一个通孔，该至少一个通孔与所述第二衬底的底面构成所述第一盲孔；
    所述至少一个通孔内填充有所述第一导热材料。
  4. 根据权利要求3所述的器件芯片，其中：
    所述衬底结构还包括形成在所述第一衬底层和所述第二衬底层之间的第三衬底层，该第三衬底层的材料是第二导热材料。
  5. 根据权利要求4所述的器件芯片，其中，
    所述第二衬底层材料的热导率大于等于所述第一衬底层材料的热导率；
    所述第一导热材料以及所述第二导热材料的热导率大于所述第一衬底层材料的热导率。
  6. 根据权利要求3所述的器件芯片，其中：
    所述导热孔结构在水平方向上的投影面积之和与所述器件芯片在水平 方向上的投影面积的比例范围是30％至90％。
  7. 根据权利要求6所述的器件芯片，其中：
    所述第一衬底层包括与所述器件单元一一对应的核心区域，每一所述核心区域位于与其相对应的所述器件单元的下方；
    所述第一衬底层除了所述核心区域之外的区域为非核心区域；
    其中，所述核心区域中所述导热孔结构的分布密度大于所述非核心区域中所述导热孔结构的分布密度。
  8. 根据权利要求7所述的器件芯片，其中：
    每一所述器件单元在水平方向上的投影边缘与位于其下方的所述核心区域在水平方向上的投影边缘构成环形形状，该环形形状的宽度小于等于100μm。
  9. 根据权利要求3所述的器件芯片，其中：
    当所述导热孔结构的数量大于等于2个时，所述第一衬底层上还形成有第一互联结构，该第一互联结构形成在所述第一衬底层上表面的凹槽内并使所述导热孔结构中的所述第一导热材料之间形成互联。
  10. 根据权利要求4所述的器件芯片，其中：
    当所述器件单元的数量大于等于2个时，所述第三衬底层包括与所述器件单元一一对应的导热区域、以及第二互联结构，其中，每一所述导热区域位于与其相对应的所述器件单元的下方，所述第二互联结构使所述导热区域之间形成互联。
  11. 根据权利要求10所述的器件芯片，其中：
    所述第三衬底层在水平方向上的投影面积与所述器件芯片在水平方向上的投影面积的比例范围是30％至90％；以及
    每一所述导热区域在水平方向上的投影与相对应的所述器件单元在水 平方向上的投影之间存在重叠区域，该重叠区域的投影面积与相对应的所述器件单元在水平方向上的投影面积的比例大于50％。
  12. 一种器件芯片的制造方法，该制造方法包括：
    形成衬底结构，该衬底结构底部形成有至少一个导热孔结构，每一所述导热孔结构均包括形成在所述衬底结构底部的第一盲孔以及填充在该第一盲孔内的第一导热材料；
    在所述衬底结构上形成至少一个器件单元。
  13. 根据权利要求12所述的制造方法，其中，
    每一所述器件单元从下至上依次是下电极、压电层以及上电极，且每一所述器件单元与所述衬底结构之间均形成有声反射结构。
  14. 根据权利要求12或13所述的制造方法，其中，形成衬底结构的步骤包括：
    提供第一衬底层并在该第一衬底层的上表面形成至少一个第二盲孔；
    在所述至少一个第二盲孔内填充第一导热材料；
    在所述第一衬底层上沉积第二衬底层、以及对所述第一衬底层的下表面进行平坦化操作使所述第一导热材料暴露，以形成所述衬底结构，其中，所述第二盲孔的侧壁与所述第二衬底层的底面构成所述第一盲孔。
  15. 根据权利要求14所述的制造方法，其中，形成衬底结构的步骤还包括：
    在所述第一衬底层和所述第二衬底层之间形成第三衬底层，该第三衬底层的材料是第二导热材料。
  16. 根据权利要求15所述的制造方法，其中，
    所述第二衬底层材料的热导率大于等于所述第一衬底层材料的热导率；
    所述第一导热材料以及所述第二导热材料的热导率大于所述第一衬底 层材料的热导率。
  17. 根据权利要求14所述的制造方法，其中，
    所述导热孔结构在水平方向上的投影面积之和与所述器件芯片在水平方向上的投影面积的比例范围是30％至90％。
  18. 根据权利要求17所述的制造方法，其中：
    所述第一衬底层包括与所述器件单元一一对应的核心区域，每一所述核心区域位于相应所述器件单元的下方；
    所述第一衬底层除了所述核心区域之外的区域为非核心区域；
    其中，所述核心区域中所述导热孔结构的分布密度大于所述非核心区域中所述导热孔结构的分布密度。
  19. 根据权利要求18所述的制造方法，其中：
    每一所述器件单元在水平方向上的投影边缘与位于其下方的所述核心区域在水平方向上的投影边缘构成环形形状，该环形形状的宽度小于等于100μm。
  20. 根据权利要求14所述的制造方法，其中，当所述导热孔结构的数量大于等于2个时，形成衬底结构的步骤还包括：
    在所述第一衬底层上形成第一互联结构，该第一互联结构形成在所述第一衬底层上表面的凹槽内并使所述导热孔结构内的所述第一导热材料之间形成互联。
  21. 根据权利要求15所述的制造方法，其中：
    当所述器件单元的数量大于等于2个时，所述第三衬底层包括与所述器件单元一一对应的导热区域、以及第二互联结构，其中，每一所述导热区域位于与其相对应的所述器件单元的下方，所述第二互联结构使所述导热区域之间形成互联。
  22. 根据权利要求20所述的制造方法，其中：
    所述第三衬底层在水平方向上的投影面积与所述器件芯片在水平方向上的投影面积的比例范围是30％至90％；以及
    每一所述导热区域在水平方向上的投影与相对应的所述器件单元在水平方向上的投影之间存在重叠区域，该重叠区域的投影面积与相对应的所述器件单元在水平方向上的投影面积的比例大于50％。
  23. 一种封装结构，该封装结构包括：
    如权利要求1至11中任一项所述的器件芯片；
    盖帽，该盖帽的正面与所述器件芯片相对设置、背面设置有连接部；
    密封环，该密封环设置在所述器件芯片和所述盖帽之间，与所述器件芯片和所述盖帽形成密封结构，所述至少一个器件单元位于该密封结构的腔体内；
    封装基板，所述密封结构通过所述连接部与所述封装基板形成连接；
    塑封体，该塑封体对所述密封结构形成包裹。
  24. 一种封装结构的制造方法，该制造方法包括：
    提供器件芯片，该器件芯片采用如权利要求1至11中任一项所述的器件芯片实现或采用如权利要求12至22中任一项所述的制造方法形成；
    提供盖帽，该盖帽的正面与所述器件芯片相对设置；
    在所述器件芯片和所述盖帽之间形成密封环，该密封环与所述器件芯片和所述盖帽形成密封结构，所述至少一个器件单元位于该密封结构的腔体内；
    在所述盖帽背面形成连接部并通过该连接部将所述密封结构连接至封装基板；
    形成对所述密封结构包裹的塑封体。
  25. 一种散热基板，用于器件芯片的散热，该散热基板包括：
    基板本体；
    至少一个第一导热孔结构，其中，每一所述第一导热孔结构均包括在厚度方向上贯穿所述基板本体的第一通孔、以及填充在该第一通孔内的第一导热材料；
    第一连接部，该第一连接部形成在所述基板本体的正面，所述散热基板通过所述第一连接部连接至器件芯片的背面。
  26. 根据权利要求25所述的散热基板，该散热基板还包括：
    顶导热层，该顶导热层形成在所述基板本体的正面；
    底导热层，该底导热层形成在所述基板本体的背面。
  27. 根据权利要求26所述的散热基板，其中：
    所述顶导热层的材料、所述底导热层的材料以及所述第一导热材料的热导率均高于器件芯片封装时所采用的塑封体的热导率；
    所述基板本体其材料的热导率高于或等于器件芯片封装时所采用的塑封体的热导率。
  28. 根据权利要求26所述的散热基板，其中：
    所述顶导热层和所述底导热层的厚度均小于等于50μm；
    所述基板本体的厚度小于等于100μm。
  29. 根据权利要求26所述的散热基板，其中：
    所述顶导热层的水平投影面积与所述器件芯片的水平投影面积的比例范围是30％至130％；和/或
    所述底导热层的水平投影面积与所述器件芯片的水平投影面积的比例范围是30％至130％。
  30. 根据权利要求26所述的散热基板，其中：
    所述器件芯片中器件单元的数量大于等于2个；
    所述顶导热层包括位置上与所述器件芯片中各器件单元一一对应的第一导热区域、以及用于对所述第一导热区域进行互联的第一互联结构；和/或
    所述底导热层包括位置上与所述器件芯片中各器件单元一一对应的第二导热区域、以及用于对所述第二导热区域进行互联的第二互联结构。
  31. 根据权利要求30所述的散热基板，其中：
    每一所述第一导热区域的水平投影与相对应的所述器件单元的水平投影之间存在第一重叠区域，该第一重叠区域的投影面积与相对应的所述器件单元的水平投影面积的比例大于50％；和/或
    每一所述第二导热区域的水平投影与相对应的所述器件单元的水平投影之间存在第二重叠区域，该第二重叠区域的投影面积与相对应的所述器件单元的水平投影面积的比例大于50％。
  32. 根据权利要求25所述的散热基板，其中：
    所述第一导热孔结构的水平投影面积之和与所述器件芯片的水平投影面积的比例范围是30％至130％。
  33. 根据权利要求25所述的散热基板，其中：
    所述散热基板包括位置上与所述器件芯片中各器件单元一一对应的第一核心区域；
    所述散热基板除了所述第一核心区域之外的区域为第一非核心区域；
    其中，所述第一核心区域内所述第一导热孔结构的分布密度大于等于所述第一非核心区域内所述第一导热孔结构的分布密度。
  34. 根据权利要求33所述的散热基板，其中：
    每一所述第一核心区域的水平投影边缘与相对应的所述器件单元的水平投影边缘构成环形形状，该环形形状的宽度小于等于100μm。
  35. 一种散热基板的制造方法，该散热基板用于器件芯片的散热，该制造方法包括：
    提供基板本体；
    在所述基板本体上形成至少一个第一导热孔结构，其中，每一所述第一导热孔结构均包括在厚度方向上贯穿所述基板本体的第一通孔、以及填充在该第一通孔内的第一导热材料；
    在所述基板本体的正面形成第一连接部，所述散热基板通过所述第一连接部连接至器件芯片的背面。
  36. 根据权利要求35所述的制造方法，其中：
    在所述基板本体上形成至少一个第一导热孔结构之后，该制造方法还包括：在所述基板本体的正面形成顶导热层、以及在所述基板本体的背面形成底导热层。
  37. 根据权利要求36所述的制造方法，其中：
    所述顶导热层的材料、所述底导热层的材料以及所述第一导热材料的热导率均高于器件芯片封装时所采用的塑封体的热导率；
    所述基板本体其材料的热导率高于或等于器件芯片封装时所采用的塑封体的热导率。
  38. 根据权利要求36所述的制造方法，其中：
    所述顶导热层和所述底导热层的厚度均小于等于50μm；
    所述基板本体的厚度小于等于100μm。
  39. 根据权利要求36所述的制造方法，其中：
    所述顶导热层的水平投影面积与所述器件芯片的水平投影面积的比例范围是30％至130％；和/或
    所述底导热层的水平投影面积与所述器件芯片的水平投影面积的比例范围是30％至130％。
  40. 根据权利要求36所述的制造方法，其中：
    所述器件芯片中器件单元的数量大于等于2个；
    所述顶导热层包括位置上与所述器件芯片中各器件单元一一对应的第一导热区域、以及用于对所述第一导热区域进行互联的第一互联结构；和/或
    所述底导热层包括位置上与所述器件芯片中各器件单元一一对应的第二导热区域、以及用于对所述第二导热区域进行互联的第二互联结构。
  41. 根据权利要求40所述的制造方法，其中：
    每一所述第一导热区域的水平投影与相对应的所述器件单元的水平投影之间存在第一重叠区域，该第一重叠区域的投影面积与相对应的所述器件单元的水平投影面积的比例大于50％；和/或
    每一所述第二导热区域的水平投影与相对应的所述器件单元的水平投影之间存在第二重叠区域，该第二重叠区域的投影面积与相对应的所述器件单元的水平投影面积的比例大于50％。
  42. 根据权利要求35所述的制造方法，其中：
    所述第一导热孔结构的水平投影面积之和与所述器件芯片的水平投影面积的比例范围是30％至130％。
  43. 根据权利要求35所述的制造方法，其中：
    所述散热基板包括与所述器件芯片中各器件单元一一对应的第一核心区域，每一所述核心区域位于与其相对应的器件单元的下方；
    所述散热基板除了所述第一核心区域之外的区域为第一非核心区域；
    其中，所述第一核心区域内所述第一导热孔结构的分布密度大于等于所述第一非核心区域内所述第一导热孔结构的分布密度。
  44. 根据权利要求43所述的制造方法，其中：
    每一所述第一核心区域的水平投影边缘与相对应的所述器件单元的水平投影边缘构成环形形状，该环形形状的宽度小于等于100μm。
  45. 一种散热基板的制造方法，该散热基板用于器件芯片的散热，该制造方法包括：
    提供多层结构，该多层结构从上至下依次包括顶导热层、基板本体以及底导热层；
    在所述多层结构上形成至少一个第一导热孔结构，其中，每一所述第一导热孔结构均包括在厚度方向上贯穿所述多层结构的第一通孔、以及填充在该第一通孔内的第一导热材料；
    在所述多层结构的正面形成第一连接部，所述散热基板通过所述第一连接部连接至器件芯片的背面。
  46. 一种封装结构，该封装结构包括：
    密封结构，该密封结构包括正面相对设置的器件芯片和盖帽、以及设置在该器件芯片和盖帽之间的密封环；
    第一封装基板，该第一封装基板与所述器件芯片的背面连接，该第一封装基板采用如权利要求25至34中任一项所述的散热基板实现、或采用如权利要求35至45中任一项所述的制造方法形成；
    第二封装基板，该第二封装基板与所述盖帽的背面连接；
    塑封体，该塑封体位于所述第一封装基板和所述第二封装基板之间、并对所述密封结构形成包裹。
  47. 根据权利要求46所述的封装结构，其中：
    所述器件芯片包括衬底结构以及至少一个器件单元；
    所述衬底结构的底部形成有至少一个第二导热孔结构，每一所述第二导热孔结构均包括形成在所述衬底结构底部的盲孔以及填充在该盲孔内的第二导热材料；
    所述至少一个器件单元形成在所述衬底结构上。
  48. 根据权利要求47的所述封装结构，其中：
    所述衬底结构从下至上依次包括第一衬底层和第二衬底层；
    所述第一衬底层在厚度方向上形成有至少一个第二通孔，该至少一个第二通孔与所述第二衬底的底面构成所述盲孔；
    所述至少一个第二通孔内填充有所述第二导热材料。
  49. 根据权利要求48的所述封装结构，其中：
    所述衬底结构还包括形成在所述第一衬底层和所述第二衬底层之间的第三衬底层，该第三衬底层的材料是第三导热材料。
  50. 一种封装结构的制造方法，该制造方法包括：
    将器件芯片与盖帽正面相对设置，并通过密封环将其二者进行密封以形成密封结构；
    在所述器件芯片的背面安装第一封装基板、以及在所述盖帽的背面安装第二封装基板，其中，所述第一封装基板采用如权利要求25至34中任一项所述的散热基板实现、或利用如权利要求35至45中任一项所述的制造方法形成；
    在所述第一封装基板和所述第二封装基板之间形成对所述密封结构包裹的塑封体。
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